STM32F103

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• 0xA0000000FSMC// Flexible static memory controller

  • 0xA0000000BCR1// SRAM/NOR-Flash chip-select control register 1

    • [19]CBURSTRW (def=0x0) // CBURSTRW
    • [15]ASYNCWAIT (def=0x0) // ASYNCWAIT
    • [14]EXTMOD (def=0x0) // EXTMOD
    • [13]WAITEN (def=0x1) // WAITEN
    • [12]WREN (def=0x1) // WREN
    • [11]WAITCFG (def=0x0) // WAITCFG
    • [9]WAITPOL (def=0x0) // WAITPOL
    • [8]BURSTEN (def=0x0) // BURSTEN
    • [6]FACCEN (def=0x1) // FACCEN
    • [4:5]MWID (def=0x1) // MWID
    • [2:3]MTYP (def=0x0) // MTYP
    • [1]MUXEN (def=0x0) // MUXEN
    • [0]MBKEN (def=0x0) // MBKEN
  • 0xA0000004BTR1// SRAM/NOR-Flash chip-select timing register 1

    • [28:29]ACCMOD (def=0x3) // ACCMOD
    • [24:27]DATLAT (def=0xF) // DATLAT
    • [20:23]CLKDIV (def=0xF) // CLKDIV
    • [16:19]BUSTURN (def=0xF) // BUSTURN
    • [8:15]DATAST (def=0xFF) // DATAST
    • [4:7]ADDHLD (def=0xF) // ADDHLD
    • [0:3]ADDSET (def=0xF) // ADDSET
  • 0xA0000008BCR2// SRAM/NOR-Flash chip-select control register 2

    • [19]CBURSTRW (def=0x0) // CBURSTRW
    • [15]ASYNCWAIT (def=0x0) // ASYNCWAIT
    • [14]EXTMOD (def=0x0) // EXTMOD
    • [13]WAITEN (def=0x1) // WAITEN
    • [12]WREN (def=0x1) // WREN
    • [11]WAITCFG (def=0x0) // WAITCFG
    • [10]WRAPMOD (def=0x0) // WRAPMOD
    • [9]WAITPOL (def=0x0) // WAITPOL
    • [8]BURSTEN (def=0x0) // BURSTEN
    • [6]FACCEN (def=0x1) // FACCEN
    • [4:5]MWID (def=0x1) // MWID
    • [2:3]MTYP (def=0x0) // MTYP
    • [1]MUXEN (def=0x0) // MUXEN
    • [0]MBKEN (def=0x0) // MBKEN
  • 0xA000000CBTR2// SRAM/NOR-Flash chip-select timing register 2

    • [28:29]ACCMOD (def=0x3) // ACCMOD
    • [24:27]DATLAT (def=0xF) // DATLAT
    • [20:23]CLKDIV (def=0xF) // CLKDIV
    • [16:19]BUSTURN (def=0xF) // BUSTURN
    • [8:15]DATAST (def=0xFF) // DATAST
    • [4:7]ADDHLD (def=0xF) // ADDHLD
    • [0:3]ADDSET (def=0xF) // ADDSET
  • 0xA0000010BCR3// SRAM/NOR-Flash chip-select control register 3

    • [19]CBURSTRW (def=0x0) // CBURSTRW
    • [15]ASYNCWAIT (def=0x0) // ASYNCWAIT
    • [14]EXTMOD (def=0x0) // EXTMOD
    • [13]WAITEN (def=0x1) // WAITEN
    • [12]WREN (def=0x1) // WREN
    • [11]WAITCFG (def=0x0) // WAITCFG
    • [10]WRAPMOD (def=0x0) // WRAPMOD
    • [9]WAITPOL (def=0x0) // WAITPOL
    • [8]BURSTEN (def=0x0) // BURSTEN
    • [6]FACCEN (def=0x1) // FACCEN
    • [4:5]MWID (def=0x1) // MWID
    • [2:3]MTYP (def=0x0) // MTYP
    • [1]MUXEN (def=0x0) // MUXEN
    • [0]MBKEN (def=0x0) // MBKEN
  • 0xA0000014BTR3// SRAM/NOR-Flash chip-select timing register 3

    • [28:29]ACCMOD (def=0x3) // ACCMOD
    • [24:27]DATLAT (def=0xF) // DATLAT
    • [20:23]CLKDIV (def=0xF) // CLKDIV
    • [16:19]BUSTURN (def=0xF) // BUSTURN
    • [8:15]DATAST (def=0xFF) // DATAST
    • [4:7]ADDHLD (def=0xF) // ADDHLD
    • [0:3]ADDSET (def=0xF) // ADDSET
  • 0xA0000018BCR4// SRAM/NOR-Flash chip-select control register 4

    • [19]CBURSTRW (def=0x0) // CBURSTRW
    • [15]ASYNCWAIT (def=0x0) // ASYNCWAIT
    • [14]EXTMOD (def=0x0) // EXTMOD
    • [13]WAITEN (def=0x1) // WAITEN
    • [12]WREN (def=0x1) // WREN
    • [11]WAITCFG (def=0x0) // WAITCFG
    • [10]WRAPMOD (def=0x0) // WRAPMOD
    • [9]WAITPOL (def=0x0) // WAITPOL
    • [8]BURSTEN (def=0x0) // BURSTEN
    • [6]FACCEN (def=0x1) // FACCEN
    • [4:5]MWID (def=0x1) // MWID
    • [2:3]MTYP (def=0x0) // MTYP
    • [1]MUXEN (def=0x0) // MUXEN
    • [0]MBKEN (def=0x0) // MBKEN
  • 0xA000001CBTR4// SRAM/NOR-Flash chip-select timing register 4

    • [28:29]ACCMOD (def=0x3) // ACCMOD
    • [24:27]DATLAT (def=0xF) // DATLAT
    • [20:23]CLKDIV (def=0xF) // CLKDIV
    • [16:19]BUSTURN (def=0xF) // BUSTURN
    • [8:15]DATAST (def=0xFF) // DATAST
    • [4:7]ADDHLD (def=0xF) // ADDHLD
    • [0:3]ADDSET (def=0xF) // ADDSET
  • 0xA0000060PCR2// PC Card/NAND Flash control register 2

    • [17:19]ECCPS (def=0x0) // ECCPS
    • [13:16]TAR (def=0x0) // TAR
    • [9:12]TCLR (def=0x0) // TCLR
    • [6]ECCEN (def=0x0) // ECCEN
    • [4:5]PWID (def=0x1) // PWID
    • [3]PTYP (def=0x1) // PTYP
    • [2]PBKEN (def=0x0) // PBKEN
    • [1]PWAITEN (def=0x0) // PWAITEN
  • 0xA0000064SR2// FIFO status and interrupt register 2

    • [6]FEMPT (def=0x1) // FEMPT
    • [5]IFEN (def=0x0) // IFEN
    • [4]ILEN (def=0x0) // ILEN
    • [3]IREN (def=0x0) // IREN
    • [2]IFS (def=0x0) // IFS
    • [1]ILS (def=0x0) // ILS
    • [0]IRS (def=0x0) // IRS
  • 0xA0000068PMEM2// Common memory space timing register 2

    • [24:31]MEMHIZx (def=0xFC) // MEMHIZx
    • [16:23]MEMHOLDx (def=0xFC) // MEMHOLDx
    • [8:15]MEMWAITx (def=0xFC) // MEMWAITx
    • [0:7]MEMSETx (def=0xFC) // MEMSETx
  • 0xA000006CPATT2// Attribute memory space timing register 2

    • [24:31]ATTHIZx (def=0xFC) // Attribute memory x databus HiZ time
    • [16:23]ATTHOLDx (def=0xFC) // Attribute memory x hold time
    • [8:15]ATTWAITx (def=0xFC) // Attribute memory x wait time
    • [0:7]ATTSETx (def=0xFC) // Attribute memory x setup time
  • 0xA0000074ECCR2// ECC result register 2

    • [0:31]ECCx (def=0x0) // ECC result
  • 0xA0000080PCR3// PC Card/NAND Flash control register 3

    • [17:19]ECCPS (def=0x0) // ECCPS
    • [13:16]TAR (def=0x0) // TAR
    • [9:12]TCLR (def=0x0) // TCLR
    • [6]ECCEN (def=0x0) // ECCEN
    • [4:5]PWID (def=0x1) // PWID
    • [3]PTYP (def=0x1) // PTYP
    • [2]PBKEN (def=0x0) // PBKEN
    • [1]PWAITEN (def=0x0) // PWAITEN
  • 0xA0000084SR3// FIFO status and interrupt register 3

    • [6]FEMPT (def=0x1) // FEMPT
    • [5]IFEN (def=0x0) // IFEN
    • [4]ILEN (def=0x0) // ILEN
    • [3]IREN (def=0x0) // IREN
    • [2]IFS (def=0x0) // IFS
    • [1]ILS (def=0x0) // ILS
    • [0]IRS (def=0x0) // IRS
  • 0xA0000088PMEM3// Common memory space timing register 3

    • [24:31]MEMHIZx (def=0xFC) // MEMHIZx
    • [16:23]MEMHOLDx (def=0xFC) // MEMHOLDx
    • [8:15]MEMWAITx (def=0xFC) // MEMWAITx
    • [0:7]MEMSETx (def=0xFC) // MEMSETx
  • 0xA000008CPATT3// Attribute memory space timing register 3

    • [24:31]ATTHIZx (def=0xFC) // ATTHIZx
    • [16:23]ATTHOLDx (def=0xFC) // ATTHOLDx
    • [8:15]ATTWAITx (def=0xFC) // ATTWAITx
    • [0:7]ATTSETx (def=0xFC) // ATTSETx
  • 0xA0000094ECCR3// ECC result register 3

    • [0:31]ECCx (def=0x0) // ECCx
  • 0xA00000A0PCR4// PC Card/NAND Flash control register 4

    • [17:19]ECCPS (def=0x0) // ECCPS
    • [13:16]TAR (def=0x0) // TAR
    • [9:12]TCLR (def=0x0) // TCLR
    • [6]ECCEN (def=0x0) // ECCEN
    • [4:5]PWID (def=0x1) // PWID
    • [3]PTYP (def=0x1) // PTYP
    • [2]PBKEN (def=0x0) // PBKEN
    • [1]PWAITEN (def=0x0) // PWAITEN
  • 0xA00000A4SR4// FIFO status and interrupt register 4

    • [6]FEMPT (def=0x1) // FEMPT
    • [5]IFEN (def=0x0) // IFEN
    • [4]ILEN (def=0x0) // ILEN
    • [3]IREN (def=0x0) // IREN
    • [2]IFS (def=0x0) // IFS
    • [1]ILS (def=0x0) // ILS
    • [0]IRS (def=0x0) // IRS
  • 0xA00000A8PMEM4// Common memory space timing register 4

    • [24:31]MEMHIZx (def=0xFC) // MEMHIZx
    • [16:23]MEMHOLDx (def=0xFC) // MEMHOLDx
    • [8:15]MEMWAITx (def=0xFC) // MEMWAITx
    • [0:7]MEMSETx (def=0xFC) // MEMSETx
  • 0xA00000ACPATT4// Attribute memory space timing register 4

    • [24:31]ATTHIZx (def=0xFC) // ATTHIZx
    • [16:23]ATTHOLDx (def=0xFC) // ATTHOLDx
    • [8:15]ATTWAITx (def=0xFC) // ATTWAITx
    • [0:7]ATTSETx (def=0xFC) // ATTSETx
  • 0xA00000B0PIO4// I/O space timing register 4

    • [24:31]IOHIZx (def=0xFC) // IOHIZx
    • [16:23]IOHOLDx (def=0xFC) // IOHOLDx
    • [8:15]IOWAITx (def=0xFC) // IOWAITx
    • [0:7]IOSETx (def=0xFC) // IOSETx
  • 0xA0000104BWTR1// SRAM/NOR-Flash write timing registers 1

    • [28:29]ACCMOD (def=0x0) // ACCMOD
    • [24:27]DATLAT (def=0xF) // DATLAT
    • [20:23]CLKDIV (def=0xF) // CLKDIV
    • [8:15]DATAST (def=0xFF) // DATAST
    • [4:7]ADDHLD (def=0xF) // ADDHLD
    • [0:3]ADDSET (def=0xF) // ADDSET
  • 0xA000010CBWTR2// SRAM/NOR-Flash write timing registers 2

    • [28:29]ACCMOD (def=0x0) // ACCMOD
    • [24:27]DATLAT (def=0xF) // DATLAT
    • [20:23]CLKDIV (def=0xF) // CLKDIV
    • [8:15]DATAST (def=0xFF) // DATAST
    • [4:7]ADDHLD (def=0xF) // ADDHLD
    • [0:3]ADDSET (def=0xF) // ADDSET
  • 0xA0000114BWTR3// SRAM/NOR-Flash write timing registers 3

    • [28:29]ACCMOD (def=0x0) // ACCMOD
    • [24:27]DATLAT (def=0xF) // DATLAT
    • [20:23]CLKDIV (def=0xF) // CLKDIV
    • [8:15]DATAST (def=0xFF) // DATAST
    • [4:7]ADDHLD (def=0xF) // ADDHLD
    • [0:3]ADDSET (def=0xF) // ADDSET
  • 0xA000011CBWTR4// SRAM/NOR-Flash write timing registers 4

    • [28:29]ACCMOD (def=0x0) // ACCMOD
    • [24:27]DATLAT (def=0xF) // DATLAT
    • [20:23]CLKDIV (def=0xF) // CLKDIV
    • [8:15]DATAST (def=0xFF) // DATAST
    • [4:7]ADDHLD (def=0xF) // ADDHLD
    • [0:3]ADDSET (def=0xF) // ADDSET
  interrupts:
  • [48] FSMC // FSMC global interrupt
• 0x40007000PWR// Power control

  • 0x40007000CR// Power control register (PWR_CR)

    • [0]LPDS (def=0x0) // Low Power Deep Sleep
    • [1]PDDS (def=0x0) // Power Down Deep Sleep
    • [2]CWUF (def=0x0) // Clear Wake-up Flag
    • [3]CSBF (def=0x0) // Clear STANDBY Flag
    • [4]PVDE (def=0x0) // Power Voltage Detector Enable
    • [5:7]PLS (def=0x0) // PVD Level Selection
    • [8]DBP (def=0x0) // Disable Backup Domain write protection
  • 0x40007004CSR// Power control register (PWR_CR)

    • [0]WUF (def=0x0) // Wake-Up Flag
    • [1]SBF (def=0x0) // STANDBY Flag
    • [2]PVDO (def=0x0) // PVD Output
    • [8]EWUP (def=0x0) // Enable WKUP pin
  interrupts:
  • [1] PVD // PVD through EXTI line detection interrupt
• 0x40021000RCC// Reset and clock control

  • 0x40021000CR// Clock control register

    • [0]HSION (def=0x1) // Internal High Speed clock enable
    • [1]HSIRDY (def=0x1) // Internal High Speed clock ready flag
    • [3:7]HSITRIM (def=0x10) // Internal High Speed clock trimming
    • [8:15]HSICAL (def=0x0) // Internal High Speed clock Calibration
    • [16]HSEON (def=0x0) // External High Speed clock enable
    • [17]HSERDY (def=0x0) // External High Speed clock ready flag
    • [18]HSEBYP (def=0x0) // External High Speed clock Bypass
    • [19]CSSON (def=0x0) // Clock Security System enable
    • [24]PLLON (def=0x0) // PLL enable
    • [25]PLLRDY (def=0x0) // PLL clock ready flag
  • 0x40021004CFGR// Clock configuration register (RCC_CFGR)

    • [0:1]SW (def=0x0) // System clock Switch
    • [2:3]SWS (def=0x0) // System Clock Switch Status
    • [4:7]HPRE (def=0x0) // AHB prescaler
    • [8:10]PPRE1 (def=0x0) // APB Low speed prescaler (APB1)
    • [11:13]PPRE2 (def=0x0) // APB High speed prescaler (APB2)
    • [14:15]ADCPRE (def=0x0) // ADC prescaler
    • [16]PLLSRC (def=0x0) // PLL entry clock source
    • [17]PLLXTPRE (def=0x0) // HSE divider for PLL entry
    • [18:21]PLLMUL (def=0x0) // PLL Multiplication Factor
    • [22]OTGFSPRE (def=0x0) // USB OTG FS prescaler
    • [24:26]MCO (def=0x0) // Microcontroller clock output
  • 0x40021008CIR// Clock interrupt register (RCC_CIR)

    • [0]LSIRDYF (def=0x0) // LSI Ready Interrupt flag
    • [1]LSERDYF (def=0x0) // LSE Ready Interrupt flag
    • [2]HSIRDYF (def=0x0) // HSI Ready Interrupt flag
    • [3]HSERDYF (def=0x0) // HSE Ready Interrupt flag
    • [4]PLLRDYF (def=0x0) // PLL Ready Interrupt flag
    • [7]CSSF (def=0x0) // Clock Security System Interrupt flag
    • [8]LSIRDYIE (def=0x0) // LSI Ready Interrupt Enable
    • [9]LSERDYIE (def=0x0) // LSE Ready Interrupt Enable
    • [10]HSIRDYIE (def=0x0) // HSI Ready Interrupt Enable
    • [11]HSERDYIE (def=0x0) // HSE Ready Interrupt Enable
    • [12]PLLRDYIE (def=0x0) // PLL Ready Interrupt Enable
    • [16]LSIRDYC (def=0x0) // LSI Ready Interrupt Clear
    • [17]LSERDYC (def=0x0) // LSE Ready Interrupt Clear
    • [18]HSIRDYC (def=0x0) // HSI Ready Interrupt Clear
    • [19]HSERDYC (def=0x0) // HSE Ready Interrupt Clear
    • [20]PLLRDYC (def=0x0) // PLL Ready Interrupt Clear
    • [23]CSSC (def=0x0) // Clock security system interrupt clear
  • 0x4002100CAPB2RSTR// APB2 peripheral reset register (RCC_APB2RSTR)

    • [0]AFIORST (def=0x0) // Alternate function I/O reset
    • [2]IOPARST (def=0x0) // IO port A reset
    • [3]IOPBRST (def=0x0) // IO port B reset
    • [4]IOPCRST (def=0x0) // IO port C reset
    • [5]IOPDRST (def=0x0) // IO port D reset
    • [6]IOPERST (def=0x0) // IO port E reset
    • [7]IOPFRST (def=0x0) // IO port F reset
    • [8]IOPGRST (def=0x0) // IO port G reset
    • [9]ADC1RST (def=0x0) // ADC 1 interface reset
    • [10]ADC2RST (def=0x0) // ADC 2 interface reset
    • [11]TIM1RST (def=0x0) // TIM1 timer reset
    • [12]SPI1RST (def=0x0) // SPI 1 reset
    • [13]TIM8RST (def=0x0) // TIM8 timer reset
    • [14]USART1RST (def=0x0) // USART1 reset
    • [15]ADC3RST (def=0x0) // ADC 3 interface reset
    • [19]TIM9RST (def=0x0) // TIM9 timer reset
    • [20]TIM10RST (def=0x0) // TIM10 timer reset
    • [21]TIM11RST (def=0x0) // TIM11 timer reset
  • 0x40021010APB1RSTR// APB1 peripheral reset register (RCC_APB1RSTR)

    • [0]TIM2RST (def=0x0) // Timer 2 reset
    • [1]TIM3RST (def=0x0) // Timer 3 reset
    • [2]TIM4RST (def=0x0) // Timer 4 reset
    • [3]TIM5RST (def=0x0) // Timer 5 reset
    • [4]TIM6RST (def=0x0) // Timer 6 reset
    • [5]TIM7RST (def=0x0) // Timer 7 reset
    • [6]TIM12RST (def=0x0) // Timer 12 reset
    • [7]TIM13RST (def=0x0) // Timer 13 reset
    • [8]TIM14RST (def=0x0) // Timer 14 reset
    • [11]WWDGRST (def=0x0) // Window watchdog reset
    • [14]SPI2RST (def=0x0) // SPI2 reset
    • [15]SPI3RST (def=0x0) // SPI3 reset
    • [17]USART2RST (def=0x0) // USART 2 reset
    • [18]USART3RST (def=0x0) // USART 3 reset
    • [19]UART4RST (def=0x0) // UART 4 reset
    • [20]UART5RST (def=0x0) // UART 5 reset
    • [21]I2C1RST (def=0x0) // I2C1 reset
    • [22]I2C2RST (def=0x0) // I2C2 reset
    • [23]USBRST (def=0x0) // USB reset
    • [25]CANRST (def=0x0) // CAN reset
    • [27]BKPRST (def=0x0) // Backup interface reset
    • [28]PWRRST (def=0x0) // Power interface reset
    • [29]DACRST (def=0x0) // DAC interface reset
  • 0x40021014AHBENR// AHB Peripheral Clock enable register (RCC_AHBENR)

    • [0]DMA1EN (def=0x0) // DMA1 clock enable
    • [1]DMA2EN (def=0x0) // DMA2 clock enable
    • [2]SRAMEN (def=0x1) // SRAM interface clock enable
    • [4]FLITFEN (def=0x1) // FLITF clock enable
    • [6]CRCEN (def=0x0) // CRC clock enable
    • [8]FSMCEN (def=0x0) // FSMC clock enable
    • [10]SDIOEN (def=0x0) // SDIO clock enable
  • 0x40021018APB2ENR// APB2 peripheral clock enable register (RCC_APB2ENR)

    • [0]AFIOEN (def=0x0) // Alternate function I/O clock enable
    • [2]IOPAEN (def=0x0) // I/O port A clock enable
    • [3]IOPBEN (def=0x0) // I/O port B clock enable
    • [4]IOPCEN (def=0x0) // I/O port C clock enable
    • [5]IOPDEN (def=0x0) // I/O port D clock enable
    • [6]IOPEEN (def=0x0) // I/O port E clock enable
    • [7]IOPFEN (def=0x0) // I/O port F clock enable
    • [8]IOPGEN (def=0x0) // I/O port G clock enable
    • [9]ADC1EN (def=0x0) // ADC 1 interface clock enable
    • [10]ADC2EN (def=0x0) // ADC 2 interface clock enable
    • [11]TIM1EN (def=0x0) // TIM1 Timer clock enable
    • [12]SPI1EN (def=0x0) // SPI 1 clock enable
    • [13]TIM8EN (def=0x0) // TIM8 Timer clock enable
    • [14]USART1EN (def=0x0) // USART1 clock enable
    • [15]ADC3EN (def=0x0) // ADC3 interface clock enable
    • [19]TIM9EN (def=0x0) // TIM9 Timer clock enable
    • [20]TIM10EN (def=0x0) // TIM10 Timer clock enable
    • [21]TIM11EN (def=0x0) // TIM11 Timer clock enable
  • 0x4002101CAPB1ENR// APB1 peripheral clock enable register (RCC_APB1ENR)

    • [0]TIM2EN (def=0x0) // Timer 2 clock enable
    • [1]TIM3EN (def=0x0) // Timer 3 clock enable
    • [2]TIM4EN (def=0x0) // Timer 4 clock enable
    • [3]TIM5EN (def=0x0) // Timer 5 clock enable
    • [4]TIM6EN (def=0x0) // Timer 6 clock enable
    • [5]TIM7EN (def=0x0) // Timer 7 clock enable
    • [6]TIM12EN (def=0x0) // Timer 12 clock enable
    • [7]TIM13EN (def=0x0) // Timer 13 clock enable
    • [8]TIM14EN (def=0x0) // Timer 14 clock enable
    • [11]WWDGEN (def=0x0) // Window watchdog clock enable
    • [14]SPI2EN (def=0x0) // SPI 2 clock enable
    • [15]SPI3EN (def=0x0) // SPI 3 clock enable
    • [17]USART2EN (def=0x0) // USART 2 clock enable
    • [18]USART3EN (def=0x0) // USART 3 clock enable
    • [19]UART4EN (def=0x0) // UART 4 clock enable
    • [20]UART5EN (def=0x0) // UART 5 clock enable
    • [21]I2C1EN (def=0x0) // I2C 1 clock enable
    • [22]I2C2EN (def=0x0) // I2C 2 clock enable
    • [23]USBEN (def=0x0) // USB clock enable
    • [25]CANEN (def=0x0) // CAN clock enable
    • [27]BKPEN (def=0x0) // Backup interface clock enable
    • [28]PWREN (def=0x0) // Power interface clock enable
    • [29]DACEN (def=0x0) // DAC interface clock enable
  • 0x40021020BDCR// Backup domain control register (RCC_BDCR)

    • [0]LSEON (def=0x0) // External Low Speed oscillator enable
    • [1]LSERDY (def=0x0) // External Low Speed oscillator ready
    • [2]LSEBYP (def=0x0) // External Low Speed oscillator bypass
    • [8:9]RTCSEL (def=0x0) // RTC clock source selection
    • [15]RTCEN (def=0x0) // RTC clock enable
    • [16]BDRST (def=0x0) // Backup domain software reset
  • 0x40021024CSR// Control/status register (RCC_CSR)

    • [0]LSION (def=0x0) // Internal low speed oscillator enable
    • [1]LSIRDY (def=0x0) // Internal low speed oscillator ready
    • [24]RMVF (def=0x0) // Remove reset flag
    • [26]PINRSTF (def=0x1) // PIN reset flag
    • [27]PORRSTF (def=0x1) // POR/PDR reset flag
    • [28]SFTRSTF (def=0x0) // Software reset flag
    • [29]IWDGRSTF (def=0x0) // Independent watchdog reset flag
    • [30]WWDGRSTF (def=0x0) // Window watchdog reset flag
    • [31]LPWRRSTF (def=0x0) // Low-power reset flag
  interrupts:
  • [5] RCC // RCC global interrupt
• 0x40010800GPIOA// General purpose I/O

  • 0x40010800CRL// Port configuration register low (GPIOn_CRL)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40010804CRH// Port configuration register high (GPIOn_CRL)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40010808IDR// Port input data register (GPIOn_IDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x4001080CODR// Port output data register (GPIOn_ODR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40010810BSRR// Port bit set/reset register (GPIOn_BSRR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40010814BRR// Port bit reset register (GPIOn_BRR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40010818LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40010C00GPIOB//

  • 0x40010C00CRL// Port configuration register low (GPIOn_CRL)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40010C04CRH// Port configuration register high (GPIOn_CRL)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40010C08IDR// Port input data register (GPIOn_IDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x40010C0CODR// Port output data register (GPIOn_ODR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40010C10BSRR// Port bit set/reset register (GPIOn_BSRR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40010C14BRR// Port bit reset register (GPIOn_BRR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40010C18LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40011000GPIOC//

  • 0x40011000CRL// Port configuration register low (GPIOn_CRL)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40011004CRH// Port configuration register high (GPIOn_CRL)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40011008IDR// Port input data register (GPIOn_IDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x4001100CODR// Port output data register (GPIOn_ODR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40011010BSRR// Port bit set/reset register (GPIOn_BSRR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40011014BRR// Port bit reset register (GPIOn_BRR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40011018LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40011400GPIOD//

  • 0x40011400CRL// Port configuration register low (GPIOn_CRL)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40011404CRH// Port configuration register high (GPIOn_CRL)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40011408IDR// Port input data register (GPIOn_IDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x4001140CODR// Port output data register (GPIOn_ODR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40011410BSRR// Port bit set/reset register (GPIOn_BSRR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40011414BRR// Port bit reset register (GPIOn_BRR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40011418LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40011800GPIOE//

  • 0x40011800CRL// Port configuration register low (GPIOn_CRL)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40011804CRH// Port configuration register high (GPIOn_CRL)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40011808IDR// Port input data register (GPIOn_IDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x4001180CODR// Port output data register (GPIOn_ODR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40011810BSRR// Port bit set/reset register (GPIOn_BSRR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40011814BRR// Port bit reset register (GPIOn_BRR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40011818LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40011C00GPIOF//

  • 0x40011C00CRL// Port configuration register low (GPIOn_CRL)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40011C04CRH// Port configuration register high (GPIOn_CRL)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40011C08IDR// Port input data register (GPIOn_IDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x40011C0CODR// Port output data register (GPIOn_ODR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40011C10BSRR// Port bit set/reset register (GPIOn_BSRR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40011C14BRR// Port bit reset register (GPIOn_BRR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40011C18LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40012000GPIOG//

  • 0x40012000CRL// Port configuration register low (GPIOn_CRL)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40012004CRH// Port configuration register high (GPIOn_CRL)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40012008IDR// Port input data register (GPIOn_IDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x4001200CODR// Port output data register (GPIOn_ODR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40012010BSRR// Port bit set/reset register (GPIOn_BSRR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40012014BRR// Port bit reset register (GPIOn_BRR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40012018LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40010000AFIO// Alternate function I/O

  • 0x40010000EVCR// Event Control Register (AFIO_EVCR)

    • [0:3]PIN (def=0x0) // Pin selection
    • [4:6]PORT (def=0x0) // Port selection
    • [7]EVOE (def=0x0) // Event Output Enable
  • 0x40010004MAPR// AF remap and debug I/O configuration register (AFIO_MAPR)

    • [0]SPI1_REMAP (def=0x0) // SPI1 remapping
    • [1]I2C1_REMAP (def=0x0) // I2C1 remapping
    • [2]USART1_REMAP (def=0x0) // USART1 remapping
    • [3]USART2_REMAP (def=0x0) // USART2 remapping
    • [4:5]USART3_REMAP (def=0x0) // USART3 remapping
    • [6:7]TIM1_REMAP (def=0x0) // TIM1 remapping
    • [8:9]TIM2_REMAP (def=0x0) // TIM2 remapping
    • [10:11]TIM3_REMAP (def=0x0) // TIM3 remapping
    • [12]TIM4_REMAP (def=0x0) // TIM4 remapping
    • [13:14]CAN_REMAP (def=0x0) // CAN1 remapping
    • [15]PD01_REMAP (def=0x0) // Port D0/Port D1 mapping on OSCIN/OSCOUT
    • [16]TIM5CH4_IREMAP (def=0x0) // Set and cleared by software
    • [17]ADC1_ETRGINJ_REMAP (def=0x0) // ADC 1 External trigger injected conversion remapping
    • [18]ADC1_ETRGREG_REMAP (def=0x0) // ADC 1 external trigger regular conversion remapping
    • [19]ADC2_ETRGINJ_REMAP (def=0x0) // ADC 2 external trigger injected conversion remapping
    • [20]ADC2_ETRGREG_REMAP (def=0x0) // ADC 2 external trigger regular conversion remapping
    • [24:26]SWJ_CFG (def=0x0) // Serial wire JTAG configuration
  • 0x40010008EXTICR1// External interrupt configuration register 1 (AFIO_EXTICR1)

    • [0:3]EXTI0 (def=0x0) // EXTI0 configuration
    • [4:7]EXTI1 (def=0x0) // EXTI1 configuration
    • [8:11]EXTI2 (def=0x0) // EXTI2 configuration
    • [12:15]EXTI3 (def=0x0) // EXTI3 configuration
  • 0x4001000CEXTICR2// External interrupt configuration register 2 (AFIO_EXTICR2)

    • [0:3]EXTI4 (def=0x0) // EXTI4 configuration
    • [4:7]EXTI5 (def=0x0) // EXTI5 configuration
    • [8:11]EXTI6 (def=0x0) // EXTI6 configuration
    • [12:15]EXTI7 (def=0x0) // EXTI7 configuration
  • 0x40010010EXTICR3// External interrupt configuration register 3 (AFIO_EXTICR3)

    • [0:3]EXTI8 (def=0x0) // EXTI8 configuration
    • [4:7]EXTI9 (def=0x0) // EXTI9 configuration
    • [8:11]EXTI10 (def=0x0) // EXTI10 configuration
    • [12:15]EXTI11 (def=0x0) // EXTI11 configuration
  • 0x40010014EXTICR4// External interrupt configuration register 4 (AFIO_EXTICR4)

    • [0:3]EXTI12 (def=0x0) // EXTI12 configuration
    • [4:7]EXTI13 (def=0x0) // EXTI13 configuration
    • [8:11]EXTI14 (def=0x0) // EXTI14 configuration
    • [12:15]EXTI15 (def=0x0) // EXTI15 configuration
  • 0x4001001CMAPR2// AF remap and debug I/O configuration register

    • [5]TIM9_REMAP (def=0x0) // TIM9 remapping
    • [6]TIM10_REMAP (def=0x0) // TIM10 remapping
    • [7]TIM11_REMAP (def=0x0) // TIM11 remapping
    • [8]TIM13_REMAP (def=0x0) // TIM13 remapping
    • [9]TIM14_REMAP (def=0x0) // TIM14 remapping
    • [10]FSMC_NADV (def=0x0) // NADV connect/disconnect
• 0x40010400EXTI// EXTI

  • 0x40010400IMR// Interrupt mask register (EXTI_IMR)

    • [0]MR0 (def=0x0) // Interrupt Mask on line 0
    • [1]MR1 (def=0x0) // Interrupt Mask on line 1
    • [2]MR2 (def=0x0) // Interrupt Mask on line 2
    • [3]MR3 (def=0x0) // Interrupt Mask on line 3
    • [4]MR4 (def=0x0) // Interrupt Mask on line 4
    • [5]MR5 (def=0x0) // Interrupt Mask on line 5
    • [6]MR6 (def=0x0) // Interrupt Mask on line 6
    • [7]MR7 (def=0x0) // Interrupt Mask on line 7
    • [8]MR8 (def=0x0) // Interrupt Mask on line 8
    • [9]MR9 (def=0x0) // Interrupt Mask on line 9
    • [10]MR10 (def=0x0) // Interrupt Mask on line 10
    • [11]MR11 (def=0x0) // Interrupt Mask on line 11
    • [12]MR12 (def=0x0) // Interrupt Mask on line 12
    • [13]MR13 (def=0x0) // Interrupt Mask on line 13
    • [14]MR14 (def=0x0) // Interrupt Mask on line 14
    • [15]MR15 (def=0x0) // Interrupt Mask on line 15
    • [16]MR16 (def=0x0) // Interrupt Mask on line 16
    • [17]MR17 (def=0x0) // Interrupt Mask on line 17
    • [18]MR18 (def=0x0) // Interrupt Mask on line 18
  • 0x40010404EMR// Event mask register (EXTI_EMR)

    • [0]MR0 (def=0x0) // Event Mask on line 0
    • [1]MR1 (def=0x0) // Event Mask on line 1
    • [2]MR2 (def=0x0) // Event Mask on line 2
    • [3]MR3 (def=0x0) // Event Mask on line 3
    • [4]MR4 (def=0x0) // Event Mask on line 4
    • [5]MR5 (def=0x0) // Event Mask on line 5
    • [6]MR6 (def=0x0) // Event Mask on line 6
    • [7]MR7 (def=0x0) // Event Mask on line 7
    • [8]MR8 (def=0x0) // Event Mask on line 8
    • [9]MR9 (def=0x0) // Event Mask on line 9
    • [10]MR10 (def=0x0) // Event Mask on line 10
    • [11]MR11 (def=0x0) // Event Mask on line 11
    • [12]MR12 (def=0x0) // Event Mask on line 12
    • [13]MR13 (def=0x0) // Event Mask on line 13
    • [14]MR14 (def=0x0) // Event Mask on line 14
    • [15]MR15 (def=0x0) // Event Mask on line 15
    • [16]MR16 (def=0x0) // Event Mask on line 16
    • [17]MR17 (def=0x0) // Event Mask on line 17
    • [18]MR18 (def=0x0) // Event Mask on line 18
  • 0x40010408RTSR// Rising Trigger selection register (EXTI_RTSR)

    • [0]TR0 (def=0x0) // Rising trigger event configuration of line 0
    • [1]TR1 (def=0x0) // Rising trigger event configuration of line 1
    • [2]TR2 (def=0x0) // Rising trigger event configuration of line 2
    • [3]TR3 (def=0x0) // Rising trigger event configuration of line 3
    • [4]TR4 (def=0x0) // Rising trigger event configuration of line 4
    • [5]TR5 (def=0x0) // Rising trigger event configuration of line 5
    • [6]TR6 (def=0x0) // Rising trigger event configuration of line 6
    • [7]TR7 (def=0x0) // Rising trigger event configuration of line 7
    • [8]TR8 (def=0x0) // Rising trigger event configuration of line 8
    • [9]TR9 (def=0x0) // Rising trigger event configuration of line 9
    • [10]TR10 (def=0x0) // Rising trigger event configuration of line 10
    • [11]TR11 (def=0x0) // Rising trigger event configuration of line 11
    • [12]TR12 (def=0x0) // Rising trigger event configuration of line 12
    • [13]TR13 (def=0x0) // Rising trigger event configuration of line 13
    • [14]TR14 (def=0x0) // Rising trigger event configuration of line 14
    • [15]TR15 (def=0x0) // Rising trigger event configuration of line 15
    • [16]TR16 (def=0x0) // Rising trigger event configuration of line 16
    • [17]TR17 (def=0x0) // Rising trigger event configuration of line 17
    • [18]TR18 (def=0x0) // Rising trigger event configuration of line 18
  • 0x4001040CFTSR// Falling Trigger selection register (EXTI_FTSR)

    • [0]TR0 (def=0x0) // Falling trigger event configuration of line 0
    • [1]TR1 (def=0x0) // Falling trigger event configuration of line 1
    • [2]TR2 (def=0x0) // Falling trigger event configuration of line 2
    • [3]TR3 (def=0x0) // Falling trigger event configuration of line 3
    • [4]TR4 (def=0x0) // Falling trigger event configuration of line 4
    • [5]TR5 (def=0x0) // Falling trigger event configuration of line 5
    • [6]TR6 (def=0x0) // Falling trigger event configuration of line 6
    • [7]TR7 (def=0x0) // Falling trigger event configuration of line 7
    • [8]TR8 (def=0x0) // Falling trigger event configuration of line 8
    • [9]TR9 (def=0x0) // Falling trigger event configuration of line 9
    • [10]TR10 (def=0x0) // Falling trigger event configuration of line 10
    • [11]TR11 (def=0x0) // Falling trigger event configuration of line 11
    • [12]TR12 (def=0x0) // Falling trigger event configuration of line 12
    • [13]TR13 (def=0x0) // Falling trigger event configuration of line 13
    • [14]TR14 (def=0x0) // Falling trigger event configuration of line 14
    • [15]TR15 (def=0x0) // Falling trigger event configuration of line 15
    • [16]TR16 (def=0x0) // Falling trigger event configuration of line 16
    • [17]TR17 (def=0x0) // Falling trigger event configuration of line 17
    • [18]TR18 (def=0x0) // Falling trigger event configuration of line 18
  • 0x40010410SWIER// Software interrupt event register (EXTI_SWIER)

    • [0]SWIER0 (def=0x0) // Software Interrupt on line 0
    • [1]SWIER1 (def=0x0) // Software Interrupt on line 1
    • [2]SWIER2 (def=0x0) // Software Interrupt on line 2
    • [3]SWIER3 (def=0x0) // Software Interrupt on line 3
    • [4]SWIER4 (def=0x0) // Software Interrupt on line 4
    • [5]SWIER5 (def=0x0) // Software Interrupt on line 5
    • [6]SWIER6 (def=0x0) // Software Interrupt on line 6
    • [7]SWIER7 (def=0x0) // Software Interrupt on line 7
    • [8]SWIER8 (def=0x0) // Software Interrupt on line 8
    • [9]SWIER9 (def=0x0) // Software Interrupt on line 9
    • [10]SWIER10 (def=0x0) // Software Interrupt on line 10
    • [11]SWIER11 (def=0x0) // Software Interrupt on line 11
    • [12]SWIER12 (def=0x0) // Software Interrupt on line 12
    • [13]SWIER13 (def=0x0) // Software Interrupt on line 13
    • [14]SWIER14 (def=0x0) // Software Interrupt on line 14
    • [15]SWIER15 (def=0x0) // Software Interrupt on line 15
    • [16]SWIER16 (def=0x0) // Software Interrupt on line 16
    • [17]SWIER17 (def=0x0) // Software Interrupt on line 17
    • [18]SWIER18 (def=0x0) // Software Interrupt on line 18
  • 0x40010414PR// Pending register (EXTI_PR)

    • [0]PR0 (def=0x0) // Pending bit 0
    • [1]PR1 (def=0x0) // Pending bit 1
    • [2]PR2 (def=0x0) // Pending bit 2
    • [3]PR3 (def=0x0) // Pending bit 3
    • [4]PR4 (def=0x0) // Pending bit 4
    • [5]PR5 (def=0x0) // Pending bit 5
    • [6]PR6 (def=0x0) // Pending bit 6
    • [7]PR7 (def=0x0) // Pending bit 7
    • [8]PR8 (def=0x0) // Pending bit 8
    • [9]PR9 (def=0x0) // Pending bit 9
    • [10]PR10 (def=0x0) // Pending bit 10
    • [11]PR11 (def=0x0) // Pending bit 11
    • [12]PR12 (def=0x0) // Pending bit 12
    • [13]PR13 (def=0x0) // Pending bit 13
    • [14]PR14 (def=0x0) // Pending bit 14
    • [15]PR15 (def=0x0) // Pending bit 15
    • [16]PR16 (def=0x0) // Pending bit 16
    • [17]PR17 (def=0x0) // Pending bit 17
    • [18]PR18 (def=0x0) // Pending bit 18
  interrupts:
  • [2] TAMPER // Tamper interrupt
  • [6] EXTI0 // EXTI Line0 interrupt
  • [7] EXTI1 // EXTI Line1 interrupt
  • [8] EXTI2 // EXTI Line2 interrupt
  • [9] EXTI3 // EXTI Line3 interrupt
  • [10] EXTI4 // EXTI Line4 interrupt
  • [23] EXTI9_5 // EXTI Line[9:5] interrupts
  • [40] EXTI15_10 // EXTI Line[15:10] interrupts
• 0x40020000DMA1// DMA controller

  • 0x40020000ISR// DMA interrupt status register (DMA_ISR)

    • [0]GIF1 (def=0x0) // Channel 1 Global interrupt flag
    • [1]TCIF1 (def=0x0) // Channel 1 Transfer Complete flag
    • [2]HTIF1 (def=0x0) // Channel 1 Half Transfer Complete flag
    • [3]TEIF1 (def=0x0) // Channel 1 Transfer Error flag
    • [4]GIF2 (def=0x0) // Channel 2 Global interrupt flag
    • [5]TCIF2 (def=0x0) // Channel 2 Transfer Complete flag
    • [6]HTIF2 (def=0x0) // Channel 2 Half Transfer Complete flag
    • [7]TEIF2 (def=0x0) // Channel 2 Transfer Error flag
    • [8]GIF3 (def=0x0) // Channel 3 Global interrupt flag
    • [9]TCIF3 (def=0x0) // Channel 3 Transfer Complete flag
    • [10]HTIF3 (def=0x0) // Channel 3 Half Transfer Complete flag
    • [11]TEIF3 (def=0x0) // Channel 3 Transfer Error flag
    • [12]GIF4 (def=0x0) // Channel 4 Global interrupt flag
    • [13]TCIF4 (def=0x0) // Channel 4 Transfer Complete flag
    • [14]HTIF4 (def=0x0) // Channel 4 Half Transfer Complete flag
    • [15]TEIF4 (def=0x0) // Channel 4 Transfer Error flag
    • [16]GIF5 (def=0x0) // Channel 5 Global interrupt flag
    • [17]TCIF5 (def=0x0) // Channel 5 Transfer Complete flag
    • [18]HTIF5 (def=0x0) // Channel 5 Half Transfer Complete flag
    • [19]TEIF5 (def=0x0) // Channel 5 Transfer Error flag
    • [20]GIF6 (def=0x0) // Channel 6 Global interrupt flag
    • [21]TCIF6 (def=0x0) // Channel 6 Transfer Complete flag
    • [22]HTIF6 (def=0x0) // Channel 6 Half Transfer Complete flag
    • [23]TEIF6 (def=0x0) // Channel 6 Transfer Error flag
    • [24]GIF7 (def=0x0) // Channel 7 Global interrupt flag
    • [25]TCIF7 (def=0x0) // Channel 7 Transfer Complete flag
    • [26]HTIF7 (def=0x0) // Channel 7 Half Transfer Complete flag
    • [27]TEIF7 (def=0x0) // Channel 7 Transfer Error flag
  • 0x40020004IFCR// DMA interrupt flag clear register (DMA_IFCR)

    • [0]CGIF1 (def=0x0) // Channel 1 Global interrupt clear
    • [4]CGIF2 (def=0x0) // Channel 2 Global interrupt clear
    • [8]CGIF3 (def=0x0) // Channel 3 Global interrupt clear
    • [12]CGIF4 (def=0x0) // Channel 4 Global interrupt clear
    • [16]CGIF5 (def=0x0) // Channel 5 Global interrupt clear
    • [20]CGIF6 (def=0x0) // Channel 6 Global interrupt clear
    • [24]CGIF7 (def=0x0) // Channel 7 Global interrupt clear
    • [1]CTCIF1 (def=0x0) // Channel 1 Transfer Complete clear
    • [5]CTCIF2 (def=0x0) // Channel 2 Transfer Complete clear
    • [9]CTCIF3 (def=0x0) // Channel 3 Transfer Complete clear
    • [13]CTCIF4 (def=0x0) // Channel 4 Transfer Complete clear
    • [17]CTCIF5 (def=0x0) // Channel 5 Transfer Complete clear
    • [21]CTCIF6 (def=0x0) // Channel 6 Transfer Complete clear
    • [25]CTCIF7 (def=0x0) // Channel 7 Transfer Complete clear
    • [2]CHTIF1 (def=0x0) // Channel 1 Half Transfer clear
    • [6]CHTIF2 (def=0x0) // Channel 2 Half Transfer clear
    • [10]CHTIF3 (def=0x0) // Channel 3 Half Transfer clear
    • [14]CHTIF4 (def=0x0) // Channel 4 Half Transfer clear
    • [18]CHTIF5 (def=0x0) // Channel 5 Half Transfer clear
    • [22]CHTIF6 (def=0x0) // Channel 6 Half Transfer clear
    • [26]CHTIF7 (def=0x0) // Channel 7 Half Transfer clear
    • [3]CTEIF1 (def=0x0) // Channel 1 Transfer Error clear
    • [7]CTEIF2 (def=0x0) // Channel 2 Transfer Error clear
    • [11]CTEIF3 (def=0x0) // Channel 3 Transfer Error clear
    • [15]CTEIF4 (def=0x0) // Channel 4 Transfer Error clear
    • [19]CTEIF5 (def=0x0) // Channel 5 Transfer Error clear
    • [23]CTEIF6 (def=0x0) // Channel 6 Transfer Error clear
    • [27]CTEIF7 (def=0x0) // Channel 7 Transfer Error clear
  • 0x40020008CCR1// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x4002000CCNDTR1// DMA channel 1 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020010CPAR1// DMA channel 1 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020014CMAR1// DMA channel 1 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002001CCCR2// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020020CNDTR2// DMA channel 2 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020024CPAR2// DMA channel 2 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020028CMAR2// DMA channel 2 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020030CCR3// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020034CNDTR3// DMA channel 3 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020038CPAR3// DMA channel 3 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x4002003CCMAR3// DMA channel 3 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020044CCR4// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020048CNDTR4// DMA channel 4 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x4002004CCPAR4// DMA channel 4 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020050CMAR4// DMA channel 4 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020058CCR5// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x4002005CCNDTR5// DMA channel 5 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020060CPAR5// DMA channel 5 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020064CMAR5// DMA channel 5 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002006CCCR6// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020070CNDTR6// DMA channel 6 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020074CPAR6// DMA channel 6 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020078CMAR6// DMA channel 6 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020080CCR7// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020084CNDTR7// DMA channel 7 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020088CPAR7// DMA channel 7 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x4002008CCMAR7// DMA channel 7 memory address register

    • [0:31]MA (def=0x0) // Memory address
  interrupts:
  • [11] DMA1_Channel1 // DMA1 Channel1 global interrupt
  • [12] DMA1_Channel2 // DMA1 Channel2 global interrupt
  • [13] DMA1_Channel3 // DMA1 Channel3 global interrupt
  • [14] DMA1_Channel4 // DMA1 Channel4 global interrupt
  • [15] DMA1_Channel5 // DMA1 Channel5 global interrupt
  • [16] DMA1_Channel6 // DMA1 Channel6 global interrupt
  • [17] DMA1_Channel7 // DMA1 Channel7 global interrupt
• 0x40020400DMA2//

  • 0x40020400ISR// DMA interrupt status register (DMA_ISR)

    • [0]GIF1 (def=0x0) // Channel 1 Global interrupt flag
    • [1]TCIF1 (def=0x0) // Channel 1 Transfer Complete flag
    • [2]HTIF1 (def=0x0) // Channel 1 Half Transfer Complete flag
    • [3]TEIF1 (def=0x0) // Channel 1 Transfer Error flag
    • [4]GIF2 (def=0x0) // Channel 2 Global interrupt flag
    • [5]TCIF2 (def=0x0) // Channel 2 Transfer Complete flag
    • [6]HTIF2 (def=0x0) // Channel 2 Half Transfer Complete flag
    • [7]TEIF2 (def=0x0) // Channel 2 Transfer Error flag
    • [8]GIF3 (def=0x0) // Channel 3 Global interrupt flag
    • [9]TCIF3 (def=0x0) // Channel 3 Transfer Complete flag
    • [10]HTIF3 (def=0x0) // Channel 3 Half Transfer Complete flag
    • [11]TEIF3 (def=0x0) // Channel 3 Transfer Error flag
    • [12]GIF4 (def=0x0) // Channel 4 Global interrupt flag
    • [13]TCIF4 (def=0x0) // Channel 4 Transfer Complete flag
    • [14]HTIF4 (def=0x0) // Channel 4 Half Transfer Complete flag
    • [15]TEIF4 (def=0x0) // Channel 4 Transfer Error flag
    • [16]GIF5 (def=0x0) // Channel 5 Global interrupt flag
    • [17]TCIF5 (def=0x0) // Channel 5 Transfer Complete flag
    • [18]HTIF5 (def=0x0) // Channel 5 Half Transfer Complete flag
    • [19]TEIF5 (def=0x0) // Channel 5 Transfer Error flag
    • [20]GIF6 (def=0x0) // Channel 6 Global interrupt flag
    • [21]TCIF6 (def=0x0) // Channel 6 Transfer Complete flag
    • [22]HTIF6 (def=0x0) // Channel 6 Half Transfer Complete flag
    • [23]TEIF6 (def=0x0) // Channel 6 Transfer Error flag
    • [24]GIF7 (def=0x0) // Channel 7 Global interrupt flag
    • [25]TCIF7 (def=0x0) // Channel 7 Transfer Complete flag
    • [26]HTIF7 (def=0x0) // Channel 7 Half Transfer Complete flag
    • [27]TEIF7 (def=0x0) // Channel 7 Transfer Error flag
  • 0x40020404IFCR// DMA interrupt flag clear register (DMA_IFCR)

    • [0]CGIF1 (def=0x0) // Channel 1 Global interrupt clear
    • [4]CGIF2 (def=0x0) // Channel 2 Global interrupt clear
    • [8]CGIF3 (def=0x0) // Channel 3 Global interrupt clear
    • [12]CGIF4 (def=0x0) // Channel 4 Global interrupt clear
    • [16]CGIF5 (def=0x0) // Channel 5 Global interrupt clear
    • [20]CGIF6 (def=0x0) // Channel 6 Global interrupt clear
    • [24]CGIF7 (def=0x0) // Channel 7 Global interrupt clear
    • [1]CTCIF1 (def=0x0) // Channel 1 Transfer Complete clear
    • [5]CTCIF2 (def=0x0) // Channel 2 Transfer Complete clear
    • [9]CTCIF3 (def=0x0) // Channel 3 Transfer Complete clear
    • [13]CTCIF4 (def=0x0) // Channel 4 Transfer Complete clear
    • [17]CTCIF5 (def=0x0) // Channel 5 Transfer Complete clear
    • [21]CTCIF6 (def=0x0) // Channel 6 Transfer Complete clear
    • [25]CTCIF7 (def=0x0) // Channel 7 Transfer Complete clear
    • [2]CHTIF1 (def=0x0) // Channel 1 Half Transfer clear
    • [6]CHTIF2 (def=0x0) // Channel 2 Half Transfer clear
    • [10]CHTIF3 (def=0x0) // Channel 3 Half Transfer clear
    • [14]CHTIF4 (def=0x0) // Channel 4 Half Transfer clear
    • [18]CHTIF5 (def=0x0) // Channel 5 Half Transfer clear
    • [22]CHTIF6 (def=0x0) // Channel 6 Half Transfer clear
    • [26]CHTIF7 (def=0x0) // Channel 7 Half Transfer clear
    • [3]CTEIF1 (def=0x0) // Channel 1 Transfer Error clear
    • [7]CTEIF2 (def=0x0) // Channel 2 Transfer Error clear
    • [11]CTEIF3 (def=0x0) // Channel 3 Transfer Error clear
    • [15]CTEIF4 (def=0x0) // Channel 4 Transfer Error clear
    • [19]CTEIF5 (def=0x0) // Channel 5 Transfer Error clear
    • [23]CTEIF6 (def=0x0) // Channel 6 Transfer Error clear
    • [27]CTEIF7 (def=0x0) // Channel 7 Transfer Error clear
  • 0x40020408CCR1// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x4002040CCNDTR1// DMA channel 1 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020410CPAR1// DMA channel 1 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020414CMAR1// DMA channel 1 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002041CCCR2// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020420CNDTR2// DMA channel 2 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020424CPAR2// DMA channel 2 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020428CMAR2// DMA channel 2 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020430CCR3// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020434CNDTR3// DMA channel 3 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020438CPAR3// DMA channel 3 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x4002043CCMAR3// DMA channel 3 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020444CCR4// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020448CNDTR4// DMA channel 4 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x4002044CCPAR4// DMA channel 4 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020450CMAR4// DMA channel 4 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020458CCR5// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x4002045CCNDTR5// DMA channel 5 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020460CPAR5// DMA channel 5 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020464CMAR5// DMA channel 5 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002046CCCR6// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020470CNDTR6// DMA channel 6 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020474CPAR6// DMA channel 6 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020478CMAR6// DMA channel 6 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020480CCR7// DMA channel configuration register (DMA_CCR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020484CNDTR7// DMA channel 7 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020488CPAR7// DMA channel 7 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x4002048CCMAR7// DMA channel 7 memory address register

    • [0:31]MA (def=0x0) // Memory address
  interrupts:
  • [56] DMA2_Channel1 // DMA2 Channel1 global interrupt
  • [57] DMA2_Channel2 // DMA2 Channel2 global interrupt
  • [58] DMA2_Channel3 // DMA2 Channel3 global interrupt
  • [59] DMA2_Channel4_5 // DMA2 Channel4 and DMA2 Channel5 global interrupt
• 0x40018000SDIO// Secure digital input/output interface

  • 0x40018000POWER// Bits 1:0 = PWRCTRL: Power supply control bits

    • [0:1]PWRCTRL (def=0x0) // PWRCTRL
  • 0x40018004CLKCR// SDI clock control register (SDIO_CLKCR)

    • [0:7]CLKDIV (def=0x0) // Clock divide factor
    • [8]CLKEN (def=0x0) // Clock enable bit
    • [9]PWRSAV (def=0x0) // Power saving configuration bit
    • [10]BYPASS (def=0x0) // Clock divider bypass enable bit
    • [11:12]WIDBUS (def=0x0) // Wide bus mode enable bit
    • [13]NEGEDGE (def=0x0) // SDIO_CK dephasing selection bit
    • [14]HWFC_EN (def=0x0) // HW Flow Control enable
  • 0x40018008ARG// Bits 31:0 = : Command argument

    • [0:31]CMDARG (def=0x0) // Command argument
  • 0x4001800CCMD// SDIO command register (SDIO_CMD)

    • [0:5]CMDINDEX (def=0x0) // CMDINDEX
    • [6:7]WAITRESP (def=0x0) // WAITRESP
    • [8]WAITINT (def=0x0) // WAITINT
    • [9]WAITPEND (def=0x0) // WAITPEND
    • [10]CPSMEN (def=0x0) // CPSMEN
    • [11]SDIOSuspend (def=0x0) // SDIOSuspend
    • [12]ENCMDcompl (def=0x0) // ENCMDcompl
    • [13]nIEN (def=0x0) // nIEN
    • [14]CE_ATACMD (def=0x0) // CE_ATACMD
  • 0x40018010RESPCMD// SDIO command register

    • [0:5]RESPCMD (def=0x0) // RESPCMD
  • 0x40018014RESPI1// Bits 31:0 = CARDSTATUS1

    • [0:31]CARDSTATUS1 (def=0x0) // CARDSTATUS1
  • 0x40018018RESP2// Bits 31:0 = CARDSTATUS2

    • [0:31]CARDSTATUS2 (def=0x0) // CARDSTATUS2
  • 0x4001801CRESP3// Bits 31:0 = CARDSTATUS3

    • [0:31]CARDSTATUS3 (def=0x0) // CARDSTATUS3
  • 0x40018020RESP4// Bits 31:0 = CARDSTATUS4

    • [0:31]CARDSTATUS4 (def=0x0) // CARDSTATUS4
  • 0x40018024DTIMER// Bits 31:0 = DATATIME: Data timeout period

    • [0:31]DATATIME (def=0x0) // Data timeout period
  • 0x40018028DLEN// Bits 24:0 = DATALENGTH: Data length value

    • [0:24]DATALENGTH (def=0x0) // Data length value
  • 0x4001802CDCTRL// SDIO data control register (SDIO_DCTRL)

    • [0]DTEN (def=0x0) // DTEN
    • [1]DTDIR (def=0x0) // DTDIR
    • [2]DTMODE (def=0x0) // DTMODE
    • [3]DMAEN (def=0x0) // DMAEN
    • [4:7]DBLOCKSIZE (def=0x0) // DBLOCKSIZE
    • [8]PWSTART (def=0x0) // PWSTART
    • [9]PWSTOP (def=0x0) // PWSTOP
    • [10]RWMOD (def=0x0) // RWMOD
    • [11]SDIOEN (def=0x0) // SDIOEN
  • 0x40018030DCOUNT// Bits 24:0 = DATACOUNT: Data count value

    • [0:24]DATACOUNT (def=0x0) // Data count value
  • 0x40018034STA// SDIO status register (SDIO_STA)

    • [0]CCRCFAIL (def=0x0) // CCRCFAIL
    • [1]DCRCFAIL (def=0x0) // DCRCFAIL
    • [2]CTIMEOUT (def=0x0) // CTIMEOUT
    • [3]DTIMEOUT (def=0x0) // DTIMEOUT
    • [4]TXUNDERR (def=0x0) // TXUNDERR
    • [5]RXOVERR (def=0x0) // RXOVERR
    • [6]CMDREND (def=0x0) // CMDREND
    • [7]CMDSENT (def=0x0) // CMDSENT
    • [8]DATAEND (def=0x0) // DATAEND
    • [9]STBITERR (def=0x0) // STBITERR
    • [10]DBCKEND (def=0x0) // DBCKEND
    • [11]CMDACT (def=0x0) // CMDACT
    • [12]TXACT (def=0x0) // TXACT
    • [13]RXACT (def=0x0) // RXACT
    • [14]TXFIFOHE (def=0x0) // TXFIFOHE
    • [15]RXFIFOHF (def=0x0) // RXFIFOHF
    • [16]TXFIFOF (def=0x0) // TXFIFOF
    • [17]RXFIFOF (def=0x0) // RXFIFOF
    • [18]TXFIFOE (def=0x0) // TXFIFOE
    • [19]RXFIFOE (def=0x0) // RXFIFOE
    • [20]TXDAVL (def=0x0) // TXDAVL
    • [21]RXDAVL (def=0x0) // RXDAVL
    • [22]SDIOIT (def=0x0) // SDIOIT
    • [23]CEATAEND (def=0x0) // CEATAEND
  • 0x40018038ICR// SDIO interrupt clear register (SDIO_ICR)

    • [0]CCRCFAILC (def=0x0) // CCRCFAILC
    • [1]DCRCFAILC (def=0x0) // DCRCFAILC
    • [2]CTIMEOUTC (def=0x0) // CTIMEOUTC
    • [3]DTIMEOUTC (def=0x0) // DTIMEOUTC
    • [4]TXUNDERRC (def=0x0) // TXUNDERRC
    • [5]RXOVERRC (def=0x0) // RXOVERRC
    • [6]CMDRENDC (def=0x0) // CMDRENDC
    • [7]CMDSENTC (def=0x0) // CMDSENTC
    • [8]DATAENDC (def=0x0) // DATAENDC
    • [9]STBITERRC (def=0x0) // STBITERRC
    • [10]DBCKENDC (def=0x0) // DBCKENDC
    • [22]SDIOITC (def=0x0) // SDIOITC
    • [23]CEATAENDC (def=0x0) // CEATAENDC
  • 0x4001803CMASK// SDIO mask register (SDIO_MASK)

    • [0]CCRCFAILIE (def=0x0) // CCRCFAILIE
    • [1]DCRCFAILIE (def=0x0) // DCRCFAILIE
    • [2]CTIMEOUTIE (def=0x0) // CTIMEOUTIE
    • [3]DTIMEOUTIE (def=0x0) // DTIMEOUTIE
    • [4]TXUNDERRIE (def=0x0) // TXUNDERRIE
    • [5]RXOVERRIE (def=0x0) // RXOVERRIE
    • [6]CMDRENDIE (def=0x0) // CMDRENDIE
    • [7]CMDSENTIE (def=0x0) // CMDSENTIE
    • [8]DATAENDIE (def=0x0) // DATAENDIE
    • [9]STBITERRIE (def=0x0) // STBITERRIE
    • [10]DBACKENDIE (def=0x0) // DBACKENDIE
    • [11]CMDACTIE (def=0x0) // CMDACTIE
    • [12]TXACTIE (def=0x0) // TXACTIE
    • [13]RXACTIE (def=0x0) // RXACTIE
    • [14]TXFIFOHEIE (def=0x0) // TXFIFOHEIE
    • [15]RXFIFOHFIE (def=0x0) // RXFIFOHFIE
    • [16]TXFIFOFIE (def=0x0) // TXFIFOFIE
    • [17]RXFIFOFIE (def=0x0) // RXFIFOFIE
    • [18]TXFIFOEIE (def=0x0) // TXFIFOEIE
    • [19]RXFIFOEIE (def=0x0) // RXFIFOEIE
    • [20]TXDAVLIE (def=0x0) // TXDAVLIE
    • [21]RXDAVLIE (def=0x0) // RXDAVLIE
    • [22]SDIOITIE (def=0x0) // SDIOITIE
    • [23]CEATENDIE (def=0x0) // CEATENDIE
  • 0x40018048FIFOCNT// Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the

    • [0:23]FIF0COUNT (def=0x0) // FIF0COUNT
  • 0x40018080FIFO// bits 31:0 = FIFOData: Receive and transmit FIFO data

    • [0:31]FIFOData (def=0x0) // FIFOData
  interrupts:
  • [49] SDIO // SDIO global interrupt
• 0x40002800RTC// Real time clock

  • 0x40002800CRH// RTC Control Register High

    • [0]SECIE (def=0x0) // Second interrupt Enable
    • [1]ALRIE (def=0x0) // Alarm interrupt Enable
    • [2]OWIE (def=0x0) // Overflow interrupt Enable
  • 0x40002804CRL// RTC Control Register Low

    • [0]SECF (def=0x0) // Second Flag
    • [1]ALRF (def=0x0) // Alarm Flag
    • [2]OWF (def=0x0) // Overflow Flag
    • [3]RSF (def=0x0) // Registers Synchronized Flag
    • [4]CNF (def=0x0) // Configuration Flag
    • [5]RTOFF (def=0x1) // RTC operation OFF
  • 0x40002808PRLH// RTC Prescaler Load Register High

    • [0:3]PRLH (def=0x0) // RTC Prescaler Load Register High
  • 0x4000280CPRLL// RTC Prescaler Load Register Low

    • [0:15]PRLL (def=0x8000) // RTC Prescaler Divider Register Low
  • 0x40002810DIVH// RTC Prescaler Divider Register High

    • [0:3]DIVH (def=0x0) // RTC prescaler divider register high
  • 0x40002814DIVL// RTC Prescaler Divider Register Low

    • [0:15]DIVL (def=0x8000) // RTC prescaler divider register Low
  • 0x40002818CNTH// RTC Counter Register High

    • [0:15]CNTH (def=0x0) // RTC counter register high
  • 0x4000281CCNTL// RTC Counter Register Low

    • [0:15]CNTL (def=0x0) // RTC counter register Low
  • 0x40002820ALRH// RTC Alarm Register High

    • [0:15]ALRH (def=0xFFFF) // RTC alarm register high
  • 0x40002824ALRL// RTC Alarm Register Low

    • [0:15]ALRL (def=0xFFFF) // RTC alarm register low
  interrupts:
  • [3] RTC // RTC global interrupt
  • [41] RTCAlarm // RTC Alarms through EXTI line interrupt
• 0x40006C00BKP// Backup registers

  • 0x40006C00DR1// Backup data register (BKP_DR)

    • [0:15]D1 (def=0x0) // Backup data
  • 0x40006C04DR2// Backup data register (BKP_DR)

    • [0:15]D2 (def=0x0) // Backup data
  • 0x40006C08DR3// Backup data register (BKP_DR)

    • [0:15]D3 (def=0x0) // Backup data
  • 0x40006C0CDR4// Backup data register (BKP_DR)

    • [0:15]D4 (def=0x0) // Backup data
  • 0x40006C10DR5// Backup data register (BKP_DR)

    • [0:15]D5 (def=0x0) // Backup data
  • 0x40006C14DR6// Backup data register (BKP_DR)

    • [0:15]D6 (def=0x0) // Backup data
  • 0x40006C18DR7// Backup data register (BKP_DR)

    • [0:15]D7 (def=0x0) // Backup data
  • 0x40006C1CDR8// Backup data register (BKP_DR)

    • [0:15]D8 (def=0x0) // Backup data
  • 0x40006C20DR9// Backup data register (BKP_DR)

    • [0:15]D9 (def=0x0) // Backup data
  • 0x40006C24DR10// Backup data register (BKP_DR)

    • [0:15]D10 (def=0x0) // Backup data
  • 0x40006C3CDR11// Backup data register (BKP_DR)

    • [0:15]DR11 (def=0x0) // Backup data
  • 0x40006C40DR12// Backup data register (BKP_DR)

    • [0:15]DR12 (def=0x0) // Backup data
  • 0x40006C44DR13// Backup data register (BKP_DR)

    • [0:15]DR13 (def=0x0) // Backup data
  • 0x40006C48DR14// Backup data register (BKP_DR)

    • [0:15]D14 (def=0x0) // Backup data
  • 0x40006C4CDR15// Backup data register (BKP_DR)

    • [0:15]D15 (def=0x0) // Backup data
  • 0x40006C50DR16// Backup data register (BKP_DR)

    • [0:15]D16 (def=0x0) // Backup data
  • 0x40006C54DR17// Backup data register (BKP_DR)

    • [0:15]D17 (def=0x0) // Backup data
  • 0x40006C58DR18// Backup data register (BKP_DR)

    • [0:15]D18 (def=0x0) // Backup data
  • 0x40006C5CDR19// Backup data register (BKP_DR)

    • [0:15]D19 (def=0x0) // Backup data
  • 0x40006C60DR20// Backup data register (BKP_DR)

    • [0:15]D20 (def=0x0) // Backup data
  • 0x40006C64DR21// Backup data register (BKP_DR)

    • [0:15]D21 (def=0x0) // Backup data
  • 0x40006C68DR22// Backup data register (BKP_DR)

    • [0:15]D22 (def=0x0) // Backup data
  • 0x40006C6CDR23// Backup data register (BKP_DR)

    • [0:15]D23 (def=0x0) // Backup data
  • 0x40006C70DR24// Backup data register (BKP_DR)

    • [0:15]D24 (def=0x0) // Backup data
  • 0x40006C74DR25// Backup data register (BKP_DR)

    • [0:15]D25 (def=0x0) // Backup data
  • 0x40006C78DR26// Backup data register (BKP_DR)

    • [0:15]D26 (def=0x0) // Backup data
  • 0x40006C7CDR27// Backup data register (BKP_DR)

    • [0:15]D27 (def=0x0) // Backup data
  • 0x40006C80DR28// Backup data register (BKP_DR)

    • [0:15]D28 (def=0x0) // Backup data
  • 0x40006C84DR29// Backup data register (BKP_DR)

    • [0:15]D29 (def=0x0) // Backup data
  • 0x40006C88DR30// Backup data register (BKP_DR)

    • [0:15]D30 (def=0x0) // Backup data
  • 0x40006C8CDR31// Backup data register (BKP_DR)

    • [0:15]D31 (def=0x0) // Backup data
  • 0x40006C90DR32// Backup data register (BKP_DR)

    • [0:15]D32 (def=0x0) // Backup data
  • 0x40006C94DR33// Backup data register (BKP_DR)

    • [0:15]D33 (def=0x0) // Backup data
  • 0x40006C98DR34// Backup data register (BKP_DR)

    • [0:15]D34 (def=0x0) // Backup data
  • 0x40006C9CDR35// Backup data register (BKP_DR)

    • [0:15]D35 (def=0x0) // Backup data
  • 0x40006CA0DR36// Backup data register (BKP_DR)

    • [0:15]D36 (def=0x0) // Backup data
  • 0x40006CA4DR37// Backup data register (BKP_DR)

    • [0:15]D37 (def=0x0) // Backup data
  • 0x40006CA8DR38// Backup data register (BKP_DR)

    • [0:15]D38 (def=0x0) // Backup data
  • 0x40006CACDR39// Backup data register (BKP_DR)

    • [0:15]D39 (def=0x0) // Backup data
  • 0x40006CB0DR40// Backup data register (BKP_DR)

    • [0:15]D40 (def=0x0) // Backup data
  • 0x40006CB4DR41// Backup data register (BKP_DR)

    • [0:15]D41 (def=0x0) // Backup data
  • 0x40006CB8DR42// Backup data register (BKP_DR)

    • [0:15]D42 (def=0x0) // Backup data
  • 0x40006C28RTCCR// RTC clock calibration register (BKP_RTCCR)

    • [0:6]CAL (def=0x0) // Calibration value
    • [7]CCO (def=0x0) // Calibration Clock Output
    • [8]ASOE (def=0x0) // Alarm or second output enable
    • [9]ASOS (def=0x0) // Alarm or second output selection
  • 0x40006C2CCR// Backup control register (BKP_CR)

    • [0]TPE (def=0x0) // Tamper pin enable
    • [1]TPAL (def=0x0) // Tamper pin active level
  • 0x40006C30CSR// BKP_CSR control/status register (BKP_CSR)

    • [0]CTE (def=0x0) // Clear Tamper event
    • [1]CTI (def=0x0) // Clear Tamper Interrupt
    • [2]TPIE (def=0x0) // Tamper Pin interrupt enable
    • [8]TEF (def=0x0) // Tamper Event Flag
    • [9]TIF (def=0x0) // Tamper Interrupt Flag
• 0x40003000IWDG// Independent watchdog

  • 0x40003000KR// Key register (IWDG_KR)

    • [0:15]KEY (def=0x0) // Key value
  • 0x40003004PR// Prescaler register (IWDG_PR)

    • [0:2]PR (def=0x0) // Prescaler divider
  • 0x40003008RLR// Reload register (IWDG_RLR)

    • [0:11]RL (def=0xFFF) // Watchdog counter reload value
  • 0x4000300CSR// Status register (IWDG_SR)

    • [0]PVU (def=0x0) // Watchdog prescaler value update
    • [1]RVU (def=0x0) // Watchdog counter reload value update
• 0x40002C00WWDG// Window watchdog

  • 0x40002C00CR// Control register (WWDG_CR)

    • [0:6]T (def=0x7F) // 7-bit counter (MSB to LSB)
    • [7]WDGA (def=0x0) // Activation bit
  • 0x40002C04CFR// Configuration register (WWDG_CFR)

    • [0:6]W (def=0x7F) // 7-bit window value
    • [7:8]WDGTB (def=0x0) // Timer Base
    • [9]EWI (def=0x0) // Early Wakeup Interrupt
  • 0x40002C08SR// Status register (WWDG_SR)

    • [0]EWI (def=0x0) // Early Wakeup Interrupt
  interrupts:
  • [0] WWDG // Window Watchdog interrupt
• 0x40012C00TIM1// Advanced timer

  • 0x40012C00CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40012C04CR2// control register 2

    • [14]OIS4 (def=0x0) // Output Idle state 4
    • [13]OIS3N (def=0x0) // Output Idle state 3
    • [12]OIS3 (def=0x0) // Output Idle state 3
    • [11]OIS2N (def=0x0) // Output Idle state 2
    • [10]OIS2 (def=0x0) // Output Idle state 2
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x40012C08SMCR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x40012C0CDIER// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
  • 0x40012C10SR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [7]BIF (def=0x0) // Break interrupt flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40012C14EGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [6]TG (def=0x0) // Trigger generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40012C18CCMR1_Output// capture/compare mode register (output mode)

    • [15]OC2CE (def=0x0) // Output Compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40012C18CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PCS (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]ICPCS (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40012C1CCCMR2_Output// capture/compare mode register (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40012C1CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/compare 3 selection
  • 0x40012C20CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [10]CC3NE (def=0x0) // Capture/Compare 3 complementary output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [6]CC2NE (def=0x0) // Capture/Compare 2 complementary output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40012C24CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40012C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x40012C2CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40012C34CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40012C38CCR2// capture/compare register 2

    • [0:15]CCR2 (def=0x0) // Capture/Compare 2 value
  • 0x40012C3CCCR3// capture/compare register 3

    • [0:15]CCR3 (def=0x0) // Capture/Compare value
  • 0x40012C40CCR4// capture/compare register 4

    • [0:15]CCR4 (def=0x0) // Capture/Compare value
  • 0x40012C48DCR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x40012C4CDMAR// DMA address for full transfer

    • [0:15]DMAB (def=0x0) // DMA register for burst accesses
  • 0x40012C30RCR// repetition counter register

    • [0:7]REP (def=0x0) // Repetition counter value
  • 0x40012C44BDTR// break and dead-time register

    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  interrupts:
  • [24] TIM1_BRK // TIM1 Break interrupt
  • [27] TIM1_CC // TIM1 Capture Compare interrupt
• 0x40013400TIM8//

  • 0x40013400CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40013404CR2// control register 2

    • [14]OIS4 (def=0x0) // Output Idle state 4
    • [13]OIS3N (def=0x0) // Output Idle state 3
    • [12]OIS3 (def=0x0) // Output Idle state 3
    • [11]OIS2N (def=0x0) // Output Idle state 2
    • [10]OIS2 (def=0x0) // Output Idle state 2
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x40013408SMCR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4001340CDIER// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
  • 0x40013410SR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [7]BIF (def=0x0) // Break interrupt flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40013414EGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [6]TG (def=0x0) // Trigger generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40013418CCMR1_Output// capture/compare mode register (output mode)

    • [15]OC2CE (def=0x0) // Output Compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40013418CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PCS (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]ICPCS (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4001341CCCMR2_Output// capture/compare mode register (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4001341CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/compare 3 selection
  • 0x40013420CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [10]CC3NE (def=0x0) // Capture/Compare 3 complementary output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [6]CC2NE (def=0x0) // Capture/Compare 2 complementary output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40013424CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40013428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4001342CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40013434CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40013438CCR2// capture/compare register 2

    • [0:15]CCR2 (def=0x0) // Capture/Compare 2 value
  • 0x4001343CCCR3// capture/compare register 3

    • [0:15]CCR3 (def=0x0) // Capture/Compare value
  • 0x40013440CCR4// capture/compare register 4

    • [0:15]CCR4 (def=0x0) // Capture/Compare value
  • 0x40013448DCR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4001344CDMAR// DMA address for full transfer

    • [0:15]DMAB (def=0x0) // DMA register for burst accesses
  • 0x40013430RCR// repetition counter register

    • [0:7]REP (def=0x0) // Repetition counter value
  • 0x40013444BDTR// break and dead-time register

    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  interrupts:
  • [43] TIM8_BRK // TIM8 Break interrupt
  • [44] TIM8_UP // TIM8 Update interrupt
  • [45] TIM8_TRG_COM // TIM8 Trigger and Commutation interrupts
  • [46] TIM8_CC // TIM8 Capture Compare interrupt
• 0x40000000TIM2// General purpose timer

  • 0x40000000CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000004CR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x40000008SMCR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000000CDIER// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000010SR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000014EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000018CCMR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000018CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4000001CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [15]O24CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4000001CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000020CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000024CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40000028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000002CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40000034CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40000038CCR2// capture/compare register 2

    • [0:15]CCR2 (def=0x0) // Capture/Compare 2 value
  • 0x4000003CCCR3// capture/compare register 3

    • [0:15]CCR3 (def=0x0) // Capture/Compare value
  • 0x40000040CCR4// capture/compare register 4

    • [0:15]CCR4 (def=0x0) // Capture/Compare value
  • 0x40000048DCR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4000004CDMAR// DMA address for full transfer

    • [0:15]DMAB (def=0x0) // DMA register for burst accesses
  interrupts:
  • [28] TIM2 // TIM2 global interrupt
• 0x40000400TIM3//

  • 0x40000400CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000404CR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x40000408SMCR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000040CDIER// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000410SR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000414EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000418CCMR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000418CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4000041CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [15]O24CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4000041CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000420CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000424CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40000428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000042CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40000434CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40000438CCR2// capture/compare register 2

    • [0:15]CCR2 (def=0x0) // Capture/Compare 2 value
  • 0x4000043CCCR3// capture/compare register 3

    • [0:15]CCR3 (def=0x0) // Capture/Compare value
  • 0x40000440CCR4// capture/compare register 4

    • [0:15]CCR4 (def=0x0) // Capture/Compare value
  • 0x40000448DCR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4000044CDMAR// DMA address for full transfer

    • [0:15]DMAB (def=0x0) // DMA register for burst accesses
  interrupts:
  • [29] TIM3 // TIM3 global interrupt
• 0x40000800TIM4//

  • 0x40000800CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000804CR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x40000808SMCR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000080CDIER// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000810SR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000814EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000818CCMR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000818CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4000081CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [15]O24CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4000081CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000820CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000824CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40000828PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000082CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40000834CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40000838CCR2// capture/compare register 2

    • [0:15]CCR2 (def=0x0) // Capture/Compare 2 value
  • 0x4000083CCCR3// capture/compare register 3

    • [0:15]CCR3 (def=0x0) // Capture/Compare value
  • 0x40000840CCR4// capture/compare register 4

    • [0:15]CCR4 (def=0x0) // Capture/Compare value
  • 0x40000848DCR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4000084CDMAR// DMA address for full transfer

    • [0:15]DMAB (def=0x0) // DMA register for burst accesses
  interrupts:
  • [30] TIM4 // TIM4 global interrupt
• 0x40000C00TIM5//

  • 0x40000C00CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000C04CR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
  • 0x40000C08SMCR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x40000C0CDIER// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000C10SR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000C14EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000C18CCMR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000C18CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000C1CCCMR2_Output// capture/compare mode register 2 (output mode)

    • [15]O24CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000C1CCCMR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000C20CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000C24CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40000C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x40000C2CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40000C34CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40000C38CCR2// capture/compare register 2

    • [0:15]CCR2 (def=0x0) // Capture/Compare 2 value
  • 0x40000C3CCCR3// capture/compare register 3

    • [0:15]CCR3 (def=0x0) // Capture/Compare value
  • 0x40000C40CCR4// capture/compare register 4

    • [0:15]CCR4 (def=0x0) // Capture/Compare value
  • 0x40000C48DCR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x40000C4CDMAR// DMA address for full transfer

    • [0:15]DMAB (def=0x0) // DMA register for burst accesses
  interrupts:
  • [50] TIM5 // TIM5 global interrupt
• 0x40014C00TIM9// General purpose timer

  • 0x40014C00CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40014C04CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x40014C08SMCR// slave mode control register

    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x40014C0CDIER// DMA/Interrupt enable register

    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40014C10SR// status register

    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40014C14EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40014C18CCMR1_Output// capture/compare mode register 1 (output mode)

    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014C18CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014C20CCER// capture/compare enable register

    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40014C24CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40014C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x40014C2CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40014C34CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40014C38CCR2// capture/compare register 2

    • [0:15]CCR2 (def=0x0) // Capture/Compare 2 value
• 0x40001800TIM12//

  • 0x40001800CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40001804CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x40001808SMCR// slave mode control register

    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000180CDIER// DMA/Interrupt enable register

    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40001810SR// status register

    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40001814EGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40001818CCMR1_Output// capture/compare mode register 1 (output mode)

    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40001818CCMR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40001820CCER// capture/compare enable register

    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40001824CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40001828PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000182CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40001834CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  • 0x40001838CCR2// capture/compare register 2

    • [0:15]CCR2 (def=0x0) // Capture/Compare 2 value
• 0x40015000TIM10// General purpose timer

  • 0x40015000CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40015004CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x4001500CDIER// DMA/Interrupt enable register

    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40015010SR// status register

    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40015014EGR// event generation register

    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40015018CCMR1_Output// capture/compare mode register (output mode)

    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40015018CCMR1_Input// capture/compare mode register (input mode)

    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40015020CCER// capture/compare enable register

    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40015024CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40015028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4001502CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40015034CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  interrupts:
  • [25] TIM1_UP // TIM1 Update interrupt
• 0x40015400TIM11//

  • 0x40015400CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40015404CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x4001540CDIER// DMA/Interrupt enable register

    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40015410SR// status register

    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40015414EGR// event generation register

    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40015418CCMR1_Output// capture/compare mode register (output mode)

    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40015418CCMR1_Input// capture/compare mode register (input mode)

    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40015420CCER// capture/compare enable register

    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40015424CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40015428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4001542CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40015434CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
  interrupts:
  • [26] TIM1_TRG_COM // TIM1 Trigger and Commutation interrupts
• 0x40001C00TIM13//

  • 0x40001C00CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40001C04CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x40001C0CDIER// DMA/Interrupt enable register

    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40001C10SR// status register

    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40001C14EGR// event generation register

    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40001C18CCMR1_Output// capture/compare mode register (output mode)

    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40001C18CCMR1_Input// capture/compare mode register (input mode)

    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40001C20CCER// capture/compare enable register

    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40001C24CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40001C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x40001C2CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40001C34CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
• 0x40002000TIM14//

  • 0x40002000CR1// control register 1

    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40002004CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x4000200CDIER// DMA/Interrupt enable register

    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40002010SR// status register

    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40002014EGR// event generation register

    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40002018CCMR1_Output// capture/compare mode register (output mode)

    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40002018CCMR1_Input// capture/compare mode register (input mode)

    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40002020CCER// capture/compare enable register

    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40002024CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40002028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000202CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Auto-reload value
  • 0x40002034CCR1// capture/compare register 1

    • [0:15]CCR1 (def=0x0) // Capture/Compare 1 value
• 0x40001000TIM6// Basic timer

  • 0x40001000CR1// control register 1

    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40001004CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x4000100CDIER// DMA/Interrupt enable register

    • [8]UDE (def=0x0) // Update DMA request enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40001010SR// status register

    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40001014EGR// event generation register

    • [0]UG (def=0x0) // Update generation
  • 0x40001024CNT// counter

    • [0:15]CNT (def=0x0) // Low counter value
  • 0x40001028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000102CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Low Auto-reload value
  interrupts:
  • [54] TIM6 // TIM6 global interrupt
• 0x40001400TIM7//

  • 0x40001400CR1// control register 1

    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40001404CR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x4000140CDIER// DMA/Interrupt enable register

    • [8]UDE (def=0x0) // Update DMA request enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40001410SR// status register

    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40001414EGR// event generation register

    • [0]UG (def=0x0) // Update generation
  • 0x40001424CNT// counter

    • [0:15]CNT (def=0x0) // Low counter value
  • 0x40001428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000142CARR// auto-reload register

    • [0:15]ARR (def=0x0) // Low Auto-reload value
  interrupts:
  • [55] TIM7 // TIM7 global interrupt
• 0x40005400I2C1// Inter integrated circuit

  • 0x40005400CR1// Control register 1

    • [15]SWRST (def=0x0) // Software reset
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]PEC (def=0x0) // Packet error checking
    • [11]POS (def=0x0) // Acknowledge/PEC Position (for data reception)
    • [10]ACK (def=0x0) // Acknowledge enable
    • [9]STOP (def=0x0) // Stop generation
    • [8]START (def=0x0) // Start generation
    • [7]NOSTRETCH (def=0x0) // Clock stretching disable (Slave mode)
    • [6]ENGC (def=0x0) // General call enable
    • [5]ENPEC (def=0x0) // PEC enable
    • [4]ENARP (def=0x0) // ARP enable
    • [3]SMBTYPE (def=0x0) // SMBus type
    • [1]SMBUS (def=0x0) // SMBus mode
    • [0]PE (def=0x0) // Peripheral enable
  • 0x40005404CR2// Control register 2

    • [12]LAST (def=0x0) // DMA last transfer
    • [11]DMAEN (def=0x0) // DMA requests enable
    • [10]ITBUFEN (def=0x0) // Buffer interrupt enable
    • [9]ITEVTEN (def=0x0) // Event interrupt enable
    • [8]ITERREN (def=0x0) // Error interrupt enable
    • [0:5]FREQ (def=0x0) // Peripheral clock frequency
  • 0x40005408OAR1// Own address register 1

    • [15]ADDMODE (def=0x0) // Addressing mode (slave mode)
    • [8:9]ADD10 (def=0x0) // Interface address
    • [1:7]ADD7 (def=0x0) // Interface address
    • [0]ADD0 (def=0x0) // Interface address
  • 0x4000540COAR2// Own address register 2

    • [1:7]ADD2 (def=0x0) // Interface address
    • [0]ENDUAL (def=0x0) // Dual addressing mode enable
  • 0x40005410DR// Data register

    • [0:7]DR (def=0x0) // 8-bit data register
  • 0x40005414SR1// Status register 1

    • [15]SMBALERT (def=0x0) // SMBus alert
    • [14]TIMEOUT (def=0x0) // Timeout or Tlow error
    • [12]PECERR (def=0x0) // PEC Error in reception
    • [11]OVR (def=0x0) // Overrun/Underrun
    • [10]AF (def=0x0) // Acknowledge failure
    • [9]ARLO (def=0x0) // Arbitration lost (master mode)
    • [8]BERR (def=0x0) // Bus error
    • [7]TxE (def=0x0) // Data register empty (transmitters)
    • [6]RxNE (def=0x0) // Data register not empty (receivers)
    • [4]STOPF (def=0x0) // Stop detection (slave mode)
    • [3]ADD10 (def=0x0) // 10-bit header sent (Master mode)
    • [2]BTF (def=0x0) // Byte transfer finished
    • [1]ADDR (def=0x0) // Address sent (master mode)/matched (slave mode)
    • [0]SB (def=0x0) // Start bit (Master mode)
  • 0x40005418SR2// Status register 2

    • [8:15]PEC (def=0x0) // acket error checking register
    • [7]DUALF (def=0x0) // Dual flag (Slave mode)
    • [6]SMBHOST (def=0x0) // SMBus host header (Slave mode)
    • [5]SMBDEFAULT (def=0x0) // SMBus device default address (Slave mode)
    • [4]GENCALL (def=0x0) // General call address (Slave mode)
    • [2]TRA (def=0x0) // Transmitter/receiver
    • [1]BUSY (def=0x0) // Bus busy
    • [0]MSL (def=0x0) // Master/slave
  • 0x4000541CCCR// Clock control register

    • [15]F_S (def=0x0) // I2C master mode selection
    • [14]DUTY (def=0x0) // Fast mode duty cycle
    • [0:11]CCR (def=0x0) // Clock control register in Fast/Standard mode (Master mode)
  • 0x40005420TRISE// TRISE register

    • [0:5]TRISE (def=0x2) // Maximum rise time in Fast/Standard mode (Master mode)
  interrupts:
  • [31] I2C1_EV // I2C1 event interrupt
  • [32] I2C1_ER // I2C1 error interrupt
• 0x40005800I2C2//

  • 0x40005800CR1// Control register 1

    • [15]SWRST (def=0x0) // Software reset
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]PEC (def=0x0) // Packet error checking
    • [11]POS (def=0x0) // Acknowledge/PEC Position (for data reception)
    • [10]ACK (def=0x0) // Acknowledge enable
    • [9]STOP (def=0x0) // Stop generation
    • [8]START (def=0x0) // Start generation
    • [7]NOSTRETCH (def=0x0) // Clock stretching disable (Slave mode)
    • [6]ENGC (def=0x0) // General call enable
    • [5]ENPEC (def=0x0) // PEC enable
    • [4]ENARP (def=0x0) // ARP enable
    • [3]SMBTYPE (def=0x0) // SMBus type
    • [1]SMBUS (def=0x0) // SMBus mode
    • [0]PE (def=0x0) // Peripheral enable
  • 0x40005804CR2// Control register 2

    • [12]LAST (def=0x0) // DMA last transfer
    • [11]DMAEN (def=0x0) // DMA requests enable
    • [10]ITBUFEN (def=0x0) // Buffer interrupt enable
    • [9]ITEVTEN (def=0x0) // Event interrupt enable
    • [8]ITERREN (def=0x0) // Error interrupt enable
    • [0:5]FREQ (def=0x0) // Peripheral clock frequency
  • 0x40005808OAR1// Own address register 1

    • [15]ADDMODE (def=0x0) // Addressing mode (slave mode)
    • [8:9]ADD10 (def=0x0) // Interface address
    • [1:7]ADD7 (def=0x0) // Interface address
    • [0]ADD0 (def=0x0) // Interface address
  • 0x4000580COAR2// Own address register 2

    • [1:7]ADD2 (def=0x0) // Interface address
    • [0]ENDUAL (def=0x0) // Dual addressing mode enable
  • 0x40005810DR// Data register

    • [0:7]DR (def=0x0) // 8-bit data register
  • 0x40005814SR1// Status register 1

    • [15]SMBALERT (def=0x0) // SMBus alert
    • [14]TIMEOUT (def=0x0) // Timeout or Tlow error
    • [12]PECERR (def=0x0) // PEC Error in reception
    • [11]OVR (def=0x0) // Overrun/Underrun
    • [10]AF (def=0x0) // Acknowledge failure
    • [9]ARLO (def=0x0) // Arbitration lost (master mode)
    • [8]BERR (def=0x0) // Bus error
    • [7]TxE (def=0x0) // Data register empty (transmitters)
    • [6]RxNE (def=0x0) // Data register not empty (receivers)
    • [4]STOPF (def=0x0) // Stop detection (slave mode)
    • [3]ADD10 (def=0x0) // 10-bit header sent (Master mode)
    • [2]BTF (def=0x0) // Byte transfer finished
    • [1]ADDR (def=0x0) // Address sent (master mode)/matched (slave mode)
    • [0]SB (def=0x0) // Start bit (Master mode)
  • 0x40005818SR2// Status register 2

    • [8:15]PEC (def=0x0) // acket error checking register
    • [7]DUALF (def=0x0) // Dual flag (Slave mode)
    • [6]SMBHOST (def=0x0) // SMBus host header (Slave mode)
    • [5]SMBDEFAULT (def=0x0) // SMBus device default address (Slave mode)
    • [4]GENCALL (def=0x0) // General call address (Slave mode)
    • [2]TRA (def=0x0) // Transmitter/receiver
    • [1]BUSY (def=0x0) // Bus busy
    • [0]MSL (def=0x0) // Master/slave
  • 0x4000581CCCR// Clock control register

    • [15]F_S (def=0x0) // I2C master mode selection
    • [14]DUTY (def=0x0) // Fast mode duty cycle
    • [0:11]CCR (def=0x0) // Clock control register in Fast/Standard mode (Master mode)
  • 0x40005820TRISE// TRISE register

    • [0:5]TRISE (def=0x2) // Maximum rise time in Fast/Standard mode (Master mode)
  interrupts:
  • [33] I2C2_EV // I2C2 event interrupt
  • [34] I2C2_ER // I2C2 error interrupt
• 0x40013000SPI1// Serial peripheral interface

  • 0x40013000CR1// control register 1

    • [15]BIDIMODE (def=0x0) // Bidirectional data mode enable
    • [14]BIDIOE (def=0x0) // Output enable in bidirectional mode
    • [13]CRCEN (def=0x0) // Hardware CRC calculation enable
    • [12]CRCNEXT (def=0x0) // CRC transfer next
    • [11]DFF (def=0x0) // Data frame format
    • [10]RXONLY (def=0x0) // Receive only
    • [9]SSM (def=0x0) // Software slave management
    • [8]SSI (def=0x0) // Internal slave select
    • [7]LSBFIRST (def=0x0) // Frame format
    • [6]SPE (def=0x0) // SPI enable
    • [3:5]BR (def=0x0) // Baud rate control
    • [2]MSTR (def=0x0) // Master selection
    • [1]CPOL (def=0x0) // Clock polarity
    • [0]CPHA (def=0x0) // Clock phase
  • 0x40013004CR2// control register 2

    • [7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
    • [6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
    • [5]ERRIE (def=0x0) // Error interrupt enable
    • [2]SSOE (def=0x0) // SS output enable
    • [1]TXDMAEN (def=0x0) // Tx buffer DMA enable
    • [0]RXDMAEN (def=0x0) // Rx buffer DMA enable
  • 0x40013008SR// status register

    • [7]BSY (def=0x0) // Busy flag
    • [6]OVR (def=0x0) // Overrun flag
    • [5]MODF (def=0x0) // Mode fault
    • [4]CRCERR (def=0x0) // CRC error flag
    • [3]UDR (def=0x0) // Underrun flag
    • [2]CHSIDE (def=0x0) // Channel side
    • [1]TXE (def=0x1) // Transmit buffer empty
    • [0]RXNE (def=0x0) // Receive buffer not empty
  • 0x4001300CDR// data register

    • [0:15]DR (def=0x0) // Data register
  • 0x40013010CRCPR// CRC polynomial register

    • [0:15]CRCPOLY (def=0x7) // CRC polynomial register
  • 0x40013014RXCRCR// RX CRC register

    • [0:15]RxCRC (def=0x0) // Rx CRC register
  • 0x40013018TXCRCR// TX CRC register

    • [0:15]TxCRC (def=0x0) // Tx CRC register
  • 0x4001301CI2SCFGR// I2S configuration register

    • [11]I2SMOD (def=0x0) // I2S mode selection
    • [10]I2SE (def=0x0) // I2S Enable
    • [8:9]I2SCFG (def=0x0) // I2S configuration mode
    • [7]PCMSYNC (def=0x0) // PCM frame synchronization
    • [4:5]I2SSTD (def=0x0) // I2S standard selection
    • [3]CKPOL (def=0x0) // Steady state clock polarity
    • [1:2]DATLEN (def=0x0) // Data length to be transferred
    • [0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
  • 0x40013020I2SPR// I2S prescaler register

    • [9]MCKOE (def=0x0) // Master clock output enable
    • [8]ODD (def=0x0) // Odd factor for the prescaler
    • [0:7]I2SDIV (def=0x8) // I2S Linear prescaler
  interrupts:
  • [35] SPI1 // SPI1 global interrupt
• 0x40003800SPI2//

  • 0x40003800CR1// control register 1

    • [15]BIDIMODE (def=0x0) // Bidirectional data mode enable
    • [14]BIDIOE (def=0x0) // Output enable in bidirectional mode
    • [13]CRCEN (def=0x0) // Hardware CRC calculation enable
    • [12]CRCNEXT (def=0x0) // CRC transfer next
    • [11]DFF (def=0x0) // Data frame format
    • [10]RXONLY (def=0x0) // Receive only
    • [9]SSM (def=0x0) // Software slave management
    • [8]SSI (def=0x0) // Internal slave select
    • [7]LSBFIRST (def=0x0) // Frame format
    • [6]SPE (def=0x0) // SPI enable
    • [3:5]BR (def=0x0) // Baud rate control
    • [2]MSTR (def=0x0) // Master selection
    • [1]CPOL (def=0x0) // Clock polarity
    • [0]CPHA (def=0x0) // Clock phase
  • 0x40003804CR2// control register 2

    • [7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
    • [6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
    • [5]ERRIE (def=0x0) // Error interrupt enable
    • [2]SSOE (def=0x0) // SS output enable
    • [1]TXDMAEN (def=0x0) // Tx buffer DMA enable
    • [0]RXDMAEN (def=0x0) // Rx buffer DMA enable
  • 0x40003808SR// status register

    • [7]BSY (def=0x0) // Busy flag
    • [6]OVR (def=0x0) // Overrun flag
    • [5]MODF (def=0x0) // Mode fault
    • [4]CRCERR (def=0x0) // CRC error flag
    • [3]UDR (def=0x0) // Underrun flag
    • [2]CHSIDE (def=0x0) // Channel side
    • [1]TXE (def=0x1) // Transmit buffer empty
    • [0]RXNE (def=0x0) // Receive buffer not empty
  • 0x4000380CDR// data register

    • [0:15]DR (def=0x0) // Data register
  • 0x40003810CRCPR// CRC polynomial register

    • [0:15]CRCPOLY (def=0x7) // CRC polynomial register
  • 0x40003814RXCRCR// RX CRC register

    • [0:15]RxCRC (def=0x0) // Rx CRC register
  • 0x40003818TXCRCR// TX CRC register

    • [0:15]TxCRC (def=0x0) // Tx CRC register
  • 0x4000381CI2SCFGR// I2S configuration register

    • [11]I2SMOD (def=0x0) // I2S mode selection
    • [10]I2SE (def=0x0) // I2S Enable
    • [8:9]I2SCFG (def=0x0) // I2S configuration mode
    • [7]PCMSYNC (def=0x0) // PCM frame synchronization
    • [4:5]I2SSTD (def=0x0) // I2S standard selection
    • [3]CKPOL (def=0x0) // Steady state clock polarity
    • [1:2]DATLEN (def=0x0) // Data length to be transferred
    • [0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
  • 0x40003820I2SPR// I2S prescaler register

    • [9]MCKOE (def=0x0) // Master clock output enable
    • [8]ODD (def=0x0) // Odd factor for the prescaler
    • [0:7]I2SDIV (def=0x8) // I2S Linear prescaler
  interrupts:
  • [36] SPI2 // SPI2 global interrupt
• 0x40003C00SPI3//

  • 0x40003C00CR1// control register 1

    • [15]BIDIMODE (def=0x0) // Bidirectional data mode enable
    • [14]BIDIOE (def=0x0) // Output enable in bidirectional mode
    • [13]CRCEN (def=0x0) // Hardware CRC calculation enable
    • [12]CRCNEXT (def=0x0) // CRC transfer next
    • [11]DFF (def=0x0) // Data frame format
    • [10]RXONLY (def=0x0) // Receive only
    • [9]SSM (def=0x0) // Software slave management
    • [8]SSI (def=0x0) // Internal slave select
    • [7]LSBFIRST (def=0x0) // Frame format
    • [6]SPE (def=0x0) // SPI enable
    • [3:5]BR (def=0x0) // Baud rate control
    • [2]MSTR (def=0x0) // Master selection
    • [1]CPOL (def=0x0) // Clock polarity
    • [0]CPHA (def=0x0) // Clock phase
  • 0x40003C04CR2// control register 2

    • [7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
    • [6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
    • [5]ERRIE (def=0x0) // Error interrupt enable
    • [2]SSOE (def=0x0) // SS output enable
    • [1]TXDMAEN (def=0x0) // Tx buffer DMA enable
    • [0]RXDMAEN (def=0x0) // Rx buffer DMA enable
  • 0x40003C08SR// status register

    • [7]BSY (def=0x0) // Busy flag
    • [6]OVR (def=0x0) // Overrun flag
    • [5]MODF (def=0x0) // Mode fault
    • [4]CRCERR (def=0x0) // CRC error flag
    • [3]UDR (def=0x0) // Underrun flag
    • [2]CHSIDE (def=0x0) // Channel side
    • [1]TXE (def=0x1) // Transmit buffer empty
    • [0]RXNE (def=0x0) // Receive buffer not empty
  • 0x40003C0CDR// data register

    • [0:15]DR (def=0x0) // Data register
  • 0x40003C10CRCPR// CRC polynomial register

    • [0:15]CRCPOLY (def=0x7) // CRC polynomial register
  • 0x40003C14RXCRCR// RX CRC register

    • [0:15]RxCRC (def=0x0) // Rx CRC register
  • 0x40003C18TXCRCR// TX CRC register

    • [0:15]TxCRC (def=0x0) // Tx CRC register
  • 0x40003C1CI2SCFGR// I2S configuration register

    • [11]I2SMOD (def=0x0) // I2S mode selection
    • [10]I2SE (def=0x0) // I2S Enable
    • [8:9]I2SCFG (def=0x0) // I2S configuration mode
    • [7]PCMSYNC (def=0x0) // PCM frame synchronization
    • [4:5]I2SSTD (def=0x0) // I2S standard selection
    • [3]CKPOL (def=0x0) // Steady state clock polarity
    • [1:2]DATLEN (def=0x0) // Data length to be transferred
    • [0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
  • 0x40003C20I2SPR// I2S prescaler register

    • [9]MCKOE (def=0x0) // Master clock output enable
    • [8]ODD (def=0x0) // Odd factor for the prescaler
    • [0:7]I2SDIV (def=0x8) // I2S Linear prescaler
  interrupts:
  • [51] SPI3 // SPI3 global interrupt
• 0x40013800USART1// Universal synchronous asynchronous receiver transmitter

  • 0x40013800SR// Status register

    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40013804DR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40013808BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x4001380CCR1// Control register 1

    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40013810CR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40013814CR3// Control register 3

    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40013818GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  interrupts:
  • [37] USART1 // USART1 global interrupt
• 0x40004400USART2//

  • 0x40004400SR// Status register

    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40004404DR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40004408BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x4000440CCR1// Control register 1

    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40004410CR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40004414CR3// Control register 3

    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40004418GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  interrupts:
  • [38] USART2 // USART2 global interrupt
• 0x40004800USART3//

  • 0x40004800SR// Status register

    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40004804DR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40004808BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x4000480CCR1// Control register 1

    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40004810CR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40004814CR3// Control register 3

    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40004818GTPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  interrupts:
  • [39] USART3 // USART3 global interrupt
• 0x40012400ADC1// Analog to digital converter

  • 0x40012400SR// status register

    • [4]STRT (def=0x0) // Regular channel start flag
    • [3]JSTRT (def=0x0) // Injected channel start flag
    • [2]JEOC (def=0x0) // Injected channel end of conversion
    • [1]EOC (def=0x0) // Regular channel end of conversion
    • [0]AWD (def=0x0) // Analog watchdog flag
  • 0x40012404CR1// control register 1

    • [23]AWDEN (def=0x0) // Analog watchdog enable on regular channels
    • [22]JAWDEN (def=0x0) // Analog watchdog enable on injected channels
    • [16:19]DUALMOD (def=0x0) // Dual mode selection
    • [13:15]DISCNUM (def=0x0) // Discontinuous mode channel count
    • [12]JDISCEN (def=0x0) // Discontinuous mode on injected channels
    • [11]DISCEN (def=0x0) // Discontinuous mode on regular channels
    • [10]JAUTO (def=0x0) // Automatic injected group conversion
    • [9]AWDSGL (def=0x0) // Enable the watchdog on a single channel in scan mode
    • [8]SCAN (def=0x0) // Scan mode
    • [7]JEOCIE (def=0x0) // Interrupt enable for injected channels
    • [6]AWDIE (def=0x0) // Analog watchdog interrupt enable
    • [5]EOCIE (def=0x0) // Interrupt enable for EOC
    • [0:4]AWDCH (def=0x0) // Analog watchdog channel select bits
  • 0x40012408CR2// control register 2

    • [23]TSVREFE (def=0x0) // Temperature sensor and VREFINT enable
    • [22]SWSTART (def=0x0) // Start conversion of regular channels
    • [21]JSWSTART (def=0x0) // Start conversion of injected channels
    • [20]EXTTRIG (def=0x0) // External trigger conversion mode for regular channels
    • [17:19]EXTSEL (def=0x0) // External event select for regular group
    • [15]JEXTTRIG (def=0x0) // External trigger conversion mode for injected channels
    • [12:14]JEXTSEL (def=0x0) // External event select for injected group
    • [11]ALIGN (def=0x0) // Data alignment
    • [8]DMA (def=0x0) // Direct memory access mode
    • [3]RSTCAL (def=0x0) // Reset calibration
    • [2]CAL (def=0x0) // A/D calibration
    • [1]CONT (def=0x0) // Continuous conversion
    • [0]ADON (def=0x0) // A/D converter ON / OFF
  • 0x4001240CSMPR1// sample time register 1

    • [0:2]SMP10 (def=0x0) // Channel 10 sample time selection
    • [3:5]SMP11 (def=0x0) // Channel 11 sample time selection
    • [6:8]SMP12 (def=0x0) // Channel 12 sample time selection
    • [9:11]SMP13 (def=0x0) // Channel 13 sample time selection
    • [12:14]SMP14 (def=0x0) // Channel 14 sample time selection
    • [15:17]SMP15 (def=0x0) // Channel 15 sample time selection
    • [18:20]SMP16 (def=0x0) // Channel 16 sample time selection
    • [21:23]SMP17 (def=0x0) // Channel 17 sample time selection
  • 0x40012410SMPR2// sample time register 2

    • [0:2]SMP0 (def=0x0) // Channel 0 sample time selection
    • [3:5]SMP1 (def=0x0) // Channel 1 sample time selection
    • [6:8]SMP2 (def=0x0) // Channel 2 sample time selection
    • [9:11]SMP3 (def=0x0) // Channel 3 sample time selection
    • [12:14]SMP4 (def=0x0) // Channel 4 sample time selection
    • [15:17]SMP5 (def=0x0) // Channel 5 sample time selection
    • [18:20]SMP6 (def=0x0) // Channel 6 sample time selection
    • [21:23]SMP7 (def=0x0) // Channel 7 sample time selection
    • [24:26]SMP8 (def=0x0) // Channel 8 sample time selection
    • [27:29]SMP9 (def=0x0) // Channel 9 sample time selection
  • 0x40012414JOFR1// injected channel data offset register x

    • [0:11]JOFFSET1 (def=0x0) // Data offset for injected channel x
  • 0x40012418JOFR2// injected channel data offset register x

    • [0:11]JOFFSET2 (def=0x0) // Data offset for injected channel x
  • 0x4001241CJOFR3// injected channel data offset register x

    • [0:11]JOFFSET3 (def=0x0) // Data offset for injected channel x
  • 0x40012420JOFR4// injected channel data offset register x

    • [0:11]JOFFSET4 (def=0x0) // Data offset for injected channel x
  • 0x40012424HTR// watchdog higher threshold register

    • [0:11]HT (def=0xFFF) // Analog watchdog higher threshold
  • 0x40012428LTR// watchdog lower threshold register

    • [0:11]LT (def=0x0) // Analog watchdog lower threshold
  • 0x4001242CSQR1// regular sequence register 1

    • [20:23]L (def=0x0) // Regular channel sequence length
    • [15:19]SQ16 (def=0x0) // 16th conversion in regular sequence
    • [10:14]SQ15 (def=0x0) // 15th conversion in regular sequence
    • [5:9]SQ14 (def=0x0) // 14th conversion in regular sequence
    • [0:4]SQ13 (def=0x0) // 13th conversion in regular sequence
  • 0x40012430SQR2// regular sequence register 2

    • [25:29]SQ12 (def=0x0) // 12th conversion in regular sequence
    • [20:24]SQ11 (def=0x0) // 11th conversion in regular sequence
    • [15:19]SQ10 (def=0x0) // 10th conversion in regular sequence
    • [10:14]SQ9 (def=0x0) // 9th conversion in regular sequence
    • [5:9]SQ8 (def=0x0) // 8th conversion in regular sequence
    • [0:4]SQ7 (def=0x0) // 7th conversion in regular sequence
  • 0x40012434SQR3// regular sequence register 3

    • [25:29]SQ6 (def=0x0) // 6th conversion in regular sequence
    • [20:24]SQ5 (def=0x0) // 5th conversion in regular sequence
    • [15:19]SQ4 (def=0x0) // 4th conversion in regular sequence
    • [10:14]SQ3 (def=0x0) // 3rd conversion in regular sequence
    • [5:9]SQ2 (def=0x0) // 2nd conversion in regular sequence
    • [0:4]SQ1 (def=0x0) // 1st conversion in regular sequence
  • 0x40012438JSQR// injected sequence register

    • [20:21]JL (def=0x0) // Injected sequence length
    • [15:19]JSQ4 (def=0x0) // 4th conversion in injected sequence
    • [10:14]JSQ3 (def=0x0) // 3rd conversion in injected sequence
    • [5:9]JSQ2 (def=0x0) // 2nd conversion in injected sequence
    • [0:4]JSQ1 (def=0x0) // 1st conversion in injected sequence
  • 0x4001243CJDR1// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012440JDR2// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012444JDR3// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012448JDR4// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x4001244CDR// regular data register

    • [0:15]DATA (def=0x0) // Regular data
    • [16:31]ADC2DATA (def=0x0) // ADC2 data
  interrupts:
  • [18] ADC1_2 // ADC1 and ADC2 global interrupt
• 0x40012800ADC2// Analog to digital converter

  • 0x40012800SR// status register

    • [4]STRT (def=0x0) // Regular channel start flag
    • [3]JSTRT (def=0x0) // Injected channel start flag
    • [2]JEOC (def=0x0) // Injected channel end of conversion
    • [1]EOC (def=0x0) // Regular channel end of conversion
    • [0]AWD (def=0x0) // Analog watchdog flag
  • 0x40012804CR1// control register 1

    • [23]AWDEN (def=0x0) // Analog watchdog enable on regular channels
    • [22]JAWDEN (def=0x0) // Analog watchdog enable on injected channels
    • [13:15]DISCNUM (def=0x0) // Discontinuous mode channel count
    • [12]JDISCEN (def=0x0) // Discontinuous mode on injected channels
    • [11]DISCEN (def=0x0) // Discontinuous mode on regular channels
    • [10]JAUTO (def=0x0) // Automatic injected group conversion
    • [9]AWDSGL (def=0x0) // Enable the watchdog on a single channel in scan mode
    • [8]SCAN (def=0x0) // Scan mode
    • [7]JEOCIE (def=0x0) // Interrupt enable for injected channels
    • [6]AWDIE (def=0x0) // Analog watchdog interrupt enable
    • [5]EOCIE (def=0x0) // Interrupt enable for EOC
    • [0:4]AWDCH (def=0x0) // Analog watchdog channel select bits
  • 0x40012808CR2// control register 2

    • [23]TSVREFE (def=0x0) // Temperature sensor and VREFINT enable
    • [22]SWSTART (def=0x0) // Start conversion of regular channels
    • [21]JSWSTART (def=0x0) // Start conversion of injected channels
    • [20]EXTTRIG (def=0x0) // External trigger conversion mode for regular channels
    • [17:19]EXTSEL (def=0x0) // External event select for regular group
    • [15]JEXTTRIG (def=0x0) // External trigger conversion mode for injected channels
    • [12:14]JEXTSEL (def=0x0) // External event select for injected group
    • [11]ALIGN (def=0x0) // Data alignment
    • [8]DMA (def=0x0) // Direct memory access mode
    • [3]RSTCAL (def=0x0) // Reset calibration
    • [2]CAL (def=0x0) // A/D calibration
    • [1]CONT (def=0x0) // Continuous conversion
    • [0]ADON (def=0x0) // A/D converter ON / OFF
  • 0x4001280CSMPR1// sample time register 1

    • [0:2]SMP10 (def=0x0) // Channel 10 sample time selection
    • [3:5]SMP11 (def=0x0) // Channel 11 sample time selection
    • [6:8]SMP12 (def=0x0) // Channel 12 sample time selection
    • [9:11]SMP13 (def=0x0) // Channel 13 sample time selection
    • [12:14]SMP14 (def=0x0) // Channel 14 sample time selection
    • [15:17]SMP15 (def=0x0) // Channel 15 sample time selection
    • [18:20]SMP16 (def=0x0) // Channel 16 sample time selection
    • [21:23]SMP17 (def=0x0) // Channel 17 sample time selection
  • 0x40012810SMPR2// sample time register 2

    • [0:2]SMP0 (def=0x0) // Channel 0 sample time selection
    • [3:5]SMP1 (def=0x0) // Channel 1 sample time selection
    • [6:8]SMP2 (def=0x0) // Channel 2 sample time selection
    • [9:11]SMP3 (def=0x0) // Channel 3 sample time selection
    • [12:14]SMP4 (def=0x0) // Channel 4 sample time selection
    • [15:17]SMP5 (def=0x0) // Channel 5 sample time selection
    • [18:20]SMP6 (def=0x0) // Channel 6 sample time selection
    • [21:23]SMP7 (def=0x0) // Channel 7 sample time selection
    • [24:26]SMP8 (def=0x0) // Channel 8 sample time selection
    • [27:29]SMP9 (def=0x0) // Channel 9 sample time selection
  • 0x40012814JOFR1// injected channel data offset register x

    • [0:11]JOFFSET1 (def=0x0) // Data offset for injected channel x
  • 0x40012818JOFR2// injected channel data offset register x

    • [0:11]JOFFSET2 (def=0x0) // Data offset for injected channel x
  • 0x4001281CJOFR3// injected channel data offset register x

    • [0:11]JOFFSET3 (def=0x0) // Data offset for injected channel x
  • 0x40012820JOFR4// injected channel data offset register x

    • [0:11]JOFFSET4 (def=0x0) // Data offset for injected channel x
  • 0x40012824HTR// watchdog higher threshold register

    • [0:11]HT (def=0xFFF) // Analog watchdog higher threshold
  • 0x40012828LTR// watchdog lower threshold register

    • [0:11]LT (def=0x0) // Analog watchdog lower threshold
  • 0x4001282CSQR1// regular sequence register 1

    • [20:23]L (def=0x0) // Regular channel sequence length
    • [15:19]SQ16 (def=0x0) // 16th conversion in regular sequence
    • [10:14]SQ15 (def=0x0) // 15th conversion in regular sequence
    • [5:9]SQ14 (def=0x0) // 14th conversion in regular sequence
    • [0:4]SQ13 (def=0x0) // 13th conversion in regular sequence
  • 0x40012830SQR2// regular sequence register 2

    • [25:29]SQ12 (def=0x0) // 12th conversion in regular sequence
    • [20:24]SQ11 (def=0x0) // 11th conversion in regular sequence
    • [15:19]SQ10 (def=0x0) // 10th conversion in regular sequence
    • [10:14]SQ9 (def=0x0) // 9th conversion in regular sequence
    • [5:9]SQ8 (def=0x0) // 8th conversion in regular sequence
    • [0:4]SQ7 (def=0x0) // 7th conversion in regular sequence
  • 0x40012834SQR3// regular sequence register 3

    • [25:29]SQ6 (def=0x0) // 6th conversion in regular sequence
    • [20:24]SQ5 (def=0x0) // 5th conversion in regular sequence
    • [15:19]SQ4 (def=0x0) // 4th conversion in regular sequence
    • [10:14]SQ3 (def=0x0) // 3rd conversion in regular sequence
    • [5:9]SQ2 (def=0x0) // 2nd conversion in regular sequence
    • [0:4]SQ1 (def=0x0) // 1st conversion in regular sequence
  • 0x40012838JSQR// injected sequence register

    • [20:21]JL (def=0x0) // Injected sequence length
    • [15:19]JSQ4 (def=0x0) // 4th conversion in injected sequence
    • [10:14]JSQ3 (def=0x0) // 3rd conversion in injected sequence
    • [5:9]JSQ2 (def=0x0) // 2nd conversion in injected sequence
    • [0:4]JSQ1 (def=0x0) // 1st conversion in injected sequence
  • 0x4001283CJDR1// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012840JDR2// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012844JDR3// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012848JDR4// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x4001284CDR// regular data register

    • [0:15]DATA (def=0x0) // Regular data
• 0x40013C00ADC3//

  • 0x40013C00SR// status register

    • [4]STRT (def=0x0) // Regular channel start flag
    • [3]JSTRT (def=0x0) // Injected channel start flag
    • [2]JEOC (def=0x0) // Injected channel end of conversion
    • [1]EOC (def=0x0) // Regular channel end of conversion
    • [0]AWD (def=0x0) // Analog watchdog flag
  • 0x40013C04CR1// control register 1

    • [23]AWDEN (def=0x0) // Analog watchdog enable on regular channels
    • [22]JAWDEN (def=0x0) // Analog watchdog enable on injected channels
    • [13:15]DISCNUM (def=0x0) // Discontinuous mode channel count
    • [12]JDISCEN (def=0x0) // Discontinuous mode on injected channels
    • [11]DISCEN (def=0x0) // Discontinuous mode on regular channels
    • [10]JAUTO (def=0x0) // Automatic injected group conversion
    • [9]AWDSGL (def=0x0) // Enable the watchdog on a single channel in scan mode
    • [8]SCAN (def=0x0) // Scan mode
    • [7]JEOCIE (def=0x0) // Interrupt enable for injected channels
    • [6]AWDIE (def=0x0) // Analog watchdog interrupt enable
    • [5]EOCIE (def=0x0) // Interrupt enable for EOC
    • [0:4]AWDCH (def=0x0) // Analog watchdog channel select bits
  • 0x40013C08CR2// control register 2

    • [23]TSVREFE (def=0x0) // Temperature sensor and VREFINT enable
    • [22]SWSTART (def=0x0) // Start conversion of regular channels
    • [21]JSWSTART (def=0x0) // Start conversion of injected channels
    • [20]EXTTRIG (def=0x0) // External trigger conversion mode for regular channels
    • [17:19]EXTSEL (def=0x0) // External event select for regular group
    • [15]JEXTTRIG (def=0x0) // External trigger conversion mode for injected channels
    • [12:14]JEXTSEL (def=0x0) // External event select for injected group
    • [11]ALIGN (def=0x0) // Data alignment
    • [8]DMA (def=0x0) // Direct memory access mode
    • [3]RSTCAL (def=0x0) // Reset calibration
    • [2]CAL (def=0x0) // A/D calibration
    • [1]CONT (def=0x0) // Continuous conversion
    • [0]ADON (def=0x0) // A/D converter ON / OFF
  • 0x40013C0CSMPR1// sample time register 1

    • [0:2]SMP10 (def=0x0) // Channel 10 sample time selection
    • [3:5]SMP11 (def=0x0) // Channel 11 sample time selection
    • [6:8]SMP12 (def=0x0) // Channel 12 sample time selection
    • [9:11]SMP13 (def=0x0) // Channel 13 sample time selection
    • [12:14]SMP14 (def=0x0) // Channel 14 sample time selection
    • [15:17]SMP15 (def=0x0) // Channel 15 sample time selection
    • [18:20]SMP16 (def=0x0) // Channel 16 sample time selection
    • [21:23]SMP17 (def=0x0) // Channel 17 sample time selection
  • 0x40013C10SMPR2// sample time register 2

    • [0:2]SMP0 (def=0x0) // Channel 0 sample time selection
    • [3:5]SMP1 (def=0x0) // Channel 1 sample time selection
    • [6:8]SMP2 (def=0x0) // Channel 2 sample time selection
    • [9:11]SMP3 (def=0x0) // Channel 3 sample time selection
    • [12:14]SMP4 (def=0x0) // Channel 4 sample time selection
    • [15:17]SMP5 (def=0x0) // Channel 5 sample time selection
    • [18:20]SMP6 (def=0x0) // Channel 6 sample time selection
    • [21:23]SMP7 (def=0x0) // Channel 7 sample time selection
    • [24:26]SMP8 (def=0x0) // Channel 8 sample time selection
    • [27:29]SMP9 (def=0x0) // Channel 9 sample time selection
  • 0x40013C14JOFR1// injected channel data offset register x

    • [0:11]JOFFSET1 (def=0x0) // Data offset for injected channel x
  • 0x40013C18JOFR2// injected channel data offset register x

    • [0:11]JOFFSET2 (def=0x0) // Data offset for injected channel x
  • 0x40013C1CJOFR3// injected channel data offset register x

    • [0:11]JOFFSET3 (def=0x0) // Data offset for injected channel x
  • 0x40013C20JOFR4// injected channel data offset register x

    • [0:11]JOFFSET4 (def=0x0) // Data offset for injected channel x
  • 0x40013C24HTR// watchdog higher threshold register

    • [0:11]HT (def=0xFFF) // Analog watchdog higher threshold
  • 0x40013C28LTR// watchdog lower threshold register

    • [0:11]LT (def=0x0) // Analog watchdog lower threshold
  • 0x40013C2CSQR1// regular sequence register 1

    • [20:23]L (def=0x0) // Regular channel sequence length
    • [15:19]SQ16 (def=0x0) // 16th conversion in regular sequence
    • [10:14]SQ15 (def=0x0) // 15th conversion in regular sequence
    • [5:9]SQ14 (def=0x0) // 14th conversion in regular sequence
    • [0:4]SQ13 (def=0x0) // 13th conversion in regular sequence
  • 0x40013C30SQR2// regular sequence register 2

    • [25:29]SQ12 (def=0x0) // 12th conversion in regular sequence
    • [20:24]SQ11 (def=0x0) // 11th conversion in regular sequence
    • [15:19]SQ10 (def=0x0) // 10th conversion in regular sequence
    • [10:14]SQ9 (def=0x0) // 9th conversion in regular sequence
    • [5:9]SQ8 (def=0x0) // 8th conversion in regular sequence
    • [0:4]SQ7 (def=0x0) // 7th conversion in regular sequence
  • 0x40013C34SQR3// regular sequence register 3

    • [25:29]SQ6 (def=0x0) // 6th conversion in regular sequence
    • [20:24]SQ5 (def=0x0) // 5th conversion in regular sequence
    • [15:19]SQ4 (def=0x0) // 4th conversion in regular sequence
    • [10:14]SQ3 (def=0x0) // 3rd conversion in regular sequence
    • [5:9]SQ2 (def=0x0) // 2nd conversion in regular sequence
    • [0:4]SQ1 (def=0x0) // 1st conversion in regular sequence
  • 0x40013C38JSQR// injected sequence register

    • [20:21]JL (def=0x0) // Injected sequence length
    • [15:19]JSQ4 (def=0x0) // 4th conversion in injected sequence
    • [10:14]JSQ3 (def=0x0) // 3rd conversion in injected sequence
    • [5:9]JSQ2 (def=0x0) // 2nd conversion in injected sequence
    • [0:4]JSQ1 (def=0x0) // 1st conversion in injected sequence
  • 0x40013C3CJDR1// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40013C40JDR2// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40013C44JDR3// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40013C48JDR4// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40013C4CDR// regular data register

    • [0:15]DATA (def=0x0) // Regular data
  interrupts:
  • [47] ADC3 // ADC3 global interrupt
• 0x40006400CAN1// Controller area network

  • 0x40006400CAN_MCR// CAN_MCR

    • [16]DBF (def=0x0) // DBF
    • [15]RESET (def=0x0) // RESET
    • [7]TTCM (def=0x0) // TTCM
    • [6]ABOM (def=0x0) // ABOM
    • [5]AWUM (def=0x0) // AWUM
    • [4]NART (def=0x0) // NART
    • [3]RFLM (def=0x0) // RFLM
    • [2]TXFP (def=0x0) // TXFP
    • [1]SLEEP (def=0x0) // SLEEP
    • [0]INRQ (def=0x0) // INRQ
  • 0x40006404CAN_MSR// CAN_MSR

    • [11]RX (def=0x0) // RX
    • [10]SAMP (def=0x0) // SAMP
    • [9]RXM (def=0x0) // RXM
    • [8]TXM (def=0x0) // TXM
    • [4]SLAKI (def=0x0) // SLAKI
    • [3]WKUI (def=0x0) // WKUI
    • [2]ERRI (def=0x0) // ERRI
    • [1]SLAK (def=0x0) // SLAK
    • [0]INAK (def=0x0) // INAK
  • 0x40006408CAN_TSR// CAN_TSR

    • [31]LOW2 (def=0x0) // Lowest priority flag for mailbox 2
    • [30]LOW1 (def=0x0) // Lowest priority flag for mailbox 1
    • [29]LOW0 (def=0x0) // Lowest priority flag for mailbox 0
    • [28]TME2 (def=0x0) // Lowest priority flag for mailbox 2
    • [27]TME1 (def=0x0) // Lowest priority flag for mailbox 1
    • [26]TME0 (def=0x0) // Lowest priority flag for mailbox 0
    • [24:25]CODE (def=0x0) // CODE
    • [23]ABRQ2 (def=0x0) // ABRQ2
    • [19]TERR2 (def=0x0) // TERR2
    • [18]ALST2 (def=0x0) // ALST2
    • [17]TXOK2 (def=0x0) // TXOK2
    • [16]RQCP2 (def=0x0) // RQCP2
    • [15]ABRQ1 (def=0x0) // ABRQ1
    • [11]TERR1 (def=0x0) // TERR1
    • [10]ALST1 (def=0x0) // ALST1
    • [9]TXOK1 (def=0x0) // TXOK1
    • [8]RQCP1 (def=0x0) // RQCP1
    • [7]ABRQ0 (def=0x0) // ABRQ0
    • [3]TERR0 (def=0x0) // TERR0
    • [2]ALST0 (def=0x0) // ALST0
    • [1]TXOK0 (def=0x0) // TXOK0
    • [0]RQCP0 (def=0x0) // RQCP0
  • 0x4000640CCAN_RF0R// CAN_RF0R

    • [5]RFOM0 (def=0x0) // RFOM0
    • [4]FOVR0 (def=0x0) // FOVR0
    • [3]FULL0 (def=0x0) // FULL0
    • [0:1]FMP0 (def=0x0) // FMP0
  • 0x40006410CAN_RF1R// CAN_RF1R

    • [5]RFOM1 (def=0x0) // RFOM1
    • [4]FOVR1 (def=0x0) // FOVR1
    • [3]FULL1 (def=0x0) // FULL1
    • [0:1]FMP1 (def=0x0) // FMP1
  • 0x40006414CAN_IER// CAN_IER

    • [17]SLKIE (def=0x0) // SLKIE
    • [16]WKUIE (def=0x0) // WKUIE
    • [15]ERRIE (def=0x0) // ERRIE
    • [11]LECIE (def=0x0) // LECIE
    • [10]BOFIE (def=0x0) // BOFIE
    • [9]EPVIE (def=0x0) // EPVIE
    • [8]EWGIE (def=0x0) // EWGIE
    • [6]FOVIE1 (def=0x0) // FOVIE1
    • [5]FFIE1 (def=0x0) // FFIE1
    • [4]FMPIE1 (def=0x0) // FMPIE1
    • [3]FOVIE0 (def=0x0) // FOVIE0
    • [2]FFIE0 (def=0x0) // FFIE0
    • [1]FMPIE0 (def=0x0) // FMPIE0
    • [0]TMEIE (def=0x0) // TMEIE
  • 0x40006418CAN_ESR// CAN_ESR

    • [24:31]REC (def=0x0) // REC
    • [16:23]TEC (def=0x0) // TEC
    • [4:6]LEC (def=0x0) // LEC
    • [2]BOFF (def=0x0) // BOFF
    • [1]EPVF (def=0x0) // EPVF
    • [0]EWGF (def=0x0) // EWGF
  • 0x4000641CCAN_BTR// CAN_BTR

    • [31]SILM (def=0x0) // SILM
    • [30]LBKM (def=0x0) // LBKM
    • [24:25]SJW (def=0x0) // SJW
    • [20:22]TS2 (def=0x0) // TS2
    • [16:19]TS1 (def=0x0) // TS1
    • [0:9]BRP (def=0x0) // BRP
  • 0x40006580CAN_TI0R// CAN_TI0R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
    • [0]TXRQ (def=0x0) // TXRQ
  • 0x40006584CAN_TDT0R// CAN_TDT0R

    • [16:31]TIME (def=0x0) // TIME
    • [8]TGT (def=0x0) // TGT
    • [0:3]DLC (def=0x0) // DLC
  • 0x40006588CAN_TDL0R// CAN_TDL0R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x4000658CCAN_TDH0R// CAN_TDH0R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x40006590CAN_TI1R// CAN_TI1R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
    • [0]TXRQ (def=0x0) // TXRQ
  • 0x40006594CAN_TDT1R// CAN_TDT1R

    • [16:31]TIME (def=0x0) // TIME
    • [8]TGT (def=0x0) // TGT
    • [0:3]DLC (def=0x0) // DLC
  • 0x40006598CAN_TDL1R// CAN_TDL1R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x4000659CCAN_TDH1R// CAN_TDH1R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x400065A0CAN_TI2R// CAN_TI2R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
    • [0]TXRQ (def=0x0) // TXRQ
  • 0x400065A4CAN_TDT2R// CAN_TDT2R

    • [16:31]TIME (def=0x0) // TIME
    • [8]TGT (def=0x0) // TGT
    • [0:3]DLC (def=0x0) // DLC
  • 0x400065A8CAN_TDL2R// CAN_TDL2R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x400065ACCAN_TDH2R// CAN_TDH2R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x400065B0CAN_RI0R// CAN_RI0R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
  • 0x400065B4CAN_RDT0R// CAN_RDT0R

    • [16:31]TIME (def=0x0) // TIME
    • [8:15]FMI (def=0x0) // FMI
    • [0:3]DLC (def=0x0) // DLC
  • 0x400065B8CAN_RDL0R// CAN_RDL0R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x400065BCCAN_RDH0R// CAN_RDH0R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x400065C0CAN_RI1R// CAN_RI1R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
  • 0x400065C4CAN_RDT1R// CAN_RDT1R

    • [16:31]TIME (def=0x0) // TIME
    • [8:15]FMI (def=0x0) // FMI
    • [0:3]DLC (def=0x0) // DLC
  • 0x400065C8CAN_RDL1R// CAN_RDL1R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x400065CCCAN_RDH1R// CAN_RDH1R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x40006600CAN_FMR// CAN_FMR

    • [0]FINIT (def=0x0) // FINIT
  • 0x40006604CAN_FM1R// CAN_FM1R

    • [0]FBM0 (def=0x0) // Filter mode
    • [1]FBM1 (def=0x0) // Filter mode
    • [2]FBM2 (def=0x0) // Filter mode
    • [3]FBM3 (def=0x0) // Filter mode
    • [4]FBM4 (def=0x0) // Filter mode
    • [5]FBM5 (def=0x0) // Filter mode
    • [6]FBM6 (def=0x0) // Filter mode
    • [7]FBM7 (def=0x0) // Filter mode
    • [8]FBM8 (def=0x0) // Filter mode
    • [9]FBM9 (def=0x0) // Filter mode
    • [10]FBM10 (def=0x0) // Filter mode
    • [11]FBM11 (def=0x0) // Filter mode
    • [12]FBM12 (def=0x0) // Filter mode
    • [13]FBM13 (def=0x0) // Filter mode
  • 0x4000660CCAN_FS1R// CAN_FS1R

    • [0]FSC0 (def=0x0) // Filter scale configuration
    • [1]FSC1 (def=0x0) // Filter scale configuration
    • [2]FSC2 (def=0x0) // Filter scale configuration
    • [3]FSC3 (def=0x0) // Filter scale configuration
    • [4]FSC4 (def=0x0) // Filter scale configuration
    • [5]FSC5 (def=0x0) // Filter scale configuration
    • [6]FSC6 (def=0x0) // Filter scale configuration
    • [7]FSC7 (def=0x0) // Filter scale configuration
    • [8]FSC8 (def=0x0) // Filter scale configuration
    • [9]FSC9 (def=0x0) // Filter scale configuration
    • [10]FSC10 (def=0x0) // Filter scale configuration
    • [11]FSC11 (def=0x0) // Filter scale configuration
    • [12]FSC12 (def=0x0) // Filter scale configuration
    • [13]FSC13 (def=0x0) // Filter scale configuration
  • 0x40006614CAN_FFA1R// CAN_FFA1R

    • [0]FFA0 (def=0x0) // Filter FIFO assignment for filter 0
    • [1]FFA1 (def=0x0) // Filter FIFO assignment for filter 1
    • [2]FFA2 (def=0x0) // Filter FIFO assignment for filter 2
    • [3]FFA3 (def=0x0) // Filter FIFO assignment for filter 3
    • [4]FFA4 (def=0x0) // Filter FIFO assignment for filter 4
    • [5]FFA5 (def=0x0) // Filter FIFO assignment for filter 5
    • [6]FFA6 (def=0x0) // Filter FIFO assignment for filter 6
    • [7]FFA7 (def=0x0) // Filter FIFO assignment for filter 7
    • [8]FFA8 (def=0x0) // Filter FIFO assignment for filter 8
    • [9]FFA9 (def=0x0) // Filter FIFO assignment for filter 9
    • [10]FFA10 (def=0x0) // Filter FIFO assignment for filter 10
    • [11]FFA11 (def=0x0) // Filter FIFO assignment for filter 11
    • [12]FFA12 (def=0x0) // Filter FIFO assignment for filter 12
    • [13]FFA13 (def=0x0) // Filter FIFO assignment for filter 13
  • 0x4000661CCAN_FA1R// CAN_FA1R

    • [0]FACT0 (def=0x0) // Filter active
    • [1]FACT1 (def=0x0) // Filter active
    • [2]FACT2 (def=0x0) // Filter active
    • [3]FACT3 (def=0x0) // Filter active
    • [4]FACT4 (def=0x0) // Filter active
    • [5]FACT5 (def=0x0) // Filter active
    • [6]FACT6 (def=0x0) // Filter active
    • [7]FACT7 (def=0x0) // Filter active
    • [8]FACT8 (def=0x0) // Filter active
    • [9]FACT9 (def=0x0) // Filter active
    • [10]FACT10 (def=0x0) // Filter active
    • [11]FACT11 (def=0x0) // Filter active
    • [12]FACT12 (def=0x0) // Filter active
    • [13]FACT13 (def=0x0) // Filter active
  • 0x40006640F0R1// Filter bank 0 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006644F0R2// Filter bank 0 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006648F1R1// Filter bank 1 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x4000664CF1R2// Filter bank 1 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006650F2R1// Filter bank 2 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006654F2R2// Filter bank 2 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006658F3R1// Filter bank 3 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x4000665CF3R2// Filter bank 3 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006660F4R1// Filter bank 4 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006664F4R2// Filter bank 4 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006668F5R1// Filter bank 5 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x4000666CF5R2// Filter bank 5 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006670F6R1// Filter bank 6 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006674F6R2// Filter bank 6 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006678F7R1// Filter bank 7 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x4000667CF7R2// Filter bank 7 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006680F8R1// Filter bank 8 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006684F8R2// Filter bank 8 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006688F9R1// Filter bank 9 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x4000668CF9R2// Filter bank 9 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006690F10R1// Filter bank 10 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006694F10R2// Filter bank 10 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006698F11R1// Filter bank 11 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x4000669CF11R2// Filter bank 11 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x400066A0F12R1// Filter bank 4 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x400066A4F12R2// Filter bank 12 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x400066A8F13R1// Filter bank 13 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x400066ACF13R2// Filter bank 13 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  interrupts:
  • [21] CAN_RX1 // CAN RX1 interrupt
  • [22] CAN_SCE // CAN SCE interrupt
  • [22] CAN_SCE // CAN SCE interrupt
• 0x40006800CAN2//

  • 0x40006800CAN_MCR// CAN_MCR

    • [16]DBF (def=0x0) // DBF
    • [15]RESET (def=0x0) // RESET
    • [7]TTCM (def=0x0) // TTCM
    • [6]ABOM (def=0x0) // ABOM
    • [5]AWUM (def=0x0) // AWUM
    • [4]NART (def=0x0) // NART
    • [3]RFLM (def=0x0) // RFLM
    • [2]TXFP (def=0x0) // TXFP
    • [1]SLEEP (def=0x0) // SLEEP
    • [0]INRQ (def=0x0) // INRQ
  • 0x40006804CAN_MSR// CAN_MSR

    • [11]RX (def=0x0) // RX
    • [10]SAMP (def=0x0) // SAMP
    • [9]RXM (def=0x0) // RXM
    • [8]TXM (def=0x0) // TXM
    • [4]SLAKI (def=0x0) // SLAKI
    • [3]WKUI (def=0x0) // WKUI
    • [2]ERRI (def=0x0) // ERRI
    • [1]SLAK (def=0x0) // SLAK
    • [0]INAK (def=0x0) // INAK
  • 0x40006808CAN_TSR// CAN_TSR

    • [31]LOW2 (def=0x0) // Lowest priority flag for mailbox 2
    • [30]LOW1 (def=0x0) // Lowest priority flag for mailbox 1
    • [29]LOW0 (def=0x0) // Lowest priority flag for mailbox 0
    • [28]TME2 (def=0x0) // Lowest priority flag for mailbox 2
    • [27]TME1 (def=0x0) // Lowest priority flag for mailbox 1
    • [26]TME0 (def=0x0) // Lowest priority flag for mailbox 0
    • [24:25]CODE (def=0x0) // CODE
    • [23]ABRQ2 (def=0x0) // ABRQ2
    • [19]TERR2 (def=0x0) // TERR2
    • [18]ALST2 (def=0x0) // ALST2
    • [17]TXOK2 (def=0x0) // TXOK2
    • [16]RQCP2 (def=0x0) // RQCP2
    • [15]ABRQ1 (def=0x0) // ABRQ1
    • [11]TERR1 (def=0x0) // TERR1
    • [10]ALST1 (def=0x0) // ALST1
    • [9]TXOK1 (def=0x0) // TXOK1
    • [8]RQCP1 (def=0x0) // RQCP1
    • [7]ABRQ0 (def=0x0) // ABRQ0
    • [3]TERR0 (def=0x0) // TERR0
    • [2]ALST0 (def=0x0) // ALST0
    • [1]TXOK0 (def=0x0) // TXOK0
    • [0]RQCP0 (def=0x0) // RQCP0
  • 0x4000680CCAN_RF0R// CAN_RF0R

    • [5]RFOM0 (def=0x0) // RFOM0
    • [4]FOVR0 (def=0x0) // FOVR0
    • [3]FULL0 (def=0x0) // FULL0
    • [0:1]FMP0 (def=0x0) // FMP0
  • 0x40006810CAN_RF1R// CAN_RF1R

    • [5]RFOM1 (def=0x0) // RFOM1
    • [4]FOVR1 (def=0x0) // FOVR1
    • [3]FULL1 (def=0x0) // FULL1
    • [0:1]FMP1 (def=0x0) // FMP1
  • 0x40006814CAN_IER// CAN_IER

    • [17]SLKIE (def=0x0) // SLKIE
    • [16]WKUIE (def=0x0) // WKUIE
    • [15]ERRIE (def=0x0) // ERRIE
    • [11]LECIE (def=0x0) // LECIE
    • [10]BOFIE (def=0x0) // BOFIE
    • [9]EPVIE (def=0x0) // EPVIE
    • [8]EWGIE (def=0x0) // EWGIE
    • [6]FOVIE1 (def=0x0) // FOVIE1
    • [5]FFIE1 (def=0x0) // FFIE1
    • [4]FMPIE1 (def=0x0) // FMPIE1
    • [3]FOVIE0 (def=0x0) // FOVIE0
    • [2]FFIE0 (def=0x0) // FFIE0
    • [1]FMPIE0 (def=0x0) // FMPIE0
    • [0]TMEIE (def=0x0) // TMEIE
  • 0x40006818CAN_ESR// CAN_ESR

    • [24:31]REC (def=0x0) // REC
    • [16:23]TEC (def=0x0) // TEC
    • [4:6]LEC (def=0x0) // LEC
    • [2]BOFF (def=0x0) // BOFF
    • [1]EPVF (def=0x0) // EPVF
    • [0]EWGF (def=0x0) // EWGF
  • 0x4000681CCAN_BTR// CAN_BTR

    • [31]SILM (def=0x0) // SILM
    • [30]LBKM (def=0x0) // LBKM
    • [24:25]SJW (def=0x0) // SJW
    • [20:22]TS2 (def=0x0) // TS2
    • [16:19]TS1 (def=0x0) // TS1
    • [0:9]BRP (def=0x0) // BRP
  • 0x40006980CAN_TI0R// CAN_TI0R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
    • [0]TXRQ (def=0x0) // TXRQ
  • 0x40006984CAN_TDT0R// CAN_TDT0R

    • [16:31]TIME (def=0x0) // TIME
    • [8]TGT (def=0x0) // TGT
    • [0:3]DLC (def=0x0) // DLC
  • 0x40006988CAN_TDL0R// CAN_TDL0R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x4000698CCAN_TDH0R// CAN_TDH0R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x40006990CAN_TI1R// CAN_TI1R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
    • [0]TXRQ (def=0x0) // TXRQ
  • 0x40006994CAN_TDT1R// CAN_TDT1R

    • [16:31]TIME (def=0x0) // TIME
    • [8]TGT (def=0x0) // TGT
    • [0:3]DLC (def=0x0) // DLC
  • 0x40006998CAN_TDL1R// CAN_TDL1R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x4000699CCAN_TDH1R// CAN_TDH1R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x400069A0CAN_TI2R// CAN_TI2R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
    • [0]TXRQ (def=0x0) // TXRQ
  • 0x400069A4CAN_TDT2R// CAN_TDT2R

    • [16:31]TIME (def=0x0) // TIME
    • [8]TGT (def=0x0) // TGT
    • [0:3]DLC (def=0x0) // DLC
  • 0x400069A8CAN_TDL2R// CAN_TDL2R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x400069ACCAN_TDH2R// CAN_TDH2R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x400069B0CAN_RI0R// CAN_RI0R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
  • 0x400069B4CAN_RDT0R// CAN_RDT0R

    • [16:31]TIME (def=0x0) // TIME
    • [8:15]FMI (def=0x0) // FMI
    • [0:3]DLC (def=0x0) // DLC
  • 0x400069B8CAN_RDL0R// CAN_RDL0R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x400069BCCAN_RDH0R// CAN_RDH0R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x400069C0CAN_RI1R// CAN_RI1R

    • [21:31]STID (def=0x0) // STID
    • [3:20]EXID (def=0x0) // EXID
    • [2]IDE (def=0x0) // IDE
    • [1]RTR (def=0x0) // RTR
  • 0x400069C4CAN_RDT1R// CAN_RDT1R

    • [16:31]TIME (def=0x0) // TIME
    • [8:15]FMI (def=0x0) // FMI
    • [0:3]DLC (def=0x0) // DLC
  • 0x400069C8CAN_RDL1R// CAN_RDL1R

    • [24:31]DATA3 (def=0x0) // DATA3
    • [16:23]DATA2 (def=0x0) // DATA2
    • [8:15]DATA1 (def=0x0) // DATA1
    • [0:7]DATA0 (def=0x0) // DATA0
  • 0x400069CCCAN_RDH1R// CAN_RDH1R

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  • 0x40006A00CAN_FMR// CAN_FMR

    • [0]FINIT (def=0x0) // FINIT
  • 0x40006A04CAN_FM1R// CAN_FM1R

    • [0]FBM0 (def=0x0) // Filter mode
    • [1]FBM1 (def=0x0) // Filter mode
    • [2]FBM2 (def=0x0) // Filter mode
    • [3]FBM3 (def=0x0) // Filter mode
    • [4]FBM4 (def=0x0) // Filter mode
    • [5]FBM5 (def=0x0) // Filter mode
    • [6]FBM6 (def=0x0) // Filter mode
    • [7]FBM7 (def=0x0) // Filter mode
    • [8]FBM8 (def=0x0) // Filter mode
    • [9]FBM9 (def=0x0) // Filter mode
    • [10]FBM10 (def=0x0) // Filter mode
    • [11]FBM11 (def=0x0) // Filter mode
    • [12]FBM12 (def=0x0) // Filter mode
    • [13]FBM13 (def=0x0) // Filter mode
  • 0x40006A0CCAN_FS1R// CAN_FS1R

    • [0]FSC0 (def=0x0) // Filter scale configuration
    • [1]FSC1 (def=0x0) // Filter scale configuration
    • [2]FSC2 (def=0x0) // Filter scale configuration
    • [3]FSC3 (def=0x0) // Filter scale configuration
    • [4]FSC4 (def=0x0) // Filter scale configuration
    • [5]FSC5 (def=0x0) // Filter scale configuration
    • [6]FSC6 (def=0x0) // Filter scale configuration
    • [7]FSC7 (def=0x0) // Filter scale configuration
    • [8]FSC8 (def=0x0) // Filter scale configuration
    • [9]FSC9 (def=0x0) // Filter scale configuration
    • [10]FSC10 (def=0x0) // Filter scale configuration
    • [11]FSC11 (def=0x0) // Filter scale configuration
    • [12]FSC12 (def=0x0) // Filter scale configuration
    • [13]FSC13 (def=0x0) // Filter scale configuration
  • 0x40006A14CAN_FFA1R// CAN_FFA1R

    • [0]FFA0 (def=0x0) // Filter FIFO assignment for filter 0
    • [1]FFA1 (def=0x0) // Filter FIFO assignment for filter 1
    • [2]FFA2 (def=0x0) // Filter FIFO assignment for filter 2
    • [3]FFA3 (def=0x0) // Filter FIFO assignment for filter 3
    • [4]FFA4 (def=0x0) // Filter FIFO assignment for filter 4
    • [5]FFA5 (def=0x0) // Filter FIFO assignment for filter 5
    • [6]FFA6 (def=0x0) // Filter FIFO assignment for filter 6
    • [7]FFA7 (def=0x0) // Filter FIFO assignment for filter 7
    • [8]FFA8 (def=0x0) // Filter FIFO assignment for filter 8
    • [9]FFA9 (def=0x0) // Filter FIFO assignment for filter 9
    • [10]FFA10 (def=0x0) // Filter FIFO assignment for filter 10
    • [11]FFA11 (def=0x0) // Filter FIFO assignment for filter 11
    • [12]FFA12 (def=0x0) // Filter FIFO assignment for filter 12
    • [13]FFA13 (def=0x0) // Filter FIFO assignment for filter 13
  • 0x40006A1CCAN_FA1R// CAN_FA1R

    • [0]FACT0 (def=0x0) // Filter active
    • [1]FACT1 (def=0x0) // Filter active
    • [2]FACT2 (def=0x0) // Filter active
    • [3]FACT3 (def=0x0) // Filter active
    • [4]FACT4 (def=0x0) // Filter active
    • [5]FACT5 (def=0x0) // Filter active
    • [6]FACT6 (def=0x0) // Filter active
    • [7]FACT7 (def=0x0) // Filter active
    • [8]FACT8 (def=0x0) // Filter active
    • [9]FACT9 (def=0x0) // Filter active
    • [10]FACT10 (def=0x0) // Filter active
    • [11]FACT11 (def=0x0) // Filter active
    • [12]FACT12 (def=0x0) // Filter active
    • [13]FACT13 (def=0x0) // Filter active
  • 0x40006A40F0R1// Filter bank 0 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A44F0R2// Filter bank 0 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A48F1R1// Filter bank 1 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A4CF1R2// Filter bank 1 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A50F2R1// Filter bank 2 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A54F2R2// Filter bank 2 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A58F3R1// Filter bank 3 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A5CF3R2// Filter bank 3 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A60F4R1// Filter bank 4 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A64F4R2// Filter bank 4 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A68F5R1// Filter bank 5 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A6CF5R2// Filter bank 5 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A70F6R1// Filter bank 6 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A74F6R2// Filter bank 6 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A78F7R1// Filter bank 7 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A7CF7R2// Filter bank 7 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A80F8R1// Filter bank 8 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A84F8R2// Filter bank 8 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A88F9R1// Filter bank 9 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A8CF9R2// Filter bank 9 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A90F10R1// Filter bank 10 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A94F10R2// Filter bank 10 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A98F11R1// Filter bank 11 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006A9CF11R2// Filter bank 11 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006AA0F12R1// Filter bank 4 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006AA4F12R2// Filter bank 12 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006AA8F13R1// Filter bank 13 register 1

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
  • 0x40006AACF13R2// Filter bank 13 register 2

    • [0]FB0 (def=0x0) // Filter bits
    • [1]FB1 (def=0x0) // Filter bits
    • [2]FB2 (def=0x0) // Filter bits
    • [3]FB3 (def=0x0) // Filter bits
    • [4]FB4 (def=0x0) // Filter bits
    • [5]FB5 (def=0x0) // Filter bits
    • [6]FB6 (def=0x0) // Filter bits
    • [7]FB7 (def=0x0) // Filter bits
    • [8]FB8 (def=0x0) // Filter bits
    • [9]FB9 (def=0x0) // Filter bits
    • [10]FB10 (def=0x0) // Filter bits
    • [11]FB11 (def=0x0) // Filter bits
    • [12]FB12 (def=0x0) // Filter bits
    • [13]FB13 (def=0x0) // Filter bits
    • [14]FB14 (def=0x0) // Filter bits
    • [15]FB15 (def=0x0) // Filter bits
    • [16]FB16 (def=0x0) // Filter bits
    • [17]FB17 (def=0x0) // Filter bits
    • [18]FB18 (def=0x0) // Filter bits
    • [19]FB19 (def=0x0) // Filter bits
    • [20]FB20 (def=0x0) // Filter bits
    • [21]FB21 (def=0x0) // Filter bits
    • [22]FB22 (def=0x0) // Filter bits
    • [23]FB23 (def=0x0) // Filter bits
    • [24]FB24 (def=0x0) // Filter bits
    • [25]FB25 (def=0x0) // Filter bits
    • [26]FB26 (def=0x0) // Filter bits
    • [27]FB27 (def=0x0) // Filter bits
    • [28]FB28 (def=0x0) // Filter bits
    • [29]FB29 (def=0x0) // Filter bits
    • [30]FB30 (def=0x0) // Filter bits
    • [31]FB31 (def=0x0) // Filter bits
• 0x40007400DAC// Digital to analog converter

  • 0x40007400CR// Control register (DAC_CR)

    • [0]EN1 (def=0x0) // DAC channel1 enable
    • [1]BOFF1 (def=0x0) // DAC channel1 output buffer disable
    • [2]TEN1 (def=0x0) // DAC channel1 trigger enable
    • [3:5]TSEL1 (def=0x0) // DAC channel1 trigger selection
    • [6:7]WAVE1 (def=0x0) // DAC channel1 noise/triangle wave generation enable
    • [8:11]MAMP1 (def=0x0) // DAC channel1 mask/amplitude selector
    • [12]DMAEN1 (def=0x0) // DAC channel1 DMA enable
    • [16]EN2 (def=0x0) // DAC channel2 enable
    • [17]BOFF2 (def=0x0) // DAC channel2 output buffer disable
    • [18]TEN2 (def=0x0) // DAC channel2 trigger enable
    • [19:21]TSEL2 (def=0x0) // DAC channel2 trigger selection
    • [22:23]WAVE2 (def=0x0) // DAC channel2 noise/triangle wave generation enable
    • [24:27]MAMP2 (def=0x0) // DAC channel2 mask/amplitude selector
    • [28]DMAEN2 (def=0x0) // DAC channel2 DMA enable
  • 0x40007404SWTRIGR// DAC software trigger register (DAC_SWTRIGR)

    • [0]SWTRIG1 (def=0x0) // DAC channel1 software trigger
    • [1]SWTRIG2 (def=0x0) // DAC channel2 software trigger
  • 0x40007408DHR12R1// DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)

    • [0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
  • 0x4000740CDHR12L1// DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)

    • [4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
  • 0x40007410DHR8R1// DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)

    • [0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
  • 0x40007414DHR12R2// DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)

    • [0:11]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x40007418DHR12L2// DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)

    • [4:15]DACC2DHR (def=0x0) // DAC channel2 12-bit left-aligned data
  • 0x4000741CDHR8R2// DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)

    • [0:7]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
  • 0x40007420DHR12RD// Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, B

    • [0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
    • [16:27]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x40007424DHR12LD// DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bi

    • [4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
    • [20:31]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x40007428DHR8RD// DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

    • [0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
    • [8:15]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
  • 0x4000742CDOR1// DAC channel1 data output register (DAC_DOR1)

    • [0:11]DACC1DOR (def=0x0) // DAC channel1 data output
  • 0x40007430DOR2// DAC channel2 data output register (DAC_DOR2)

    • [0:11]DACC2DOR (def=0x0) // DAC channel2 data output
• 0xE0042000DBG// Debug support

  • 0xE0042000IDCODE// DBGMCU_IDCODE

    • [0:11]DEV_ID (def=0x0) // DEV_ID
    • [16:31]REV_ID (def=0x0) // REV_ID
  • 0xE0042004CR// DBGMCU_CR

    • [0]DBG_SLEEP (def=0x0) // DBG_SLEEP
    • [1]DBG_STOP (def=0x0) // DBG_STOP
    • [2]DBG_STANDBY (def=0x0) // DBG_STANDBY
    • [5]TRACE_IOEN (def=0x0) // TRACE_IOEN
    • [6:7]TRACE_MODE (def=0x0) // TRACE_MODE
    • [8]DBG_IWDG_STOP (def=0x0) // DBG_IWDG_STOP
    • [9]DBG_WWDG_STOP (def=0x0) // DBG_WWDG_STOP
    • [10]DBG_TIM1_STOP (def=0x0) // DBG_TIM1_STOP
    • [11]DBG_TIM2_STOP (def=0x0) // DBG_TIM2_STOP
    • [12]DBG_TIM3_STOP (def=0x0) // DBG_TIM3_STOP
    • [13]DBG_TIM4_STOP (def=0x0) // DBG_TIM4_STOP
    • [14]DBG_CAN1_STOP (def=0x0) // DBG_CAN1_STOP
    • [15]DBG_I2C1_SMBUS_TIMEOUT (def=0x0) // DBG_I2C1_SMBUS_TIMEOUT
    • [16]DBG_I2C2_SMBUS_TIMEOUT (def=0x0) // DBG_I2C2_SMBUS_TIMEOUT
    • [17]DBG_TIM8_STOP (def=0x0) // DBG_TIM8_STOP
    • [18]DBG_TIM5_STOP (def=0x0) // DBG_TIM5_STOP
    • [19]DBG_TIM6_STOP (def=0x0) // DBG_TIM6_STOP
    • [20]DBG_TIM7_STOP (def=0x0) // DBG_TIM7_STOP
    • [21]DBG_CAN2_STOP (def=0x0) // DBG_CAN2_STOP
• 0x40004C00UART4// Universal asynchronous receiver transmitter

  • 0x40004C00SR// UART4_SR

    • [0]PE (def=0x0) // Parity error
    • [1]FE (def=0x0) // Framing error
    • [2]NE (def=0x0) // Noise error flag
    • [3]ORE (def=0x0) // Overrun error
    • [4]IDLE (def=0x0) // IDLE line detected
    • [5]RXNE (def=0x0) // Read data register not empty
    • [6]TC (def=0x0) // Transmission complete
    • [7]TXE (def=0x0) // Transmit data register empty
    • [8]LBD (def=0x0) // LIN break detection flag
  • 0x40004C04DR// UART4_DR

    • [0:8]DR (def=0x0) // DR
  • 0x40004C08BRR// UART4_BRR

    • [0:3]DIV_Fraction (def=0x0) // DIV_Fraction
    • [4:15]DIV_Mantissa (def=0x0) // DIV_Mantissa
  • 0x40004C0CCR1// UART4_CR1

    • [0]SBK (def=0x0) // Send break
    • [1]RWU (def=0x0) // Receiver wakeup
    • [2]RE (def=0x0) // Receiver enable
    • [3]TE (def=0x0) // Transmitter enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [9]PS (def=0x0) // Parity selection
    • [10]PCE (def=0x0) // Parity control enable
    • [11]WAKE (def=0x0) // Wakeup method
    • [12]M (def=0x0) // Word length
    • [13]UE (def=0x0) // USART enable
  • 0x40004C10CR2// UART4_CR2

    • [0:3]ADD (def=0x0) // Address of the USART node
    • [5]LBDL (def=0x0) // lin break detection length
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [14]LINEN (def=0x0) // LIN mode enable
  • 0x40004C14CR3// UART4_CR3

    • [0]EIE (def=0x0) // Error interrupt enable
    • [1]IREN (def=0x0) // IrDA mode enable
    • [2]IRLP (def=0x0) // IrDA low-power
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [7]DMAT (def=0x0) // DMA enable transmitter
  interrupts:
  • [52] UART4 // UART4 global interrupt
• 0x40005000UART5// Universal asynchronous receiver transmitter

  • 0x40005000SR// UART4_SR

    • [0]PE (def=0x0) // PE
    • [1]FE (def=0x0) // FE
    • [2]NE (def=0x0) // NE
    • [3]ORE (def=0x0) // ORE
    • [4]IDLE (def=0x0) // IDLE
    • [5]RXNE (def=0x0) // RXNE
    • [6]TC (def=0x0) // TC
    • [7]TXE (def=0x0) // TXE
    • [8]LBD (def=0x0) // LBD
  • 0x40005004DR// UART4_DR

    • [0:8]DR (def=0x0) // DR
  • 0x40005008BRR// UART4_BRR

    • [0:3]DIV_Fraction (def=0x0) // DIV_Fraction
    • [4:15]DIV_Mantissa (def=0x0) // DIV_Mantissa
  • 0x4000500CCR1// UART4_CR1

    • [0]SBK (def=0x0) // SBK
    • [1]RWU (def=0x0) // RWU
    • [2]RE (def=0x0) // RE
    • [3]TE (def=0x0) // TE
    • [4]IDLEIE (def=0x0) // IDLEIE
    • [5]RXNEIE (def=0x0) // RXNEIE
    • [6]TCIE (def=0x0) // TCIE
    • [7]TXEIE (def=0x0) // TXEIE
    • [8]PEIE (def=0x0) // PEIE
    • [9]PS (def=0x0) // PS
    • [10]PCE (def=0x0) // PCE
    • [11]WAKE (def=0x0) // WAKE
    • [12]M (def=0x0) // M
    • [13]UE (def=0x0) // UE
  • 0x40005010CR2// UART4_CR2

    • [0:3]ADD (def=0x0) // ADD
    • [5]LBDL (def=0x0) // LBDL
    • [6]LBDIE (def=0x0) // LBDIE
    • [12:13]STOP (def=0x0) // STOP
    • [14]LINEN (def=0x0) // LINEN
  • 0x40005014CR3// UART4_CR3

    • [0]EIE (def=0x0) // Error interrupt enable
    • [1]IREN (def=0x0) // IrDA mode enable
    • [2]IRLP (def=0x0) // IrDA low-power
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [7]DMAT (def=0x0) // DMA enable transmitter
  interrupts:
  • [53] UART5 // UART5 global interrupt
• 0x40023000CRC// CRC calculation unit

  • 0x40023000DR// Data register

    • [0:31]DR (def=0xFFFFFFFF) // Data Register
  • 0x40023004IDR// Independent Data register

    • [0:7]IDR (def=0x0) // Independent Data register
  • 0x40023008CR// Control register

    • [0]RESET (def=0x0) // Reset bit
• 0x40022000FLASH// FLASH

  • 0x40022000ACR// Flash access control register

    • [0:2]LATENCY (def=0x0) // Latency
    • [3]HLFCYA (def=0x0) // Flash half cycle access enable
    • [4]PRFTBE (def=0x1) // Prefetch buffer enable
    • [5]PRFTBS (def=0x1) // Prefetch buffer status
  • 0x40022004KEYR// Flash key register

    • [0:31]KEY (def=0x0) // FPEC key
  • 0x40022008OPTKEYR// Flash option key register

    • [0:31]OPTKEY (def=0x0) // Option byte key
  • 0x4002200CSR// Status register

    • [5]EOP (def=0x0) // End of operation
    • [4]WRPRTERR (def=0x0) // Write protection error
    • [2]PGERR (def=0x0) // Programming error
    • [0]BSY (def=0x0) // Busy
  • 0x40022010CR// Control register

    • [0]PG (def=0x0) // Programming
    • [1]PER (def=0x0) // Page Erase
    • [2]MER (def=0x0) // Mass Erase
    • [4]OPTPG (def=0x0) // Option byte programming
    • [5]OPTER (def=0x0) // Option byte erase
    • [6]STRT (def=0x0) // Start
    • [7]LOCK (def=0x1) // Lock
    • [9]OPTWRE (def=0x0) // Option bytes write enable
    • [10]ERRIE (def=0x0) // Error interrupt enable
    • [12]EOPIE (def=0x0) // End of operation interrupt enable
  • 0x40022014AR// Flash address register

    • [0:31]FAR (def=0x0) // Flash Address
  • 0x4002201COBR// Option byte register

    • [0]OPTERR (def=0x0) // Option byte error
    • [1]RDPRT (def=0x0) // Read protection
    • [2]WDG_SW (def=0x1) // WDG_SW
    • [3]nRST_STOP (def=0x1) // nRST_STOP
    • [4]nRST_STDBY (def=0x1) // nRST_STDBY
    • [10:17]Data0 (def=0xFF) // Data0
    • [18:25]Data1 (def=0xFF) // Data1
  • 0x40022020WRPR// Write protection register

    • [0:31]WRP (def=0xFFFFFFFF) // Write protect
  interrupts:
  • [4] FLASH // Flash global interrupt
• 0xE000E000NVIC// Nested Vectored Interrupt Controller

  • 0xE000E004ICTR// Interrupt Controller Type Register

    • [0:3]INTLINESNUM (def=0x0) // Total number of interrupt lines in groups
  • 0xE000EF00STIR// Software Triggered Interrupt Register

    • [0:8]INTID (def=0x0) // interrupt to be triggered
  • 0xE000E100ISER0// Interrupt Set-Enable Register

    • [0:31]SETENA (def=0x0) // SETENA
  • 0xE000E104ISER1// Interrupt Set-Enable Register

    • [0:31]SETENA (def=0x0) // SETENA
  • 0xE000E180ICER0// Interrupt Clear-Enable Register

    • [0:31]CLRENA (def=0x0) // CLRENA
  • 0xE000E184ICER1// Interrupt Clear-Enable Register

    • [0:31]CLRENA (def=0x0) // CLRENA
  • 0xE000E200ISPR0// Interrupt Set-Pending Register

    • [0:31]SETPEND (def=0x0) // SETPEND
  • 0xE000E204ISPR1// Interrupt Set-Pending Register

    • [0:31]SETPEND (def=0x0) // SETPEND
  • 0xE000E280ICPR0// Interrupt Clear-Pending Register

    • [0:31]CLRPEND (def=0x0) // CLRPEND
  • 0xE000E284ICPR1// Interrupt Clear-Pending Register

    • [0:31]CLRPEND (def=0x0) // CLRPEND
  • 0xE000E300IABR0// Interrupt Active Bit Register

    • [0:31]ACTIVE (def=0x0) // ACTIVE
  • 0xE000E304IABR1// Interrupt Active Bit Register

    • [0:31]ACTIVE (def=0x0) // ACTIVE
  • 0xE000E400IPR0// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E404IPR1// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E408IPR2// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E40CIPR3// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E410IPR4// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E414IPR5// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E418IPR6// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E41CIPR7// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E420IPR8// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E424IPR9// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E428IPR10// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E42CIPR11// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E430IPR12// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E434IPR13// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
  • 0xE000E438IPR14// Interrupt Priority Register

    • [0:7]IPR_N0 (def=0x0) // IPR_N0
    • [8:15]IPR_N1 (def=0x0) // IPR_N1
    • [16:23]IPR_N2 (def=0x0) // IPR_N2
    • [24:31]IPR_N3 (def=0x0) // IPR_N3
• 0x40005C00USB// Universal serial bus full-speed device interface

  • 0x40005C00EP0R// endpoint 0 register

    • [0:3]EA (def=0x0) // Endpoint address
    • [4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
    • [6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
    • [7]CTR_TX (def=0x0) // Correct Transfer for transmission
    • [8]EP_KIND (def=0x0) // Endpoint kind
    • [9:10]EP_TYPE (def=0x0) // Endpoint type
    • [11]SETUP (def=0x0) // Setup transaction completed
    • [12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
    • [14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
    • [15]CTR_RX (def=0x0) // Correct transfer for reception
  • 0x40005C04EP1R// endpoint 1 register

    • [0:3]EA (def=0x0) // Endpoint address
    • [4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
    • [6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
    • [7]CTR_TX (def=0x0) // Correct Transfer for transmission
    • [8]EP_KIND (def=0x0) // Endpoint kind
    • [9:10]EP_TYPE (def=0x0) // Endpoint type
    • [11]SETUP (def=0x0) // Setup transaction completed
    • [12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
    • [14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
    • [15]CTR_RX (def=0x0) // Correct transfer for reception
  • 0x40005C08EP2R// endpoint 2 register

    • [0:3]EA (def=0x0) // Endpoint address
    • [4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
    • [6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
    • [7]CTR_TX (def=0x0) // Correct Transfer for transmission
    • [8]EP_KIND (def=0x0) // Endpoint kind
    • [9:10]EP_TYPE (def=0x0) // Endpoint type
    • [11]SETUP (def=0x0) // Setup transaction completed
    • [12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
    • [14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
    • [15]CTR_RX (def=0x0) // Correct transfer for reception
  • 0x40005C0CEP3R// endpoint 3 register

    • [0:3]EA (def=0x0) // Endpoint address
    • [4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
    • [6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
    • [7]CTR_TX (def=0x0) // Correct Transfer for transmission
    • [8]EP_KIND (def=0x0) // Endpoint kind
    • [9:10]EP_TYPE (def=0x0) // Endpoint type
    • [11]SETUP (def=0x0) // Setup transaction completed
    • [12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
    • [14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
    • [15]CTR_RX (def=0x0) // Correct transfer for reception
  • 0x40005C10EP4R// endpoint 4 register

    • [0:3]EA (def=0x0) // Endpoint address
    • [4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
    • [6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
    • [7]CTR_TX (def=0x0) // Correct Transfer for transmission
    • [8]EP_KIND (def=0x0) // Endpoint kind
    • [9:10]EP_TYPE (def=0x0) // Endpoint type
    • [11]SETUP (def=0x0) // Setup transaction completed
    • [12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
    • [14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
    • [15]CTR_RX (def=0x0) // Correct transfer for reception
  • 0x40005C14EP5R// endpoint 5 register

    • [0:3]EA (def=0x0) // Endpoint address
    • [4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
    • [6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
    • [7]CTR_TX (def=0x0) // Correct Transfer for transmission
    • [8]EP_KIND (def=0x0) // Endpoint kind
    • [9:10]EP_TYPE (def=0x0) // Endpoint type
    • [11]SETUP (def=0x0) // Setup transaction completed
    • [12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
    • [14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
    • [15]CTR_RX (def=0x0) // Correct transfer for reception
  • 0x40005C18EP6R// endpoint 6 register

    • [0:3]EA (def=0x0) // Endpoint address
    • [4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
    • [6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
    • [7]CTR_TX (def=0x0) // Correct Transfer for transmission
    • [8]EP_KIND (def=0x0) // Endpoint kind
    • [9:10]EP_TYPE (def=0x0) // Endpoint type
    • [11]SETUP (def=0x0) // Setup transaction completed
    • [12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
    • [14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
    • [15]CTR_RX (def=0x0) // Correct transfer for reception
  • 0x40005C1CEP7R// endpoint 7 register

    • [0:3]EA (def=0x0) // Endpoint address
    • [4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
    • [6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
    • [7]CTR_TX (def=0x0) // Correct Transfer for transmission
    • [8]EP_KIND (def=0x0) // Endpoint kind
    • [9:10]EP_TYPE (def=0x0) // Endpoint type
    • [11]SETUP (def=0x0) // Setup transaction completed
    • [12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
    • [14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
    • [15]CTR_RX (def=0x0) // Correct transfer for reception
  • 0x40005C40CNTR// control register

    • [0]FRES (def=0x1) // Force USB Reset
    • [1]PDWN (def=0x1) // Power down
    • [2]LPMODE (def=0x0) // Low-power mode
    • [3]FSUSP (def=0x0) // Force suspend
    • [4]RESUME (def=0x0) // Resume request
    • [8]ESOFM (def=0x0) // Expected start of frame interrupt mask
    • [9]SOFM (def=0x0) // Start of frame interrupt mask
    • [10]RESETM (def=0x0) // USB reset interrupt mask
    • [11]SUSPM (def=0x0) // Suspend mode interrupt mask
    • [12]WKUPM (def=0x0) // Wakeup interrupt mask
    • [13]ERRM (def=0x0) // Error interrupt mask
    • [14]PMAOVRM (def=0x0) // Packet memory area over / underrun interrupt mask
    • [15]CTRM (def=0x0) // Correct transfer interrupt mask
  • 0x40005C44ISTR// interrupt status register

    • [0:3]EP_ID (def=0x0) // Endpoint Identifier
    • [4]DIR (def=0x0) // Direction of transaction
    • [8]ESOF (def=0x0) // Expected start frame
    • [9]SOF (def=0x0) // start of frame
    • [10]RESET (def=0x0) // reset request
    • [11]SUSP (def=0x0) // Suspend mode request
    • [12]WKUP (def=0x0) // Wakeup
    • [13]ERR (def=0x0) // Error
    • [14]PMAOVR (def=0x0) // Packet memory area over / underrun
    • [15]CTR (def=0x0) // Correct transfer
  • 0x40005C48FNR// frame number register

    • [0:10]FN (def=0x0) // Frame number
    • [11:12]LSOF (def=0x0) // Lost SOF
    • [13]LCK (def=0x0) // Locked
    • [14]RXDM (def=0x0) // Receive data - line status
    • [15]RXDP (def=0x0) // Receive data + line status
  • 0x40005C4CDADDR// device address

    • [0:6]ADD (def=0x0) // Device address
    • [7]EF (def=0x0) // Enable function
  • 0x40005C50BTABLE// Buffer table address

    • [3:15]BTABLE (def=0x0) // Buffer table
  interrupts:
  • [19] USB_HP_CAN_TX // USB High Priority or CAN TX interrupts
  • [20] USB_LP_CAN_RX0 // USB Low Priority or CAN RX0 interrupts
• 0x50000800OTG_FS_DEVICE// USB on the go full speed

  • 0x50000800FS_DCFG// OTG_FS device configuration register (OTG_FS_DCFG)

    • [0:1]DSPD (def=0x0) // Device speed
    • [2]NZLSOHSK (def=0x0) // Non-zero-length status OUT handshake
    • [4:10]DAD (def=0x0) // Device address
    • [11:12]PFIVL (def=0x0) // Periodic frame interval
  • 0x50000804FS_DCTL// OTG_FS device control register (OTG_FS_DCTL)

    • [0]RWUSIG (def=0x0) // Remote wakeup signaling
    • [1]SDIS (def=0x0) // Soft disconnect
    • [2]GINSTS (def=0x0) // Global IN NAK status
    • [3]GONSTS (def=0x0) // Global OUT NAK status
    • [4:6]TCTL (def=0x0) // Test control
    • [7]SGINAK (def=0x0) // Set global IN NAK
    • [8]CGINAK (def=0x0) // Clear global IN NAK
    • [9]SGONAK (def=0x0) // Set global OUT NAK
    • [10]CGONAK (def=0x0) // Clear global OUT NAK
    • [11]POPRGDNE (def=0x0) // Power-on programming done
  • 0x50000808FS_DSTS// OTG_FS device status register (OTG_FS_DSTS)

    • [0]SUSPSTS (def=0x0) // Suspend status
    • [1:2]ENUMSPD (def=0x0) // Enumerated speed
    • [3]EERR (def=0x0) // Erratic error
    • [8:21]FNSOF (def=0x0) // Frame number of the received SOF
  • 0x50000810FS_DIEPMSK// OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)

    • [0]XFRCM (def=0x0) // Transfer completed interrupt mask
    • [1]EPDM (def=0x0) // Endpoint disabled interrupt mask
    • [3]TOM (def=0x0) // Timeout condition mask (Non-isochronous endpoints)
    • [4]ITTXFEMSK (def=0x0) // IN token received when TxFIFO empty mask
    • [5]INEPNMM (def=0x0) // IN token received with EP mismatch mask
    • [6]INEPNEM (def=0x0) // IN endpoint NAK effective mask
  • 0x50000814FS_DOEPMSK// OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)

    • [0]XFRCM (def=0x0) // Transfer completed interrupt mask
    • [1]EPDM (def=0x0) // Endpoint disabled interrupt mask
    • [3]STUPM (def=0x0) // SETUP phase done mask
    • [4]OTEPDM (def=0x0) // OUT token received when endpoint disabled mask
  • 0x50000818FS_DAINT// OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)

    • [0:15]IEPINT (def=0x0) // IN endpoint interrupt bits
    • [16:31]OEPINT (def=0x0) // OUT endpoint interrupt bits
  • 0x5000081CFS_DAINTMSK// OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)

    • [0:15]IEPM (def=0x0) // IN EP interrupt mask bits
    • [16:31]OEPINT (def=0x0) // OUT endpoint interrupt bits
  • 0x50000828DVBUSDIS// OTG_FS device VBUS discharge time register

    • [0:15]VBUSDT (def=0x17D7) // Device VBUS discharge time
  • 0x5000082CDVBUSPULSE// OTG_FS device VBUS pulsing time register

    • [0:11]DVBUSP (def=0x5B8) // Device VBUS pulsing time
  • 0x50000834DIEPEMPMSK// OTG_FS device IN endpoint FIFO empty interrupt mask register

    • [0:15]INEPTXFEM (def=0x0) // IN EP Tx FIFO empty interrupt mask bits
  • 0x50000900FS_DIEPCTL0// OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)

    • [0:1]MPSIZ (def=0x0) // Maximum packet size
    • [15]USBAEP (def=0x0) // USB active endpoint
    • [17]NAKSTS (def=0x0) // NAK status
    • [18:19]EPTYP (def=0x0) // Endpoint type
    • [21]STALL (def=0x0) // STALL handshake
    • [22:25]TXFNUM (def=0x0) // TxFIFO number
    • [26]CNAK (def=0x0) // Clear NAK
    • [27]SNAK (def=0x0) // Set NAK
    • [30]EPDIS (def=0x0) // Endpoint disable
    • [31]EPENA (def=0x0) // Endpoint enable
  • 0x50000920DIEPCTL1// OTG device endpoint-1 control register

    • [31]EPENA (def=0x0) // EPENA
    • [30]EPDIS (def=0x0) // EPDIS
    • [29]SODDFRM_SD1PID (def=0x0) // SODDFRM/SD1PID
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID/SEVNFRM
    • [27]SNAK (def=0x0) // SNAK
    • [26]CNAK (def=0x0) // CNAK
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [21]Stall (def=0x0) // Stall
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [16]EONUM_DPID (def=0x0) // EONUM/DPID
    • [15]USBAEP (def=0x0) // USBAEP
    • [0:10]MPSIZ (def=0x0) // MPSIZ
  • 0x50000940DIEPCTL2// OTG device endpoint-2 control register

    • [31]EPENA (def=0x0) // EPENA
    • [30]EPDIS (def=0x0) // EPDIS
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID/SEVNFRM
    • [27]SNAK (def=0x0) // SNAK
    • [26]CNAK (def=0x0) // CNAK
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [21]Stall (def=0x0) // Stall
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [16]EONUM_DPID (def=0x0) // EONUM/DPID
    • [15]USBAEP (def=0x0) // USBAEP
    • [0:10]MPSIZ (def=0x0) // MPSIZ
  • 0x50000960DIEPCTL3// OTG device endpoint-3 control register

    • [31]EPENA (def=0x0) // EPENA
    • [30]EPDIS (def=0x0) // EPDIS
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID/SEVNFRM
    • [27]SNAK (def=0x0) // SNAK
    • [26]CNAK (def=0x0) // CNAK
    • [22:25]TXFNUM (def=0x0) // TXFNUM
    • [21]Stall (def=0x0) // Stall
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [16]EONUM_DPID (def=0x0) // EONUM/DPID
    • [15]USBAEP (def=0x0) // USBAEP
    • [0:10]MPSIZ (def=0x0) // MPSIZ
  • 0x50000B00DOEPCTL0// device endpoint-0 control register

    • [31]EPENA (def=0x0) // EPENA
    • [30]EPDIS (def=0x0) // EPDIS
    • [27]SNAK (def=0x0) // SNAK
    • [26]CNAK (def=0x0) // CNAK
    • [21]Stall (def=0x0) // Stall
    • [20]SNPM (def=0x0) // SNPM
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [15]USBAEP (def=0x1) // USBAEP
    • [0:1]MPSIZ (def=0x0) // MPSIZ
  • 0x50000B20DOEPCTL1// device endpoint-1 control register

    • [31]EPENA (def=0x0) // EPENA
    • [30]EPDIS (def=0x0) // EPDIS
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID/SEVNFRM
    • [27]SNAK (def=0x0) // SNAK
    • [26]CNAK (def=0x0) // CNAK
    • [21]Stall (def=0x0) // Stall
    • [20]SNPM (def=0x0) // SNPM
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [16]EONUM_DPID (def=0x0) // EONUM/DPID
    • [15]USBAEP (def=0x0) // USBAEP
    • [0:10]MPSIZ (def=0x0) // MPSIZ
  • 0x50000B40DOEPCTL2// device endpoint-2 control register

    • [31]EPENA (def=0x0) // EPENA
    • [30]EPDIS (def=0x0) // EPDIS
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID/SEVNFRM
    • [27]SNAK (def=0x0) // SNAK
    • [26]CNAK (def=0x0) // CNAK
    • [21]Stall (def=0x0) // Stall
    • [20]SNPM (def=0x0) // SNPM
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [16]EONUM_DPID (def=0x0) // EONUM/DPID
    • [15]USBAEP (def=0x0) // USBAEP
    • [0:10]MPSIZ (def=0x0) // MPSIZ
  • 0x50000B60DOEPCTL3// device endpoint-3 control register

    • [31]EPENA (def=0x0) // EPENA
    • [30]EPDIS (def=0x0) // EPDIS
    • [29]SODDFRM (def=0x0) // SODDFRM
    • [28]SD0PID_SEVNFRM (def=0x0) // SD0PID/SEVNFRM
    • [27]SNAK (def=0x0) // SNAK
    • [26]CNAK (def=0x0) // CNAK
    • [21]Stall (def=0x0) // Stall
    • [20]SNPM (def=0x0) // SNPM
    • [18:19]EPTYP (def=0x0) // EPTYP
    • [17]NAKSTS (def=0x0) // NAKSTS
    • [16]EONUM_DPID (def=0x0) // EONUM/DPID
    • [15]USBAEP (def=0x0) // USBAEP
    • [0:10]MPSIZ (def=0x0) // MPSIZ
  • 0x50000908DIEPINT0// device endpoint-x interrupt register

    • [7]TXFE (def=0x1) // TXFE
    • [6]INEPNE (def=0x0) // INEPNE
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [3]TOC (def=0x0) // TOC
    • [1]EPDISD (def=0x0) // EPDISD
    • [0]XFRC (def=0x0) // XFRC
  • 0x50000928DIEPINT1// device endpoint-1 interrupt register

    • [7]TXFE (def=0x1) // TXFE
    • [6]INEPNE (def=0x0) // INEPNE
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [3]TOC (def=0x0) // TOC
    • [1]EPDISD (def=0x0) // EPDISD
    • [0]XFRC (def=0x0) // XFRC
  • 0x50000948DIEPINT2// device endpoint-2 interrupt register

    • [7]TXFE (def=0x1) // TXFE
    • [6]INEPNE (def=0x0) // INEPNE
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [3]TOC (def=0x0) // TOC
    • [1]EPDISD (def=0x0) // EPDISD
    • [0]XFRC (def=0x0) // XFRC
  • 0x50000968DIEPINT3// device endpoint-3 interrupt register

    • [7]TXFE (def=0x1) // TXFE
    • [6]INEPNE (def=0x0) // INEPNE
    • [4]ITTXFE (def=0x0) // ITTXFE
    • [3]TOC (def=0x0) // TOC
    • [1]EPDISD (def=0x0) // EPDISD
    • [0]XFRC (def=0x0) // XFRC
  • 0x50000B08DOEPINT0// device endpoint-0 interrupt register

    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [3]STUP (def=0x0) // STUP
    • [1]EPDISD (def=0x0) // EPDISD
    • [0]XFRC (def=0x0) // XFRC
  • 0x50000B28DOEPINT1// device endpoint-1 interrupt register

    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [3]STUP (def=0x0) // STUP
    • [1]EPDISD (def=0x0) // EPDISD
    • [0]XFRC (def=0x0) // XFRC
  • 0x50000B48DOEPINT2// device endpoint-2 interrupt register

    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [3]STUP (def=0x0) // STUP
    • [1]EPDISD (def=0x0) // EPDISD
    • [0]XFRC (def=0x0) // XFRC
  • 0x50000B68DOEPINT3// device endpoint-3 interrupt register

    • [6]B2BSTUP (def=0x0) // B2BSTUP
    • [4]OTEPDIS (def=0x0) // OTEPDIS
    • [3]STUP (def=0x0) // STUP
    • [1]EPDISD (def=0x0) // EPDISD
    • [0]XFRC (def=0x0) // XFRC
  • 0x50000910DIEPTSIZ0// device endpoint-0 transfer size register

    • [19:20]PKTCNT (def=0x0) // Packet count
    • [0:6]XFRSIZ (def=0x0) // Transfer size
  • 0x50000B10DOEPTSIZ0// device OUT endpoint-0 transfer size register

    • [29:30]STUPCNT (def=0x0) // SETUP packet count
    • [19]PKTCNT (def=0x0) // Packet count
    • [0:6]XFRSIZ (def=0x0) // Transfer size
  • 0x50000930DIEPTSIZ1// device endpoint-1 transfer size register

    • [29:30]MCNT (def=0x0) // Multi count
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [0:18]XFRSIZ (def=0x0) // Transfer size
  • 0x50000950DIEPTSIZ2// device endpoint-2 transfer size register

    • [29:30]MCNT (def=0x0) // Multi count
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [0:18]XFRSIZ (def=0x0) // Transfer size
  • 0x50000970DIEPTSIZ3// device endpoint-3 transfer size register

    • [29:30]MCNT (def=0x0) // Multi count
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [0:18]XFRSIZ (def=0x0) // Transfer size
  • 0x50000918DTXFSTS0// OTG_FS device IN endpoint transmit FIFO status register

    • [0:15]INEPTFSAV (def=0x0) // IN endpoint TxFIFO space available
  • 0x50000938DTXFSTS1// OTG_FS device IN endpoint transmit FIFO status register

    • [0:15]INEPTFSAV (def=0x0) // IN endpoint TxFIFO space available
  • 0x50000958DTXFSTS2// OTG_FS device IN endpoint transmit FIFO status register

    • [0:15]INEPTFSAV (def=0x0) // IN endpoint TxFIFO space available
  • 0x50000978DTXFSTS3// OTG_FS device IN endpoint transmit FIFO status register

    • [0:15]INEPTFSAV (def=0x0) // IN endpoint TxFIFO space available
  • 0x50000B30DOEPTSIZ1// device OUT endpoint-1 transfer size register

    • [29:30]RXDPID_STUPCNT (def=0x0) // Received data PID/SETUP packet count
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [0:18]XFRSIZ (def=0x0) // Transfer size
  • 0x50000B50DOEPTSIZ2// device OUT endpoint-2 transfer size register

    • [29:30]RXDPID_STUPCNT (def=0x0) // Received data PID/SETUP packet count
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [0:18]XFRSIZ (def=0x0) // Transfer size
  • 0x50000B70DOEPTSIZ3// device OUT endpoint-3 transfer size register

    • [29:30]RXDPID_STUPCNT (def=0x0) // Received data PID/SETUP packet count
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [0:18]XFRSIZ (def=0x0) // Transfer size
• 0x50000000OTG_FS_GLOBAL// USB on the go full speed

  • 0x50000000FS_GOTGCTL// OTG_FS control and status register (OTG_FS_GOTGCTL)

    • [0]SRQSCS (def=0x0) // Session request success
    • [1]SRQ (def=0x0) // Session request
    • [8]HNGSCS (def=0x0) // Host negotiation success
    • [9]HNPRQ (def=0x0) // HNP request
    • [10]HSHNPEN (def=0x0) // Host set HNP enable
    • [11]DHNPEN (def=0x1) // Device HNP enabled
    • [16]CIDSTS (def=0x0) // Connector ID status
    • [17]DBCT (def=0x0) // Long/short debounce time
    • [18]ASVLD (def=0x0) // A-session valid
    • [19]BSVLD (def=0x0) // B-session valid
  • 0x50000004FS_GOTGINT// OTG_FS interrupt register (OTG_FS_GOTGINT)

    • [2]SEDET (def=0x0) // Session end detected
    • [8]SRSSCHG (def=0x0) // Session request success status change
    • [9]HNSSCHG (def=0x0) // Host negotiation success status change
    • [17]HNGDET (def=0x0) // Host negotiation detected
    • [18]ADTOCHG (def=0x0) // A-device timeout change
    • [19]DBCDNE (def=0x0) // Debounce done
  • 0x50000008FS_GAHBCFG// OTG_FS AHB configuration register (OTG_FS_GAHBCFG)

    • [0]GINT (def=0x0) // Global interrupt mask
    • [7]TXFELVL (def=0x0) // TxFIFO empty level
    • [8]PTXFELVL (def=0x0) // Periodic TxFIFO empty level
  • 0x5000000CFS_GUSBCFG// OTG_FS USB configuration register (OTG_FS_GUSBCFG)

    • [0:2]TOCAL (def=0x0) // FS timeout calibration
    • [6]PHYSEL (def=0x0) // Full Speed serial transceiver select
    • [8]SRPCAP (def=0x0) // SRP-capable
    • [9]HNPCAP (def=0x1) // HNP-capable
    • [10:13]TRDT (def=0x2) // USB turnaround time
    • [29]FHMOD (def=0x0) // Force host mode
    • [30]FDMOD (def=0x0) // Force device mode
    • [31]CTXPKT (def=0x0) // Corrupt Tx packet
  • 0x50000010FS_GRSTCTL// OTG_FS reset register (OTG_FS_GRSTCTL)

    • [0]CSRST (def=0x0) // Core soft reset
    • [1]HSRST (def=0x0) // HCLK soft reset
    • [2]FCRST (def=0x0) // Host frame counter reset
    • [4]RXFFLSH (def=0x0) // RxFIFO flush
    • [5]TXFFLSH (def=0x0) // TxFIFO flush
    • [6:10]TXFNUM (def=0x0) // TxFIFO number
    • [31]AHBIDL (def=0x0) // AHB master idle
  • 0x50000014FS_GINTSTS// OTG_FS core interrupt register (OTG_FS_GINTSTS)

    • [0]CMOD (def=0x0) // Current mode of operation
    • [1]MMIS (def=0x0) // Mode mismatch interrupt
    • [2]OTGINT (def=0x0) // OTG interrupt
    • [3]SOF (def=0x0) // Start of frame
    • [4]RXFLVL (def=0x0) // RxFIFO non-empty
    • [5]NPTXFE (def=0x1) // Non-periodic TxFIFO empty
    • [6]GINAKEFF (def=0x0) // Global IN non-periodic NAK effective
    • [7]GOUTNAKEFF (def=0x0) // Global OUT NAK effective
    • [10]ESUSP (def=0x0) // Early suspend
    • [11]USBSUSP (def=0x0) // USB suspend
    • [12]USBRST (def=0x0) // USB reset
    • [13]ENUMDNE (def=0x0) // Enumeration done
    • [14]ISOODRP (def=0x0) // Isochronous OUT packet dropped interrupt
    • [15]EOPF (def=0x0) // End of periodic frame interrupt
    • [18]IEPINT (def=0x0) // IN endpoint interrupt
    • [19]OEPINT (def=0x0) // OUT endpoint interrupt
    • [20]IISOIXFR (def=0x0) // Incomplete isochronous IN transfer
    • [21]IPXFR_INCOMPISOOUT (def=0x0) // Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device
    • [24]HPRTINT (def=0x0) // Host port interrupt
    • [25]HCINT (def=0x0) // Host channels interrupt
    • [26]PTXFE (def=0x1) // Periodic TxFIFO empty
    • [28]CIDSCHG (def=0x0) // Connector ID status change
    • [29]DISCINT (def=0x0) // Disconnect detected interrupt
    • [30]SRQINT (def=0x0) // Session request/new session detected interrupt
    • [31]WKUPINT (def=0x0) // Resume/remote wakeup detected interrupt
  • 0x50000018FS_GINTMSK// OTG_FS interrupt mask register (OTG_FS_GINTMSK)

    • [1]MMISM (def=0x0) // Mode mismatch interrupt mask
    • [2]OTGINT (def=0x0) // OTG interrupt mask
    • [3]SOFM (def=0x0) // Start of frame mask
    • [4]RXFLVLM (def=0x0) // Receive FIFO non-empty mask
    • [5]NPTXFEM (def=0x0) // Non-periodic TxFIFO empty mask
    • [6]GINAKEFFM (def=0x0) // Global non-periodic IN NAK effective mask
    • [7]GONAKEFFM (def=0x0) // Global OUT NAK effective mask
    • [10]ESUSPM (def=0x0) // Early suspend mask
    • [11]USBSUSPM (def=0x0) // USB suspend mask
    • [12]USBRST (def=0x0) // USB reset mask
    • [13]ENUMDNEM (def=0x0) // Enumeration done mask
    • [14]ISOODRPM (def=0x0) // Isochronous OUT packet dropped interrupt mask
    • [15]EOPFM (def=0x0) // End of periodic frame interrupt mask
    • [17]EPMISM (def=0x0) // Endpoint mismatch interrupt mask
    • [18]IEPINT (def=0x0) // IN endpoints interrupt mask
    • [19]OEPINT (def=0x0) // OUT endpoints interrupt mask
    • [20]IISOIXFRM (def=0x0) // Incomplete isochronous IN transfer mask
    • [21]IPXFRM_IISOOXFRM (def=0x0) // Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask
    • [24]PRTIM (def=0x0) // Host port interrupt mask
    • [25]HCIM (def=0x0) // Host channels interrupt mask
    • [26]PTXFEM (def=0x0) // Periodic TxFIFO empty mask
    • [28]CIDSCHGM (def=0x0) // Connector ID status change mask
    • [29]DISCINT (def=0x0) // Disconnect detected interrupt mask
    • [30]SRQIM (def=0x0) // Session request/new session detected interrupt mask
    • [31]WUIM (def=0x0) // Resume/remote wakeup detected interrupt mask
  • 0x5000001CFS_GRXSTSR_Device// OTG_FS Receive status debug read(Device mode)

    • [0:3]EPNUM (def=0x0) // Endpoint number
    • [4:14]BCNT (def=0x0) // Byte count
    • [15:16]DPID (def=0x0) // Data PID
    • [17:20]PKTSTS (def=0x0) // Packet status
    • [21:24]FRMNUM (def=0x0) // Frame number
  • 0x5000001CFS_GRXSTSR_Host// OTG_FS Receive status debug read(Host mode)

    • [0:3]EPNUM (def=0x0) // Endpoint number
    • [4:14]BCNT (def=0x0) // Byte count
    • [15:16]DPID (def=0x0) // Data PID
    • [17:20]PKTSTS (def=0x0) // Packet status
    • [21:24]FRMNUM (def=0x0) // Frame number
  • 0x50000024FS_GRXFSIZ// OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)

    • [0:15]RXFD (def=0x200) // RxFIFO depth
  • 0x50000028FS_GNPTXFSIZ_Device// OTG_FS non-periodic transmit FIFO size register (Device mode)

    • [0:15]TX0FSA (def=0x200) // Endpoint 0 transmit RAM start address
    • [16:31]TX0FD (def=0x0) // Endpoint 0 TxFIFO depth
  • 0x50000028FS_GNPTXFSIZ_Host// OTG_FS non-periodic transmit FIFO size register (Host mode)

    • [0:15]NPTXFSA (def=0x200) // Non-periodic transmit RAM start address
    • [16:31]NPTXFD (def=0x0) // Non-periodic TxFIFO depth
  • 0x5000002CFS_GNPTXSTS// OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)

    • [0:15]NPTXFSAV (def=0x200) // Non-periodic TxFIFO space available
    • [16:23]NPTQXSAV (def=0x8) // Non-periodic transmit request queue space available
    • [24:30]NPTXQTOP (def=0x0) // Top of the non-periodic transmit request queue
  • 0x50000038FS_GCCFG// OTG_FS general core configuration register (OTG_FS_GCCFG)

    • [16]PWRDWN (def=0x0) // Power down
    • [18]VBUSASEN (def=0x0) // Enable the VBUS sensing device
    • [19]VBUSBSEN (def=0x0) // Enable the VBUS sensing device
    • [20]SOFOUTEN (def=0x0) // SOF output enable
  • 0x5000003CFS_CID// core ID register

    • [0:31]PRODUCT_ID (def=0x1000) // Product ID field
  • 0x50000100FS_HPTXFSIZ// OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)

    • [0:15]PTXSA (def=0x600) // Host periodic TxFIFO start address
    • [16:31]PTXFSIZ (def=0x200) // Host periodic TxFIFO depth
  • 0x50000104FS_DIEPTXF1// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)

    • [0:15]INEPTXSA (def=0x400) // IN endpoint FIFO2 transmit RAM start address
    • [16:31]INEPTXFD (def=0x200) // IN endpoint TxFIFO depth
  • 0x50000108FS_DIEPTXF2// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)

    • [0:15]INEPTXSA (def=0x400) // IN endpoint FIFO3 transmit RAM start address
    • [16:31]INEPTXFD (def=0x200) // IN endpoint TxFIFO depth
  • 0x5000010CFS_DIEPTXF3// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)

    • [0:15]INEPTXSA (def=0x400) // IN endpoint FIFO4 transmit RAM start address
    • [16:31]INEPTXFD (def=0x200) // IN endpoint TxFIFO depth
• 0x50000400OTG_FS_HOST// USB on the go full speed

  • 0x50000400FS_HCFG// OTG_FS host configuration register (OTG_FS_HCFG)

    • [0:1]FSLSPCS (def=0x0) // FS/LS PHY clock select
    • [2]FSLSS (def=0x0) // FS- and LS-only support
  • 0x50000404HFIR// OTG_FS Host frame interval register

    • [0:15]FRIVL (def=0xEA60) // Frame interval
  • 0x50000408FS_HFNUM// OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)

    • [0:15]FRNUM (def=0x3FFF) // Frame number
    • [16:31]FTREM (def=0x0) // Frame time remaining
  • 0x50000410FS_HPTXSTS// OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)

    • [0:15]PTXFSAVL (def=0x100) // Periodic transmit data FIFO space available
    • [16:23]PTXQSAV (def=0x8) // Periodic transmit request queue space available
    • [24:31]PTXQTOP (def=0x0) // Top of the periodic transmit request queue
  • 0x50000414HAINT// OTG_FS Host all channels interrupt register

    • [0:15]HAINT (def=0x0) // Channel interrupts
  • 0x50000418HAINTMSK// OTG_FS host all channels interrupt mask register

    • [0:15]HAINTM (def=0x0) // Channel interrupt mask
  • 0x50000440FS_HPRT// OTG_FS host port control and status register (OTG_FS_HPRT)

    • [0]PCSTS (def=0x0) // Port connect status
    • [1]PCDET (def=0x0) // Port connect detected
    • [2]PENA (def=0x0) // Port enable
    • [3]PENCHNG (def=0x0) // Port enable/disable change
    • [4]POCA (def=0x0) // Port overcurrent active
    • [5]POCCHNG (def=0x0) // Port overcurrent change
    • [6]PRES (def=0x0) // Port resume
    • [7]PSUSP (def=0x0) // Port suspend
    • [8]PRST (def=0x0) // Port reset
    • [10:11]PLSTS (def=0x0) // Port line status
    • [12]PPWR (def=0x0) // Port power
    • [13:16]PTCTL (def=0x0) // Port test control
    • [17:18]PSPD (def=0x0) // Port speed
  • 0x50000500FS_HCCHAR0// OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

    • [0:10]MPSIZ (def=0x0) // Maximum packet size
    • [11:14]EPNUM (def=0x0) // Endpoint number
    • [15]EPDIR (def=0x0) // Endpoint direction
    • [17]LSDEV (def=0x0) // Low-speed device
    • [18:19]EPTYP (def=0x0) // Endpoint type
    • [20:21]MCNT (def=0x0) // Multicount
    • [22:28]DAD (def=0x0) // Device address
    • [29]ODDFRM (def=0x0) // Odd frame
    • [30]CHDIS (def=0x0) // Channel disable
    • [31]CHENA (def=0x0) // Channel enable
  • 0x50000520FS_HCCHAR1// OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)

    • [0:10]MPSIZ (def=0x0) // Maximum packet size
    • [11:14]EPNUM (def=0x0) // Endpoint number
    • [15]EPDIR (def=0x0) // Endpoint direction
    • [17]LSDEV (def=0x0) // Low-speed device
    • [18:19]EPTYP (def=0x0) // Endpoint type
    • [20:21]MCNT (def=0x0) // Multicount
    • [22:28]DAD (def=0x0) // Device address
    • [29]ODDFRM (def=0x0) // Odd frame
    • [30]CHDIS (def=0x0) // Channel disable
    • [31]CHENA (def=0x0) // Channel enable
  • 0x50000540FS_HCCHAR2// OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)

    • [0:10]MPSIZ (def=0x0) // Maximum packet size
    • [11:14]EPNUM (def=0x0) // Endpoint number
    • [15]EPDIR (def=0x0) // Endpoint direction
    • [17]LSDEV (def=0x0) // Low-speed device
    • [18:19]EPTYP (def=0x0) // Endpoint type
    • [20:21]MCNT (def=0x0) // Multicount
    • [22:28]DAD (def=0x0) // Device address
    • [29]ODDFRM (def=0x0) // Odd frame
    • [30]CHDIS (def=0x0) // Channel disable
    • [31]CHENA (def=0x0) // Channel enable
  • 0x50000560FS_HCCHAR3// OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)

    • [0:10]MPSIZ (def=0x0) // Maximum packet size
    • [11:14]EPNUM (def=0x0) // Endpoint number
    • [15]EPDIR (def=0x0) // Endpoint direction
    • [17]LSDEV (def=0x0) // Low-speed device
    • [18:19]EPTYP (def=0x0) // Endpoint type
    • [20:21]MCNT (def=0x0) // Multicount
    • [22:28]DAD (def=0x0) // Device address
    • [29]ODDFRM (def=0x0) // Odd frame
    • [30]CHDIS (def=0x0) // Channel disable
    • [31]CHENA (def=0x0) // Channel enable
  • 0x50000580FS_HCCHAR4// OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)

    • [0:10]MPSIZ (def=0x0) // Maximum packet size
    • [11:14]EPNUM (def=0x0) // Endpoint number
    • [15]EPDIR (def=0x0) // Endpoint direction
    • [17]LSDEV (def=0x0) // Low-speed device
    • [18:19]EPTYP (def=0x0) // Endpoint type
    • [20:21]MCNT (def=0x0) // Multicount
    • [22:28]DAD (def=0x0) // Device address
    • [29]ODDFRM (def=0x0) // Odd frame
    • [30]CHDIS (def=0x0) // Channel disable
    • [31]CHENA (def=0x0) // Channel enable
  • 0x500005A0FS_HCCHAR5// OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)

    • [0:10]MPSIZ (def=0x0) // Maximum packet size
    • [11:14]EPNUM (def=0x0) // Endpoint number
    • [15]EPDIR (def=0x0) // Endpoint direction
    • [17]LSDEV (def=0x0) // Low-speed device
    • [18:19]EPTYP (def=0x0) // Endpoint type
    • [20:21]MCNT (def=0x0) // Multicount
    • [22:28]DAD (def=0x0) // Device address
    • [29]ODDFRM (def=0x0) // Odd frame
    • [30]CHDIS (def=0x0) // Channel disable
    • [31]CHENA (def=0x0) // Channel enable
  • 0x500005C0FS_HCCHAR6// OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)

    • [0:10]MPSIZ (def=0x0) // Maximum packet size
    • [11:14]EPNUM (def=0x0) // Endpoint number
    • [15]EPDIR (def=0x0) // Endpoint direction
    • [17]LSDEV (def=0x0) // Low-speed device
    • [18:19]EPTYP (def=0x0) // Endpoint type
    • [20:21]MCNT (def=0x0) // Multicount
    • [22:28]DAD (def=0x0) // Device address
    • [29]ODDFRM (def=0x0) // Odd frame
    • [30]CHDIS (def=0x0) // Channel disable
    • [31]CHENA (def=0x0) // Channel enable
  • 0x500005E0FS_HCCHAR7// OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)

    • [0:10]MPSIZ (def=0x0) // Maximum packet size
    • [11:14]EPNUM (def=0x0) // Endpoint number
    • [15]EPDIR (def=0x0) // Endpoint direction
    • [17]LSDEV (def=0x0) // Low-speed device
    • [18:19]EPTYP (def=0x0) // Endpoint type
    • [20:21]MCNT (def=0x0) // Multicount
    • [22:28]DAD (def=0x0) // Device address
    • [29]ODDFRM (def=0x0) // Odd frame
    • [30]CHDIS (def=0x0) // Channel disable
    • [31]CHENA (def=0x0) // Channel enable
  • 0x50000508FS_HCINT0// OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

    • [0]XFRC (def=0x0) // Transfer completed
    • [1]CHH (def=0x0) // Channel halted
    • [3]STALL (def=0x0) // STALL response received interrupt
    • [4]NAK (def=0x0) // NAK response received interrupt
    • [5]ACK (def=0x0) // ACK response received/transmitted interrupt
    • [7]TXERR (def=0x0) // Transaction error
    • [8]BBERR (def=0x0) // Babble error
    • [9]FRMOR (def=0x0) // Frame overrun
    • [10]DTERR (def=0x0) // Data toggle error
  • 0x50000528FS_HCINT1// OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)

    • [0]XFRC (def=0x0) // Transfer completed
    • [1]CHH (def=0x0) // Channel halted
    • [3]STALL (def=0x0) // STALL response received interrupt
    • [4]NAK (def=0x0) // NAK response received interrupt
    • [5]ACK (def=0x0) // ACK response received/transmitted interrupt
    • [7]TXERR (def=0x0) // Transaction error
    • [8]BBERR (def=0x0) // Babble error
    • [9]FRMOR (def=0x0) // Frame overrun
    • [10]DTERR (def=0x0) // Data toggle error
  • 0x50000548FS_HCINT2// OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)

    • [0]XFRC (def=0x0) // Transfer completed
    • [1]CHH (def=0x0) // Channel halted
    • [3]STALL (def=0x0) // STALL response received interrupt
    • [4]NAK (def=0x0) // NAK response received interrupt
    • [5]ACK (def=0x0) // ACK response received/transmitted interrupt
    • [7]TXERR (def=0x0) // Transaction error
    • [8]BBERR (def=0x0) // Babble error
    • [9]FRMOR (def=0x0) // Frame overrun
    • [10]DTERR (def=0x0) // Data toggle error
  • 0x50000568FS_HCINT3// OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)

    • [0]XFRC (def=0x0) // Transfer completed
    • [1]CHH (def=0x0) // Channel halted
    • [3]STALL (def=0x0) // STALL response received interrupt
    • [4]NAK (def=0x0) // NAK response received interrupt
    • [5]ACK (def=0x0) // ACK response received/transmitted interrupt
    • [7]TXERR (def=0x0) // Transaction error
    • [8]BBERR (def=0x0) // Babble error
    • [9]FRMOR (def=0x0) // Frame overrun
    • [10]DTERR (def=0x0) // Data toggle error
  • 0x50000588FS_HCINT4// OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)

    • [0]XFRC (def=0x0) // Transfer completed
    • [1]CHH (def=0x0) // Channel halted
    • [3]STALL (def=0x0) // STALL response received interrupt
    • [4]NAK (def=0x0) // NAK response received interrupt
    • [5]ACK (def=0x0) // ACK response received/transmitted interrupt
    • [7]TXERR (def=0x0) // Transaction error
    • [8]BBERR (def=0x0) // Babble error
    • [9]FRMOR (def=0x0) // Frame overrun
    • [10]DTERR (def=0x0) // Data toggle error
  • 0x500005A8FS_HCINT5// OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)

    • [0]XFRC (def=0x0) // Transfer completed
    • [1]CHH (def=0x0) // Channel halted
    • [3]STALL (def=0x0) // STALL response received interrupt
    • [4]NAK (def=0x0) // NAK response received interrupt
    • [5]ACK (def=0x0) // ACK response received/transmitted interrupt
    • [7]TXERR (def=0x0) // Transaction error
    • [8]BBERR (def=0x0) // Babble error
    • [9]FRMOR (def=0x0) // Frame overrun
    • [10]DTERR (def=0x0) // Data toggle error
  • 0x500005C8FS_HCINT6// OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)

    • [0]XFRC (def=0x0) // Transfer completed
    • [1]CHH (def=0x0) // Channel halted
    • [3]STALL (def=0x0) // STALL response received interrupt
    • [4]NAK (def=0x0) // NAK response received interrupt
    • [5]ACK (def=0x0) // ACK response received/transmitted interrupt
    • [7]TXERR (def=0x0) // Transaction error
    • [8]BBERR (def=0x0) // Babble error
    • [9]FRMOR (def=0x0) // Frame overrun
    • [10]DTERR (def=0x0) // Data toggle error
  • 0x500005E8FS_HCINT7// OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)

    • [0]XFRC (def=0x0) // Transfer completed
    • [1]CHH (def=0x0) // Channel halted
    • [3]STALL (def=0x0) // STALL response received interrupt
    • [4]NAK (def=0x0) // NAK response received interrupt
    • [5]ACK (def=0x0) // ACK response received/transmitted interrupt
    • [7]TXERR (def=0x0) // Transaction error
    • [8]BBERR (def=0x0) // Babble error
    • [9]FRMOR (def=0x0) // Frame overrun
    • [10]DTERR (def=0x0) // Data toggle error
  • 0x5000050CFS_HCINTMSK0// OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

    • [0]XFRCM (def=0x0) // Transfer completed mask
    • [1]CHHM (def=0x0) // Channel halted mask
    • [3]STALLM (def=0x0) // STALL response received interrupt mask
    • [4]NAKM (def=0x0) // NAK response received interrupt mask
    • [5]ACKM (def=0x0) // ACK response received/transmitted interrupt mask
    • [6]NYET (def=0x0) // response received interrupt mask
    • [7]TXERRM (def=0x0) // Transaction error mask
    • [8]BBERRM (def=0x0) // Babble error mask
    • [9]FRMORM (def=0x0) // Frame overrun mask
    • [10]DTERRM (def=0x0) // Data toggle error mask
  • 0x5000052CFS_HCINTMSK1// OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)

    • [0]XFRCM (def=0x0) // Transfer completed mask
    • [1]CHHM (def=0x0) // Channel halted mask
    • [3]STALLM (def=0x0) // STALL response received interrupt mask
    • [4]NAKM (def=0x0) // NAK response received interrupt mask
    • [5]ACKM (def=0x0) // ACK response received/transmitted interrupt mask
    • [6]NYET (def=0x0) // response received interrupt mask
    • [7]TXERRM (def=0x0) // Transaction error mask
    • [8]BBERRM (def=0x0) // Babble error mask
    • [9]FRMORM (def=0x0) // Frame overrun mask
    • [10]DTERRM (def=0x0) // Data toggle error mask
  • 0x5000054CFS_HCINTMSK2// OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)

    • [0]XFRCM (def=0x0) // Transfer completed mask
    • [1]CHHM (def=0x0) // Channel halted mask
    • [3]STALLM (def=0x0) // STALL response received interrupt mask
    • [4]NAKM (def=0x0) // NAK response received interrupt mask
    • [5]ACKM (def=0x0) // ACK response received/transmitted interrupt mask
    • [6]NYET (def=0x0) // response received interrupt mask
    • [7]TXERRM (def=0x0) // Transaction error mask
    • [8]BBERRM (def=0x0) // Babble error mask
    • [9]FRMORM (def=0x0) // Frame overrun mask
    • [10]DTERRM (def=0x0) // Data toggle error mask
  • 0x5000056CFS_HCINTMSK3// OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)

    • [0]XFRCM (def=0x0) // Transfer completed mask
    • [1]CHHM (def=0x0) // Channel halted mask
    • [3]STALLM (def=0x0) // STALL response received interrupt mask
    • [4]NAKM (def=0x0) // NAK response received interrupt mask
    • [5]ACKM (def=0x0) // ACK response received/transmitted interrupt mask
    • [6]NYET (def=0x0) // response received interrupt mask
    • [7]TXERRM (def=0x0) // Transaction error mask
    • [8]BBERRM (def=0x0) // Babble error mask
    • [9]FRMORM (def=0x0) // Frame overrun mask
    • [10]DTERRM (def=0x0) // Data toggle error mask
  • 0x5000058CFS_HCINTMSK4// OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)

    • [0]XFRCM (def=0x0) // Transfer completed mask
    • [1]CHHM (def=0x0) // Channel halted mask
    • [3]STALLM (def=0x0) // STALL response received interrupt mask
    • [4]NAKM (def=0x0) // NAK response received interrupt mask
    • [5]ACKM (def=0x0) // ACK response received/transmitted interrupt mask
    • [6]NYET (def=0x0) // response received interrupt mask
    • [7]TXERRM (def=0x0) // Transaction error mask
    • [8]BBERRM (def=0x0) // Babble error mask
    • [9]FRMORM (def=0x0) // Frame overrun mask
    • [10]DTERRM (def=0x0) // Data toggle error mask
  • 0x500005ACFS_HCINTMSK5// OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)

    • [0]XFRCM (def=0x0) // Transfer completed mask
    • [1]CHHM (def=0x0) // Channel halted mask
    • [3]STALLM (def=0x0) // STALL response received interrupt mask
    • [4]NAKM (def=0x0) // NAK response received interrupt mask
    • [5]ACKM (def=0x0) // ACK response received/transmitted interrupt mask
    • [6]NYET (def=0x0) // response received interrupt mask
    • [7]TXERRM (def=0x0) // Transaction error mask
    • [8]BBERRM (def=0x0) // Babble error mask
    • [9]FRMORM (def=0x0) // Frame overrun mask
    • [10]DTERRM (def=0x0) // Data toggle error mask
  • 0x500005CCFS_HCINTMSK6// OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)

    • [0]XFRCM (def=0x0) // Transfer completed mask
    • [1]CHHM (def=0x0) // Channel halted mask
    • [3]STALLM (def=0x0) // STALL response received interrupt mask
    • [4]NAKM (def=0x0) // NAK response received interrupt mask
    • [5]ACKM (def=0x0) // ACK response received/transmitted interrupt mask
    • [6]NYET (def=0x0) // response received interrupt mask
    • [7]TXERRM (def=0x0) // Transaction error mask
    • [8]BBERRM (def=0x0) // Babble error mask
    • [9]FRMORM (def=0x0) // Frame overrun mask
    • [10]DTERRM (def=0x0) // Data toggle error mask
  • 0x500005ECFS_HCINTMSK7// OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)

    • [0]XFRCM (def=0x0) // Transfer completed mask
    • [1]CHHM (def=0x0) // Channel halted mask
    • [3]STALLM (def=0x0) // STALL response received interrupt mask
    • [4]NAKM (def=0x0) // NAK response received interrupt mask
    • [5]ACKM (def=0x0) // ACK response received/transmitted interrupt mask
    • [6]NYET (def=0x0) // response received interrupt mask
    • [7]TXERRM (def=0x0) // Transaction error mask
    • [8]BBERRM (def=0x0) // Babble error mask
    • [9]FRMORM (def=0x0) // Frame overrun mask
    • [10]DTERRM (def=0x0) // Data toggle error mask
  • 0x50000510FS_HCTSIZ0// OTG_FS host channel-0 transfer size register

    • [0:18]XFRSIZ (def=0x0) // Transfer size
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [29:30]DPID (def=0x0) // Data PID
  • 0x50000530FS_HCTSIZ1// OTG_FS host channel-1 transfer size register

    • [0:18]XFRSIZ (def=0x0) // Transfer size
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [29:30]DPID (def=0x0) // Data PID
  • 0x50000550FS_HCTSIZ2// OTG_FS host channel-2 transfer size register

    • [0:18]XFRSIZ (def=0x0) // Transfer size
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [29:30]DPID (def=0x0) // Data PID
  • 0x50000570FS_HCTSIZ3// OTG_FS host channel-3 transfer size register

    • [0:18]XFRSIZ (def=0x0) // Transfer size
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [29:30]DPID (def=0x0) // Data PID
  • 0x50000590FS_HCTSIZ4// OTG_FS host channel-x transfer size register

    • [0:18]XFRSIZ (def=0x0) // Transfer size
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [29:30]DPID (def=0x0) // Data PID
  • 0x500005B0FS_HCTSIZ5// OTG_FS host channel-5 transfer size register

    • [0:18]XFRSIZ (def=0x0) // Transfer size
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [29:30]DPID (def=0x0) // Data PID
  • 0x500005D0FS_HCTSIZ6// OTG_FS host channel-6 transfer size register

    • [0:18]XFRSIZ (def=0x0) // Transfer size
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [29:30]DPID (def=0x0) // Data PID
  • 0x500005F0FS_HCTSIZ7// OTG_FS host channel-7 transfer size register

    • [0:18]XFRSIZ (def=0x0) // Transfer size
    • [19:28]PKTCNT (def=0x0) // Packet count
    • [29:30]DPID (def=0x0) // Data PID
• 0x50000E00OTG_FS_PWRCLK// USB on the go full speed

  • 0x50000E00FS_PCGCCTL// OTG_FS power and clock gating control register

    • [0]STPPCLK (def=0x0) // Stop PHY clock
    • [1]GATEHCLK (def=0x0) // Gate HCLK
    • [4]PHYSUSP (def=0x0) // PHY Suspended
• 0x40028100ETHERNET_MMC// Ethernet: MAC management counters

  • 0x40028100MMCCR// Ethernet MMC control register (ETH_MMCCR)

    • [0]CR (def=0x0) // Counter reset
    • [1]CSR (def=0x0) // Counter stop rollover
    • [2]ROR (def=0x0) // Reset on read
    • [31]MCF (def=0x0) // MMC counter freeze
  • 0x40028104MMCRIR// Ethernet MMC receive interrupt register (ETH_MMCRIR)

    • [5]RFCES (def=0x0) // Received frames CRC error status
    • [6]RFAES (def=0x0) // Received frames alignment error status
    • [17]RGUFS (def=0x0) // Received Good Unicast Frames Status
  • 0x40028108MMCTIR// Ethernet MMC transmit interrupt register (ETH_MMCTIR)

    • [14]TGFSCS (def=0x0) // Transmitted good frames single collision status
    • [15]TGFMSCS (def=0x0) // Transmitted good frames more single collision status
    • [21]TGFS (def=0x0) // Transmitted good frames status
  • 0x4002810CMMCRIMR// Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)

    • [5]RFCEM (def=0x0) // Received frame CRC error mask
    • [6]RFAEM (def=0x0) // Received frames alignment error mask
    • [17]RGUFM (def=0x0) // Received good unicast frames mask
  • 0x40028110MMCTIMR// Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)

    • [14]TGFSCM (def=0x0) // Transmitted good frames single collision mask
    • [15]TGFMSCM (def=0x0) // Transmitted good frames more single collision mask
    • [21]TGFM (def=0x0) // Transmitted good frames mask
  • 0x4002814CMMCTGFSCCR// Ethernet MMC transmitted good frames after a single collision counter

    • [0:31]TGFSCC (def=0x0) // Transmitted good frames after a single collision counter
  • 0x40028150MMCTGFMSCCR// Ethernet MMC transmitted good frames after more than a single collision

    • [0:31]TGFMSCC (def=0x0) // Transmitted good frames after more than a single collision counter
  • 0x40028168MMCTGFCR// Ethernet MMC transmitted good frames counter register

    • [0:31]TGFC (def=0x0) // Transmitted good frames counter
  • 0x40028194MMCRFCECR// Ethernet MMC received frames with CRC error counter register

    • [0:31]RFCFC (def=0x0) // Received frames with CRC error counter
  • 0x40028198MMCRFAECR// Ethernet MMC received frames with alignment error counter register

    • [0:31]RFAEC (def=0x0) // Received frames with alignment error counter
  • 0x400281C4MMCRGUFCR// MMC received good unicast frames counter register

    • [0:31]RGUFC (def=0x0) // Received good unicast frames counter
• 0x40028000ETHERNET_MAC// Ethernet: media access control

  • 0x40028000MACCR// Ethernet MAC configuration register (ETH_MACCR)

    • [2]RE (def=0x0) // Receiver enable
    • [3]TE (def=0x0) // Transmitter enable
    • [4]DC (def=0x0) // Deferral check
    • [5:6]BL (def=0x0) // Back-off limit
    • [7]APCS (def=0x0) // Automatic pad/CRC stripping
    • [9]RD (def=0x0) // Retry disable
    • [10]IPCO (def=0x0) // IPv4 checksum offload
    • [11]DM (def=0x0) // Duplex mode
    • [12]LM (def=0x0) // Loopback mode
    • [13]ROD (def=0x0) // Receive own disable
    • [14]FES (def=0x0) // Fast Ethernet speed
    • [16]CSD (def=0x0) // Carrier sense disable
    • [17:19]IFG (def=0x0) // Interframe gap
    • [22]JD (def=0x0) // Jabber disable
    • [23]WD (def=0x0) // Watchdog disable
  • 0x40028004MACFFR// Ethernet MAC frame filter register (ETH_MACCFFR)

    • [0]PM (def=0x0) // Promiscuous mode
    • [1]HU (def=0x0) // Hash unicast
    • [2]HM (def=0x0) // Hash multicast
    • [3]DAIF (def=0x0) // Destination address inverse filtering
    • [4]PAM (def=0x0) // Pass all multicast
    • [5]BFD (def=0x0) // Broadcast frames disable
    • [6:7]PCF (def=0x0) // Pass control frames
    • [8]SAIF (def=0x0) // Source address inverse filtering
    • [9]SAF (def=0x0) // Source address filter
    • [10]HPF (def=0x0) // Hash or perfect filter
    • [31]RA (def=0x0) // Receive all
  • 0x40028008MACHTHR// Ethernet MAC hash table high register

    • [0:31]HTH (def=0x0) // Hash table high
  • 0x4002800CMACHTLR// Ethernet MAC hash table low register

    • [0:31]HTL (def=0x0) // Hash table low
  • 0x40028010MACMIIAR// Ethernet MAC MII address register (ETH_MACMIIAR)

    • [0]MB (def=0x0) // MII busy
    • [1]MW (def=0x0) // MII write
    • [2:4]CR (def=0x0) // Clock range
    • [6:10]MR (def=0x0) // MII register
    • [11:15]PA (def=0x0) // PHY address
  • 0x40028014MACMIIDR// Ethernet MAC MII data register (ETH_MACMIIDR)

    • [0:15]MD (def=0x0) // MII data
  • 0x40028018MACFCR// Ethernet MAC flow control register (ETH_MACFCR)

    • [0]FCB_BPA (def=0x0) // Flow control busy/back pressure activate
    • [1]TFCE (def=0x0) // Transmit flow control enable
    • [2]RFCE (def=0x0) // Receive flow control enable
    • [3]UPFD (def=0x0) // Unicast pause frame detect
    • [4:5]PLT (def=0x0) // Pause low threshold
    • [7]ZQPD (def=0x0) // Zero-quanta pause disable
    • [16:31]PT (def=0x0) // Pass control frames
  • 0x4002801CMACVLANTR// Ethernet MAC VLAN tag register (ETH_MACVLANTR)

    • [0:15]VLANTI (def=0x0) // VLAN tag identifier (for receive frames)
    • [16]VLANTC (def=0x0) // 12-bit VLAN tag comparison
  • 0x40028028MACRWUFFR// Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)
  • 0x4002802CMACPMTCSR// Ethernet MAC PMT control and status register (ETH_MACPMTCSR)

    • [0]PD (def=0x0) // Power down
    • [1]MPE (def=0x0) // Magic Packet enable
    • [2]WFE (def=0x0) // Wakeup frame enable
    • [5]MPR (def=0x0) // Magic packet received
    • [6]WFR (def=0x0) // Wakeup frame received
    • [9]GU (def=0x0) // Global unicast
    • [31]WFFRPR (def=0x0) // Wakeup frame filter register pointer reset
  • 0x40028038MACSR// Ethernet MAC interrupt status register (ETH_MACSR)

    • [3]PMTS (def=0x0) // PMT status
    • [4]MMCS (def=0x0) // MMC status
    • [5]MMCRS (def=0x0) // MMC receive status
    • [6]MMCTS (def=0x0) // MMC transmit status
    • [9]TSTS (def=0x0) // Time stamp trigger status
  • 0x4002803CMACIMR// Ethernet MAC interrupt mask register (ETH_MACIMR)

    • [3]PMTIM (def=0x0) // PMT interrupt mask
    • [9]TSTIM (def=0x0) // Time stamp trigger interrupt mask
  • 0x40028040MACA0HR// Ethernet MAC address 0 high register (ETH_MACA0HR)

    • [0:15]MACA0H (def=0xFFFF) // MAC address0 high
    • [31]MO (def=0x0) // Always 1
  • 0x40028044MACA0LR// Ethernet MAC address 0 low register

    • [0:31]MACA0L (def=0xFFFFFFFF) // MAC address0 low
  • 0x40028048MACA1HR// Ethernet MAC address 1 high register (ETH_MACA1HR)

    • [0:15]MACA1H (def=0xFFFF) // MAC address1 high
    • [24:29]MBC (def=0x0) // Mask byte control
    • [30]SA (def=0x0) // Source address
    • [31]AE (def=0x0) // Address enable
  • 0x4002804CMACA1LR// Ethernet MAC address1 low register

    • [0:31]MACA1L (def=0xFFFFFFFF) // MAC address1 low
  • 0x40028050MACA2HR// Ethernet MAC address 2 high register (ETH_MACA2HR)

    • [0:15]ETH_MACA2HR (def=0x50) // Ethernet MAC address 2 high register
    • [24:29]MBC (def=0x0) // Mask byte control
    • [30]SA (def=0x0) // Source address
    • [31]AE (def=0x0) // Address enable
  • 0x40028054MACA2LR// Ethernet MAC address 2 low register

    • [0:30]MACA2L (def=0x7FFFFFFF) // MAC address2 low
  • 0x40028058MACA3HR// Ethernet MAC address 3 high register (ETH_MACA3HR)

    • [0:15]MACA3H (def=0xFFFF) // MAC address3 high
    • [24:29]MBC (def=0x0) // Mask byte control
    • [30]SA (def=0x0) // Source address
    • [31]AE (def=0x0) // Address enable
  • 0x4002805CMACA3LR// Ethernet MAC address 3 low register

    • [0:31]MBCA3L (def=0xFFFFFFFF) // MAC address3 low
• 0x40028700ETHERNET_PTP// Ethernet: Precision time protocol

  • 0x40028700PTPTSCR// Ethernet PTP time stamp control register (ETH_PTPTSCR)

    • [0]TSE (def=0x0) // Time stamp enable
    • [1]TSFCU (def=0x0) // Time stamp fine or coarse update
    • [2]TSSTI (def=0x0) // Time stamp system time initialize
    • [3]TSSTU (def=0x0) // Time stamp system time update
    • [4]TSITE (def=0x0) // Time stamp interrupt trigger enable
    • [5]TSARU (def=0x0) // Time stamp addend register update
  • 0x40028704PTPSSIR// Ethernet PTP subsecond increment register

    • [0:7]STSSI (def=0x0) // System time subsecond increment
  • 0x40028708PTPTSHR// Ethernet PTP time stamp high register

    • [0:31]STS (def=0x0) // System time second
  • 0x4002870CPTPTSLR// Ethernet PTP time stamp low register (ETH_PTPTSLR)

    • [0:30]STSS (def=0x0) // System time subseconds
    • [31]STPNS (def=0x0) // System time positive or negative sign
  • 0x40028710PTPTSHUR// Ethernet PTP time stamp high update register

    • [0:31]TSUS (def=0x0) // Time stamp update second
  • 0x40028714PTPTSLUR// Ethernet PTP time stamp low update register (ETH_PTPTSLUR)

    • [0:30]TSUSS (def=0x0) // Time stamp update subseconds
    • [31]TSUPNS (def=0x0) // Time stamp update positive or negative sign
  • 0x40028718PTPTSAR// Ethernet PTP time stamp addend register

    • [0:31]TSA (def=0x0) // Time stamp addend
  • 0x4002871CPTPTTHR// Ethernet PTP target time high register

    • [0:31]TTSH (def=0x0) // Target time stamp high
  • 0x40028720PTPTTLR// Ethernet PTP target time low register

    • [0:31]TTSL (def=0x0) // Target time stamp low
• 0x40029000ETHERNET_DMA// Ethernet: DMA controller operation

  • 0x40029000DMABMR// Ethernet DMA bus mode register

    • [0]SR (def=0x1) // Software reset
    • [1]DA (def=0x0) // DMA Arbitration
    • [2:6]DSL (def=0x0) // Descriptor skip length
    • [8:13]PBL (def=0x1) // Programmable burst length
    • [14:15]RTPR (def=0x0) // Rx Tx priority ratio
    • [16]FB (def=0x0) // Fixed burst
    • [17:22]RDP (def=0x1) // Rx DMA PBL
    • [23]USP (def=0x0) // Use separate PBL
    • [24]FPM (def=0x0) // 4xPBL mode
    • [25]AAB (def=0x0) // Address-aligned beats
  • 0x40029004DMATPDR// Ethernet DMA transmit poll demand register

    • [0:31]TPD (def=0x0) // Transmit poll demand
  • 0x40029008DMARPDR// EHERNET DMA receive poll demand register

    • [0:31]RPD (def=0x0) // Receive poll demand
  • 0x4002900CDMARDLAR// Ethernet DMA receive descriptor list address register

    • [0:31]SRL (def=0x0) // Start of receive list
  • 0x40029010DMATDLAR// Ethernet DMA transmit descriptor list address register

    • [0:31]STL (def=0x0) // Start of transmit list
  • 0x40029014DMASR// Ethernet DMA status register

    • [0]TS (def=0x0) // Transmit status
    • [1]TPSS (def=0x0) // Transmit process stopped status
    • [2]TBUS (def=0x0) // Transmit buffer unavailable status
    • [3]TJTS (def=0x0) // Transmit jabber timeout status
    • [4]ROS (def=0x0) // Receive overflow status
    • [5]TUS (def=0x0) // Transmit underflow status
    • [6]RS (def=0x0) // Receive status
    • [7]RBUS (def=0x0) // Receive buffer unavailable status
    • [8]RPSS (def=0x0) // Receive process stopped status
    • [9]PWTS (def=0x0) // Receive watchdog timeout status
    • [10]ETS (def=0x0) // Early transmit status
    • [13]FBES (def=0x0) // Fatal bus error status
    • [14]ERS (def=0x0) // Early receive status
    • [15]AIS (def=0x0) // Abnormal interrupt summary
    • [16]NIS (def=0x0) // Normal interrupt summary
    • [17:19]RPS (def=0x0) // Receive process state
    • [20:22]TPS (def=0x0) // Transmit process state
    • [23:25]EBS (def=0x0) // Error bits status
    • [27]MMCS (def=0x0) // MMC status
    • [28]PMTS (def=0x0) // PMT status
    • [29]TSTS (def=0x0) // Time stamp trigger status
  • 0x40029018DMAOMR// Ethernet DMA operation mode register

    • [1]SR (def=0x0) // SR
    • [2]OSF (def=0x0) // OSF
    • [3:4]RTC (def=0x0) // RTC
    • [6]FUGF (def=0x0) // FUGF
    • [7]FEF (def=0x0) // FEF
    • [13]ST (def=0x0) // ST
    • [14:16]TTC (def=0x0) // TTC
    • [20]FTF (def=0x0) // FTF
    • [21]TSF (def=0x0) // TSF
    • [24]DFRF (def=0x0) // DFRF
    • [25]RSF (def=0x0) // RSF
    • [26]DTCEFD (def=0x0) // DTCEFD
  • 0x4002901CDMAIER// Ethernet DMA interrupt enable register

    • [0]TIE (def=0x0) // Transmit interrupt enable
    • [1]TPSIE (def=0x0) // Transmit process stopped interrupt enable
    • [2]TBUIE (def=0x0) // Transmit buffer unavailable interrupt enable
    • [3]TJTIE (def=0x0) // Transmit jabber timeout interrupt enable
    • [4]ROIE (def=0x0) // Overflow interrupt enable
    • [5]TUIE (def=0x0) // Underflow interrupt enable
    • [6]RIE (def=0x0) // Receive interrupt enable
    • [7]RBUIE (def=0x0) // Receive buffer unavailable interrupt enable
    • [8]RPSIE (def=0x0) // Receive process stopped interrupt enable
    • [9]RWTIE (def=0x0) // receive watchdog timeout interrupt enable
    • [10]ETIE (def=0x0) // Early transmit interrupt enable
    • [13]FBEIE (def=0x0) // Fatal bus error interrupt enable
    • [14]ERIE (def=0x0) // Early receive interrupt enable
    • [15]AISE (def=0x0) // Abnormal interrupt summary enable
    • [16]NISE (def=0x0) // Normal interrupt summary enable
  • 0x40029020DMAMFBOCR// Ethernet DMA missed frame and buffer overflow counter register

    • [0:15]MFC (def=0x0) // Missed frames by the controller
    • [16]OMFC (def=0x0) // Overflow bit for missed frame counter
    • [17:27]MFA (def=0x0) // Missed frames by the application
    • [28]OFOC (def=0x0) // Overflow bit for FIFO overflow counter
  • 0x40029048DMACHTDR// Ethernet DMA current host transmit descriptor register

    • [0:31]HTDAP (def=0x0) // Host transmit descriptor address pointer
  • 0x4002904CDMACHRDR// Ethernet DMA current host receive descriptor register

    • [0:31]HRDAP (def=0x0) // Host receive descriptor address pointer
  • 0x40029050DMACHTBAR// Ethernet DMA current host transmit buffer address register

    • [0:31]HTBAP (def=0x0) // Host transmit buffer address pointer
  • 0x40029054DMACHRBAR// Ethernet DMA current host receive buffer address register

    • [0:31]HRBAP (def=0x0) // Host receive buffer address pointer