K1921VG015

Search Reset

• 0x3000E000RCU// Reset and clock unit registers

  • 0x3000E000CGCFGAHB// Clockgate AHB configuration register

    • [0]CANEN (def=0x0) // Enable clock CAN
    • [1]USBEN (def=0x0) // Enable clock USB
    • [2]CRYPTOEN (def=0x0) // Enable clock CRYPTO
    • [3]HASHEN (def=0x0) // Enable clock HASH
    • [4]QSPIEN (def=0x0) // Enable clock QSPI
    • [5]SPI0EN (def=0x0) // Enable clock SPI0
    • [6]SPI1EN (def=0x0) // Enable clock SPI1
    • [8]GPIOAEN (def=0x0) // Enable clock GPIOA
    • [9]GPIOBEN (def=0x0) // Enable clock GPIOB
    • [10]GPIOCEN (def=0x0) // Enable clock GPIOC
    • [12]CRC0EN (def=0x0) // Enable clock CRC0
    • [13]CRC1EN (def=0x0) // Enable clock CRC1
  • 0x3000E008CGCFGAPB// Clockgate APB configuration register

    • [0]TMR32EN (def=0x0) // Enable clock TMR32
    • [1]TMR0EN (def=0x0) // Enable clock TMR0
    • [2]TMR1EN (def=0x0) // Enable clock TMR1
    • [3]TMR2EN (def=0x0) // Enable clock TMR2
    • [4]TRNGEN (def=0x0) // Enable clock TRNG
    • [5]I2CEN (def=0x0) // Enable clock I2C
    • [6]UART0EN (def=0x0) // Enable clock UART0
    • [7]UART1EN (def=0x0) // Enable clock UART1
    • [8]UART2EN (def=0x0) // Enable clock UART2
    • [9]UART3EN (def=0x0) // Enable clock UART3
    • [10]UART4EN (def=0x0) // Enable clock UART4
    • [11]WDTEN (def=0x0) // Enable clock WDT
    • [15]ADCSDEN (def=0x0) // Enable clock ADCSD
    • [16]ADCSAREN (def=0x0) // Enable clock ADCSAR
    • [18]CMPEN (def=0x0) // Enable clock CMP
  • 0x3000E010RSTDISAHB// Reset disable AHB configuration register

    • [0]CANEN (def=0x0) // Disable reset from CAN
    • [1]USBEN (def=0x0) // Disable reset from USB
    • [2]CRYPTOEN (def=0x0) // Disable reset from CRYPTO
    • [3]HASHEN (def=0x0) // Disable reset from HASH
    • [4]QSPIEN (def=0x0) // Disable reset from QSPI
    • [5]SPI0EN (def=0x0) // Disable reset from SPI0
    • [6]SPI1EN (def=0x0) // Disable reset from SPI1
    • [8]GPIOAEN (def=0x0) // Disable reset from GPIOA
    • [9]GPIOBEN (def=0x0) // Disable reset from GPIOB
    • [10]GPIOCEN (def=0x0) // Disable reset from GPIOC
    • [12]CRC0EN (def=0x0) // Disable reset from CRC0
    • [13]CRC1EN (def=0x0) // Disable reset from CRC1
  • 0x3000E018RSTDISAPB// Reset disable APB register

    • [0]TMR32EN (def=0x0) // Disable reset from TMR32
    • [1]TMR0EN (def=0x0) // Disable reset from TMR0
    • [2]TMR1EN (def=0x0) // Disable reset from TMR1
    • [3]TMR2EN (def=0x0) // Disable reset from TMR2
    • [4]TRNGEN (def=0x0) // Disable reset from TRNG
    • [5]I2CEN (def=0x0) // Disable reset from I2C
    • [6]UART0EN (def=0x0) // Disable reset from UART0
    • [7]UART1EN (def=0x0) // Disable reset from UART1
    • [8]UART2EN (def=0x0) // Disable reset from UART2
    • [9]UART3EN (def=0x0) // Disable reset from UART3
    • [10]UART4EN (def=0x0) // Disable reset from UART4
    • [11]WDTEN (def=0x0) // Disable reset from WDT
    • [15]ADCSDEN (def=0x0) // Disable reset from ADCSD
    • [16]ADCSAREN (def=0x0) // Disable reset from ADCSAR
    • [18]CMPEN (def=0x0) // Disable reset from CMP
  • 0x3000E020RSTSTAT// Reset Status Register

    • [0]PORVBAT (def=0x0) // PowerOn Reset status
    • [1]POR (def=0x0) // WatchDog Reset status
    • [2]WDOG (def=0x0) // System Reset Status
    • [3]IWDOG (def=0x0) // Lockup Reset Status
    • [4]SYSRST (def=0x0) //
  • 0x3000E030SYSCLKCFG// System clock configuration register

    • [0:1]SRC (def=0x0) // System clock source
    • [16]SECEN (def=0x0) //
  • 0x3000E034SECCNT0// Security counter configuration 0 register

    • [0:15]VAL0 (def=0x0) //
    • [16:31]VAL1 (def=0x0) //
  • 0x3000E038SECCNT1// Security counter configuration 1 register

    • [0:15]VAL2 (def=0x0) //
    • [16:31]VAL3 (def=0x0) //
  • 0x3000E03CCLKSTAT// System clock status register

    • [0:1]SRC (def=0x0) // REFCLK:0:HSI 1MHz if CPE=0 or HSE(XTALL) if CPE=1;SRCCLK:1:HSE(XTALL) if CPE=0 or HSI 1MHz if CPE=1
    • [8]CLKGOOD0 (def=0x0) //
    • [9]CLKGOOD1 (def=0x0) //
    • [10]CLKGOOD2 (def=0x0) //
    • [11]CLKGOOD3 (def=0x0) //
    • [16]CLKERR0 (def=0x0) //
    • [17]CLKERR1 (def=0x0) //
    • [18]CLKERR2 (def=0x0) //
    • [19]CLKERR3 (def=0x0) //
  • 0x3000E050PLLSYSCFG0// PLL configudration 0 register

    • [0]PLLEN (def=0x0) // PLL enable
    • [1:2]BYP (def=0x0) // Bypass
    • [3]DACEN (def=0x0) //
    • [4]DSMEN (def=0x0) //
    • [5:6]FOUTEN (def=0x0) // Output frequency enabled
    • [7:12]REFDIV (def=0x0) //
    • [13:15]PD0A (def=0x0) //
    • [16:21]PD0B (def=0x0) //
    • [22:24]PD1A (def=0x0) //
    • [25:30]PD1B (def=0x0) //
  • 0x3000E054PLLSYSCFG1// PLL configudration 1 register

    • [0:23]FRAC (def=0x0) //
  • 0x3000E058PLLSYSCFG2// PLL configudration 2 register

    • [0:11]FBDIV (def=0x0) //
  • 0x3000E05CPLLSYSCFG3// PLL configudration 3 register

    • [0]DSKEWEN (def=0x0) // Bit must be 0
    • [1]DSKEWCALBYP (def=0x0) //
    • [2:4]DSKEWCALCNT (def=0x0) //
    • [5]DSKEWCALEN (def=0x0) //
    • [6]DSKEWFASTCAL (def=0x0) //
    • [8:19]DSKEWCALIN (def=0x0) //
    • [24]REFSEL (def=0x0) // 0-RefClk; 1- SrcClk
  • 0x3000E060PLLSYSSTAT// PLL Status Register

    • [0]LOCK (def=0x0) // Lock status PLL
  • 0x3000E0B0ADCSARCLKCFG// ADC SAR Configuraton Register

    • [0]CLKEN (def=0x0) // Clock enable
    • [8]RSTDIS (def=0x0) // Reset disable
    • [16:17]CLKSEL (def=0x0) // Clock select
    • [20]DIVEN (def=0x0) // Divider enabled
    • [24:29]DIVN (def=0x0) // Divider coefficient
  • 0x3000E0B4ADCSDCLKCFG// ADC Sigma Delta Configuraton Register

    • [0]CLKEN (def=0x0) // Clock enable
    • [8]RSTDIS (def=0x0) // Reset disable
    • [16:17]CLKSEL (def=0x0) // Clock select
    • [20]DIVEN (def=0x0) // Divider enabled
    • [24:29]DIVN (def=0x0) // Divider coefficient
  • 0x3000E0B8WDOGCLKCFG// Watchdog clock configuration register

    • [0]CLKEN (def=0x0) // Clock enable
    • [8]RSTDIS (def=0x0) // Reset disable
    • [16:17]CLKSEL (def=0x0) // Clock select
    • [20]DIVEN (def=0x0) // Divider enabled
    • [24:29]DIVN (def=0x0) // Divider coefficient
  • 0x3000E0BCCLKOUTCFG// Clockout configuration register

    • [0]CLKEN (def=0x0) // Clock enable
    • [4:5]CLKSEL (def=0x0) // Clock select
    • [8]RSTDIS (def=0x0) // Reset disable
    • [12]DIVEN (def=0x0) // Divider enabled
    • [16:31]DIVN (def=0x0) // Divider coefficient
  • 0x3000E0C0RSTSYS// System Reset Register

    • [0]RSTEN (def=0x0) // Reset enable
    • [16:31]KEY (def=0x0) // KEY 'A55A' in hexadecimal for unblocking
• 0x3000F000PMUSYS// Power management unit registers

  • 0x3000F000PDEN// PMU Core Periph powerdown register

    • [0]PLLEN (def=0x0) // PLL powerdown after WFI command
    • [1]USBEN (def=0x0) // USB powerdown after WFI command
    • [2]ADCEN (def=0x0) // ADC powerdown after WFI command
    • [3]FLASHEN (def=0x0) // FLASH powerdown after WFI command
    • [4]SCMEN (def=0x0) // System clock manager powerdown after WFI command
    • [8]SRAM0EN (def=0x0) // SRAM0 0-32k powerdown
    • [9]SRAM1EN (def=0x0) // SRAM0 32-64k powerdown
    • [10]SRAM2EN (def=0x0) // SRAM0 64-96k powerdown
    • [11]SRAM3EN (def=0x0) // SRAM0 96-128k powerdown
    • [12]SRAM4EN (def=0x0) // SRAM0 128-160k powerdown
    • [13]SRAM5EN (def=0x0) // SRAM0 160-192k powerdown
    • [14]SRAM6EN (def=0x0) // SRAM0 192-224k powerdown
    • [15]SRAM7EN (def=0x0) // SRAM0 224-256k powerdown
  • 0x3000F004PDENFORCE// PMU Core Periph powerdown Force register

    • [0]PLLEN (def=0x0) // PLL powerdown after write this bit
    • [1]USBEN (def=0x0) // USB powerdown after write this bit
    • [2]ADCEN (def=0x0) // ADC powerdown after write this bit
    • [3]FLASHEN (def=0x0) // FLASH powerdown after write this bit
    • [4]SCMEN (def=0x0) // this bit write down no (always read 0)
    • [8]SRAM0EN (def=0x0) // SRAM0 0-32k powerdown
    • [9]SRAM1EN (def=0x0) // SRAM0 32-64k powerdown
    • [10]SRAM2EN (def=0x0) // SRAM0 64-96k powerdown
    • [11]SRAM3EN (def=0x0) // SRAM0 96-128k powerdown
    • [12]SRAM4EN (def=0x0) // SRAM0 128-160k powerdown
    • [13]SRAM5EN (def=0x0) // SRAM0 160-192k powerdown
    • [14]SRAM6EN (def=0x0) // SRAM0 192-224k powerdown
    • [15]SRAM7EN (def=0x0) // SRAM0 224-256k powerdown
  • 0x3000F008RETEN// PMU Enable SRAM retention register

    • [8]SRAM0EN (def=0x0) // Retention SRAM0 block
    • [9]SRAM1EN (def=0x0) // Retention SRAM0 block
    • [10]SRAM2EN (def=0x0) // Retention SRAM0 block
    • [11]SRAM3EN (def=0x0) // Retention SRAM0 block
    • [12]SRAM4EN (def=0x0) // Retention SRAM0 block
    • [13]SRAM5EN (def=0x0) // Retention SRAM0 block
    • [14]SRAM6EN (def=0x0) // Retention SRAM0 block
    • [15]SRAM7EN (def=0x0) // Retention SRAM0 block
  • 0x3000F010ADCPWRCFG// SAR ADC Powerdown configuration register

    • [0]LDOEN (def=0x0) // Enable ADC module Low Drop Out Regulator (LDO)
    • [1]LVLDIS (def=0x0) // Disable ADC level-shifters to go into deep LP mode
  • 0x3000F100CHIPID// Chip identifier register

    • [0:3]REV (def=0x0) // Revision
    • [4:31]ID (def=0x0) // Chip identifier
  • 0x3000F104SERVCTL// Service mode control register

    • [0]SERVEN (def=0x0) // SERV_EN_STAT
    • [8]DONE (def=0x0) // WR_serv_all_erase_req__RD_serv_done
• 0x38012000IWDT// Watchdog control registers

  • 0x38012000LOAD// Watchdog Load Register

    • [0:31]VAL (def=0x0) //
  • 0x38012004VALUE// Watchdog Value Register

    • [0:31]VAL (def=0x0) //
  • 0x38012008CTRL// Watchdog Control Register

    • [0]INTEN (def=0x0) // Enable the interrupt event
    • [1]RESEN (def=0x0) // Enable watchdog reset output
    • [2]BLK (def=0x0) // Blocking configuration
  • 0x3801200CINTCLR// Watchdog Clear Interrupt Register

    • [0:31]WDTCLR (def=0x0) //
  • 0x38012010RIS// Watchdog Raw Interrupt Status Register

    • [0]RAWWDTINT (def=0x0) // Raw interrupt status from the counter
  • 0x38012014MIS// Watchdog Interrupt Status Register

    • [0]WDTINT (def=0x0) // Enabled interrupt status from the counter
  • 0x38012C00LOCK// Watchdog Lock Register

    • [0]REGWRDIS (def=0x0) // Disable write to all registers Watchdog
• 0x3000B000WDT// Watchdog control registers

  • 0x3000B000LOAD// Watchdog Load Register

    • [0:31]VAL (def=0x0) //
  • 0x3000B004VALUE// Watchdog Value Register

    • [0:31]VAL (def=0x0) //
  • 0x3000B008CTRL// Watchdog Control Register

    • [0]INTEN (def=0x0) // Enable the interrupt event
    • [1]RESEN (def=0x0) // Enable watchdog reset output
  • 0x3000B00CINTCLR// Watchdog Clear Interrupt Register

    • [0:31]WDTCLR (def=0x0) //
  • 0x3000B010RIS// Watchdog Raw Interrupt Status Register

    • [0]RAWWDTINT (def=0x0) // Raw interrupt status from the counter
  • 0x3000B014MIS// Watchdog Interrupt Status Register

    • [0]WDTINT (def=0x0) // Enabled interrupt status from the counter
  • 0x3000BC00LOCK// Watchdog Lock Register

    • [0]REGWRDIS (def=0x0) // Disable write to all registers Watchdog
  interrupts:
  • [1] WDT // Watchdog timer interrupt
• 0x30001000TMR0// TMR 16-bit controller registers

  • 0x30001000CTRL// Timer control register

    • [2]CLR (def=0x0) // Timer Clear
    • [4:5]MODE (def=0x0) // Count mode
    • [6:7]DIV (def=0x0) // Divider
    • [8]CLKSEL (def=0x0) // Clock Source Select
  • 0x30001004COUNT// Current value timer register

    • [0:15]VAL (def=0x0) //
  • 0x30001008IM// Interrupt mask register

    • [0]TMR (def=0x0) // Timer Interrupt Enable
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Enable
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Enable
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Enable
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Enable
  • 0x3000100CRIS// Raw Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Status
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Status
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Status
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Status
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Status
  • 0x30001010MIS// Masked Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Status
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Status
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Status
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Status
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Status
  • 0x30001014IC// Clear Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Clear
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Clear
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Clear
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Clear
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Clear
  • 0x30001038DMA_IM// DMA request mask register

    • [0]TMR (def=0x0) // Timer DMA Request Enable
    • [1]CAP0 (def=0x0) // Capcom0 DMA Request Enable
    • [2]CAP1 (def=0x0) // Capcom1 DMA Request Enable
    • [3]CAP2 (def=0x0) // Capcom2 DMA Request Enable
    • [4]CAP3 (def=0x0) // Capcom3 DMA Request Enable
  • 0x3000103CADC_IM// ADC request mask register

    • [0]TMR (def=0x0) // Timer ADC Request Enable
    • [1]CAP0 (def=0x0) // Capcom0 ADC Request Enable
    • [2]CAP1 (def=0x0) // Capcom1 ADC Request Enable
    • [3]CAP2 (def=0x0) // Capcom2 ADC Request Enable
    • [4]CAP3 (def=0x0) // Capcom3 ADC Request Enable
  interrupts:
  • [7] TMR0 // Timer 0 interrupt
• 0x30002000TMR1//

  • 0x30002000CTRL// Timer control register

    • [2]CLR (def=0x0) // Timer Clear
    • [4:5]MODE (def=0x0) // Count mode
    • [6:7]DIV (def=0x0) // Divider
    • [8]CLKSEL (def=0x0) // Clock Source Select
  • 0x30002004COUNT// Current value timer register

    • [0:15]VAL (def=0x0) //
  • 0x30002008IM// Interrupt mask register

    • [0]TMR (def=0x0) // Timer Interrupt Enable
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Enable
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Enable
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Enable
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Enable
  • 0x3000200CRIS// Raw Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Status
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Status
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Status
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Status
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Status
  • 0x30002010MIS// Masked Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Status
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Status
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Status
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Status
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Status
  • 0x30002014IC// Clear Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Clear
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Clear
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Clear
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Clear
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Clear
  • 0x30002038DMA_IM// DMA request mask register

    • [0]TMR (def=0x0) // Timer DMA Request Enable
    • [1]CAP0 (def=0x0) // Capcom0 DMA Request Enable
    • [2]CAP1 (def=0x0) // Capcom1 DMA Request Enable
    • [3]CAP2 (def=0x0) // Capcom2 DMA Request Enable
    • [4]CAP3 (def=0x0) // Capcom3 DMA Request Enable
  • 0x3000203CADC_IM// ADC request mask register

    • [0]TMR (def=0x0) // Timer ADC Request Enable
    • [1]CAP0 (def=0x0) // Capcom0 ADC Request Enable
    • [2]CAP1 (def=0x0) // Capcom1 ADC Request Enable
    • [3]CAP2 (def=0x0) // Capcom2 ADC Request Enable
    • [4]CAP3 (def=0x0) // Capcom3 ADC Request Enable
  interrupts:
  • [8] TMR1 // Timer 1 interrupt
• 0x30003000TMR2//

  • 0x30003000CTRL// Timer control register

    • [2]CLR (def=0x0) // Timer Clear
    • [4:5]MODE (def=0x0) // Count mode
    • [6:7]DIV (def=0x0) // Divider
    • [8]CLKSEL (def=0x0) // Clock Source Select
  • 0x30003004COUNT// Current value timer register

    • [0:15]VAL (def=0x0) //
  • 0x30003008IM// Interrupt mask register

    • [0]TMR (def=0x0) // Timer Interrupt Enable
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Enable
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Enable
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Enable
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Enable
  • 0x3000300CRIS// Raw Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Status
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Status
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Status
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Status
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Status
  • 0x30003010MIS// Masked Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Status
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Status
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Status
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Status
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Status
  • 0x30003014IC// Clear Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Clear
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Clear
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Clear
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Clear
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Clear
  • 0x30003038DMA_IM// DMA request mask register

    • [0]TMR (def=0x0) // Timer DMA Request Enable
    • [1]CAP0 (def=0x0) // Capcom0 DMA Request Enable
    • [2]CAP1 (def=0x0) // Capcom1 DMA Request Enable
    • [3]CAP2 (def=0x0) // Capcom2 DMA Request Enable
    • [4]CAP3 (def=0x0) // Capcom3 DMA Request Enable
  • 0x3000303CADC_IM// ADC request mask register

    • [0]TMR (def=0x0) // Timer ADC Request Enable
    • [1]CAP0 (def=0x0) // Capcom0 ADC Request Enable
    • [2]CAP1 (def=0x0) // Capcom1 ADC Request Enable
    • [3]CAP2 (def=0x0) // Capcom2 ADC Request Enable
    • [4]CAP3 (def=0x0) // Capcom3 ADC Request Enable
  interrupts:
  • [9] TMR2 // Timer 2 interrupt
• 0x30000000TMR32// TMR 32-bit controller registers

  • 0x30000000CTRL// Timer control register

    • [2]CLR (def=0x0) // Timer Clear
    • [4:5]MODE (def=0x0) // Count mode
    • [6:7]DIV (def=0x0) // Divider
    • [8]CLKSEL (def=0x0) // Clock Source Select
  • 0x30000004COUNT// Current value timer register

    • [0:31]VAL (def=0x0) //
  • 0x30000008IM// Interrupt mask register

    • [0]TMR (def=0x0) // Timer Interrupt Enable
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Enable
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Enable
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Enable
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Enable
  • 0x3000000CRIS// Raw Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Status
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Status
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Status
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Status
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Status
  • 0x30000010MIS// Masked Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Status
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Status
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Status
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Status
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Status
  • 0x30000014IC// Clear Interrupt Status register

    • [0]TMR (def=0x0) // Timer Interrupt Clear
    • [1]CAP0 (def=0x0) // Capcom0 Interrupt Clear
    • [2]CAP1 (def=0x0) // Capcom1 Interrupt Clear
    • [3]CAP2 (def=0x0) // Capcom2 Interrupt Clear
    • [4]CAP3 (def=0x0) // Capcom3 Interrupt Clear
  • 0x30000038DMA_IM// DMA request mask register

    • [0]TMR (def=0x0) // Timer DMA Request Enable
    • [1]CAP0 (def=0x0) // Capcom0 DMA Request Enable
    • [2]CAP1 (def=0x0) // Capcom1 DMA Request Enable
    • [3]CAP2 (def=0x0) // Capcom2 DMA Request Enable
    • [4]CAP3 (def=0x0) // Capcom3 DMA Request Enable
  • 0x3000003CADC_IM// ADC request mask register

    • [0]TMR (def=0x0) // Timer ADC Request Enable
    • [1]CAP0 (def=0x0) // Capcom0 ADC Request Enable
    • [2]CAP1 (def=0x0) // Capcom1 ADC Request Enable
    • [3]CAP2 (def=0x0) // Capcom2 ADC Request Enable
    • [4]CAP3 (def=0x0) // Capcom3 ADC Request Enable
• 0x30004000TRNG// Random Number Generators (TRNG) control registers

  • 0x30004000CR// Control register

    • [0]START (def=0x0) // Start/enable the NDRNG
    • [1]LFSR (def=0x0) // Select between the NDRNG with asynchronous free running oscillators (when 0) and the Pseudo-Random
    • [2]TESTEN (def=0x0) // Select input for conditioning function and continuous tests: 0: Noise source (normal mode) 1: Test
    • [3]CONDBYPASS (def=0x0) // 0: Conditioning function is used (normal mode); 1: Conditioning function is bypassed (to observe en
    • [4]TFAILINTEN (def=0x0) // Enable interrupt if any of the health test fails
    • [7]FFULLINTEN (def=0x0) // Enable interrupt if FIFO is full
    • [8]SOFTRST (def=0x0) // Datapath content 2ush and control FSM reset: 0: Normal mode; 1: Datapath components - the health te
    • [11]FORCEROS (def=0x0) // Force oscillators to run when FIFO is full
    • [12]IGNORHTF (def=0x0) // Results of the health tests during start-up and online test do not affect the control FSM state. It
    • [16:19]COUNTBLOCK (def=0x0) // Number of 128-bit blocks used in conditioning (AES-CBC-MAC) post-processing. Zero value is not allo
    • [20]FIFOFILLST (def=0x0) // Enable write of the samples in the FIFO during start-up
    • [21]REPTSTDIS (def=0x0) // All repetition tests (each share) are disabled via this single bit
    • [22]PROPTSTDIS (def=0x0) // All proportion tests (each share) are disabled via this single bit
    • [23:24]AUTOCORRDIS (def=0x0) // Disable speci1c delay(s) check in auto-correlation test - same RO: x1: vs. the following sample of
    • [27:29]CORRTSTDIS (def=0x0) // Disable speci1c delay(s) check in correlation test - different ROs: xx1: vs. the same sample of the
    • [30:31]BLENDMETHOD (def=0x0) // Select blending method: 00: Concatenation; 01: XOR_LEVEL_1; 10: XOR_LEVEL_2; 11: VON-NEUMANN debias
  • 0x30004004FIFOLEV// FIFOLevel register

    • [0:31]VAL (def=0x0) // Number of 32 bits words of random available in the FIFO. Any write to this register clears the Fifo
  • 0x30004008FIFOTHR// FIFOThreshold register

    • [0:6]VAL (def=0x0) // FIFO level below which the module starts to refill the FIFO, expressed in number of 128bit blocks.
  • 0x3000400CFIFODEP// FIFODepth register

    • [0:31]VAL (def=0x0) // Maximum number of 32 bits words that can be stored in the FIFO
  • 0x30004020TESTDATA// Test data register

    • [0:31]VAL (def=0x0) // Test data
  • 0x30004024REPTSTCUTOFF// Cut-off value for the repetition tests register

    • [0:5]VAL (def=0x0) // Cut-off value for the repetition tests
  • 0x30004028PROPTESTCUTOFF// Proportion test cut-off value register

    • [0:8]VAL (def=0x0) // Proportion test cut-off value
  • 0x3000402CLFSRSEED// LFSRSeed register

    • [0:23]SEED (def=0x0) // LFSR initialization value
    • [24:25]SEL (def=0x0) // Share index for which initialization value should be used
  • 0x30004030STAT// Status register

    • [0]DATABUSYTEST (def=0x0) // High when data written to TestData register is being processed
    • [1:3]STATE (def=0x0) // State of the control FSM
    • [4]REPTESTFAIL (def=0x0) // NIST Repetition test(s) failure
    • [5]PROPTESTFAIL (def=0x0) // NIST Proportion test(s) failure
    • [6]ANYTESTFAIL (def=0x0) // Any of the enabled health tests is failing
    • [7]FIFOFULL (def=0x0) // FIFO full status
    • [10]STARTUPFAIL (def=0x0) // Start-up test(s) failure
    • [12:15]REPTSTFAILSH (def=0x0) // NIST Repetition test failure per share
    • [16:19]PRTSTFAILSH (def=0x0) // NIST Proportion test failure per share
    • [20]CONDSLOW (def=0x0) // Conditioning consumes data slower than they are provided to it
  • 0x30004034WARMPERIOD// WarmupPeriod register

    • [0:31]VAL (def=0x0) // Number of clock cycles to wait during warm-up sequence
  • 0x30004038DISOSC// DisableOsc registers

    • [0:7]VAL (def=0x0) // Disable oscillator rings 0 to size-1
  • 0x30004044SAMPERIOD// SamplingPeriod register

    • [0:31]VAL (def=0x0) // Number of clock cycles to wait between sampling moments
  • 0x30004058HWCFG// HW Configuration register

    • [0:7]INVCOUNT (def=0x0) // Generic g_NbOfInverters value
    • [8:11]AUTOCORRTEST (def=0x0) // Generic g_Log2NbOfAutoCorrTestsPerShare value
    • [12:15]FIFODEP (def=0x0) // Generic g_Log2FifoDepth value
  • 0x3000405CCOOLDPERIOD// CooldownPeriod register

    • [0:31]VAL (def=0x0) // Number of clock cycles to wait during cool-down sequence
  • 0x30004060AUTOCORRTESTCUTOFF0// AutoCorrTestCutoff register 0

    • [0:15]ZEROCUTOFF (def=0x0) // Auto-correlation test cut-off value for delay of 0 samples
    • [16:31]ONECUTOFF (def=0x0) // Auto-correlation test cut-off value for delay of +1 sample
  • 0x30004064AUTOCORRTESTCUTOFF1// AutoCorrTestCutoff register 1

    • [0:15]TWOCUTOFF (def=0x0) // Auto-correlation test cut-off value for delay +2 samples
    • [16:31]THREECUTOFF (def=0x0) // Auto-correlation test cut-off value for delay +3 samples
  • 0x30004068CORRTESTCUTOFF0// CorrTestCutoff register 0

    • [0:15]ZEROCUTOFF (def=0x0) // Correlation test cut-off value for time shift/delay of 0 samples
    • [16:31]ONECUTOFF (def=0x0) // Correlation test cut-off value for time shift/delay of +/-1 sample
  • 0x3000406CCORRTESTCUTOFF1// CorrTestCutoff register 1

    • [0:15]TWOCUTOFF (def=0x0) // Correlation test cut-off value for time shift/delay of +/-2 samples
    • [16:31]THREECUTOFF (def=0x0) // Correlation test cut-off value for time shift/delay of +/-3 samples
  • 0x30004070AUTOCORRTESTFAILED// AutoCorrTestFailed register

    • [0:7]VAL (def=0x0) // Auto-correlation test failing ring(s)
  • 0x30004074CORRTESTFAILED// CorrTestFailed register

    • [0:7]VAL (def=0x0) // Correlation test failing rings
  • 0x3000407CHWVERSION// HW Version register

    • [0]HWVER (def=0x0) //
  interrupts:
  • [28] TRNG // TRNG interrupt
• 0x20030000CRC0// CRC controller registers

  • 0x20030000DR// CRC Data register

    • [0:31]VAL (def=0x0) // Data register
  • 0x20030004POST// CRC post register

    • [0:31]VAL (def=0x0) // Post-processing CRC value
  • 0x20030008CR// CRC control register

    • [0]RESET (def=0x0) // RESET bit
    • [1]MODE (def=0x0) // Mode calc CRC
    • [2]XOROUT (def=0x0) // XOR for data out
    • [3:4]POLYSIZE (def=0x0) // Polynomial size. These bits control the size of the polynomial
    • [5:6]REV_IN (def=0x0) // Reverse input data. These bits control the reversal of the bit order of the input data
    • [7]REV_OUT (def=0x0) // Reverse output data
  • 0x2003000CINIT// CRC initial value register

    • [0:31]VAL (def=0x0) // Initial CRC value
  • 0x20030010POL// CRC polynomial register

    • [0:31]VAL (def=0x0) // Programmable polynomial value
• 0x20031000CRC1//

  • 0x20031000DR// CRC Data register

    • [0:31]VAL (def=0x0) // Data register
  • 0x20031004POST// CRC post register

    • [0:31]VAL (def=0x0) // Post-processing CRC value
  • 0x20031008CR// CRC control register

    • [0]RESET (def=0x0) // RESET bit
    • [1]MODE (def=0x0) // Mode calc CRC
    • [2]XOROUT (def=0x0) // XOR for data out
    • [3:4]POLYSIZE (def=0x0) // Polynomial size. These bits control the size of the polynomial
    • [5:6]REV_IN (def=0x0) // Reverse input data. These bits control the reversal of the bit order of the input data
    • [7]REV_OUT (def=0x0) // Reverse output data
  • 0x2003100CINIT// CRC initial value register

    • [0:31]VAL (def=0x0) // Initial CRC value
  • 0x20031010POL// CRC polynomial register

    • [0:31]VAL (def=0x0) // Programmable polynomial value
• 0x20032000HASH// HASH controller registers

  • 0x20032000CR// Control register

    • [0]INIT (def=0x0) // Initialize message digest calculation
    • [1]MODE (def=0x0) // Mode selection
    • [2]LKEY (def=0x0) // Long key selection
    • [3]SAMK (def=0x0) // Same key option
    • [4:5]DATATYPE (def=0x0) // Datatype selection
    • [6]DMAE (def=0x0) // DMA enable
    • [7]MDMAT (def=0x0) // Multiple DMA transfers
    • [8:11]NBW (def=0x0) // Number of words already pushed
    • [12]DINNE (def=0x0) // DIN not empty
    • [14:15]ALGO (def=0x0) // Algorithm selection
  • 0x20032004DATAIN// Data input register

    • [0:31]VAL (def=0x0) // Data input
  • 0x20032008STR// Start register

    • [0:4]NBLW (def=0x0) // Number of valid bits in the last word of the message
    • [8]DCAL (def=0x0) // Digest calculation
  • 0x2003200CIMR// Interrupt enable register

    • [0]DINIE (def=0x0) // Data input interrupt enable
    • [1]DCIE (def=0x0) // Digest calculation completion interrupt enable
  • 0x20032010SR// Interrupt status register

    • [0]DINIS (def=0x0) // Data input interrupt status
    • [1]DCIS (def=0x0) // Digest calculation completion interrupt status
    • [2]DMAS (def=0x0) // DMA status
    • [3]BUSY (def=0x0) // Busy bit
• 0x20020000CRYPTO// Cryptographic module registers (AES_128, AES_256, Magma, Kuznechik algorithms)

  • 0x20020040IRQ_ENABLE// Interrupt enable register

    • [0]DONE (def=0x0) //
    • [1]WR_IGNORED (def=0x0) //
    • [2]DMA_DONE (def=0x0) //
    • [3]DMA_FAIL (def=0x0) //
  • 0x20020044CONTROL// Operation control register

    • [0]UPDATE_KEY (def=0x0) //
    • [1]START (def=0x0) //
    • [2]DIRECTION (def=0x0) //
    • [3:4]ALGORITHM (def=0x0) //
    • [5:6]MODE (def=0x0) //
    • [8]SELF_UPDATE (def=0x0) //
    • [9:10]GCM_PHASE (def=0x0) //
  • 0x20020048BASE_DESCRIPTOR// Register of address of base descriptor

    • [0:3]ZEROES (def=0x0) //
    • [4:31]ADDRESS (def=0x0) //
  • 0x2002004CDMA_CONTROL// DMA operations control register

    • [0]START (def=0x0) //
    • [1]BYTES_SWAP (def=0x0) //
    • [2]WORDS_SWAP (def=0x0) //
  • 0x20020050TERMINATE// Operation emergency terminate register (write of 0xD0 terminate current oeparation)

    • [0:7]CODE (def=0x0) //
  • 0x20020060IRQ// Interrupts pending register

    • [0]DONE (def=0x0) //
    • [1]WR_IGNORED (def=0x0) //
    • [2]DMA_DONE (def=0x0) //
    • [3]DMA_FAIL (def=0x0) //
  • 0x20020080STATUS// Operation status register

    • [0]READY (def=0x0) //
    • [1]KEYS_READY (def=0x0) //
    • [2]OUT_VALID (def=0x0) //
    • [3]IRQ_PENDING (def=0x0) //
    • [4:7]KEYS_STORED (def=0x0) //
    • [8]DMA_ACTIVE (def=0x0) //
    • [9:11]AHB_ERROR (def=0x0) //
    • [12:15]BAD_DESCR (def=0x0) //
    • [16:27]DMA_COUNTER (def=0x0) //
    • [31]DMA_LAST (def=0x0) //
  • 0x20020084CURRENT_DESCRIPTOR// Register of address of current handling descriptor

    • [0:3]ZEROES (def=0x0) //
    • [4:31]ADDRESS (def=0x0) //
  • 0x20020088NEXT_DESCRIPTOR// Register of address of next descriptor

    • [0:3]ZEROES (def=0x0) //
    • [4:31]ADDRESS (def=0x0) //
• 0x30011000TSENS// Temperature sensor controller registers

  • 0x30011000CTRL// TSENS control register

    • [0]EN (def=0x0) // Enable temperatire sensor
    • [1]ADCSEL (def=0x0) // ADC select
    • [2]STYP (def=0x0) // Sense type select
    • [3]ISWAP (def=0x0) //
    • [4]ISEL (def=0x0) // Current source
    • [5]ZS (def=0x0) // Zero sample for calibration
• 0x30010000ADCSAR// ADC SAR control registers

  • 0x30010000SEQEN// Enable sequencer register

    • [0]SEQEN0 (def=0x0) // Enable sequencer 0
    • [1]SEQEN1 (def=0x0) // Enable sequencer 1
  • 0x30010004SEQSYNC// Sequencer sync register

    • [0]SYNC0 (def=0x0) // Enable sequencer 0 software sync
    • [1]SYNC1 (def=0x0) // Enable sequencer 1 software sync
    • [31]GSYNC (def=0x0) // Sync all sequencers
  • 0x30010008FSTAT// FIFO overflow status register

    • [0]OV0 (def=0x0) // Sequencer 0 FIFO overflow
    • [1]OV1 (def=0x0) // Sequencer 1 FIFO overflow
    • [8]UN0 (def=0x0) // Sequencer 0 FIFO underflow
    • [9]UN1 (def=0x0) // Sequencer 1 FIFO underflow
    • [16]DOV0 (def=0x0) // Sequencer 0 FIFO DMA request overflow
    • [17]DOV1 (def=0x0) // Sequencer 1 FIFO DMA request overflow
  • 0x3001000CBSTAT// Busy status register

    • [0]SEQBUSY0 (def=0x0) // Sequencer 0 busy
    • [1]SEQBUSY1 (def=0x0) // Sequencer 1 busy
    • [16]ADCBUSY (def=0x0) // ADC module conversion busy
  • 0x30010010DCTRIG// Digital comparator output trigger status register

    • [0]TOS0 (def=0x0) // DC 0 output trigger status
    • [1]TOS1 (def=0x0) // DC 1 output trigger status
    • [2]TOS2 (def=0x0) // DC 2 output trigger status
    • [3]TOS3 (def=0x0) // DC 3 output trigger status
    • [4]TOS4 (def=0x0) // DC 4 output trigger status
    • [5]TOS5 (def=0x0) // DC 5 output trigger status
    • [6]TOS6 (def=0x0) // DC 6 output trigger status
    • [7]TOS7 (def=0x0) // DC 7 output trigger status
  • 0x30010014DCEV// Digital comparator compare event status register

    • [0]DCEV0 (def=0x0) // Digital compare event 0
    • [1]DCEV1 (def=0x0) // Digital compare event 1
    • [2]DCEV2 (def=0x0) // Digital compare event 2
    • [3]DCEV3 (def=0x0) // Digital compare event 3
    • [4]DCEV4 (def=0x0) // Digital compare event 4
    • [5]DCEV5 (def=0x0) // Digital compare event 5
    • [6]DCEV6 (def=0x0) // Digital compare event 6
    • [7]DCEV7 (def=0x0) // Digital compare event 7
  • 0x30010018CICNT// Interrupt counter clear control

    • [0]ICNT0 (def=0x0) // Clear interrupt counter on sequencer 0 start
    • [1]ICNT1 (def=0x0) // Clear interrupt counter on sequencer 1 start
  • 0x3001001CEMUX// Sequencer start event selection register

    • [0:3]VAL (def=0x0) // Select start event for sequencer 0
  • 0x30010020RIS// Raw interrupt status register

    • [0]SEQRIS0 (def=0x0) // Sequencer 0 raw interrupt status
    • [1]SEQRIS1 (def=0x0) // Sequencer 1 raw interrupt status
    • [8]DCRIS0 (def=0x0) // Raw interrupt status of Digital Comparator 0
    • [9]DCRIS1 (def=0x0) // Raw interrupt status of Digital Comparator 1
    • [10]DCRIS2 (def=0x0) // Raw interrupt status of Digital Comparator 2
    • [11]DCRIS3 (def=0x0) // Raw interrupt status of Digital Comparator 3
    • [12]DCRIS4 (def=0x0) // Raw interrupt status of Digital Comparator 4
    • [13]DCRIS5 (def=0x0) // Raw interrupt status of Digital Comparator 5
    • [14]DCRIS6 (def=0x0) // Raw interrupt status of Digital Comparator 6
    • [15]DCRIS7 (def=0x0) // Raw interrupt status of Digital Comparator 7
  • 0x30010024IM// Interrupt mask register

    • [0]SEQIM0 (def=0x0) // Sequencer 0 interrupt mask
    • [1]SEQIM1 (def=0x0) // Sequencer 1 interrupt mask
    • [8]DCIM0 (def=0x0) // Interrupt mask of Digital Comparator 0
    • [9]DCIM1 (def=0x0) // Interrupt mask of Digital Comparator 1
    • [10]DCIM2 (def=0x0) // Interrupt mask of Digital Comparator 2
    • [11]DCIM3 (def=0x0) // Interrupt mask of Digital Comparator 3
    • [12]DCIM4 (def=0x0) // Interrupt mask of Digital Comparator 4
    • [13]DCIM5 (def=0x0) // Interrupt mask of Digital Comparator 5
    • [14]DCIM6 (def=0x0) // Interrupt mask of Digital Comparator 6
    • [15]DCIM7 (def=0x0) // Interrupt mask of Digital Comparator 7
  • 0x30010028MIS// Masked interrupt status and clear register

    • [0]SEQMIS0 (def=0x0) // Sequencer 0 masked interrupt status
    • [1]SEQMIS1 (def=0x0) // Sequencer 1 masked interrupt status
    • [8]DCMIS0 (def=0x0) // DC 0 masked interrupt status
    • [9]DCMIS1 (def=0x0) // DC 1 masked interrupt status
    • [10]DCMIS2 (def=0x0) // DC 2 masked interrupt status
    • [11]DCMIS3 (def=0x0) // DC 3 masked interrupt status
    • [12]DCMIS4 (def=0x0) // DC 4 masked interrupt status
    • [13]DCMIS5 (def=0x0) // DC 5 masked interrupt status
    • [14]DCMIS6 (def=0x0) // DC 6 masked interrupt status
    • [15]DCMIS7 (def=0x0) // DC 7 masked interrupt status
  • 0x3001002CIC// Interrupt clear register

    • [0]SEQIC0 (def=0x0) // Sequencer 0 interrupt status clear
    • [1]SEQIC1 (def=0x0) // Sequencer 1 interrupt status clear
    • [8]DCIC0 (def=0x0) // DC 0 interrupt status clear
    • [9]DCIC1 (def=0x0) // DC 1 interrupt status clear
    • [10]DCIC2 (def=0x0) // DC 2 interrupt status clear
    • [11]DCIC3 (def=0x0) // DC 3 interrupt status clear
    • [12]DCIC4 (def=0x0) // DC 4 interrupt status clear
    • [13]DCIC5 (def=0x0) // DC 5 interrupt status clear
    • [14]DCIC6 (def=0x0) // DC 6 interrupt status clear
    • [15]DCIC7 (def=0x0) // DC 7 interrupt status clear
  • 0x30010540ACTL// ADC module control register

    • [0]ADCEN (def=0x0) // Enable ADC module
    • [1]ADCRDY (def=0x0) // ADC ready for conversions
    • [4:5]SELRES (def=0x0) // ADC resolution select
    • [8]CALEN (def=0x0) //
    • [9]CALLOAD (def=0x0) //
    • [10]CALSTART (def=0x0) //
    • [11]CALBUSY (def=0x0) // Enable ADC internal calibration
    • [16:22]CALIN (def=0x0) // ADC calibration input value
    • [24:30]CALOUT (def=0x0) // ADC calibration output value
• 0x30012000ADCSD// ADC SAR control registers

  • 0x30012000CTRL// Enable sequencer register

    • [0]ENB (def=0x0) // reserved
    • [1]PUREF (def=0x0) // reserved
    • [4]RST (def=0x0) // reserved
    • [5]SFRST (def=0x0) // reserved
    • [8:9]DR (def=0x0) // reserved
    • [12:14]MDC (def=0x0) // reserved
    • [16:18]WTCYC (def=0x0) // reserved
  • 0x30012004MODE// Sequencer sync register

    • [0:1]CH0 (def=0x0) // Inverce input data on Chanel0
    • [4:5]CH1 (def=0x0) // Inverce input data on Chanel4
    • [8:9]CH2 (def=0x0) // reserved
    • [12:13]CH3 (def=0x0) // reserved
    • [16:17]CH4 (def=0x0) // reserved
    • [20:21]CH5 (def=0x0) // reserved
    • [24:25]CH6 (def=0x0) // reserved
    • [28:29]CH7 (def=0x0) // reserved
  • 0x30012008AMPL// Chanel amplifier register

    • [0:2]CH0 (def=0x0) // Amplifying for Chanel0
    • [4:6]CH1 (def=0x0) // Amplifying for Chanel1
    • [8:10]CH2 (def=0x0) // Amplifying for Chanel2
    • [12:14]CH3 (def=0x0) // Amplifying for Chanel3
    • [16:18]CH4 (def=0x0) // Amplifying for Chanel4
    • [20:22]CH5 (def=0x0) // Amplifying for Chanel5
    • [24:26]CH6 (def=0x0) // Amplifying for Chanel6
    • [28:30]CH7 (def=0x0) // Amplifying for Chanel7
  • 0x3001200CENB// Enable conversion register

    • [0]CH0 (def=0x0) // Enable conversion on Chanel0
    • [1]CH1 (def=0x0) // Enable conversion on Chanel1
    • [2]CH2 (def=0x0) // Enable conversion on Chanel2
    • [3]CH3 (def=0x0) // Enable conversion on Chanel3
    • [4]CH4 (def=0x0) // Enable conversion on Chanel4
    • [5]CH5 (def=0x0) // Enable conversion on Chanel5
    • [6]CH6 (def=0x0) // Enable conversion on Chanel6
    • [7]CH7 (def=0x0) // Enable conversion on Chanel7
  • 0x30012010DIFF// Enable differencial mode for channels

    • [0]CH0 (def=0x0) // Enable conversion on Chanel0
    • [1]CH1 (def=0x0) // Enable conversion on Chanel1
    • [2]CH2 (def=0x0) // Enable conversion on Chanel2
    • [3]CH3 (def=0x0) // Enable conversion on Chanel3
    • [4]CH4 (def=0x0) // Enable conversion on Chanel4
    • [5]CH5 (def=0x0) // Enable conversion on Chanel5
    • [6]CH6 (def=0x0) // Enable conversion on Chanel6
    • [7]CH7 (def=0x0) // Enable conversion on Chanel7
  • 0x30012014READY// Ready for conversion result register

    • [0]CH0 (def=0x0) // Status of Chanel 0
    • [1]CH1 (def=0x0) // Status of Chanel 1
    • [2]CH2 (def=0x0) // Status of Chanel 2
    • [3]CH3 (def=0x0) // Status of Chanel 3
    • [4]CH4 (def=0x0) // Status of Chanel 4
    • [5]CH5 (def=0x0) // Status of Chanel 5
    • [6]CH6 (def=0x0) // Status of Chanel 6
    • [7]CH7 (def=0x0) // Status of Chanel 7
  • 0x30012018DATAUPD// Flag of successful conversion

    • [0]CH0 (def=0x0) //
    • [1]CH1 (def=0x0) //
    • [2]CH2 (def=0x0) //
    • [3]CH3 (def=0x0) //
    • [4]CH4 (def=0x0) //
    • [5]CH5 (def=0x0) //
    • [6]CH6 (def=0x0) //
    • [7]CH7 (def=0x0) //
  • 0x3001201CIM// Interrupt mask

    • [0]CH0 (def=0x0) //
    • [1]CH1 (def=0x0) //
    • [2]CH2 (def=0x0) //
    • [3]CH3 (def=0x0) //
    • [4]CH4 (def=0x0) //
    • [5]CH5 (def=0x0) //
    • [6]CH6 (def=0x0) //
    • [7]CH7 (def=0x0) //
  • 0x30012020MIS// Masked Interrupt Status

    • [0]CH0 (def=0x0) //
    • [1]CH1 (def=0x0) //
    • [2]CH2 (def=0x0) //
    • [3]CH3 (def=0x0) //
    • [4]CH4 (def=0x0) //
    • [5]CH5 (def=0x0) //
    • [6]CH6 (def=0x0) //
    • [7]CH7 (def=0x0) //
  • 0x30012024IC// Interrupt Status Clear

    • [0]CH0 (def=0x0) //
    • [1]CH1 (def=0x0) //
    • [2]CH2 (def=0x0) //
    • [3]CH3 (def=0x0) //
    • [4]CH4 (def=0x0) //
    • [5]CH5 (def=0x0) //
    • [6]CH6 (def=0x0) //
    • [7]CH7 (def=0x0) //
• 0x28000000GPIOA// GPIO control registers

  • 0x28000000DATA// Data Input register

    • [0:15]VAL (def=0x0) //
  • 0x28000004DATAOUT// Data output register

    • [0:15]VAL (def=0x0) //
  • 0x28000008DATAOUTSET// Data output set bits register

    • [0]PIN0 (def=0x0) // Data output set bit 0
    • [1]PIN1 (def=0x0) // Data output set bit 1
    • [2]PIN2 (def=0x0) // Data output set bit 2
    • [3]PIN3 (def=0x0) // Data output set bit 3
    • [4]PIN4 (def=0x0) // Data output set bit 4
    • [5]PIN5 (def=0x0) // Data output set bit 5
    • [6]PIN6 (def=0x0) // Data output set bit 6
    • [7]PIN7 (def=0x0) // Data output set bit 7
    • [8]PIN8 (def=0x0) // Data output set bit 8
    • [9]PIN9 (def=0x0) // Data output set bit 9
    • [10]PIN10 (def=0x0) // Data output set bit 10
    • [11]PIN11 (def=0x0) // Data output set bit 11
    • [12]PIN12 (def=0x0) // Data output set bit 12
    • [13]PIN13 (def=0x0) // Data output set bit 13
    • [14]PIN14 (def=0x0) // Data output set bit 14
    • [15]PIN15 (def=0x0) // Data output set bit 15
  • 0x2800000CDATAOUTCLR// Data output clear bits register

    • [0:15]VAL (def=0x0) // Data output clear
  • 0x28000010DATAOUTTGL// Data output toggle bits register

    • [0:15]VAL (def=0x0) // Data output toggle
  • 0x28000020PULLMODE// Select pull mode register

    • [0]PIN0 (def=0x0) // Select pull mode for pin 0
    • [1]PIN1 (def=0x0) // Select pull mode for pin 1
    • [2]PIN2 (def=0x0) // Select pull mode for pin 2
    • [3]PIN3 (def=0x0) // Select pull mode for pin 3
    • [4]PIN4 (def=0x0) // Select pull mode for pin 4
    • [5]PIN5 (def=0x0) // Select pull mode for pin 5
    • [6]PIN6 (def=0x0) // Select pull mode for pin 6
    • [7]PIN7 (def=0x0) // Select pull mode for pin 7
    • [8]PIN8 (def=0x0) // Select pull mode for pin 8
    • [9]PIN9 (def=0x0) // Select pull mode for pin 9
    • [10]PIN10 (def=0x0) // Select pull mode for pin 10
    • [11]PIN11 (def=0x0) // Select pull mode for pin 11
    • [12]PIN12 (def=0x0) // Select pull mode for pin 12
    • [13]PIN13 (def=0x0) // Select pull mode for pin 13
    • [14]PIN14 (def=0x0) // Select pull mode for pin 14
    • [15]PIN15 (def=0x0) // Select pull mode for pin 15
  • 0x28000024OUTMODE// Select output mode register

    • [0:1]PIN0 (def=0x0) // Select output mode for pin 0
    • [2:3]PIN1 (def=0x0) // Select output mode for pin 1
    • [4:5]PIN2 (def=0x0) // Select output mode for pin 2
    • [6:7]PIN3 (def=0x0) // Select output mode for pin 3
    • [8:9]PIN4 (def=0x0) // Select output mode for pin 4
    • [10:11]PIN5 (def=0x0) // Select output mode for pin 5
    • [12:13]PIN6 (def=0x0) // Select output mode for pin 6
    • [14:15]PIN7 (def=0x0) // Select output mode for pin 7
    • [16:17]PIN8 (def=0x0) // Select output mode for pin 8
    • [18:19]PIN9 (def=0x0) // Select output mode for pin 9
    • [20:21]PIN10 (def=0x0) // Select output mode for pin 10
    • [22:23]PIN11 (def=0x0) // Select output mode for pin 11
    • [24:25]PIN12 (def=0x0) // Select output mode for pin 12
    • [26:27]PIN13 (def=0x0) // Select output mode for pin 13
    • [28:29]PIN14 (def=0x0) // Select output mode for pin 14
    • [30:31]PIN15 (def=0x0) // Select output mode for pin 15
  • 0x2800002COUTENSET// Output enable register

    • [0]PIN0 (def=0x0) // Output enable for pin 0
    • [1]PIN1 (def=0x0) // Output enable for pin 1
    • [2]PIN2 (def=0x0) // Output enable for pin 2
    • [3]PIN3 (def=0x0) // Output enable for pin 3
    • [4]PIN4 (def=0x0) // Output enable for pin 4
    • [5]PIN5 (def=0x0) // Output enable for pin 5
    • [6]PIN6 (def=0x0) // Output enable for pin 6
    • [7]PIN7 (def=0x0) // Output enable for pin 7
    • [8]PIN8 (def=0x0) // Output enable for pin 8
    • [9]PIN9 (def=0x0) // Output enable for pin 9
    • [10]PIN10 (def=0x0) // Output enable for pin 10
    • [11]PIN11 (def=0x0) // Output enable for pin 11
    • [12]PIN12 (def=0x0) // Output enable for pin 12
    • [13]PIN13 (def=0x0) // Output enable for pin 13
    • [14]PIN14 (def=0x0) // Output enable for pin 14
    • [15]PIN15 (def=0x0) // Output enable for pin 15
  • 0x28000030OUTENCLR// Output disable register

    • [0:15]VAL (def=0x0) // Output disable
  • 0x28000034ALTFUNCSET// Alternative function enable register

    • [0]PIN0 (def=0x0) // Alternative function enable for pin 0
    • [1]PIN1 (def=0x0) // Alternative function enable for pin 1
    • [2]PIN2 (def=0x0) // Alternative function enable for pin 2
    • [3]PIN3 (def=0x0) // Alternative function enable for pin 3
    • [4]PIN4 (def=0x0) // Alternative function enable for pin 4
    • [5]PIN5 (def=0x0) // Alternative function enable for pin 5
    • [6]PIN6 (def=0x0) // Alternative function enable for pin 6
    • [7]PIN7 (def=0x0) // Alternative function enable for pin 7
    • [8]PIN8 (def=0x0) // Alternative function enable for pin 8
    • [9]PIN9 (def=0x0) // Alternative function enable for pin 9
    • [10]PIN10 (def=0x0) // Alternative function enable for pin 10
    • [11]PIN11 (def=0x0) // Alternative function enable for pin 11
    • [12]PIN12 (def=0x0) // Alternative function enable for pin 12
    • [13]PIN13 (def=0x0) // Alternative function enable for pin 13
    • [14]PIN14 (def=0x0) // Alternative function enable for pin 14
    • [15]PIN15 (def=0x0) // Alternative function enable for pin 15
  • 0x28000038ALTFUNCCLR// Alternative function disable register

    • [0:15]VAL (def=0x0) // Alternative function disable
  • 0x2800003CALTFUNCNUM// Alternative function number register

    • [0:1]PIN0 (def=0x0) // Select altfunc number for pin 0
    • [2:3]PIN1 (def=0x0) // Select altfunc number for pin 0
    • [4:5]PIN2 (def=0x0) // Select altfunc number for pin 1
    • [6:7]PIN3 (def=0x0) // Select altfunc number for pin 1
    • [8:9]PIN4 (def=0x0) // Select altfunc number for pin 2
    • [10:11]PIN5 (def=0x0) // Select altfunc number for pin 2
    • [12:13]PIN6 (def=0x0) // Select altfunc number for pin 3
    • [14:15]PIN7 (def=0x0) // Select altfunc number for pin 3
    • [16:17]PIN8 (def=0x0) // Select altfunc number for pin 4
    • [18:19]PIN9 (def=0x0) // Select altfunc number for pin 4
    • [20:21]PIN10 (def=0x0) // Select altfunc number for pin 5
    • [22:23]PIN11 (def=0x0) // Select altfunc number for pin 5
    • [24:25]PIN12 (def=0x0) // Select altfunc number for pin 6
    • [26:27]PIN13 (def=0x0) // Select altfunc number for pin 6
    • [28:29]PIN14 (def=0x0) // Select altfunc number for pin 7
    • [30:31]PIN15 (def=0x0) // Select altfunc number for pin 7
  • 0x28000044SYNCSET// Additional double flip-flop syncronization enable register

    • [0]PIN0 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 0
    • [1]PIN1 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 1
    • [2]PIN2 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 2
    • [3]PIN3 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 3
    • [4]PIN4 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 4
    • [5]PIN5 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 5
    • [6]PIN6 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 6
    • [7]PIN7 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 7
    • [8]PIN8 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 8
    • [9]PIN9 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 9
    • [10]PIN10 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 10
    • [11]PIN11 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 11
    • [12]PIN12 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 12
    • [13]PIN13 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 13
    • [14]PIN14 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 14
    • [15]PIN15 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 15
  • 0x28000048SYNCCLR// Additional double flip-flop syncronization disable register

    • [0:15]VAL (def=0x0) // Additional double flip-flop syncronization disable
  • 0x2800004CQUALSET// Qualifier enable register

    • [0]PIN0 (def=0x0) // Qualifier enable for pin 0
    • [1]PIN1 (def=0x0) // Qualifier enable for pin 1
    • [2]PIN2 (def=0x0) // Qualifier enable for pin 2
    • [3]PIN3 (def=0x0) // Qualifier enable for pin 3
    • [4]PIN4 (def=0x0) // Qualifier enable for pin 4
    • [5]PIN5 (def=0x0) // Qualifier enable for pin 5
    • [6]PIN6 (def=0x0) // Qualifier enable for pin 6
    • [7]PIN7 (def=0x0) // Qualifier enable for pin 7
    • [8]PIN8 (def=0x0) // Qualifier enable for pin 8
    • [9]PIN9 (def=0x0) // Qualifier enable for pin 9
    • [10]PIN10 (def=0x0) // Qualifier enable for pin 10
    • [11]PIN11 (def=0x0) // Qualifier enable for pin 11
    • [12]PIN12 (def=0x0) // Qualifier enable for pin 12
    • [13]PIN13 (def=0x0) // Qualifier enable for pin 13
    • [14]PIN14 (def=0x0) // Qualifier enable for pin 14
    • [15]PIN15 (def=0x0) // Qualifier enable for pin 15
  • 0x28000050QUALCLR// Qualifier disable register

    • [0:15]VAL (def=0x0) // Qualifier disable
  • 0x28000054QUALMODESET// Qualifier mode set register

    • [0]PIN0 (def=0x0) // Qualifier mode set for pin 0
    • [1]PIN1 (def=0x0) // Qualifier mode set for pin 1
    • [2]PIN2 (def=0x0) // Qualifier mode set for pin 2
    • [3]PIN3 (def=0x0) // Qualifier mode set for pin 3
    • [4]PIN4 (def=0x0) // Qualifier mode set for pin 4
    • [5]PIN5 (def=0x0) // Qualifier mode set for pin 5
    • [6]PIN6 (def=0x0) // Qualifier mode set for pin 6
    • [7]PIN7 (def=0x0) // Qualifier mode set for pin 7
    • [8]PIN8 (def=0x0) // Qualifier mode set for pin 8
    • [9]PIN9 (def=0x0) // Qualifier mode set for pin 9
    • [10]PIN10 (def=0x0) // Qualifier mode set for pin 10
    • [11]PIN11 (def=0x0) // Qualifier mode set for pin 11
    • [12]PIN12 (def=0x0) // Qualifier mode set for pin 12
    • [13]PIN13 (def=0x0) // Qualifier mode set for pin 13
    • [14]PIN14 (def=0x0) // Qualifier mode set for pin 14
    • [15]PIN15 (def=0x0) // Qualifier mode set for pin 15
  • 0x28000058QUALMODECLR// Qualifier mode clear register

    • [0:15]VAL (def=0x0) // Qualifier mode clear
  • 0x2800005CQUALSAMPLE// Qualifier sample period register

    • [0:19]VAL (def=0x0) // Qualifier sample period
  • 0x28000060INTENSET// Interrupt enable register

    • [0]PIN0 (def=0x0) // Interrupt enable for pin 0
    • [1]PIN1 (def=0x0) // Interrupt enable for pin 1
    • [2]PIN2 (def=0x0) // Interrupt enable for pin 2
    • [3]PIN3 (def=0x0) // Interrupt enable for pin 3
    • [4]PIN4 (def=0x0) // Interrupt enable for pin 4
    • [5]PIN5 (def=0x0) // Interrupt enable for pin 5
    • [6]PIN6 (def=0x0) // Interrupt enable for pin 6
    • [7]PIN7 (def=0x0) // Interrupt enable for pin 7
    • [8]PIN8 (def=0x0) // Interrupt enable for pin 8
    • [9]PIN9 (def=0x0) // Interrupt enable for pin 9
    • [10]PIN10 (def=0x0) // Interrupt enable for pin 10
    • [11]PIN11 (def=0x0) // Interrupt enable for pin 11
    • [12]PIN12 (def=0x0) // Interrupt enable for pin 12
    • [13]PIN13 (def=0x0) // Interrupt enable for pin 13
    • [14]PIN14 (def=0x0) // Interrupt enable for pin 14
    • [15]PIN15 (def=0x0) // Interrupt enable for pin 15
  • 0x28000064INTENCLR// Interrupt disable register

    • [0:15]VAL (def=0x0) // Interrupt disable
  • 0x28000068INTTYPESET// Interrupt type set register

    • [0]PIN0 (def=0x0) // Interrupt type set for pin 0
    • [1]PIN1 (def=0x0) // Interrupt type set for pin 1
    • [2]PIN2 (def=0x0) // Interrupt type set for pin 2
    • [3]PIN3 (def=0x0) // Interrupt type set for pin 3
    • [4]PIN4 (def=0x0) // Interrupt type set for pin 4
    • [5]PIN5 (def=0x0) // Interrupt type set for pin 5
    • [6]PIN6 (def=0x0) // Interrupt type set for pin 6
    • [7]PIN7 (def=0x0) // Interrupt type set for pin 7
    • [8]PIN8 (def=0x0) // Interrupt type set for pin 8
    • [9]PIN9 (def=0x0) // Interrupt type set for pin 9
    • [10]PIN10 (def=0x0) // Interrupt type set for pin 10
    • [11]PIN11 (def=0x0) // Interrupt type set for pin 11
    • [12]PIN12 (def=0x0) // Interrupt type set for pin 12
    • [13]PIN13 (def=0x0) // Interrupt type set for pin 13
    • [14]PIN14 (def=0x0) // Interrupt type set for pin 14
    • [15]PIN15 (def=0x0) // Interrupt type set for pin 15
  • 0x2800006CINTTYPECLR// Interrupt type clear register

    • [0:15]VAL (def=0x0) // Interrupt type clear
  • 0x28000070INTPOLSET// Interrupt polarity set register

    • [0]PIN0 (def=0x0) // Interrupt polarity set for pin 0
    • [1]PIN1 (def=0x0) // Interrupt polarity set for pin 1
    • [2]PIN2 (def=0x0) // Interrupt polarity set for pin 2
    • [3]PIN3 (def=0x0) // Interrupt polarity set for pin 3
    • [4]PIN4 (def=0x0) // Interrupt polarity set for pin 4
    • [5]PIN5 (def=0x0) // Interrupt polarity set for pin 5
    • [6]PIN6 (def=0x0) // Interrupt polarity set for pin 6
    • [7]PIN7 (def=0x0) // Interrupt polarity set for pin 7
    • [8]PIN8 (def=0x0) // Interrupt polarity set for pin 8
    • [9]PIN9 (def=0x0) // Interrupt polarity set for pin 9
    • [10]PIN10 (def=0x0) // Interrupt polarity set for pin 10
    • [11]PIN11 (def=0x0) // Interrupt polarity set for pin 11
    • [12]PIN12 (def=0x0) // Interrupt polarity set for pin 12
    • [13]PIN13 (def=0x0) // Interrupt polarity set for pin 13
    • [14]PIN14 (def=0x0) // Interrupt polarity set for pin 14
    • [15]PIN15 (def=0x0) // Interrupt polarity set for pin 15
  • 0x28000074INTPOLCLR// Interrupt polarity clear register

    • [0:15]VAL (def=0x0) // Interrupt polarity clear
  • 0x28000078INTEDGESET// Interrupt every edge set register

    • [0]PIN0 (def=0x0) // Interrupt every edge set for pin 0
    • [1]PIN1 (def=0x0) // Interrupt every edge set for pin 1
    • [2]PIN2 (def=0x0) // Interrupt every edge set for pin 2
    • [3]PIN3 (def=0x0) // Interrupt every edge set for pin 3
    • [4]PIN4 (def=0x0) // Interrupt every edge set for pin 4
    • [5]PIN5 (def=0x0) // Interrupt every edge set for pin 5
    • [6]PIN6 (def=0x0) // Interrupt every edge set for pin 6
    • [7]PIN7 (def=0x0) // Interrupt every edge set for pin 7
    • [8]PIN8 (def=0x0) // Interrupt every edge set for pin 8
    • [9]PIN9 (def=0x0) // Interrupt every edge set for pin 9
    • [10]PIN10 (def=0x0) // Interrupt every edge set for pin 10
    • [11]PIN11 (def=0x0) // Interrupt every edge set for pin 11
    • [12]PIN12 (def=0x0) // Interrupt every edge set for pin 12
    • [13]PIN13 (def=0x0) // Interrupt every edge set for pin 13
    • [14]PIN14 (def=0x0) // Interrupt every edge set for pin 14
    • [15]PIN15 (def=0x0) // Interrupt every edge set for pin 15
  • 0x2800007CINTEDGECLR// Interrupt every edge clear register

    • [0:15]VAL (def=0x0) // Interrupt every edge clear
  • 0x28000080INTSTATUS// Interrupt status

    • [0]PIN0 (def=0x0) // Interrupt status of pin 0
    • [1]PIN1 (def=0x0) // Interrupt status of pin 1
    • [2]PIN2 (def=0x0) // Interrupt status of pin 2
    • [3]PIN3 (def=0x0) // Interrupt status of pin 3
    • [4]PIN4 (def=0x0) // Interrupt status of pin 4
    • [5]PIN5 (def=0x0) // Interrupt status of pin 5
    • [6]PIN6 (def=0x0) // Interrupt status of pin 6
    • [7]PIN7 (def=0x0) // Interrupt status of pin 7
    • [8]PIN8 (def=0x0) // Interrupt status of pin 8
    • [9]PIN9 (def=0x0) // Interrupt status of pin 9
    • [10]PIN10 (def=0x0) // Interrupt status of pin 10
    • [11]PIN11 (def=0x0) // Interrupt status of pin 11
    • [12]PIN12 (def=0x0) // Interrupt status of pin 12
    • [13]PIN13 (def=0x0) // Interrupt status of pin 13
    • [14]PIN14 (def=0x0) // Interrupt status of pin 14
    • [15]PIN15 (def=0x0) // Interrupt status of pin 15
  • 0x28000084DMAREQSET// DMA request enable register

    • [0]PIN0 (def=0x0) // DMA request enable for pin 0
    • [1]PIN1 (def=0x0) // DMA request enable for pin 1
    • [2]PIN2 (def=0x0) // DMA request enable for pin 2
    • [3]PIN3 (def=0x0) // DMA request enable for pin 3
    • [4]PIN4 (def=0x0) // DMA request enable for pin 4
    • [5]PIN5 (def=0x0) // DMA request enable for pin 5
    • [6]PIN6 (def=0x0) // DMA request enable for pin 6
    • [7]PIN7 (def=0x0) // DMA request enable for pin 7
    • [8]PIN8 (def=0x0) // DMA request enable for pin 8
    • [9]PIN9 (def=0x0) // DMA request enable for pin 9
    • [10]PIN10 (def=0x0) // DMA request enable for pin 10
    • [11]PIN11 (def=0x0) // DMA request enable for pin 11
    • [12]PIN12 (def=0x0) // DMA request enable for pin 12
    • [13]PIN13 (def=0x0) // DMA request enable for pin 13
    • [14]PIN14 (def=0x0) // DMA request enable for pin 14
    • [15]PIN15 (def=0x0) // DMA request enable for pin 15
  • 0x28000088DMAREQCLR// DMA request disable register

    • [0:15]VAL (def=0x0) // DMA request disable
  • 0x2800008CADCSOCSET// ADC Start Of Conversion enable register

    • [0]PIN0 (def=0x0) // ADC SOC enable for pin 0
    • [1]PIN1 (def=0x0) // ADC SOC enable for pin 1
    • [2]PIN2 (def=0x0) // ADC SOC enable for pin 2
    • [3]PIN3 (def=0x0) // ADC SOC enable for pin 3
    • [4]PIN4 (def=0x0) // ADC SOC enable for pin 4
    • [5]PIN5 (def=0x0) // ADC SOC enable for pin 5
    • [6]PIN6 (def=0x0) // ADC SOC enable for pin 6
    • [7]PIN7 (def=0x0) // ADC SOC enable for pin 7
    • [8]PIN8 (def=0x0) // ADC SOC enable for pin 8
    • [9]PIN9 (def=0x0) // ADC SOC enable for pin 9
    • [10]PIN10 (def=0x0) // ADC SOC enable for pin 10
    • [11]PIN11 (def=0x0) // ADC SOC enable for pin 11
    • [12]PIN12 (def=0x0) // ADC SOC enable for pin 12
    • [13]PIN13 (def=0x0) // ADC SOC enable for pin 13
    • [14]PIN14 (def=0x0) // ADC SOC enable for pin 14
    • [15]PIN15 (def=0x0) // ADC SOC enable for pin 15
  • 0x28000090ADCSOCCLR// ADC Start Of Conversion disable register

    • [0:15]VAL (def=0x0) // ADC SOC disable
  • 0x2800009CLOCKKEY// Key register to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE)

    • [0:31]VAL (def=0x0) // Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE)
  • 0x280000A0LOCKSET// Lock pins configuration enable register

    • [0]PIN0 (def=0x0) // Lock configuration enable for pin 0
    • [1]PIN1 (def=0x0) // Lock configuration enable for pin 1
    • [2]PIN2 (def=0x0) // Lock configuration enable for pin 2
    • [3]PIN3 (def=0x0) // Lock configuration enable for pin 3
    • [4]PIN4 (def=0x0) // Lock configuration enable for pin 4
    • [5]PIN5 (def=0x0) // Lock configuration enable for pin 5
    • [6]PIN6 (def=0x0) // Lock configuration enable for pin 6
    • [7]PIN7 (def=0x0) // Lock configuration enable for pin 7
    • [8]PIN8 (def=0x0) // Lock configuration enable for pin 8
    • [9]PIN9 (def=0x0) // Lock configuration enable for pin 9
    • [10]PIN10 (def=0x0) // Lock configuration enable for pin 10
    • [11]PIN11 (def=0x0) // Lock configuration enable for pin 11
    • [12]PIN12 (def=0x0) // Lock configuration enable for pin 12
    • [13]PIN13 (def=0x0) // Lock configuration enable for pin 13
    • [14]PIN14 (def=0x0) // Lock configuration enable for pin 14
    • [15]PIN15 (def=0x0) // Lock configuration enable for pin 15
  • 0x280000A4LOCKCLR// Lock pins configuration disable register

    • [0:15]VAL (def=0x0) // Lock configuration disable
• 0x28001000GPIOB//

  • 0x28001000DATA// Data Input register

    • [0:15]VAL (def=0x0) //
  • 0x28001004DATAOUT// Data output register

    • [0:15]VAL (def=0x0) //
  • 0x28001008DATAOUTSET// Data output set bits register

    • [0]PIN0 (def=0x0) // Data output set bit 0
    • [1]PIN1 (def=0x0) // Data output set bit 1
    • [2]PIN2 (def=0x0) // Data output set bit 2
    • [3]PIN3 (def=0x0) // Data output set bit 3
    • [4]PIN4 (def=0x0) // Data output set bit 4
    • [5]PIN5 (def=0x0) // Data output set bit 5
    • [6]PIN6 (def=0x0) // Data output set bit 6
    • [7]PIN7 (def=0x0) // Data output set bit 7
    • [8]PIN8 (def=0x0) // Data output set bit 8
    • [9]PIN9 (def=0x0) // Data output set bit 9
    • [10]PIN10 (def=0x0) // Data output set bit 10
    • [11]PIN11 (def=0x0) // Data output set bit 11
    • [12]PIN12 (def=0x0) // Data output set bit 12
    • [13]PIN13 (def=0x0) // Data output set bit 13
    • [14]PIN14 (def=0x0) // Data output set bit 14
    • [15]PIN15 (def=0x0) // Data output set bit 15
  • 0x2800100CDATAOUTCLR// Data output clear bits register

    • [0:15]VAL (def=0x0) // Data output clear
  • 0x28001010DATAOUTTGL// Data output toggle bits register

    • [0:15]VAL (def=0x0) // Data output toggle
  • 0x28001020PULLMODE// Select pull mode register

    • [0]PIN0 (def=0x0) // Select pull mode for pin 0
    • [1]PIN1 (def=0x0) // Select pull mode for pin 1
    • [2]PIN2 (def=0x0) // Select pull mode for pin 2
    • [3]PIN3 (def=0x0) // Select pull mode for pin 3
    • [4]PIN4 (def=0x0) // Select pull mode for pin 4
    • [5]PIN5 (def=0x0) // Select pull mode for pin 5
    • [6]PIN6 (def=0x0) // Select pull mode for pin 6
    • [7]PIN7 (def=0x0) // Select pull mode for pin 7
    • [8]PIN8 (def=0x0) // Select pull mode for pin 8
    • [9]PIN9 (def=0x0) // Select pull mode for pin 9
    • [10]PIN10 (def=0x0) // Select pull mode for pin 10
    • [11]PIN11 (def=0x0) // Select pull mode for pin 11
    • [12]PIN12 (def=0x0) // Select pull mode for pin 12
    • [13]PIN13 (def=0x0) // Select pull mode for pin 13
    • [14]PIN14 (def=0x0) // Select pull mode for pin 14
    • [15]PIN15 (def=0x0) // Select pull mode for pin 15
  • 0x28001024OUTMODE// Select output mode register

    • [0:1]PIN0 (def=0x0) // Select output mode for pin 0
    • [2:3]PIN1 (def=0x0) // Select output mode for pin 1
    • [4:5]PIN2 (def=0x0) // Select output mode for pin 2
    • [6:7]PIN3 (def=0x0) // Select output mode for pin 3
    • [8:9]PIN4 (def=0x0) // Select output mode for pin 4
    • [10:11]PIN5 (def=0x0) // Select output mode for pin 5
    • [12:13]PIN6 (def=0x0) // Select output mode for pin 6
    • [14:15]PIN7 (def=0x0) // Select output mode for pin 7
    • [16:17]PIN8 (def=0x0) // Select output mode for pin 8
    • [18:19]PIN9 (def=0x0) // Select output mode for pin 9
    • [20:21]PIN10 (def=0x0) // Select output mode for pin 10
    • [22:23]PIN11 (def=0x0) // Select output mode for pin 11
    • [24:25]PIN12 (def=0x0) // Select output mode for pin 12
    • [26:27]PIN13 (def=0x0) // Select output mode for pin 13
    • [28:29]PIN14 (def=0x0) // Select output mode for pin 14
    • [30:31]PIN15 (def=0x0) // Select output mode for pin 15
  • 0x2800102COUTENSET// Output enable register

    • [0]PIN0 (def=0x0) // Output enable for pin 0
    • [1]PIN1 (def=0x0) // Output enable for pin 1
    • [2]PIN2 (def=0x0) // Output enable for pin 2
    • [3]PIN3 (def=0x0) // Output enable for pin 3
    • [4]PIN4 (def=0x0) // Output enable for pin 4
    • [5]PIN5 (def=0x0) // Output enable for pin 5
    • [6]PIN6 (def=0x0) // Output enable for pin 6
    • [7]PIN7 (def=0x0) // Output enable for pin 7
    • [8]PIN8 (def=0x0) // Output enable for pin 8
    • [9]PIN9 (def=0x0) // Output enable for pin 9
    • [10]PIN10 (def=0x0) // Output enable for pin 10
    • [11]PIN11 (def=0x0) // Output enable for pin 11
    • [12]PIN12 (def=0x0) // Output enable for pin 12
    • [13]PIN13 (def=0x0) // Output enable for pin 13
    • [14]PIN14 (def=0x0) // Output enable for pin 14
    • [15]PIN15 (def=0x0) // Output enable for pin 15
  • 0x28001030OUTENCLR// Output disable register

    • [0:15]VAL (def=0x0) // Output disable
  • 0x28001034ALTFUNCSET// Alternative function enable register

    • [0]PIN0 (def=0x0) // Alternative function enable for pin 0
    • [1]PIN1 (def=0x0) // Alternative function enable for pin 1
    • [2]PIN2 (def=0x0) // Alternative function enable for pin 2
    • [3]PIN3 (def=0x0) // Alternative function enable for pin 3
    • [4]PIN4 (def=0x0) // Alternative function enable for pin 4
    • [5]PIN5 (def=0x0) // Alternative function enable for pin 5
    • [6]PIN6 (def=0x0) // Alternative function enable for pin 6
    • [7]PIN7 (def=0x0) // Alternative function enable for pin 7
    • [8]PIN8 (def=0x0) // Alternative function enable for pin 8
    • [9]PIN9 (def=0x0) // Alternative function enable for pin 9
    • [10]PIN10 (def=0x0) // Alternative function enable for pin 10
    • [11]PIN11 (def=0x0) // Alternative function enable for pin 11
    • [12]PIN12 (def=0x0) // Alternative function enable for pin 12
    • [13]PIN13 (def=0x0) // Alternative function enable for pin 13
    • [14]PIN14 (def=0x0) // Alternative function enable for pin 14
    • [15]PIN15 (def=0x0) // Alternative function enable for pin 15
  • 0x28001038ALTFUNCCLR// Alternative function disable register

    • [0:15]VAL (def=0x0) // Alternative function disable
  • 0x2800103CALTFUNCNUM// Alternative function number register

    • [0:1]PIN0 (def=0x0) // Select altfunc number for pin 0
    • [2:3]PIN1 (def=0x0) // Select altfunc number for pin 0
    • [4:5]PIN2 (def=0x0) // Select altfunc number for pin 1
    • [6:7]PIN3 (def=0x0) // Select altfunc number for pin 1
    • [8:9]PIN4 (def=0x0) // Select altfunc number for pin 2
    • [10:11]PIN5 (def=0x0) // Select altfunc number for pin 2
    • [12:13]PIN6 (def=0x0) // Select altfunc number for pin 3
    • [14:15]PIN7 (def=0x0) // Select altfunc number for pin 3
    • [16:17]PIN8 (def=0x0) // Select altfunc number for pin 4
    • [18:19]PIN9 (def=0x0) // Select altfunc number for pin 4
    • [20:21]PIN10 (def=0x0) // Select altfunc number for pin 5
    • [22:23]PIN11 (def=0x0) // Select altfunc number for pin 5
    • [24:25]PIN12 (def=0x0) // Select altfunc number for pin 6
    • [26:27]PIN13 (def=0x0) // Select altfunc number for pin 6
    • [28:29]PIN14 (def=0x0) // Select altfunc number for pin 7
    • [30:31]PIN15 (def=0x0) // Select altfunc number for pin 7
  • 0x28001044SYNCSET// Additional double flip-flop syncronization enable register

    • [0]PIN0 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 0
    • [1]PIN1 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 1
    • [2]PIN2 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 2
    • [3]PIN3 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 3
    • [4]PIN4 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 4
    • [5]PIN5 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 5
    • [6]PIN6 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 6
    • [7]PIN7 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 7
    • [8]PIN8 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 8
    • [9]PIN9 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 9
    • [10]PIN10 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 10
    • [11]PIN11 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 11
    • [12]PIN12 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 12
    • [13]PIN13 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 13
    • [14]PIN14 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 14
    • [15]PIN15 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 15
  • 0x28001048SYNCCLR// Additional double flip-flop syncronization disable register

    • [0:15]VAL (def=0x0) // Additional double flip-flop syncronization disable
  • 0x2800104CQUALSET// Qualifier enable register

    • [0]PIN0 (def=0x0) // Qualifier enable for pin 0
    • [1]PIN1 (def=0x0) // Qualifier enable for pin 1
    • [2]PIN2 (def=0x0) // Qualifier enable for pin 2
    • [3]PIN3 (def=0x0) // Qualifier enable for pin 3
    • [4]PIN4 (def=0x0) // Qualifier enable for pin 4
    • [5]PIN5 (def=0x0) // Qualifier enable for pin 5
    • [6]PIN6 (def=0x0) // Qualifier enable for pin 6
    • [7]PIN7 (def=0x0) // Qualifier enable for pin 7
    • [8]PIN8 (def=0x0) // Qualifier enable for pin 8
    • [9]PIN9 (def=0x0) // Qualifier enable for pin 9
    • [10]PIN10 (def=0x0) // Qualifier enable for pin 10
    • [11]PIN11 (def=0x0) // Qualifier enable for pin 11
    • [12]PIN12 (def=0x0) // Qualifier enable for pin 12
    • [13]PIN13 (def=0x0) // Qualifier enable for pin 13
    • [14]PIN14 (def=0x0) // Qualifier enable for pin 14
    • [15]PIN15 (def=0x0) // Qualifier enable for pin 15
  • 0x28001050QUALCLR// Qualifier disable register

    • [0:15]VAL (def=0x0) // Qualifier disable
  • 0x28001054QUALMODESET// Qualifier mode set register

    • [0]PIN0 (def=0x0) // Qualifier mode set for pin 0
    • [1]PIN1 (def=0x0) // Qualifier mode set for pin 1
    • [2]PIN2 (def=0x0) // Qualifier mode set for pin 2
    • [3]PIN3 (def=0x0) // Qualifier mode set for pin 3
    • [4]PIN4 (def=0x0) // Qualifier mode set for pin 4
    • [5]PIN5 (def=0x0) // Qualifier mode set for pin 5
    • [6]PIN6 (def=0x0) // Qualifier mode set for pin 6
    • [7]PIN7 (def=0x0) // Qualifier mode set for pin 7
    • [8]PIN8 (def=0x0) // Qualifier mode set for pin 8
    • [9]PIN9 (def=0x0) // Qualifier mode set for pin 9
    • [10]PIN10 (def=0x0) // Qualifier mode set for pin 10
    • [11]PIN11 (def=0x0) // Qualifier mode set for pin 11
    • [12]PIN12 (def=0x0) // Qualifier mode set for pin 12
    • [13]PIN13 (def=0x0) // Qualifier mode set for pin 13
    • [14]PIN14 (def=0x0) // Qualifier mode set for pin 14
    • [15]PIN15 (def=0x0) // Qualifier mode set for pin 15
  • 0x28001058QUALMODECLR// Qualifier mode clear register

    • [0:15]VAL (def=0x0) // Qualifier mode clear
  • 0x2800105CQUALSAMPLE// Qualifier sample period register

    • [0:19]VAL (def=0x0) // Qualifier sample period
  • 0x28001060INTENSET// Interrupt enable register

    • [0]PIN0 (def=0x0) // Interrupt enable for pin 0
    • [1]PIN1 (def=0x0) // Interrupt enable for pin 1
    • [2]PIN2 (def=0x0) // Interrupt enable for pin 2
    • [3]PIN3 (def=0x0) // Interrupt enable for pin 3
    • [4]PIN4 (def=0x0) // Interrupt enable for pin 4
    • [5]PIN5 (def=0x0) // Interrupt enable for pin 5
    • [6]PIN6 (def=0x0) // Interrupt enable for pin 6
    • [7]PIN7 (def=0x0) // Interrupt enable for pin 7
    • [8]PIN8 (def=0x0) // Interrupt enable for pin 8
    • [9]PIN9 (def=0x0) // Interrupt enable for pin 9
    • [10]PIN10 (def=0x0) // Interrupt enable for pin 10
    • [11]PIN11 (def=0x0) // Interrupt enable for pin 11
    • [12]PIN12 (def=0x0) // Interrupt enable for pin 12
    • [13]PIN13 (def=0x0) // Interrupt enable for pin 13
    • [14]PIN14 (def=0x0) // Interrupt enable for pin 14
    • [15]PIN15 (def=0x0) // Interrupt enable for pin 15
  • 0x28001064INTENCLR// Interrupt disable register

    • [0:15]VAL (def=0x0) // Interrupt disable
  • 0x28001068INTTYPESET// Interrupt type set register

    • [0]PIN0 (def=0x0) // Interrupt type set for pin 0
    • [1]PIN1 (def=0x0) // Interrupt type set for pin 1
    • [2]PIN2 (def=0x0) // Interrupt type set for pin 2
    • [3]PIN3 (def=0x0) // Interrupt type set for pin 3
    • [4]PIN4 (def=0x0) // Interrupt type set for pin 4
    • [5]PIN5 (def=0x0) // Interrupt type set for pin 5
    • [6]PIN6 (def=0x0) // Interrupt type set for pin 6
    • [7]PIN7 (def=0x0) // Interrupt type set for pin 7
    • [8]PIN8 (def=0x0) // Interrupt type set for pin 8
    • [9]PIN9 (def=0x0) // Interrupt type set for pin 9
    • [10]PIN10 (def=0x0) // Interrupt type set for pin 10
    • [11]PIN11 (def=0x0) // Interrupt type set for pin 11
    • [12]PIN12 (def=0x0) // Interrupt type set for pin 12
    • [13]PIN13 (def=0x0) // Interrupt type set for pin 13
    • [14]PIN14 (def=0x0) // Interrupt type set for pin 14
    • [15]PIN15 (def=0x0) // Interrupt type set for pin 15
  • 0x2800106CINTTYPECLR// Interrupt type clear register

    • [0:15]VAL (def=0x0) // Interrupt type clear
  • 0x28001070INTPOLSET// Interrupt polarity set register

    • [0]PIN0 (def=0x0) // Interrupt polarity set for pin 0
    • [1]PIN1 (def=0x0) // Interrupt polarity set for pin 1
    • [2]PIN2 (def=0x0) // Interrupt polarity set for pin 2
    • [3]PIN3 (def=0x0) // Interrupt polarity set for pin 3
    • [4]PIN4 (def=0x0) // Interrupt polarity set for pin 4
    • [5]PIN5 (def=0x0) // Interrupt polarity set for pin 5
    • [6]PIN6 (def=0x0) // Interrupt polarity set for pin 6
    • [7]PIN7 (def=0x0) // Interrupt polarity set for pin 7
    • [8]PIN8 (def=0x0) // Interrupt polarity set for pin 8
    • [9]PIN9 (def=0x0) // Interrupt polarity set for pin 9
    • [10]PIN10 (def=0x0) // Interrupt polarity set for pin 10
    • [11]PIN11 (def=0x0) // Interrupt polarity set for pin 11
    • [12]PIN12 (def=0x0) // Interrupt polarity set for pin 12
    • [13]PIN13 (def=0x0) // Interrupt polarity set for pin 13
    • [14]PIN14 (def=0x0) // Interrupt polarity set for pin 14
    • [15]PIN15 (def=0x0) // Interrupt polarity set for pin 15
  • 0x28001074INTPOLCLR// Interrupt polarity clear register

    • [0:15]VAL (def=0x0) // Interrupt polarity clear
  • 0x28001078INTEDGESET// Interrupt every edge set register

    • [0]PIN0 (def=0x0) // Interrupt every edge set for pin 0
    • [1]PIN1 (def=0x0) // Interrupt every edge set for pin 1
    • [2]PIN2 (def=0x0) // Interrupt every edge set for pin 2
    • [3]PIN3 (def=0x0) // Interrupt every edge set for pin 3
    • [4]PIN4 (def=0x0) // Interrupt every edge set for pin 4
    • [5]PIN5 (def=0x0) // Interrupt every edge set for pin 5
    • [6]PIN6 (def=0x0) // Interrupt every edge set for pin 6
    • [7]PIN7 (def=0x0) // Interrupt every edge set for pin 7
    • [8]PIN8 (def=0x0) // Interrupt every edge set for pin 8
    • [9]PIN9 (def=0x0) // Interrupt every edge set for pin 9
    • [10]PIN10 (def=0x0) // Interrupt every edge set for pin 10
    • [11]PIN11 (def=0x0) // Interrupt every edge set for pin 11
    • [12]PIN12 (def=0x0) // Interrupt every edge set for pin 12
    • [13]PIN13 (def=0x0) // Interrupt every edge set for pin 13
    • [14]PIN14 (def=0x0) // Interrupt every edge set for pin 14
    • [15]PIN15 (def=0x0) // Interrupt every edge set for pin 15
  • 0x2800107CINTEDGECLR// Interrupt every edge clear register

    • [0:15]VAL (def=0x0) // Interrupt every edge clear
  • 0x28001080INTSTATUS// Interrupt status

    • [0]PIN0 (def=0x0) // Interrupt status of pin 0
    • [1]PIN1 (def=0x0) // Interrupt status of pin 1
    • [2]PIN2 (def=0x0) // Interrupt status of pin 2
    • [3]PIN3 (def=0x0) // Interrupt status of pin 3
    • [4]PIN4 (def=0x0) // Interrupt status of pin 4
    • [5]PIN5 (def=0x0) // Interrupt status of pin 5
    • [6]PIN6 (def=0x0) // Interrupt status of pin 6
    • [7]PIN7 (def=0x0) // Interrupt status of pin 7
    • [8]PIN8 (def=0x0) // Interrupt status of pin 8
    • [9]PIN9 (def=0x0) // Interrupt status of pin 9
    • [10]PIN10 (def=0x0) // Interrupt status of pin 10
    • [11]PIN11 (def=0x0) // Interrupt status of pin 11
    • [12]PIN12 (def=0x0) // Interrupt status of pin 12
    • [13]PIN13 (def=0x0) // Interrupt status of pin 13
    • [14]PIN14 (def=0x0) // Interrupt status of pin 14
    • [15]PIN15 (def=0x0) // Interrupt status of pin 15
  • 0x28001084DMAREQSET// DMA request enable register

    • [0]PIN0 (def=0x0) // DMA request enable for pin 0
    • [1]PIN1 (def=0x0) // DMA request enable for pin 1
    • [2]PIN2 (def=0x0) // DMA request enable for pin 2
    • [3]PIN3 (def=0x0) // DMA request enable for pin 3
    • [4]PIN4 (def=0x0) // DMA request enable for pin 4
    • [5]PIN5 (def=0x0) // DMA request enable for pin 5
    • [6]PIN6 (def=0x0) // DMA request enable for pin 6
    • [7]PIN7 (def=0x0) // DMA request enable for pin 7
    • [8]PIN8 (def=0x0) // DMA request enable for pin 8
    • [9]PIN9 (def=0x0) // DMA request enable for pin 9
    • [10]PIN10 (def=0x0) // DMA request enable for pin 10
    • [11]PIN11 (def=0x0) // DMA request enable for pin 11
    • [12]PIN12 (def=0x0) // DMA request enable for pin 12
    • [13]PIN13 (def=0x0) // DMA request enable for pin 13
    • [14]PIN14 (def=0x0) // DMA request enable for pin 14
    • [15]PIN15 (def=0x0) // DMA request enable for pin 15
  • 0x28001088DMAREQCLR// DMA request disable register

    • [0:15]VAL (def=0x0) // DMA request disable
  • 0x2800108CADCSOCSET// ADC Start Of Conversion enable register

    • [0]PIN0 (def=0x0) // ADC SOC enable for pin 0
    • [1]PIN1 (def=0x0) // ADC SOC enable for pin 1
    • [2]PIN2 (def=0x0) // ADC SOC enable for pin 2
    • [3]PIN3 (def=0x0) // ADC SOC enable for pin 3
    • [4]PIN4 (def=0x0) // ADC SOC enable for pin 4
    • [5]PIN5 (def=0x0) // ADC SOC enable for pin 5
    • [6]PIN6 (def=0x0) // ADC SOC enable for pin 6
    • [7]PIN7 (def=0x0) // ADC SOC enable for pin 7
    • [8]PIN8 (def=0x0) // ADC SOC enable for pin 8
    • [9]PIN9 (def=0x0) // ADC SOC enable for pin 9
    • [10]PIN10 (def=0x0) // ADC SOC enable for pin 10
    • [11]PIN11 (def=0x0) // ADC SOC enable for pin 11
    • [12]PIN12 (def=0x0) // ADC SOC enable for pin 12
    • [13]PIN13 (def=0x0) // ADC SOC enable for pin 13
    • [14]PIN14 (def=0x0) // ADC SOC enable for pin 14
    • [15]PIN15 (def=0x0) // ADC SOC enable for pin 15
  • 0x28001090ADCSOCCLR// ADC Start Of Conversion disable register

    • [0:15]VAL (def=0x0) // ADC SOC disable
  • 0x2800109CLOCKKEY// Key register to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE)

    • [0:31]VAL (def=0x0) // Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE)
  • 0x280010A0LOCKSET// Lock pins configuration enable register

    • [0]PIN0 (def=0x0) // Lock configuration enable for pin 0
    • [1]PIN1 (def=0x0) // Lock configuration enable for pin 1
    • [2]PIN2 (def=0x0) // Lock configuration enable for pin 2
    • [3]PIN3 (def=0x0) // Lock configuration enable for pin 3
    • [4]PIN4 (def=0x0) // Lock configuration enable for pin 4
    • [5]PIN5 (def=0x0) // Lock configuration enable for pin 5
    • [6]PIN6 (def=0x0) // Lock configuration enable for pin 6
    • [7]PIN7 (def=0x0) // Lock configuration enable for pin 7
    • [8]PIN8 (def=0x0) // Lock configuration enable for pin 8
    • [9]PIN9 (def=0x0) // Lock configuration enable for pin 9
    • [10]PIN10 (def=0x0) // Lock configuration enable for pin 10
    • [11]PIN11 (def=0x0) // Lock configuration enable for pin 11
    • [12]PIN12 (def=0x0) // Lock configuration enable for pin 12
    • [13]PIN13 (def=0x0) // Lock configuration enable for pin 13
    • [14]PIN14 (def=0x0) // Lock configuration enable for pin 14
    • [15]PIN15 (def=0x0) // Lock configuration enable for pin 15
  • 0x280010A4LOCKCLR// Lock pins configuration disable register

    • [0:15]VAL (def=0x0) // Lock configuration disable
• 0x28002000GPIOC//

  • 0x28002000DATA// Data Input register

    • [0:15]VAL (def=0x0) //
  • 0x28002004DATAOUT// Data output register

    • [0:15]VAL (def=0x0) //
  • 0x28002008DATAOUTSET// Data output set bits register

    • [0]PIN0 (def=0x0) // Data output set bit 0
    • [1]PIN1 (def=0x0) // Data output set bit 1
    • [2]PIN2 (def=0x0) // Data output set bit 2
    • [3]PIN3 (def=0x0) // Data output set bit 3
    • [4]PIN4 (def=0x0) // Data output set bit 4
    • [5]PIN5 (def=0x0) // Data output set bit 5
    • [6]PIN6 (def=0x0) // Data output set bit 6
    • [7]PIN7 (def=0x0) // Data output set bit 7
    • [8]PIN8 (def=0x0) // Data output set bit 8
    • [9]PIN9 (def=0x0) // Data output set bit 9
    • [10]PIN10 (def=0x0) // Data output set bit 10
    • [11]PIN11 (def=0x0) // Data output set bit 11
    • [12]PIN12 (def=0x0) // Data output set bit 12
    • [13]PIN13 (def=0x0) // Data output set bit 13
    • [14]PIN14 (def=0x0) // Data output set bit 14
    • [15]PIN15 (def=0x0) // Data output set bit 15
  • 0x2800200CDATAOUTCLR// Data output clear bits register

    • [0:15]VAL (def=0x0) // Data output clear
  • 0x28002010DATAOUTTGL// Data output toggle bits register

    • [0:15]VAL (def=0x0) // Data output toggle
  • 0x28002020PULLMODE// Select pull mode register

    • [0]PIN0 (def=0x0) // Select pull mode for pin 0
    • [1]PIN1 (def=0x0) // Select pull mode for pin 1
    • [2]PIN2 (def=0x0) // Select pull mode for pin 2
    • [3]PIN3 (def=0x0) // Select pull mode for pin 3
    • [4]PIN4 (def=0x0) // Select pull mode for pin 4
    • [5]PIN5 (def=0x0) // Select pull mode for pin 5
    • [6]PIN6 (def=0x0) // Select pull mode for pin 6
    • [7]PIN7 (def=0x0) // Select pull mode for pin 7
    • [8]PIN8 (def=0x0) // Select pull mode for pin 8
    • [9]PIN9 (def=0x0) // Select pull mode for pin 9
    • [10]PIN10 (def=0x0) // Select pull mode for pin 10
    • [11]PIN11 (def=0x0) // Select pull mode for pin 11
    • [12]PIN12 (def=0x0) // Select pull mode for pin 12
    • [13]PIN13 (def=0x0) // Select pull mode for pin 13
    • [14]PIN14 (def=0x0) // Select pull mode for pin 14
    • [15]PIN15 (def=0x0) // Select pull mode for pin 15
  • 0x28002024OUTMODE// Select output mode register

    • [0:1]PIN0 (def=0x0) // Select output mode for pin 0
    • [2:3]PIN1 (def=0x0) // Select output mode for pin 1
    • [4:5]PIN2 (def=0x0) // Select output mode for pin 2
    • [6:7]PIN3 (def=0x0) // Select output mode for pin 3
    • [8:9]PIN4 (def=0x0) // Select output mode for pin 4
    • [10:11]PIN5 (def=0x0) // Select output mode for pin 5
    • [12:13]PIN6 (def=0x0) // Select output mode for pin 6
    • [14:15]PIN7 (def=0x0) // Select output mode for pin 7
    • [16:17]PIN8 (def=0x0) // Select output mode for pin 8
    • [18:19]PIN9 (def=0x0) // Select output mode for pin 9
    • [20:21]PIN10 (def=0x0) // Select output mode for pin 10
    • [22:23]PIN11 (def=0x0) // Select output mode for pin 11
    • [24:25]PIN12 (def=0x0) // Select output mode for pin 12
    • [26:27]PIN13 (def=0x0) // Select output mode for pin 13
    • [28:29]PIN14 (def=0x0) // Select output mode for pin 14
    • [30:31]PIN15 (def=0x0) // Select output mode for pin 15
  • 0x2800202COUTENSET// Output enable register

    • [0]PIN0 (def=0x0) // Output enable for pin 0
    • [1]PIN1 (def=0x0) // Output enable for pin 1
    • [2]PIN2 (def=0x0) // Output enable for pin 2
    • [3]PIN3 (def=0x0) // Output enable for pin 3
    • [4]PIN4 (def=0x0) // Output enable for pin 4
    • [5]PIN5 (def=0x0) // Output enable for pin 5
    • [6]PIN6 (def=0x0) // Output enable for pin 6
    • [7]PIN7 (def=0x0) // Output enable for pin 7
    • [8]PIN8 (def=0x0) // Output enable for pin 8
    • [9]PIN9 (def=0x0) // Output enable for pin 9
    • [10]PIN10 (def=0x0) // Output enable for pin 10
    • [11]PIN11 (def=0x0) // Output enable for pin 11
    • [12]PIN12 (def=0x0) // Output enable for pin 12
    • [13]PIN13 (def=0x0) // Output enable for pin 13
    • [14]PIN14 (def=0x0) // Output enable for pin 14
    • [15]PIN15 (def=0x0) // Output enable for pin 15
  • 0x28002030OUTENCLR// Output disable register

    • [0:15]VAL (def=0x0) // Output disable
  • 0x28002034ALTFUNCSET// Alternative function enable register

    • [0]PIN0 (def=0x0) // Alternative function enable for pin 0
    • [1]PIN1 (def=0x0) // Alternative function enable for pin 1
    • [2]PIN2 (def=0x0) // Alternative function enable for pin 2
    • [3]PIN3 (def=0x0) // Alternative function enable for pin 3
    • [4]PIN4 (def=0x0) // Alternative function enable for pin 4
    • [5]PIN5 (def=0x0) // Alternative function enable for pin 5
    • [6]PIN6 (def=0x0) // Alternative function enable for pin 6
    • [7]PIN7 (def=0x0) // Alternative function enable for pin 7
    • [8]PIN8 (def=0x0) // Alternative function enable for pin 8
    • [9]PIN9 (def=0x0) // Alternative function enable for pin 9
    • [10]PIN10 (def=0x0) // Alternative function enable for pin 10
    • [11]PIN11 (def=0x0) // Alternative function enable for pin 11
    • [12]PIN12 (def=0x0) // Alternative function enable for pin 12
    • [13]PIN13 (def=0x0) // Alternative function enable for pin 13
    • [14]PIN14 (def=0x0) // Alternative function enable for pin 14
    • [15]PIN15 (def=0x0) // Alternative function enable for pin 15
  • 0x28002038ALTFUNCCLR// Alternative function disable register

    • [0:15]VAL (def=0x0) // Alternative function disable
  • 0x2800203CALTFUNCNUM// Alternative function number register

    • [0:1]PIN0 (def=0x0) // Select altfunc number for pin 0
    • [2:3]PIN1 (def=0x0) // Select altfunc number for pin 0
    • [4:5]PIN2 (def=0x0) // Select altfunc number for pin 1
    • [6:7]PIN3 (def=0x0) // Select altfunc number for pin 1
    • [8:9]PIN4 (def=0x0) // Select altfunc number for pin 2
    • [10:11]PIN5 (def=0x0) // Select altfunc number for pin 2
    • [12:13]PIN6 (def=0x0) // Select altfunc number for pin 3
    • [14:15]PIN7 (def=0x0) // Select altfunc number for pin 3
    • [16:17]PIN8 (def=0x0) // Select altfunc number for pin 4
    • [18:19]PIN9 (def=0x0) // Select altfunc number for pin 4
    • [20:21]PIN10 (def=0x0) // Select altfunc number for pin 5
    • [22:23]PIN11 (def=0x0) // Select altfunc number for pin 5
    • [24:25]PIN12 (def=0x0) // Select altfunc number for pin 6
    • [26:27]PIN13 (def=0x0) // Select altfunc number for pin 6
    • [28:29]PIN14 (def=0x0) // Select altfunc number for pin 7
    • [30:31]PIN15 (def=0x0) // Select altfunc number for pin 7
  • 0x28002044SYNCSET// Additional double flip-flop syncronization enable register

    • [0]PIN0 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 0
    • [1]PIN1 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 1
    • [2]PIN2 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 2
    • [3]PIN3 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 3
    • [4]PIN4 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 4
    • [5]PIN5 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 5
    • [6]PIN6 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 6
    • [7]PIN7 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 7
    • [8]PIN8 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 8
    • [9]PIN9 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 9
    • [10]PIN10 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 10
    • [11]PIN11 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 11
    • [12]PIN12 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 12
    • [13]PIN13 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 13
    • [14]PIN14 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 14
    • [15]PIN15 (def=0x0) // Additional double flip-flop syncronization buffer enable for pin 15
  • 0x28002048SYNCCLR// Additional double flip-flop syncronization disable register

    • [0:15]VAL (def=0x0) // Additional double flip-flop syncronization disable
  • 0x2800204CQUALSET// Qualifier enable register

    • [0]PIN0 (def=0x0) // Qualifier enable for pin 0
    • [1]PIN1 (def=0x0) // Qualifier enable for pin 1
    • [2]PIN2 (def=0x0) // Qualifier enable for pin 2
    • [3]PIN3 (def=0x0) // Qualifier enable for pin 3
    • [4]PIN4 (def=0x0) // Qualifier enable for pin 4
    • [5]PIN5 (def=0x0) // Qualifier enable for pin 5
    • [6]PIN6 (def=0x0) // Qualifier enable for pin 6
    • [7]PIN7 (def=0x0) // Qualifier enable for pin 7
    • [8]PIN8 (def=0x0) // Qualifier enable for pin 8
    • [9]PIN9 (def=0x0) // Qualifier enable for pin 9
    • [10]PIN10 (def=0x0) // Qualifier enable for pin 10
    • [11]PIN11 (def=0x0) // Qualifier enable for pin 11
    • [12]PIN12 (def=0x0) // Qualifier enable for pin 12
    • [13]PIN13 (def=0x0) // Qualifier enable for pin 13
    • [14]PIN14 (def=0x0) // Qualifier enable for pin 14
    • [15]PIN15 (def=0x0) // Qualifier enable for pin 15
  • 0x28002050QUALCLR// Qualifier disable register

    • [0:15]VAL (def=0x0) // Qualifier disable
  • 0x28002054QUALMODESET// Qualifier mode set register

    • [0]PIN0 (def=0x0) // Qualifier mode set for pin 0
    • [1]PIN1 (def=0x0) // Qualifier mode set for pin 1
    • [2]PIN2 (def=0x0) // Qualifier mode set for pin 2
    • [3]PIN3 (def=0x0) // Qualifier mode set for pin 3
    • [4]PIN4 (def=0x0) // Qualifier mode set for pin 4
    • [5]PIN5 (def=0x0) // Qualifier mode set for pin 5
    • [6]PIN6 (def=0x0) // Qualifier mode set for pin 6
    • [7]PIN7 (def=0x0) // Qualifier mode set for pin 7
    • [8]PIN8 (def=0x0) // Qualifier mode set for pin 8
    • [9]PIN9 (def=0x0) // Qualifier mode set for pin 9
    • [10]PIN10 (def=0x0) // Qualifier mode set for pin 10
    • [11]PIN11 (def=0x0) // Qualifier mode set for pin 11
    • [12]PIN12 (def=0x0) // Qualifier mode set for pin 12
    • [13]PIN13 (def=0x0) // Qualifier mode set for pin 13
    • [14]PIN14 (def=0x0) // Qualifier mode set for pin 14
    • [15]PIN15 (def=0x0) // Qualifier mode set for pin 15
  • 0x28002058QUALMODECLR// Qualifier mode clear register

    • [0:15]VAL (def=0x0) // Qualifier mode clear
  • 0x2800205CQUALSAMPLE// Qualifier sample period register

    • [0:19]VAL (def=0x0) // Qualifier sample period
  • 0x28002060INTENSET// Interrupt enable register

    • [0]PIN0 (def=0x0) // Interrupt enable for pin 0
    • [1]PIN1 (def=0x0) // Interrupt enable for pin 1
    • [2]PIN2 (def=0x0) // Interrupt enable for pin 2
    • [3]PIN3 (def=0x0) // Interrupt enable for pin 3
    • [4]PIN4 (def=0x0) // Interrupt enable for pin 4
    • [5]PIN5 (def=0x0) // Interrupt enable for pin 5
    • [6]PIN6 (def=0x0) // Interrupt enable for pin 6
    • [7]PIN7 (def=0x0) // Interrupt enable for pin 7
    • [8]PIN8 (def=0x0) // Interrupt enable for pin 8
    • [9]PIN9 (def=0x0) // Interrupt enable for pin 9
    • [10]PIN10 (def=0x0) // Interrupt enable for pin 10
    • [11]PIN11 (def=0x0) // Interrupt enable for pin 11
    • [12]PIN12 (def=0x0) // Interrupt enable for pin 12
    • [13]PIN13 (def=0x0) // Interrupt enable for pin 13
    • [14]PIN14 (def=0x0) // Interrupt enable for pin 14
    • [15]PIN15 (def=0x0) // Interrupt enable for pin 15
  • 0x28002064INTENCLR// Interrupt disable register

    • [0:15]VAL (def=0x0) // Interrupt disable
  • 0x28002068INTTYPESET// Interrupt type set register

    • [0]PIN0 (def=0x0) // Interrupt type set for pin 0
    • [1]PIN1 (def=0x0) // Interrupt type set for pin 1
    • [2]PIN2 (def=0x0) // Interrupt type set for pin 2
    • [3]PIN3 (def=0x0) // Interrupt type set for pin 3
    • [4]PIN4 (def=0x0) // Interrupt type set for pin 4
    • [5]PIN5 (def=0x0) // Interrupt type set for pin 5
    • [6]PIN6 (def=0x0) // Interrupt type set for pin 6
    • [7]PIN7 (def=0x0) // Interrupt type set for pin 7
    • [8]PIN8 (def=0x0) // Interrupt type set for pin 8
    • [9]PIN9 (def=0x0) // Interrupt type set for pin 9
    • [10]PIN10 (def=0x0) // Interrupt type set for pin 10
    • [11]PIN11 (def=0x0) // Interrupt type set for pin 11
    • [12]PIN12 (def=0x0) // Interrupt type set for pin 12
    • [13]PIN13 (def=0x0) // Interrupt type set for pin 13
    • [14]PIN14 (def=0x0) // Interrupt type set for pin 14
    • [15]PIN15 (def=0x0) // Interrupt type set for pin 15
  • 0x2800206CINTTYPECLR// Interrupt type clear register

    • [0:15]VAL (def=0x0) // Interrupt type clear
  • 0x28002070INTPOLSET// Interrupt polarity set register

    • [0]PIN0 (def=0x0) // Interrupt polarity set for pin 0
    • [1]PIN1 (def=0x0) // Interrupt polarity set for pin 1
    • [2]PIN2 (def=0x0) // Interrupt polarity set for pin 2
    • [3]PIN3 (def=0x0) // Interrupt polarity set for pin 3
    • [4]PIN4 (def=0x0) // Interrupt polarity set for pin 4
    • [5]PIN5 (def=0x0) // Interrupt polarity set for pin 5
    • [6]PIN6 (def=0x0) // Interrupt polarity set for pin 6
    • [7]PIN7 (def=0x0) // Interrupt polarity set for pin 7
    • [8]PIN8 (def=0x0) // Interrupt polarity set for pin 8
    • [9]PIN9 (def=0x0) // Interrupt polarity set for pin 9
    • [10]PIN10 (def=0x0) // Interrupt polarity set for pin 10
    • [11]PIN11 (def=0x0) // Interrupt polarity set for pin 11
    • [12]PIN12 (def=0x0) // Interrupt polarity set for pin 12
    • [13]PIN13 (def=0x0) // Interrupt polarity set for pin 13
    • [14]PIN14 (def=0x0) // Interrupt polarity set for pin 14
    • [15]PIN15 (def=0x0) // Interrupt polarity set for pin 15
  • 0x28002074INTPOLCLR// Interrupt polarity clear register

    • [0:15]VAL (def=0x0) // Interrupt polarity clear
  • 0x28002078INTEDGESET// Interrupt every edge set register

    • [0]PIN0 (def=0x0) // Interrupt every edge set for pin 0
    • [1]PIN1 (def=0x0) // Interrupt every edge set for pin 1
    • [2]PIN2 (def=0x0) // Interrupt every edge set for pin 2
    • [3]PIN3 (def=0x0) // Interrupt every edge set for pin 3
    • [4]PIN4 (def=0x0) // Interrupt every edge set for pin 4
    • [5]PIN5 (def=0x0) // Interrupt every edge set for pin 5
    • [6]PIN6 (def=0x0) // Interrupt every edge set for pin 6
    • [7]PIN7 (def=0x0) // Interrupt every edge set for pin 7
    • [8]PIN8 (def=0x0) // Interrupt every edge set for pin 8
    • [9]PIN9 (def=0x0) // Interrupt every edge set for pin 9
    • [10]PIN10 (def=0x0) // Interrupt every edge set for pin 10
    • [11]PIN11 (def=0x0) // Interrupt every edge set for pin 11
    • [12]PIN12 (def=0x0) // Interrupt every edge set for pin 12
    • [13]PIN13 (def=0x0) // Interrupt every edge set for pin 13
    • [14]PIN14 (def=0x0) // Interrupt every edge set for pin 14
    • [15]PIN15 (def=0x0) // Interrupt every edge set for pin 15
  • 0x2800207CINTEDGECLR// Interrupt every edge clear register

    • [0:15]VAL (def=0x0) // Interrupt every edge clear
  • 0x28002080INTSTATUS// Interrupt status

    • [0]PIN0 (def=0x0) // Interrupt status of pin 0
    • [1]PIN1 (def=0x0) // Interrupt status of pin 1
    • [2]PIN2 (def=0x0) // Interrupt status of pin 2
    • [3]PIN3 (def=0x0) // Interrupt status of pin 3
    • [4]PIN4 (def=0x0) // Interrupt status of pin 4
    • [5]PIN5 (def=0x0) // Interrupt status of pin 5
    • [6]PIN6 (def=0x0) // Interrupt status of pin 6
    • [7]PIN7 (def=0x0) // Interrupt status of pin 7
    • [8]PIN8 (def=0x0) // Interrupt status of pin 8
    • [9]PIN9 (def=0x0) // Interrupt status of pin 9
    • [10]PIN10 (def=0x0) // Interrupt status of pin 10
    • [11]PIN11 (def=0x0) // Interrupt status of pin 11
    • [12]PIN12 (def=0x0) // Interrupt status of pin 12
    • [13]PIN13 (def=0x0) // Interrupt status of pin 13
    • [14]PIN14 (def=0x0) // Interrupt status of pin 14
    • [15]PIN15 (def=0x0) // Interrupt status of pin 15
  • 0x28002084DMAREQSET// DMA request enable register

    • [0]PIN0 (def=0x0) // DMA request enable for pin 0
    • [1]PIN1 (def=0x0) // DMA request enable for pin 1
    • [2]PIN2 (def=0x0) // DMA request enable for pin 2
    • [3]PIN3 (def=0x0) // DMA request enable for pin 3
    • [4]PIN4 (def=0x0) // DMA request enable for pin 4
    • [5]PIN5 (def=0x0) // DMA request enable for pin 5
    • [6]PIN6 (def=0x0) // DMA request enable for pin 6
    • [7]PIN7 (def=0x0) // DMA request enable for pin 7
    • [8]PIN8 (def=0x0) // DMA request enable for pin 8
    • [9]PIN9 (def=0x0) // DMA request enable for pin 9
    • [10]PIN10 (def=0x0) // DMA request enable for pin 10
    • [11]PIN11 (def=0x0) // DMA request enable for pin 11
    • [12]PIN12 (def=0x0) // DMA request enable for pin 12
    • [13]PIN13 (def=0x0) // DMA request enable for pin 13
    • [14]PIN14 (def=0x0) // DMA request enable for pin 14
    • [15]PIN15 (def=0x0) // DMA request enable for pin 15
  • 0x28002088DMAREQCLR// DMA request disable register

    • [0:15]VAL (def=0x0) // DMA request disable
  • 0x2800208CADCSOCSET// ADC Start Of Conversion enable register

    • [0]PIN0 (def=0x0) // ADC SOC enable for pin 0
    • [1]PIN1 (def=0x0) // ADC SOC enable for pin 1
    • [2]PIN2 (def=0x0) // ADC SOC enable for pin 2
    • [3]PIN3 (def=0x0) // ADC SOC enable for pin 3
    • [4]PIN4 (def=0x0) // ADC SOC enable for pin 4
    • [5]PIN5 (def=0x0) // ADC SOC enable for pin 5
    • [6]PIN6 (def=0x0) // ADC SOC enable for pin 6
    • [7]PIN7 (def=0x0) // ADC SOC enable for pin 7
    • [8]PIN8 (def=0x0) // ADC SOC enable for pin 8
    • [9]PIN9 (def=0x0) // ADC SOC enable for pin 9
    • [10]PIN10 (def=0x0) // ADC SOC enable for pin 10
    • [11]PIN11 (def=0x0) // ADC SOC enable for pin 11
    • [12]PIN12 (def=0x0) // ADC SOC enable for pin 12
    • [13]PIN13 (def=0x0) // ADC SOC enable for pin 13
    • [14]PIN14 (def=0x0) // ADC SOC enable for pin 14
    • [15]PIN15 (def=0x0) // ADC SOC enable for pin 15
  • 0x28002090ADCSOCCLR// ADC Start Of Conversion disable register

    • [0:15]VAL (def=0x0) // ADC SOC disable
  • 0x2800209CLOCKKEY// Key register to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE)

    • [0:31]VAL (def=0x0) // Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE)
  • 0x280020A0LOCKSET// Lock pins configuration enable register

    • [0]PIN0 (def=0x0) // Lock configuration enable for pin 0
    • [1]PIN1 (def=0x0) // Lock configuration enable for pin 1
    • [2]PIN2 (def=0x0) // Lock configuration enable for pin 2
    • [3]PIN3 (def=0x0) // Lock configuration enable for pin 3
    • [4]PIN4 (def=0x0) // Lock configuration enable for pin 4
    • [5]PIN5 (def=0x0) // Lock configuration enable for pin 5
    • [6]PIN6 (def=0x0) // Lock configuration enable for pin 6
    • [7]PIN7 (def=0x0) // Lock configuration enable for pin 7
    • [8]PIN8 (def=0x0) // Lock configuration enable for pin 8
    • [9]PIN9 (def=0x0) // Lock configuration enable for pin 9
    • [10]PIN10 (def=0x0) // Lock configuration enable for pin 10
    • [11]PIN11 (def=0x0) // Lock configuration enable for pin 11
    • [12]PIN12 (def=0x0) // Lock configuration enable for pin 12
    • [13]PIN13 (def=0x0) // Lock configuration enable for pin 13
    • [14]PIN14 (def=0x0) // Lock configuration enable for pin 14
    • [15]PIN15 (def=0x0) // Lock configuration enable for pin 15
  • 0x280020A4LOCKCLR// Lock pins configuration disable register

    • [0:15]VAL (def=0x0) // Lock configuration disable
• 0x20010000USB// USB control registers

  • 0x20010000INTSTAT0// Interrupt status register

    • [0]USBBUSINT (def=0x0) // Interrupt flag events on the USB bus
    • [1]CEP_INT (def=0x0) // Interrupt flag Control EndPoint
    • [2]EP0_INT (def=0x0) // Interrupt flags EndPoint 0
    • [3]EP1_INT (def=0x0) // Interrupt flags EndPoint 1
    • [4]EP2_INT (def=0x0) // Interrupt flags EndPoint 2
    • [5]EP3_INT (def=0x0) // Interrupt flags EndPoint 3
  • 0x20010008INTEN0// Interrupt enable register

    • [0]USBBUSINTEN (def=0x0) // Enable interrupts from the events on the USB bus
    • [1]CEP_INTEN (def=0x0) // Interrupt enable for Control EndPoint
    • [2]EP0_INTEN (def=0x0) // Interrupt enable for EndPoint 0
    • [3]EP1_INTEN (def=0x0) // Interrupt enable for EndPoint 1
    • [4]EP2_INTEN (def=0x0) // Interrupt enable for EndPoint 2
    • [5]EP3_INTEN (def=0x0) // Interrupt enable for EndPoint 3
  • 0x20010010INTSTAT1// USB Interrupt status register

    • [0]SOF (def=0x0) // Flag SOF packet reception
    • [1]RESSTATUS (def=0x0) // Completion flag reset the root port
    • [2]RESUME (def=0x0) // Flag reactivate the device
    • [3]SUSPEND (def=0x0) // SUSPEND mode request bit
    • [4]HSSETTLE (def=0x0) // Completion flag reset and switching devices in high-speed mode
    • [5]DMACMPL (def=0x0) // Completion flag DMA data transfer
    • [6]CLKUNSTBL (def=0x0) // Interrupt flag, signaling an unstable clock signal UTMI and to initialize the device controller reg
  • 0x20010014INTEN1// USB Interrupt enable register

    • [0]SOF (def=0x0) // Enable SOF packet reception
    • [1]RESSTATUS (def=0x0) // Enable completion reset the root port
    • [2]RESUME (def=0x0) // Enable reactivate the device
    • [3]SUSPEND (def=0x0) // Enable SUSPEND mode request bit
    • [4]HISPEED (def=0x0) // Enable completion reset and switching devices in high-speed mode
    • [5]DMACMPL (def=0x0) // Enable completion DMA data transfer
    • [6]CLKUNSTBL (def=0x0) // Enable interrupt, signaling an unstable clock signal UTMI and to initialize the device controller r
  • 0x20010018OPERATIONS// USB Operations register

    • [0]GEN_RESUME (def=0x0) // Bit start recovery work
    • [1]HIGHSPEED (def=0x0) // Trigger bit protocol 'Chirp'
    • [2]CURRENTSPEED (def=0x0) // Speed indication device controller 1-High speed; 0 - Full speed
  • 0x2001001CFRAMECNT// USB Frame counter register

    • [0:2]MICRO_FRAME_COUNTER (def=0x0) // Number field current a chip
    • [3:13]FRAME_COUNTER (def=0x0) // Field frame counter since last SOF packet
  • 0x20010020USBADDR// USB Address register

    • [0:6]USBADDR (def=0x0) // Field of the current address of the device
  • 0x20010028CEP_DATA_BUF// Data buffer for transmission register of Control EndPoint

    • [0:15]VAL (def=0x0) // Data buffer for transmission
  • 0x2001002CCEP_CTRL_STAT// Control register and buffer status of Control EndPoint

    • [0]NAKCLEAR (def=0x0) // Receiving flag tags SETIP
    • [1]STALL (def=0x0) // Enable sending 'Stall'
    • [2]ZEROLEN (def=0x0) // Enable transmission zero length packet
    • [3]CEPFLUSH (def=0x0) // Reset buffer
  • 0x20010030CEP_IRQ_ENB// Interrupt Enable buffer register of Control EndPoint

    • [0]SETUPTOKEN (def=0x0) // Enable flag deadline tags SETUP from the host
    • [1]SETUPPKT (def=0x0) // Enable flag deadline Setup package from the host
    • [2]OUTTOKEN (def=0x0) // Enable reception end flag tags OUT from the host
    • [3]INTOKEN (def=0x0) // Enable reception end flag tags IN from the host
    • [4]PINGTOKEN (def=0x0) // Enable reception end flag tags PING from host
    • [5]DATAPKTTR (def=0x0) // Enable flag successful sending of the data packet in response to the label to obtain IN ACK confirm
    • [6]DATAPKTREC (def=0x0) // Enable flag successful reception of the data packet following the label OUT, in response to which t
    • [7]NAKSENT (def=0x0) // Enable flag closure parcel labels NAK in response to mark IN or OUT
    • [8]STALLSENT (def=0x0) // Enable flag closure parcel labels STALL in response to mark IN or OUT
    • [9]USBERR (def=0x0) // Enable error flag during the operation
    • [10]STATCMPLN (def=0x0) // Enable flag successful completion stage 'Status' operations on the USB bus
    • [11]BUFFFULL (def=0x0) // Enable flag filling control buffer
    • [12]BUFFEMPTY (def=0x0) // Enable flag emptying control buffer
  • 0x20010034CEP_IRQ_STAT// Buffer interrupt flag register of Control EndPoint

    • [0]SETUPTOKEN (def=0x0) // Flag deadline tags SETUP from the host
    • [1]SETUPPKT (def=0x0) // Flag deadline Setup package from the host
    • [2]OUTTOKEN (def=0x0) // Reception end flag tags OUT from the host
    • [3]INTOKEN (def=0x0) // Reception end flag tags IN from the host
    • [4]PINGTOKEN (def=0x0) // Reception end flag tags PING from host
    • [5]DATAPKTTR (def=0x0) // Flag successful sending of the data packet in response to the label to obtain IN ACK confirming tag
    • [6]DATAPKTREC (def=0x0) // Flag successful reception of the data packet following the label OUT, in response to which the mark
    • [7]NAKSENT (def=0x0) // Flag closure parcel labels NAK in response to mark IN or OUT
    • [8]STALLSENT (def=0x0) // Flag closure parcel labels STALL in response to mark IN or OUT
    • [9]USBERR (def=0x0) // The error flag during the operation
    • [10]STATCMPLN (def=0x0) // Flag successful completion stage 'Status' operations on the USB bus
    • [11]BUFFFULL (def=0x0) // Flag filling control buffer
    • [12]BUFFEMPTY (def=0x0) // Flag control buffer emptying
  • 0x20010038CEP_IN_XFRCNT// In transfer data count register of Control EndPoint

    • [0:7]DATACOUNT (def=0x0) // The number of bytes to be sent in response to a label IN
  • 0x2001003CCEP_OUT_XFRCNT// Out-transfer data count register of Control EndPoint

    • [0:7]DATACOUNT (def=0x0) // The number of bytes received of data
  • 0x20010040CEP_DATA_AVL// Register number of bytes received

    • [0:15]NUM_BYTES (def=0x0) // The number of bytes received of data
  • 0x20010044CEP_SETUP1_0// Register zero and first byte packet Setup of Control EndPoint

    • [0:7]BYTE0 (def=0x0) // destination
    • [8:15]BYTE1 (def=0x0) // The first byte of the packet Setup
  • 0x20010048CEP_SETUP3_2// Register 2nd and 3rd bytes of the packet Setup of Control EndPoint

    • [0:7]BYTE2 (def=0x0) // Low byte field wValue
    • [8:15]BYTE3 (def=0x0) // High byte field wValue
  • 0x2001004CCEP_SETUP5_4// Register 4th and 5th bytes of the packet Setup of Control EndPoint

    • [0:7]BYTE4 (def=0x0) // Low byte field windex
    • [8:15]BYTE5 (def=0x0) // High byte field windex
  • 0x20010050CEP_SETUP7_6// Register on the 6th and 7th byte packet Setup of Control EndPoint

    • [0:7]BYTE6 (def=0x0) // Low byte field wLength
    • [8:15]BYTE7 (def=0x0) // High byte field wLength
  • 0x20010054CEP_START_ADDR// Control EndPoint RAM start Addr register

    • [0:15]VAL (def=0x0) // Beginning of the address space
  • 0x20010058CEP_END_ADDR// Control EndPoint RAM end Addr register

    • [0:15]VAL (def=0x0) // The end of the address space
  • 0x2001005CDMA_CTRL_STS// DMA Control Register

    • [0:3]DMA_EP_ADDR (def=0x0) // Buffer address accessed by the DMA
    • [4]DMA_RW (def=0x0) // Type DMA operations 1-Read, 0-Write
    • [5]DMA_EN (def=0x0) // Enable DMA
  • 0x20010060DMA_CNT// DMA Count byte Register

    • [0:15]DMA_CNT (def=0x0) // The number of words transmitted by DMA
  • 0x20010700AHB_DMA_ADDR// AHB addr register

    • [0:31]AHBADDR (def=0x0) // It specifies the address from which the DMA has to read / write.The address must WORD (32- bits) al
  • 0x200107C0PHY_PD// USB PHY PowerDown Register

    • [0]CMN (def=0x0) // Enable powerdown function of common PHY logic
    • [1]RX (def=0x0) // Enable Powerdown of RX part
    • [2]TX (def=0x0) // Enable Powerdown of TX part
  • 0x20010800PLLUSBCFG0// PLL configudration 0 register

    • [0]PLLEN (def=0x0) // PLL enable
    • [1:2]BYP (def=0x0) // Bypass
    • [3]DACEN (def=0x0) //
    • [4]DSMEN (def=0x0) //
    • [5:6]FOUTEN (def=0x0) // Output frequency enabled
    • [7:12]REFDIV (def=0x0) //
    • [13:15]PD0A (def=0x0) //
    • [16:21]PD0B (def=0x0) //
    • [22:24]PD1A (def=0x0) //
    • [25:30]PD1B (def=0x0) //
  • 0x20010804PLLUSBCFG1// PLL configudration 1 register

    • [0:23]FRAC (def=0x0) //
  • 0x20010808PLLUSBCFG2// PLL configudration 2 register

    • [0:11]FBDIV (def=0x0) //
  • 0x2001080CPLLUSBCFG3// PLL configudration 3 register

    • [0]DSKEWEN (def=0x0) //
    • [1]DSKEWCALBYP (def=0x0) //
    • [2:4]DSKEWCALCNT (def=0x0) //
    • [5]DSKEWCALEN (def=0x0) //
    • [6]DSKEWFASTCAL (def=0x0) //
    • [8:19]DSKEWCALIN (def=0x0) //
    • [24]USBCLKSEL (def=0x0) // 0-PLLUSBClk (FOUT0); 1- SYSClk
  • 0x20010810PLLUSBSTAT// PLL Status Register

    • [0]LOCK (def=0x0) // Lock status PLL
  interrupts:
  • [4] USB // USB interrupt
• 0x30006000UART0// UART control registers

  • 0x30006000DR// Data Register

    • [0:7]DATA (def=0x0) //
    • [8]FE (def=0x0) // Framing error
    • [9]PE (def=0x0) // Parity error
    • [10]BE (def=0x0) // Break error
    • [11]OE (def=0x0) // Overrun error
  • 0x30006004RSR// Receive Status Register/Error Clear Register

    • [0]FE (def=0x0) // Framing error
    • [1]PE (def=0x0) // Parity error
    • [2]BE (def=0x0) // Break error
    • [3]OE (def=0x0) // Overrun error
  • 0x30006018FR// Flag Register

    • [0]CTS (def=0x0) // Clear to send
    • [1]DSR (def=0x0) // Data set ready
    • [2]DCD (def=0x0) // Data carrier detect
    • [3]BUSY (def=0x0) // UART busy
    • [4]RXFE (def=0x0) // Receive FIFO empty
    • [5]TXFF (def=0x0) // Transmit FIFO full
    • [6]RXFF (def=0x0) // Receive FIFO full
    • [7]TXFE (def=0x0) // Transmit FIFO empty
    • [8]RI (def=0x0) // Ring indicator
  • 0x30006020ILPR// IrDA Low-Power Counter Register

    • [0:7]ILPDVSR (def=0x0) //
  • 0x30006024IBRD// Integer Baud Rate Register

    • [0:15]DIVINT (def=0x0) //
  • 0x30006028FBRD// Fractional Baud Rate Register

    • [0:5]DIVFRAC (def=0x0) //
  • 0x3000602CLCRH// Line Control Register

    • [0]BRK (def=0x0) // Send break
    • [1]PEN (def=0x0) // Parity enable
    • [2]EPS (def=0x0) // Even parity select
    • [3]STP2 (def=0x0) // Two stop bits select
    • [4]FEN (def=0x0) // Enable FIFOs
    • [5:6]WLEN (def=0x0) //
    • [7]SPS (def=0x0) // Stick parity select
  • 0x30006030CR// Control Register

    • [0]UARTEN (def=0x0) // UART enable
    • [1]SIREN (def=0x0) // Enable IrDA SIR ENDEC
    • [2]SIRLP (def=0x0) // Enable SIR low-power IrDA mode
    • [7]LBE (def=0x0) // Loopback enable
    • [8]TXE (def=0x0) // Transmit enable
    • [9]RXE (def=0x0) // Receive enable
    • [10]DTR (def=0x0) // Data transmit ready
    • [11]RTS (def=0x0) // Request to send
    • [14]RTSEN (def=0x0) // RTS hardware flow control enable
    • [15]CTSEN (def=0x0) // CTS hardware flow control enable
  • 0x30006034IFLS// Interrupt FIFO Level Select Register

    • [0:2]TXIFLSEL (def=0x0) //
    • [3:5]RXIFLSEL (def=0x0) //
  • 0x30006038IMSC// Interrupt Mask Set/Clear Register

    • [0]RIMIM (def=0x0) // nUARTRI modem interrupt mask
    • [1]CTSMIM (def=0x0) // nUARTCTS modem interrupt mask
    • [2]DCDMIM (def=0x0) // nUARTDCD modem interrupt mask
    • [3]DSRMIM (def=0x0) // nUARTDSR modem interrupt mask
    • [4]RXIM (def=0x0) // Receive interrupt mask
    • [5]TXIM (def=0x0) // Transmit interrupt mask
    • [6]RTIM (def=0x0) // Receive timeout interrupt mask
    • [7]FERIM (def=0x0) // Framing error interrupt mask
    • [8]PERIM (def=0x0) // Parity error interrupt mask
    • [9]BERIM (def=0x0) // Break error interrupt mask
    • [10]OERIM (def=0x0) // Overrun error interrupt mask
    • [11]TDIM (def=0x0) // Transmit done interrupt mask
  • 0x3000603CRIS// Raw Interrupt Status Register

    • [0]RIRMIS (def=0x0) // nUARTRI modem interrupt status
    • [1]CTSRMIS (def=0x0) // nUARTCTS modem interrupt status
    • [2]DCDRMIS (def=0x0) // nUARTDCD modem interrupt status
    • [3]DSRRMIS (def=0x0) // nUARTDSR modem interrupt status
    • [4]RXRIS (def=0x0) // Receive interrupt status
    • [5]TXRIS (def=0x0) // Transmit interrupt status
    • [6]RTRIS (def=0x0) // Receive timeout interrupt status
    • [7]FERIS (def=0x0) // Framing error interrupt status
    • [8]PERIS (def=0x0) // Parity error interrupt status
    • [9]BERIS (def=0x0) // Break error interrupt status
    • [10]OERIS (def=0x0) // Overrun error interrupt status
    • [11]TDRIS (def=0x0) // Transmit done raw interrupt status
  • 0x30006040MIS// Masked Interrupt Status Register

    • [0]RIMMIS (def=0x0) // nUARTRI modem masked interrupt status
    • [1]CTSMMIS (def=0x0) // nUARTCTS modem masked interrupt status
    • [2]DCDMMIS (def=0x0) // nUARTDCD modem masked interrupt status
    • [3]DSRMMIS (def=0x0) // nUARTDSR modem masked interrupt status
    • [4]RXMIS (def=0x0) // Receive masked interrupt status
    • [5]TXMIS (def=0x0) // Transmit masked interrupt status
    • [6]RTMIS (def=0x0) // Receive timeout masked interrupt status
    • [7]FEMIS (def=0x0) // Framing error masked interrupt status
    • [8]PEMIS (def=0x0) // Parity error masked interrupt status
    • [9]BEMIS (def=0x0) // Break error masked interrupt status
    • [10]OEMIS (def=0x0) // Overrun error masked interrupt status
    • [11]TDMIS (def=0x0) // Transmit done masked interrupt status
  • 0x30006044ICR// Interrupt Clear Register

    • [0]RIMIC (def=0x0) // nUARTRI modem interrupt clear
    • [1]CTSMIC (def=0x0) // nUARTCTS modem interrupt clear
    • [2]DCDMIC (def=0x0) // nUARTDCD modem interrupt clear
    • [3]DSRMIC (def=0x0) // nUARTDSR modem interrupt clear
    • [4]RXIC (def=0x0) // Receive interrupt clear
    • [5]TXIC (def=0x0) // Transmit interrupt clear
    • [6]RTIC (def=0x0) // Receive timeout interrupt clear
    • [7]FEIC (def=0x0) // Framing error interrupt clear
    • [8]PEIC (def=0x0) // Parity error interrupt clear
    • [9]BEIC (def=0x0) // Break error interrupt clear
    • [10]OEIC (def=0x0) // Overrun error interrupt clear
    • [11]TDIC (def=0x0) // Transmit done interrupt clear
  • 0x30006048DMACR// DMA Control Register

    • [0]RXDMAE (def=0x0) // Receive DMA enable
    • [1]TXDMAE (def=0x0) // Transmit DMA enable
    • [2]DMAONERR (def=0x0) // DMA on error
  interrupts:
  • [22] UART0 // UART0 interrupt
• 0x30007000UART1//

  • 0x30007000DR// Data Register

    • [0:7]DATA (def=0x0) //
    • [8]FE (def=0x0) // Framing error
    • [9]PE (def=0x0) // Parity error
    • [10]BE (def=0x0) // Break error
    • [11]OE (def=0x0) // Overrun error
  • 0x30007004RSR// Receive Status Register/Error Clear Register

    • [0]FE (def=0x0) // Framing error
    • [1]PE (def=0x0) // Parity error
    • [2]BE (def=0x0) // Break error
    • [3]OE (def=0x0) // Overrun error
  • 0x30007018FR// Flag Register

    • [0]CTS (def=0x0) // Clear to send
    • [1]DSR (def=0x0) // Data set ready
    • [2]DCD (def=0x0) // Data carrier detect
    • [3]BUSY (def=0x0) // UART busy
    • [4]RXFE (def=0x0) // Receive FIFO empty
    • [5]TXFF (def=0x0) // Transmit FIFO full
    • [6]RXFF (def=0x0) // Receive FIFO full
    • [7]TXFE (def=0x0) // Transmit FIFO empty
    • [8]RI (def=0x0) // Ring indicator
  • 0x30007020ILPR// IrDA Low-Power Counter Register

    • [0:7]ILPDVSR (def=0x0) //
  • 0x30007024IBRD// Integer Baud Rate Register

    • [0:15]DIVINT (def=0x0) //
  • 0x30007028FBRD// Fractional Baud Rate Register

    • [0:5]DIVFRAC (def=0x0) //
  • 0x3000702CLCRH// Line Control Register

    • [0]BRK (def=0x0) // Send break
    • [1]PEN (def=0x0) // Parity enable
    • [2]EPS (def=0x0) // Even parity select
    • [3]STP2 (def=0x0) // Two stop bits select
    • [4]FEN (def=0x0) // Enable FIFOs
    • [5:6]WLEN (def=0x0) //
    • [7]SPS (def=0x0) // Stick parity select
  • 0x30007030CR// Control Register

    • [0]UARTEN (def=0x0) // UART enable
    • [1]SIREN (def=0x0) // Enable IrDA SIR ENDEC
    • [2]SIRLP (def=0x0) // Enable SIR low-power IrDA mode
    • [7]LBE (def=0x0) // Loopback enable
    • [8]TXE (def=0x0) // Transmit enable
    • [9]RXE (def=0x0) // Receive enable
    • [10]DTR (def=0x0) // Data transmit ready
    • [11]RTS (def=0x0) // Request to send
    • [14]RTSEN (def=0x0) // RTS hardware flow control enable
    • [15]CTSEN (def=0x0) // CTS hardware flow control enable
  • 0x30007034IFLS// Interrupt FIFO Level Select Register

    • [0:2]TXIFLSEL (def=0x0) //
    • [3:5]RXIFLSEL (def=0x0) //
  • 0x30007038IMSC// Interrupt Mask Set/Clear Register

    • [0]RIMIM (def=0x0) // nUARTRI modem interrupt mask
    • [1]CTSMIM (def=0x0) // nUARTCTS modem interrupt mask
    • [2]DCDMIM (def=0x0) // nUARTDCD modem interrupt mask
    • [3]DSRMIM (def=0x0) // nUARTDSR modem interrupt mask
    • [4]RXIM (def=0x0) // Receive interrupt mask
    • [5]TXIM (def=0x0) // Transmit interrupt mask
    • [6]RTIM (def=0x0) // Receive timeout interrupt mask
    • [7]FERIM (def=0x0) // Framing error interrupt mask
    • [8]PERIM (def=0x0) // Parity error interrupt mask
    • [9]BERIM (def=0x0) // Break error interrupt mask
    • [10]OERIM (def=0x0) // Overrun error interrupt mask
    • [11]TDIM (def=0x0) // Transmit done interrupt mask
  • 0x3000703CRIS// Raw Interrupt Status Register

    • [0]RIRMIS (def=0x0) // nUARTRI modem interrupt status
    • [1]CTSRMIS (def=0x0) // nUARTCTS modem interrupt status
    • [2]DCDRMIS (def=0x0) // nUARTDCD modem interrupt status
    • [3]DSRRMIS (def=0x0) // nUARTDSR modem interrupt status
    • [4]RXRIS (def=0x0) // Receive interrupt status
    • [5]TXRIS (def=0x0) // Transmit interrupt status
    • [6]RTRIS (def=0x0) // Receive timeout interrupt status
    • [7]FERIS (def=0x0) // Framing error interrupt status
    • [8]PERIS (def=0x0) // Parity error interrupt status
    • [9]BERIS (def=0x0) // Break error interrupt status
    • [10]OERIS (def=0x0) // Overrun error interrupt status
    • [11]TDRIS (def=0x0) // Transmit done raw interrupt status
  • 0x30007040MIS// Masked Interrupt Status Register

    • [0]RIMMIS (def=0x0) // nUARTRI modem masked interrupt status
    • [1]CTSMMIS (def=0x0) // nUARTCTS modem masked interrupt status
    • [2]DCDMMIS (def=0x0) // nUARTDCD modem masked interrupt status
    • [3]DSRMMIS (def=0x0) // nUARTDSR modem masked interrupt status
    • [4]RXMIS (def=0x0) // Receive masked interrupt status
    • [5]TXMIS (def=0x0) // Transmit masked interrupt status
    • [6]RTMIS (def=0x0) // Receive timeout masked interrupt status
    • [7]FEMIS (def=0x0) // Framing error masked interrupt status
    • [8]PEMIS (def=0x0) // Parity error masked interrupt status
    • [9]BEMIS (def=0x0) // Break error masked interrupt status
    • [10]OEMIS (def=0x0) // Overrun error masked interrupt status
    • [11]TDMIS (def=0x0) // Transmit done masked interrupt status
  • 0x30007044ICR// Interrupt Clear Register

    • [0]RIMIC (def=0x0) // nUARTRI modem interrupt clear
    • [1]CTSMIC (def=0x0) // nUARTCTS modem interrupt clear
    • [2]DCDMIC (def=0x0) // nUARTDCD modem interrupt clear
    • [3]DSRMIC (def=0x0) // nUARTDSR modem interrupt clear
    • [4]RXIC (def=0x0) // Receive interrupt clear
    • [5]TXIC (def=0x0) // Transmit interrupt clear
    • [6]RTIC (def=0x0) // Receive timeout interrupt clear
    • [7]FEIC (def=0x0) // Framing error interrupt clear
    • [8]PEIC (def=0x0) // Parity error interrupt clear
    • [9]BEIC (def=0x0) // Break error interrupt clear
    • [10]OEIC (def=0x0) // Overrun error interrupt clear
    • [11]TDIC (def=0x0) // Transmit done interrupt clear
  • 0x30007048DMACR// DMA Control Register

    • [0]RXDMAE (def=0x0) // Receive DMA enable
    • [1]TXDMAE (def=0x0) // Transmit DMA enable
    • [2]DMAONERR (def=0x0) // DMA on error
  interrupts:
  • [23] UART1 // UART1 interrupt
• 0x30008000UART2//

  • 0x30008000DR// Data Register

    • [0:7]DATA (def=0x0) //
    • [8]FE (def=0x0) // Framing error
    • [9]PE (def=0x0) // Parity error
    • [10]BE (def=0x0) // Break error
    • [11]OE (def=0x0) // Overrun error
  • 0x30008004RSR// Receive Status Register/Error Clear Register

    • [0]FE (def=0x0) // Framing error
    • [1]PE (def=0x0) // Parity error
    • [2]BE (def=0x0) // Break error
    • [3]OE (def=0x0) // Overrun error
  • 0x30008018FR// Flag Register

    • [0]CTS (def=0x0) // Clear to send
    • [1]DSR (def=0x0) // Data set ready
    • [2]DCD (def=0x0) // Data carrier detect
    • [3]BUSY (def=0x0) // UART busy
    • [4]RXFE (def=0x0) // Receive FIFO empty
    • [5]TXFF (def=0x0) // Transmit FIFO full
    • [6]RXFF (def=0x0) // Receive FIFO full
    • [7]TXFE (def=0x0) // Transmit FIFO empty
    • [8]RI (def=0x0) // Ring indicator
  • 0x30008020ILPR// IrDA Low-Power Counter Register

    • [0:7]ILPDVSR (def=0x0) //
  • 0x30008024IBRD// Integer Baud Rate Register

    • [0:15]DIVINT (def=0x0) //
  • 0x30008028FBRD// Fractional Baud Rate Register

    • [0:5]DIVFRAC (def=0x0) //
  • 0x3000802CLCRH// Line Control Register

    • [0]BRK (def=0x0) // Send break
    • [1]PEN (def=0x0) // Parity enable
    • [2]EPS (def=0x0) // Even parity select
    • [3]STP2 (def=0x0) // Two stop bits select
    • [4]FEN (def=0x0) // Enable FIFOs
    • [5:6]WLEN (def=0x0) //
    • [7]SPS (def=0x0) // Stick parity select
  • 0x30008030CR// Control Register

    • [0]UARTEN (def=0x0) // UART enable
    • [1]SIREN (def=0x0) // Enable IrDA SIR ENDEC
    • [2]SIRLP (def=0x0) // Enable SIR low-power IrDA mode
    • [7]LBE (def=0x0) // Loopback enable
    • [8]TXE (def=0x0) // Transmit enable
    • [9]RXE (def=0x0) // Receive enable
    • [10]DTR (def=0x0) // Data transmit ready
    • [11]RTS (def=0x0) // Request to send
    • [14]RTSEN (def=0x0) // RTS hardware flow control enable
    • [15]CTSEN (def=0x0) // CTS hardware flow control enable
  • 0x30008034IFLS// Interrupt FIFO Level Select Register

    • [0:2]TXIFLSEL (def=0x0) //
    • [3:5]RXIFLSEL (def=0x0) //
  • 0x30008038IMSC// Interrupt Mask Set/Clear Register

    • [0]RIMIM (def=0x0) // nUARTRI modem interrupt mask
    • [1]CTSMIM (def=0x0) // nUARTCTS modem interrupt mask
    • [2]DCDMIM (def=0x0) // nUARTDCD modem interrupt mask
    • [3]DSRMIM (def=0x0) // nUARTDSR modem interrupt mask
    • [4]RXIM (def=0x0) // Receive interrupt mask
    • [5]TXIM (def=0x0) // Transmit interrupt mask
    • [6]RTIM (def=0x0) // Receive timeout interrupt mask
    • [7]FERIM (def=0x0) // Framing error interrupt mask
    • [8]PERIM (def=0x0) // Parity error interrupt mask
    • [9]BERIM (def=0x0) // Break error interrupt mask
    • [10]OERIM (def=0x0) // Overrun error interrupt mask
    • [11]TDIM (def=0x0) // Transmit done interrupt mask
  • 0x3000803CRIS// Raw Interrupt Status Register

    • [0]RIRMIS (def=0x0) // nUARTRI modem interrupt status
    • [1]CTSRMIS (def=0x0) // nUARTCTS modem interrupt status
    • [2]DCDRMIS (def=0x0) // nUARTDCD modem interrupt status
    • [3]DSRRMIS (def=0x0) // nUARTDSR modem interrupt status
    • [4]RXRIS (def=0x0) // Receive interrupt status
    • [5]TXRIS (def=0x0) // Transmit interrupt status
    • [6]RTRIS (def=0x0) // Receive timeout interrupt status
    • [7]FERIS (def=0x0) // Framing error interrupt status
    • [8]PERIS (def=0x0) // Parity error interrupt status
    • [9]BERIS (def=0x0) // Break error interrupt status
    • [10]OERIS (def=0x0) // Overrun error interrupt status
    • [11]TDRIS (def=0x0) // Transmit done raw interrupt status
  • 0x30008040MIS// Masked Interrupt Status Register

    • [0]RIMMIS (def=0x0) // nUARTRI modem masked interrupt status
    • [1]CTSMMIS (def=0x0) // nUARTCTS modem masked interrupt status
    • [2]DCDMMIS (def=0x0) // nUARTDCD modem masked interrupt status
    • [3]DSRMMIS (def=0x0) // nUARTDSR modem masked interrupt status
    • [4]RXMIS (def=0x0) // Receive masked interrupt status
    • [5]TXMIS (def=0x0) // Transmit masked interrupt status
    • [6]RTMIS (def=0x0) // Receive timeout masked interrupt status
    • [7]FEMIS (def=0x0) // Framing error masked interrupt status
    • [8]PEMIS (def=0x0) // Parity error masked interrupt status
    • [9]BEMIS (def=0x0) // Break error masked interrupt status
    • [10]OEMIS (def=0x0) // Overrun error masked interrupt status
    • [11]TDMIS (def=0x0) // Transmit done masked interrupt status
  • 0x30008044ICR// Interrupt Clear Register

    • [0]RIMIC (def=0x0) // nUARTRI modem interrupt clear
    • [1]CTSMIC (def=0x0) // nUARTCTS modem interrupt clear
    • [2]DCDMIC (def=0x0) // nUARTDCD modem interrupt clear
    • [3]DSRMIC (def=0x0) // nUARTDSR modem interrupt clear
    • [4]RXIC (def=0x0) // Receive interrupt clear
    • [5]TXIC (def=0x0) // Transmit interrupt clear
    • [6]RTIC (def=0x0) // Receive timeout interrupt clear
    • [7]FEIC (def=0x0) // Framing error interrupt clear
    • [8]PEIC (def=0x0) // Parity error interrupt clear
    • [9]BEIC (def=0x0) // Break error interrupt clear
    • [10]OEIC (def=0x0) // Overrun error interrupt clear
    • [11]TDIC (def=0x0) // Transmit done interrupt clear
  • 0x30008048DMACR// DMA Control Register

    • [0]RXDMAE (def=0x0) // Receive DMA enable
    • [1]TXDMAE (def=0x0) // Transmit DMA enable
    • [2]DMAONERR (def=0x0) // DMA on error
  interrupts:
  • [24] UART2 // UART2 interrupt
• 0x30009000UART3//

  • 0x30009000DR// Data Register

    • [0:7]DATA (def=0x0) //
    • [8]FE (def=0x0) // Framing error
    • [9]PE (def=0x0) // Parity error
    • [10]BE (def=0x0) // Break error
    • [11]OE (def=0x0) // Overrun error
  • 0x30009004RSR// Receive Status Register/Error Clear Register

    • [0]FE (def=0x0) // Framing error
    • [1]PE (def=0x0) // Parity error
    • [2]BE (def=0x0) // Break error
    • [3]OE (def=0x0) // Overrun error
  • 0x30009018FR// Flag Register

    • [0]CTS (def=0x0) // Clear to send
    • [1]DSR (def=0x0) // Data set ready
    • [2]DCD (def=0x0) // Data carrier detect
    • [3]BUSY (def=0x0) // UART busy
    • [4]RXFE (def=0x0) // Receive FIFO empty
    • [5]TXFF (def=0x0) // Transmit FIFO full
    • [6]RXFF (def=0x0) // Receive FIFO full
    • [7]TXFE (def=0x0) // Transmit FIFO empty
    • [8]RI (def=0x0) // Ring indicator
  • 0x30009020ILPR// IrDA Low-Power Counter Register

    • [0:7]ILPDVSR (def=0x0) //
  • 0x30009024IBRD// Integer Baud Rate Register

    • [0:15]DIVINT (def=0x0) //
  • 0x30009028FBRD// Fractional Baud Rate Register

    • [0:5]DIVFRAC (def=0x0) //
  • 0x3000902CLCRH// Line Control Register

    • [0]BRK (def=0x0) // Send break
    • [1]PEN (def=0x0) // Parity enable
    • [2]EPS (def=0x0) // Even parity select
    • [3]STP2 (def=0x0) // Two stop bits select
    • [4]FEN (def=0x0) // Enable FIFOs
    • [5:6]WLEN (def=0x0) //
    • [7]SPS (def=0x0) // Stick parity select
  • 0x30009030CR// Control Register

    • [0]UARTEN (def=0x0) // UART enable
    • [1]SIREN (def=0x0) // Enable IrDA SIR ENDEC
    • [2]SIRLP (def=0x0) // Enable SIR low-power IrDA mode
    • [7]LBE (def=0x0) // Loopback enable
    • [8]TXE (def=0x0) // Transmit enable
    • [9]RXE (def=0x0) // Receive enable
    • [10]DTR (def=0x0) // Data transmit ready
    • [11]RTS (def=0x0) // Request to send
    • [14]RTSEN (def=0x0) // RTS hardware flow control enable
    • [15]CTSEN (def=0x0) // CTS hardware flow control enable
  • 0x30009034IFLS// Interrupt FIFO Level Select Register

    • [0:2]TXIFLSEL (def=0x0) //
    • [3:5]RXIFLSEL (def=0x0) //
  • 0x30009038IMSC// Interrupt Mask Set/Clear Register

    • [0]RIMIM (def=0x0) // nUARTRI modem interrupt mask
    • [1]CTSMIM (def=0x0) // nUARTCTS modem interrupt mask
    • [2]DCDMIM (def=0x0) // nUARTDCD modem interrupt mask
    • [3]DSRMIM (def=0x0) // nUARTDSR modem interrupt mask
    • [4]RXIM (def=0x0) // Receive interrupt mask
    • [5]TXIM (def=0x0) // Transmit interrupt mask
    • [6]RTIM (def=0x0) // Receive timeout interrupt mask
    • [7]FERIM (def=0x0) // Framing error interrupt mask
    • [8]PERIM (def=0x0) // Parity error interrupt mask
    • [9]BERIM (def=0x0) // Break error interrupt mask
    • [10]OERIM (def=0x0) // Overrun error interrupt mask
    • [11]TDIM (def=0x0) // Transmit done interrupt mask
  • 0x3000903CRIS// Raw Interrupt Status Register

    • [0]RIRMIS (def=0x0) // nUARTRI modem interrupt status
    • [1]CTSRMIS (def=0x0) // nUARTCTS modem interrupt status
    • [2]DCDRMIS (def=0x0) // nUARTDCD modem interrupt status
    • [3]DSRRMIS (def=0x0) // nUARTDSR modem interrupt status
    • [4]RXRIS (def=0x0) // Receive interrupt status
    • [5]TXRIS (def=0x0) // Transmit interrupt status
    • [6]RTRIS (def=0x0) // Receive timeout interrupt status
    • [7]FERIS (def=0x0) // Framing error interrupt status
    • [8]PERIS (def=0x0) // Parity error interrupt status
    • [9]BERIS (def=0x0) // Break error interrupt status
    • [10]OERIS (def=0x0) // Overrun error interrupt status
    • [11]TDRIS (def=0x0) // Transmit done raw interrupt status
  • 0x30009040MIS// Masked Interrupt Status Register

    • [0]RIMMIS (def=0x0) // nUARTRI modem masked interrupt status
    • [1]CTSMMIS (def=0x0) // nUARTCTS modem masked interrupt status
    • [2]DCDMMIS (def=0x0) // nUARTDCD modem masked interrupt status
    • [3]DSRMMIS (def=0x0) // nUARTDSR modem masked interrupt status
    • [4]RXMIS (def=0x0) // Receive masked interrupt status
    • [5]TXMIS (def=0x0) // Transmit masked interrupt status
    • [6]RTMIS (def=0x0) // Receive timeout masked interrupt status
    • [7]FEMIS (def=0x0) // Framing error masked interrupt status
    • [8]PEMIS (def=0x0) // Parity error masked interrupt status
    • [9]BEMIS (def=0x0) // Break error masked interrupt status
    • [10]OEMIS (def=0x0) // Overrun error masked interrupt status
    • [11]TDMIS (def=0x0) // Transmit done masked interrupt status
  • 0x30009044ICR// Interrupt Clear Register

    • [0]RIMIC (def=0x0) // nUARTRI modem interrupt clear
    • [1]CTSMIC (def=0x0) // nUARTCTS modem interrupt clear
    • [2]DCDMIC (def=0x0) // nUARTDCD modem interrupt clear
    • [3]DSRMIC (def=0x0) // nUARTDSR modem interrupt clear
    • [4]RXIC (def=0x0) // Receive interrupt clear
    • [5]TXIC (def=0x0) // Transmit interrupt clear
    • [6]RTIC (def=0x0) // Receive timeout interrupt clear
    • [7]FEIC (def=0x0) // Framing error interrupt clear
    • [8]PEIC (def=0x0) // Parity error interrupt clear
    • [9]BEIC (def=0x0) // Break error interrupt clear
    • [10]OEIC (def=0x0) // Overrun error interrupt clear
    • [11]TDIC (def=0x0) // Transmit done interrupt clear
  • 0x30009048DMACR// DMA Control Register

    • [0]RXDMAE (def=0x0) // Receive DMA enable
    • [1]TXDMAE (def=0x0) // Transmit DMA enable
    • [2]DMAONERR (def=0x0) // DMA on error
  interrupts:
  • [25] UART3 // UART3 interrupt
• 0x3000A000UART4//

  • 0x3000A000DR// Data Register

    • [0:7]DATA (def=0x0) //
    • [8]FE (def=0x0) // Framing error
    • [9]PE (def=0x0) // Parity error
    • [10]BE (def=0x0) // Break error
    • [11]OE (def=0x0) // Overrun error
  • 0x3000A004RSR// Receive Status Register/Error Clear Register

    • [0]FE (def=0x0) // Framing error
    • [1]PE (def=0x0) // Parity error
    • [2]BE (def=0x0) // Break error
    • [3]OE (def=0x0) // Overrun error
  • 0x3000A018FR// Flag Register

    • [0]CTS (def=0x0) // Clear to send
    • [1]DSR (def=0x0) // Data set ready
    • [2]DCD (def=0x0) // Data carrier detect
    • [3]BUSY (def=0x0) // UART busy
    • [4]RXFE (def=0x0) // Receive FIFO empty
    • [5]TXFF (def=0x0) // Transmit FIFO full
    • [6]RXFF (def=0x0) // Receive FIFO full
    • [7]TXFE (def=0x0) // Transmit FIFO empty
    • [8]RI (def=0x0) // Ring indicator
  • 0x3000A020ILPR// IrDA Low-Power Counter Register

    • [0:7]ILPDVSR (def=0x0) //
  • 0x3000A024IBRD// Integer Baud Rate Register

    • [0:15]DIVINT (def=0x0) //
  • 0x3000A028FBRD// Fractional Baud Rate Register

    • [0:5]DIVFRAC (def=0x0) //
  • 0x3000A02CLCRH// Line Control Register

    • [0]BRK (def=0x0) // Send break
    • [1]PEN (def=0x0) // Parity enable
    • [2]EPS (def=0x0) // Even parity select
    • [3]STP2 (def=0x0) // Two stop bits select
    • [4]FEN (def=0x0) // Enable FIFOs
    • [5:6]WLEN (def=0x0) //
    • [7]SPS (def=0x0) // Stick parity select
  • 0x3000A030CR// Control Register

    • [0]UARTEN (def=0x0) // UART enable
    • [1]SIREN (def=0x0) // Enable IrDA SIR ENDEC
    • [2]SIRLP (def=0x0) // Enable SIR low-power IrDA mode
    • [7]LBE (def=0x0) // Loopback enable
    • [8]TXE (def=0x0) // Transmit enable
    • [9]RXE (def=0x0) // Receive enable
    • [10]DTR (def=0x0) // Data transmit ready
    • [11]RTS (def=0x0) // Request to send
    • [14]RTSEN (def=0x0) // RTS hardware flow control enable
    • [15]CTSEN (def=0x0) // CTS hardware flow control enable
  • 0x3000A034IFLS// Interrupt FIFO Level Select Register

    • [0:2]TXIFLSEL (def=0x0) //
    • [3:5]RXIFLSEL (def=0x0) //
  • 0x3000A038IMSC// Interrupt Mask Set/Clear Register

    • [0]RIMIM (def=0x0) // nUARTRI modem interrupt mask
    • [1]CTSMIM (def=0x0) // nUARTCTS modem interrupt mask
    • [2]DCDMIM (def=0x0) // nUARTDCD modem interrupt mask
    • [3]DSRMIM (def=0x0) // nUARTDSR modem interrupt mask
    • [4]RXIM (def=0x0) // Receive interrupt mask
    • [5]TXIM (def=0x0) // Transmit interrupt mask
    • [6]RTIM (def=0x0) // Receive timeout interrupt mask
    • [7]FERIM (def=0x0) // Framing error interrupt mask
    • [8]PERIM (def=0x0) // Parity error interrupt mask
    • [9]BERIM (def=0x0) // Break error interrupt mask
    • [10]OERIM (def=0x0) // Overrun error interrupt mask
    • [11]TDIM (def=0x0) // Transmit done interrupt mask
  • 0x3000A03CRIS// Raw Interrupt Status Register

    • [0]RIRMIS (def=0x0) // nUARTRI modem interrupt status
    • [1]CTSRMIS (def=0x0) // nUARTCTS modem interrupt status
    • [2]DCDRMIS (def=0x0) // nUARTDCD modem interrupt status
    • [3]DSRRMIS (def=0x0) // nUARTDSR modem interrupt status
    • [4]RXRIS (def=0x0) // Receive interrupt status
    • [5]TXRIS (def=0x0) // Transmit interrupt status
    • [6]RTRIS (def=0x0) // Receive timeout interrupt status
    • [7]FERIS (def=0x0) // Framing error interrupt status
    • [8]PERIS (def=0x0) // Parity error interrupt status
    • [9]BERIS (def=0x0) // Break error interrupt status
    • [10]OERIS (def=0x0) // Overrun error interrupt status
    • [11]TDRIS (def=0x0) // Transmit done raw interrupt status
  • 0x3000A040MIS// Masked Interrupt Status Register

    • [0]RIMMIS (def=0x0) // nUARTRI modem masked interrupt status
    • [1]CTSMMIS (def=0x0) // nUARTCTS modem masked interrupt status
    • [2]DCDMMIS (def=0x0) // nUARTDCD modem masked interrupt status
    • [3]DSRMMIS (def=0x0) // nUARTDSR modem masked interrupt status
    • [4]RXMIS (def=0x0) // Receive masked interrupt status
    • [5]TXMIS (def=0x0) // Transmit masked interrupt status
    • [6]RTMIS (def=0x0) // Receive timeout masked interrupt status
    • [7]FEMIS (def=0x0) // Framing error masked interrupt status
    • [8]PEMIS (def=0x0) // Parity error masked interrupt status
    • [9]BEMIS (def=0x0) // Break error masked interrupt status
    • [10]OEMIS (def=0x0) // Overrun error masked interrupt status
    • [11]TDMIS (def=0x0) // Transmit done masked interrupt status
  • 0x3000A044ICR// Interrupt Clear Register

    • [0]RIMIC (def=0x0) // nUARTRI modem interrupt clear
    • [1]CTSMIC (def=0x0) // nUARTCTS modem interrupt clear
    • [2]DCDMIC (def=0x0) // nUARTDCD modem interrupt clear
    • [3]DSRMIC (def=0x0) // nUARTDSR modem interrupt clear
    • [4]RXIC (def=0x0) // Receive interrupt clear
    • [5]TXIC (def=0x0) // Transmit interrupt clear
    • [6]RTIC (def=0x0) // Receive timeout interrupt clear
    • [7]FEIC (def=0x0) // Framing error interrupt clear
    • [8]PEIC (def=0x0) // Parity error interrupt clear
    • [9]BEIC (def=0x0) // Break error interrupt clear
    • [10]OEIC (def=0x0) // Overrun error interrupt clear
    • [11]TDIC (def=0x0) // Transmit done interrupt clear
  • 0x3000A048DMACR// DMA Control Register

    • [0]RXDMAE (def=0x0) // Receive DMA enable
    • [1]TXDMAE (def=0x0) // Transmit DMA enable
    • [2]DMAONERR (def=0x0) // DMA on error
  interrupts:
  • [26] UART4 // UART4 interrupt
• 0x3000C000DMA// DMA control registers

  • 0x3000C000STATUS// Status DMA register

    • [0:3]STATE (def=0x0) // State of DMA
    • [4]MASTEREN (def=0x0) // Indicate enable DMA
    • [5:9]CHNLS (def=0x0) // Number channel DMA (write: N-1)
  • 0x3000C004CFG// DMA configuration register

    • [0:2]CHPROT (def=0x0) // Sets the AHB-Lite protection
    • [3]MASTEREN (def=0x0) // Enable DMA
  • 0x3000C008BASEPTR// Channel control data base pointer

    • [0:31]VAL (def=0x0) //
  • 0x3000C00CALTBASEPTR// Channel alternate control data base pointer

    • [0:31]VAL (def=0x0) //
  • 0x3000C010WAITONREQ// Channel wait on request status

    • [0]CH0 (def=0x0) // Returns the status of the DMA request signals
    • [1]CH1 (def=0x0) // Returns the status of the DMA request signals
    • [2]CH2 (def=0x0) // Returns the status of the DMA request signals
    • [3]CH3 (def=0x0) // Returns the status of the DMA request signals
    • [4]CH4 (def=0x0) // Returns the status of the DMA request signals
    • [5]CH5 (def=0x0) // Returns the status of the DMA request signals
    • [6]CH6 (def=0x0) // Returns the status of the DMA request signals
    • [7]CH7 (def=0x0) // Returns the status of the DMA request signals
    • [8]CH8 (def=0x0) // Returns the status of the DMA request signals
    • [9]CH9 (def=0x0) // Returns the status of the DMA request signals
    • [10]CH10 (def=0x0) // Returns the status of the DMA request signals
    • [11]CH11 (def=0x0) // Returns the status of the DMA request signals
    • [12]CH12 (def=0x0) // Returns the status of the DMA request signals
    • [13]CH13 (def=0x0) // Returns the status of the DMA request signals
    • [14]CH14 (def=0x0) // Returns the status of the DMA request signals
    • [15]CH15 (def=0x0) // Returns the status of the DMA request signals
    • [16]CH16 (def=0x0) // Returns the status of the DMA request signals
    • [17]CH17 (def=0x0) // Returns the status of the DMA request signals
    • [18]CH18 (def=0x0) // Returns the status of the DMA request signals
    • [19]CH19 (def=0x0) // Returns the status of the DMA request signals
    • [20]CH20 (def=0x0) // Returns the status of the DMA request signals
    • [21]CH21 (def=0x0) // Returns the status of the DMA request signals
    • [22]CH22 (def=0x0) // Returns the status of the DMA request signals
    • [23]CH23 (def=0x0) // Returns the status of the DMA request signals
  • 0x3000C014SWREQ// Channel software request

    • [0]CH0 (def=0x0) // Set software request on channel
    • [1]CH1 (def=0x0) // Set software request on channel
    • [2]CH2 (def=0x0) // Set software request on channel
    • [3]CH3 (def=0x0) // Set software request on channel
    • [4]CH4 (def=0x0) // Set software request on channel
    • [5]CH5 (def=0x0) // Set software request on channel
    • [6]CH6 (def=0x0) // Set software request on channel
    • [7]CH7 (def=0x0) // Set software request on channel
    • [8]CH8 (def=0x0) // Set software request on channel
    • [9]CH9 (def=0x0) // Set software request on channel
    • [10]CH10 (def=0x0) // Set software request on channel
    • [11]CH11 (def=0x0) // Set software request on channel
    • [12]CH12 (def=0x0) // Set software request on channel
    • [13]CH13 (def=0x0) // Set software request on channel
    • [14]CH14 (def=0x0) // Set software request on channel
    • [15]CH15 (def=0x0) // Set software request on channel
    • [16]CH16 (def=0x0) // Set software request on channel
    • [17]CH17 (def=0x0) // Set software request on channel
    • [18]CH18 (def=0x0) // Set software request on channel
    • [19]CH19 (def=0x0) // Set software request on channel
    • [20]CH20 (def=0x0) // Set software request on channel
    • [21]CH21 (def=0x0) // Set software request on channel
    • [22]CH22 (def=0x0) // Set software request on channel
    • [23]CH23 (def=0x0) // Set software request on channel
  • 0x3000C018USEBURSTSET// Channel useburst set

    • [0]CH0 (def=0x0) // Enable single requests
    • [1]CH1 (def=0x0) // Enable single requests
    • [2]CH2 (def=0x0) // Enable single requests
    • [3]CH3 (def=0x0) // Enable single requests
    • [4]CH4 (def=0x0) // Enable single requests
    • [5]CH5 (def=0x0) // Enable single requests
    • [6]CH6 (def=0x0) // Enable single requests
    • [7]CH7 (def=0x0) // Enable single requests
    • [8]CH8 (def=0x0) // Enable single requests
    • [9]CH9 (def=0x0) // Enable single requests
    • [10]CH10 (def=0x0) // Enable single requests
    • [11]CH11 (def=0x0) // Enable single requests
    • [12]CH12 (def=0x0) // Enable single requests
    • [13]CH13 (def=0x0) // Enable single requests
    • [14]CH14 (def=0x0) // Enable single requests
    • [15]CH15 (def=0x0) // Enable single requests
    • [16]CH16 (def=0x0) // Enable single requests
    • [17]CH17 (def=0x0) // Enable single requests
    • [18]CH18 (def=0x0) // Enable single requests
    • [19]CH19 (def=0x0) // Enable single requests
    • [20]CH20 (def=0x0) // Enable single requests
    • [21]CH21 (def=0x0) // Enable single requests
    • [22]CH22 (def=0x0) // Enable single requests
    • [23]CH23 (def=0x0) // Enable single requests
  • 0x3000C01CUSEBURSTCLR// Channel useburst clear

    • [0]CH0 (def=0x0) // Disable single requests
    • [1]CH1 (def=0x0) // Disable single requests
    • [2]CH2 (def=0x0) // Disable single requests
    • [3]CH3 (def=0x0) // Disable single requests
    • [4]CH4 (def=0x0) // Disable single requests
    • [5]CH5 (def=0x0) // Disable single requests
    • [6]CH6 (def=0x0) // Disable single requests
    • [7]CH7 (def=0x0) // Disable single requests
    • [8]CH8 (def=0x0) // Disable single requests
    • [9]CH9 (def=0x0) // Disable single requests
    • [10]CH10 (def=0x0) // Disable single requests
    • [11]CH11 (def=0x0) // Disable single requests
    • [12]CH12 (def=0x0) // Disable single requests
    • [13]CH13 (def=0x0) // Disable single requests
    • [14]CH14 (def=0x0) // Disable single requests
    • [15]CH15 (def=0x0) // Disable single requests
    • [16]CH16 (def=0x0) // Disable single requests
    • [17]CH17 (def=0x0) // Disable single requests
    • [18]CH18 (def=0x0) // Disable single requests
    • [19]CH19 (def=0x0) // Disable single requests
    • [20]CH20 (def=0x0) // Disable single requests
    • [21]CH21 (def=0x0) // Disable single requests
    • [22]CH22 (def=0x0) // Disable single requests
    • [23]CH23 (def=0x0) // Disable single requests
  • 0x3000C020REQMASKSET// Channel request mask set

    • [0]CH0 (def=0x0) // External requests are enabled for channel
    • [1]CH1 (def=0x0) // External requests are enabled for channel
    • [2]CH2 (def=0x0) // External requests are enabled for channel
    • [3]CH3 (def=0x0) // External requests are enabled for channel
    • [4]CH4 (def=0x0) // External requests are enabled for channel
    • [5]CH5 (def=0x0) // External requests are enabled for channel
    • [6]CH6 (def=0x0) // External requests are enabled for channel
    • [7]CH7 (def=0x0) // External requests are enabled for channel
    • [8]CH8 (def=0x0) // External requests are enabled for channel
    • [9]CH9 (def=0x0) // External requests are enabled for channel
    • [10]CH10 (def=0x0) // External requests are enabled for channel
    • [11]CH11 (def=0x0) // External requests are enabled for channel
    • [12]CH12 (def=0x0) // External requests are enabled for channel
    • [13]CH13 (def=0x0) // External requests are enabled for channel
    • [14]CH14 (def=0x0) // External requests are enabled for channel
    • [15]CH15 (def=0x0) // External requests are enabled for channel
    • [16]CH16 (def=0x0) // External requests are enabled for channel
    • [17]CH17 (def=0x0) // External requests are enabled for channel
    • [18]CH18 (def=0x0) // External requests are enabled for channel
    • [19]CH19 (def=0x0) // External requests are enabled for channel
    • [20]CH20 (def=0x0) // External requests are enabled for channel
    • [21]CH21 (def=0x0) // External requests are enabled for channel
    • [22]CH22 (def=0x0) // External requests are enabled for channel
    • [23]CH23 (def=0x0) // External requests are enabled for channel
  • 0x3000C024REQMASKCLR// Channel request mask clear

    • [0]CH0 (def=0x0) // External requests are disabled for channel
    • [1]CH1 (def=0x0) // External requests are disabled for channel
    • [2]CH2 (def=0x0) // External requests are disabled for channel
    • [3]CH3 (def=0x0) // External requests are disabled for channel
    • [4]CH4 (def=0x0) // External requests are disabled for channel
    • [5]CH5 (def=0x0) // External requests are disabled for channel
    • [6]CH6 (def=0x0) // External requests are disabled for channel
    • [7]CH7 (def=0x0) // External requests are disabled for channel
    • [8]CH8 (def=0x0) // External requests are disabled for channel
    • [9]CH9 (def=0x0) // External requests are disabled for channel
    • [10]CH10 (def=0x0) // External requests are disabled for channel
    • [11]CH11 (def=0x0) // External requests are disabled for channel
    • [12]CH12 (def=0x0) // External requests are disabled for channel
    • [13]CH13 (def=0x0) // External requests are disabled for channel
    • [14]CH14 (def=0x0) // External requests are disabled for channel
    • [15]CH15 (def=0x0) // External requests are disabled for channel
    • [16]CH16 (def=0x0) // External requests are disabled for channel
    • [17]CH17 (def=0x0) // External requests are disabled for channel
    • [18]CH18 (def=0x0) // External requests are disabled for channel
    • [19]CH19 (def=0x0) // External requests are disabled for channel
    • [20]CH20 (def=0x0) // External requests are disabled for channel
    • [21]CH21 (def=0x0) // External requests are disabled for channel
    • [22]CH22 (def=0x0) // External requests are disabled for channel
    • [23]CH23 (def=0x0) // External requests are disabled for channel
  • 0x3000C028ENSET// Channel enable set

    • [0]CH0 (def=0x0) // Enable channel
    • [1]CH1 (def=0x0) // Enable channel
    • [2]CH2 (def=0x0) // Enable channel
    • [3]CH3 (def=0x0) // Enable channel
    • [4]CH4 (def=0x0) // Enable channel
    • [5]CH5 (def=0x0) // Enable channel
    • [6]CH6 (def=0x0) // Enable channel
    • [7]CH7 (def=0x0) // Enable channel
    • [8]CH8 (def=0x0) // Enable channel
    • [9]CH9 (def=0x0) // Enable channel
    • [10]CH10 (def=0x0) // Enable channel
    • [11]CH11 (def=0x0) // Enable channel
    • [12]CH12 (def=0x0) // Enable channel
    • [13]CH13 (def=0x0) // Enable channel
    • [14]CH14 (def=0x0) // Enable channel
    • [15]CH15 (def=0x0) // Enable channel
    • [16]CH16 (def=0x0) // Enable channel
    • [17]CH17 (def=0x0) // Enable channel
    • [18]CH18 (def=0x0) // Enable channel
    • [19]CH19 (def=0x0) // Enable channel
    • [20]CH20 (def=0x0) // Enable channel
    • [21]CH21 (def=0x0) // Enable channel
    • [22]CH22 (def=0x0) // Enable channel
    • [23]CH23 (def=0x0) // Enable channel
  • 0x3000C02CENCLR// Channel enable clear

    • [0]CH0 (def=0x0) // Disable channel
    • [1]CH1 (def=0x0) // Disable channel
    • [2]CH2 (def=0x0) // Disable channel
    • [3]CH3 (def=0x0) // Disable channel
    • [4]CH4 (def=0x0) // Disable channel
    • [5]CH5 (def=0x0) // Disable channel
    • [6]CH6 (def=0x0) // Disable channel
    • [7]CH7 (def=0x0) // Disable channel
    • [8]CH8 (def=0x0) // Disable channel
    • [9]CH9 (def=0x0) // Disable channel
    • [10]CH10 (def=0x0) // Disable channel
    • [11]CH11 (def=0x0) // Disable channel
    • [12]CH12 (def=0x0) // Disable channel
    • [13]CH13 (def=0x0) // Disable channel
    • [14]CH14 (def=0x0) // Disable channel
    • [15]CH15 (def=0x0) // Disable channel
    • [16]CH16 (def=0x0) // Disable channel
    • [17]CH17 (def=0x0) // Disable channel
    • [18]CH18 (def=0x0) // Disable channel
    • [19]CH19 (def=0x0) // Disable channel
    • [20]CH20 (def=0x0) // Disable channel
    • [21]CH21 (def=0x0) // Disable channel
    • [22]CH22 (def=0x0) // Disable channel
    • [23]CH23 (def=0x0) // Disable channel
  • 0x3000C030PRIALTSET// Channel primary-alternate set

    • [0]CH0 (def=0x0) // Set primary / alternate channel control data structure
    • [1]CH1 (def=0x0) // Set primary / alternate channel control data structure
    • [2]CH2 (def=0x0) // Set primary / alternate channel control data structure
    • [3]CH3 (def=0x0) // Set primary / alternate channel control data structure
    • [4]CH4 (def=0x0) // Set primary / alternate channel control data structure
    • [5]CH5 (def=0x0) // Set primary / alternate channel control data structure
    • [6]CH6 (def=0x0) // Set primary / alternate channel control data structure
    • [7]CH7 (def=0x0) // Set primary / alternate channel control data structure
    • [8]CH8 (def=0x0) // Set primary / alternate channel control data structure
    • [9]CH9 (def=0x0) // Set primary / alternate channel control data structure
    • [10]CH10 (def=0x0) // Set primary / alternate channel control data structure
    • [11]CH11 (def=0x0) // Set primary / alternate channel control data structure
    • [12]CH12 (def=0x0) // Set primary / alternate channel control data structure
    • [13]CH13 (def=0x0) // Set primary / alternate channel control data structure
    • [14]CH14 (def=0x0) // Set primary / alternate channel control data structure
    • [15]CH15 (def=0x0) // Set primary / alternate channel control data structure
    • [16]CH16 (def=0x0) // Set primary / alternate channel control data structure
    • [17]CH17 (def=0x0) // Set primary / alternate channel control data structure
    • [18]CH18 (def=0x0) // Set primary / alternate channel control data structure
    • [19]CH19 (def=0x0) // Set primary / alternate channel control data structure
    • [20]CH20 (def=0x0) // Set primary / alternate channel control data structure
    • [21]CH21 (def=0x0) // Set primary / alternate channel control data structure
    • [22]CH22 (def=0x0) // Set primary / alternate channel control data structure
    • [23]CH23 (def=0x0) // Set primary / alternate channel control data structure
  • 0x3000C034PRIALTCLR// Channel primary-alternate clear

    • [0]CH0 (def=0x0) // Clear primary / alternate channel control data structure
    • [1]CH1 (def=0x0) // Clear primary / alternate channel control data structure
    • [2]CH2 (def=0x0) // Clear primary / alternate channel control data structure
    • [3]CH3 (def=0x0) // Clear primary / alternate channel control data structure
    • [4]CH4 (def=0x0) // Clear primary / alternate channel control data structure
    • [5]CH5 (def=0x0) // Clear primary / alternate channel control data structure
    • [6]CH6 (def=0x0) // Clear primary / alternate channel control data structure
    • [7]CH7 (def=0x0) // Clear primary / alternate channel control data structure
    • [8]CH8 (def=0x0) // Clear primary / alternate channel control data structure
    • [9]CH9 (def=0x0) // Clear primary / alternate channel control data structure
    • [10]CH10 (def=0x0) // Clear primary / alternate channel control data structure
    • [11]CH11 (def=0x0) // Clear primary / alternate channel control data structure
    • [12]CH12 (def=0x0) // Clear primary / alternate channel control data structure
    • [13]CH13 (def=0x0) // Clear primary / alternate channel control data structure
    • [14]CH14 (def=0x0) // Clear primary / alternate channel control data structure
    • [15]CH15 (def=0x0) // Clear primary / alternate channel control data structure
    • [16]CH16 (def=0x0) // Clear primary / alternate channel control data structure
    • [17]CH17 (def=0x0) // Clear primary / alternate channel control data structure
    • [18]CH18 (def=0x0) // Clear primary / alternate channel control data structure
    • [19]CH19 (def=0x0) // Clear primary / alternate channel control data structure
    • [20]CH20 (def=0x0) // Clear primary / alternate channel control data structure
    • [21]CH21 (def=0x0) // Clear primary / alternate channel control data structure
    • [22]CH22 (def=0x0) // Clear primary / alternate channel control data structure
    • [23]CH23 (def=0x0) // Clear primary / alternate channel control data structure
  • 0x3000C038PRIORITYSET// Channel priority set

    • [0]CH0 (def=0x0) // Set the priority of channel
    • [1]CH1 (def=0x0) // Set the priority of channel
    • [2]CH2 (def=0x0) // Set the priority of channel
    • [3]CH3 (def=0x0) // Set the priority of channel
    • [4]CH4 (def=0x0) // Set the priority of channel
    • [5]CH5 (def=0x0) // Set the priority of channel
    • [6]CH6 (def=0x0) // Set the priority of channel
    • [7]CH7 (def=0x0) // Set the priority of channel
    • [8]CH8 (def=0x0) // Set the priority of channel
    • [9]CH9 (def=0x0) // Set the priority of channel
    • [10]CH10 (def=0x0) // Set the priority of channel
    • [11]CH11 (def=0x0) // Set the priority of channel
    • [12]CH12 (def=0x0) // Set the priority of channel
    • [13]CH13 (def=0x0) // Set the priority of channel
    • [14]CH14 (def=0x0) // Set the priority of channel
    • [15]CH15 (def=0x0) // Set the priority of channel
    • [16]CH16 (def=0x0) // Set the priority of channel
    • [17]CH17 (def=0x0) // Set the priority of channel
    • [18]CH18 (def=0x0) // Set the priority of channel
    • [19]CH19 (def=0x0) // Set the priority of channel
    • [20]CH20 (def=0x0) // Set the priority of channel
    • [21]CH21 (def=0x0) // Set the priority of channel
    • [22]CH22 (def=0x0) // Set the priority of channel
    • [23]CH23 (def=0x0) // Set the priority of channel
  • 0x3000C03CPRIORITYCLR// Channel priority clear

    • [0]CH0 (def=0x0) // Clear the priority
    • [1]CH1 (def=0x0) // Clear the priority
    • [2]CH2 (def=0x0) // Clear the priority
    • [3]CH3 (def=0x0) // Clear the priority
    • [4]CH4 (def=0x0) // Clear the priority
    • [5]CH5 (def=0x0) // Clear the priority
    • [6]CH6 (def=0x0) // Clear the priority
    • [7]CH7 (def=0x0) // Clear the priority
    • [8]CH8 (def=0x0) // Clear the priority
    • [9]CH9 (def=0x0) // Clear the priority
    • [10]CH10 (def=0x0) // Clear the priority
    • [11]CH11 (def=0x0) // Clear the priority
    • [12]CH12 (def=0x0) // Clear the priority
    • [13]CH13 (def=0x0) // Clear the priority
    • [14]CH14 (def=0x0) // Clear the priority
    • [15]CH15 (def=0x0) // Clear the priority
    • [16]CH16 (def=0x0) // Clear the priority
    • [17]CH17 (def=0x0) // Clear the priority
    • [18]CH18 (def=0x0) // Clear the priority
    • [19]CH19 (def=0x0) // Clear the priority
    • [20]CH20 (def=0x0) // Clear the priority
    • [21]CH21 (def=0x0) // Clear the priority
    • [22]CH22 (def=0x0) // Clear the priority
    • [23]CH23 (def=0x0) // Clear the priority
  • 0x3000C040CIRCULARSET// Channel circular set

    • [0]CH0 (def=0x0) // Set the channel circular mode
    • [1]CH1 (def=0x0) // Set the channel circular mode
    • [2]CH2 (def=0x0) // Set the channel circular mode
    • [3]CH3 (def=0x0) // Set the channel circular mode
    • [4]CH4 (def=0x0) // Set the channel circular mode
    • [5]CH5 (def=0x0) // Set the channel circular mode
    • [6]CH6 (def=0x0) // Set the channel circular mode
    • [7]CH7 (def=0x0) // Set the channel circular mode
    • [8]CH8 (def=0x0) // Set the channel circular mode
    • [9]CH9 (def=0x0) // Set the channel circular mode
    • [10]CH10 (def=0x0) // Set the channel circular mode
    • [11]CH11 (def=0x0) // Set the channel circular mode
    • [12]CH12 (def=0x0) // Set the channel circular mode
    • [13]CH13 (def=0x0) // Set the channel circular mode
    • [14]CH14 (def=0x0) // Set the channel circular mode
    • [15]CH15 (def=0x0) // Set the channel circular mode
    • [16]CH16 (def=0x0) // Set the channel circular mode
    • [17]CH17 (def=0x0) // Set the channel circular mode
    • [18]CH18 (def=0x0) // Set the channel circular mode
    • [19]CH19 (def=0x0) // Set the channel circular mode
    • [20]CH20 (def=0x0) // Set the channel circular mode
    • [21]CH21 (def=0x0) // Set the channel circular mode
    • [22]CH22 (def=0x0) // Set the channel circular mode
    • [23]CH23 (def=0x0) // Set the channel circular mode
  • 0x3000C044CIRCULARCLR// Channel circular clear

    • [0]CH0 (def=0x0) // Clear the channel circular mode
    • [1]CH1 (def=0x0) // Clear the channel circular mode
    • [2]CH2 (def=0x0) // Clear the channel circular mode
    • [3]CH3 (def=0x0) // Clear the channel circular mode
    • [4]CH4 (def=0x0) // Clear the channel circular mode
    • [5]CH5 (def=0x0) // Clear the channel circular mode
    • [6]CH6 (def=0x0) // Clear the channel circular mode
    • [7]CH7 (def=0x0) // Clear the channel circular mode
    • [8]CH8 (def=0x0) // Clear the channel circular mode
    • [9]CH9 (def=0x0) // Clear the channel circular mode
    • [10]CH10 (def=0x0) // Clear the channel circular mode
    • [11]CH11 (def=0x0) // Clear the channel circular mode
    • [12]CH12 (def=0x0) // Clear the channel circular mode
    • [13]CH13 (def=0x0) // Clear the channel circular mode
    • [14]CH14 (def=0x0) // Clear the channel circular mode
    • [15]CH15 (def=0x0) // Clear the channel circular mode
    • [16]CH16 (def=0x0) // Clear the channel circular mode
    • [17]CH17 (def=0x0) // Clear the channel circular mode
    • [18]CH18 (def=0x0) // Clear the channel circular mode
    • [19]CH19 (def=0x0) // Clear the channel circular mode
    • [20]CH20 (def=0x0) // Clear the channel circular mode
    • [21]CH21 (def=0x0) // Clear the channel circular mode
    • [22]CH22 (def=0x0) // Clear the channel circular mode
    • [23]CH23 (def=0x0) // Clear the channel circular mode
  • 0x3000C04CERRCLR// Bus error register

    • [0]VAL (def=0x0) // Indicate Error on bus AHB-Lite
  • 0x3000C050IRQSTAT// IRQ Status register

    • [0]CH0 (def=0x0) //
    • [1]CH1 (def=0x0) //
    • [2]CH2 (def=0x0) //
    • [3]CH3 (def=0x0) //
    • [4]CH4 (def=0x0) //
    • [5]CH5 (def=0x0) //
    • [6]CH6 (def=0x0) //
    • [7]CH7 (def=0x0) //
    • [8]CH8 (def=0x0) //
    • [9]CH9 (def=0x0) //
    • [10]CH10 (def=0x0) //
    • [11]CH11 (def=0x0) //
    • [12]CH12 (def=0x0) //
    • [13]CH13 (def=0x0) //
    • [14]CH14 (def=0x0) //
    • [15]CH15 (def=0x0) //
    • [16]CH16 (def=0x0) //
    • [17]CH17 (def=0x0) //
    • [18]CH18 (def=0x0) //
    • [19]CH19 (def=0x0) //
    • [20]CH20 (def=0x0) //
    • [21]CH21 (def=0x0) //
    • [22]CH22 (def=0x0) //
    • [23]CH23 (def=0x0) //
  • 0x3000C054IRQSTATCLR// IRQ Clear Status register

    • [0]CH0 (def=0x0) //
    • [1]CH1 (def=0x0) //
    • [2]CH2 (def=0x0) //
    • [3]CH3 (def=0x0) //
    • [4]CH4 (def=0x0) //
    • [5]CH5 (def=0x0) //
    • [6]CH6 (def=0x0) //
    • [7]CH7 (def=0x0) //
    • [8]CH8 (def=0x0) //
    • [9]CH9 (def=0x0) //
    • [10]CH10 (def=0x0) //
    • [11]CH11 (def=0x0) //
    • [12]CH12 (def=0x0) //
    • [13]CH13 (def=0x0) //
    • [14]CH14 (def=0x0) //
    • [15]CH15 (def=0x0) //
    • [16]CH16 (def=0x0) //
    • [17]CH17 (def=0x0) //
    • [18]CH18 (def=0x0) //
    • [19]CH19 (def=0x0) //
    • [20]CH20 (def=0x0) //
    • [21]CH21 (def=0x0) //
    • [22]CH22 (def=0x0) //
    • [23]CH23 (def=0x0) //
  interrupts:
  • [13] DMA0 // DMA channel 0,1,2 interrupt
  • [14] DMA1 // DMA channel 3,4,5 interrupt
  • [15] DMA2 // DMA channel 6,7,8 interrupt
  • [16] DMA3 // DMA channel 9,10,11 interrupt
  • [17] DMA4 // DMA channel 12,13,14 interrupt
  • [18] DMA5 // DMA channel 15,16,17 interrupt
  • [19] DMA6 // DMA channel 18,19,20 interrupt
  • [20] DMA7 // DMA channel 21,22,23 interrupt
• 0x3000D000FLASH// Mainflash control registers

  • 0x3000D000ADDR// Address Register

    • [0:18]VAL (def=0x0) // Address value for flash operations
  • 0x3000D044CMD// Command Register

    • [0]RD (def=0x0) // Read enable command
    • [1]WR (def=0x0) // Write enable command
    • [2]ERSEC (def=0x0) // Erase sector enable command
    • [3]ALLSEC (def=0x0) // Enable Erase all flash memory
    • [8]NVRON (def=0x0) // INFO access bit
    • [16:31]KEY (def=0x0) // Magic Key for flash access "C0DE"
  • 0x3000D048STAT// Status Register

    • [0]BUSY (def=0x0) // Busy status bit when command is processing
    • [1]IRQF (def=0x0) // IRQ Flag set when command done. Set by hardware only if IRQEN bit is set.
  • 0x3000D04CCTRL// Control Register

    • [1]CEN (def=0x0) // Cache enable bit
    • [8]CFLUSH (def=0x0) // Cache bit
    • [16:19]LAT (def=0x0) // Flash latency
  • 0x3000D0C8LP// LP mode Register

    • [0]LPEN (def=0x0) // LowPower mode enable
• 0x20050000SPI0// SPI control registers

  • 0x20050000CR0// Control register 0

    • [0:3]DSS (def=0x0) //
    • [4:5]FRF (def=0x0) //
    • [6]SPO (def=0x0) // Polarity SSPCLKOUT
    • [7]SPH (def=0x0) // Phase SSPCLKOUT
    • [8:15]SCR (def=0x0) //
  • 0x20050004CR1// Control register 1

    • [1]SSE (def=0x0) // Enable transceiver
    • [2]MS (def=0x0) // Select mode
    • [3]SOD (def=0x0) // Disable bit data
    • [8:11]RXIFLSEL (def=0x0) //
    • [12:15]TXIFLSEL (def=0x0) //
  • 0x20050008DR// Data register

    • [0:15]DATA (def=0x0) //
  • 0x2005000CSR// State register

    • [0]TFE (def=0x0) // FIFO buffer empty flag transmitter
    • [1]TNF (def=0x0) // Indicator the transmitter FIFO buffer is not full
    • [2]RNE (def=0x0) // Indicate not empty receive buffer
    • [3]RFF (def=0x0) // Indicate full receive buffer
    • [4]BSY (def=0x0) // Activity flag
  • 0x20050010CPSR// Clock division factor register

    • [0:7]CPSDVSR (def=0x0) //
  • 0x20050014IMSC// Mask interrupt register

    • [0]RORIM (def=0x0) // Interrupt mask bit SSPRORINTR buffer overflow receiver
    • [1]RTIM (def=0x0) // Interrupt mask bit SSPRTINTR timeout receiver
    • [2]RXIM (def=0x0) // SSPRXINTR interrupt mask bit to fill 50% or less of the receiver FIFO buffer
    • [3]TXIM (def=0x0) // SSPTXINTR interrupt mask bit to fill 50% or less of the FIFO buffer of the transmitter
  • 0x20050018RIS// Status register interrupt without mask

    • [0]RORRIS (def=0x0) // Interrupt status before masking SSPRORINTR
    • [1]RTRIS (def=0x0) // Interrupt status before masking SSPRTINTR
    • [2]RXRIS (def=0x0) // Interrupt status before masking SSPRXINTR
    • [3]TXRIS (def=0x0) // Interrupt status before masking SSPTXINTR
  • 0x2005001CMIS// Status register interrupt masking account

    • [0]RORMIS (def=0x0) // Masked interrupt status SSPRORINTR
    • [1]RTMIS (def=0x0) // Masked interrupt status SSPRTINTR
    • [2]RXMIS (def=0x0) // Masked interrupt status SSPRXINTR
    • [3]TXMIS (def=0x0) // Masked interrupt status SSPTXINTR
  • 0x20050020ICR// Register reset interrupt

    • [0]RORIC (def=0x0) // Reset interrupt SSPRORINTR
    • [1]RTIC (def=0x0) // Reset interrupt SSPRTINTR
  • 0x20050024DMACR// Control register DMA

    • [0]RXDMAE (def=0x0) // DMA enable bit at reception
    • [1]TXDMAE (def=0x0) // DMA enable bit transmission
  interrupts:
  • [11] SPI0 // SPI0 interrupt
• 0x20060000SPI1//

  • 0x20060000CR0// Control register 0

    • [0:3]DSS (def=0x0) //
    • [4:5]FRF (def=0x0) //
    • [6]SPO (def=0x0) // Polarity SSPCLKOUT
    • [7]SPH (def=0x0) // Phase SSPCLKOUT
    • [8:15]SCR (def=0x0) //
  • 0x20060004CR1// Control register 1

    • [1]SSE (def=0x0) // Enable transceiver
    • [2]MS (def=0x0) // Select mode
    • [3]SOD (def=0x0) // Disable bit data
    • [8:11]RXIFLSEL (def=0x0) //
    • [12:15]TXIFLSEL (def=0x0) //
  • 0x20060008DR// Data register

    • [0:15]DATA (def=0x0) //
  • 0x2006000CSR// State register

    • [0]TFE (def=0x0) // FIFO buffer empty flag transmitter
    • [1]TNF (def=0x0) // Indicator the transmitter FIFO buffer is not full
    • [2]RNE (def=0x0) // Indicate not empty receive buffer
    • [3]RFF (def=0x0) // Indicate full receive buffer
    • [4]BSY (def=0x0) // Activity flag
  • 0x20060010CPSR// Clock division factor register

    • [0:7]CPSDVSR (def=0x0) //
  • 0x20060014IMSC// Mask interrupt register

    • [0]RORIM (def=0x0) // Interrupt mask bit SSPRORINTR buffer overflow receiver
    • [1]RTIM (def=0x0) // Interrupt mask bit SSPRTINTR timeout receiver
    • [2]RXIM (def=0x0) // SSPRXINTR interrupt mask bit to fill 50% or less of the receiver FIFO buffer
    • [3]TXIM (def=0x0) // SSPTXINTR interrupt mask bit to fill 50% or less of the FIFO buffer of the transmitter
  • 0x20060018RIS// Status register interrupt without mask

    • [0]RORRIS (def=0x0) // Interrupt status before masking SSPRORINTR
    • [1]RTRIS (def=0x0) // Interrupt status before masking SSPRTINTR
    • [2]RXRIS (def=0x0) // Interrupt status before masking SSPRXINTR
    • [3]TXRIS (def=0x0) // Interrupt status before masking SSPTXINTR
  • 0x2006001CMIS// Status register interrupt masking account

    • [0]RORMIS (def=0x0) // Masked interrupt status SSPRORINTR
    • [1]RTMIS (def=0x0) // Masked interrupt status SSPRTINTR
    • [2]RXMIS (def=0x0) // Masked interrupt status SSPRXINTR
    • [3]TXMIS (def=0x0) // Masked interrupt status SSPTXINTR
  • 0x20060020ICR// Register reset interrupt

    • [0]RORIC (def=0x0) // Reset interrupt SSPRORINTR
    • [1]RTIC (def=0x0) // Reset interrupt SSPRTINTR
  • 0x20060024DMACR// Control register DMA

    • [0]RXDMAE (def=0x0) // DMA enable bit at reception
    • [1]TXDMAE (def=0x0) // DMA enable bit transmission
  interrupts:
  • [12] SPI1 // SPI1 interrupt
• 0x20040000QSPI// QSPI control registers

  • 0x20040000HCR// Host Control Register

    • [0]DEN (def=0x0) // Device enable
    • [1]DRS (def=0x0) // Device reset ( SW reset )
    • [2]TXFCLR (def=0x0) // Tx FIFO clear
    • [3]RXFCLR (def=0x0) // Rx FIFO clear
  • 0x20040004DCR// Device Config Register

    • [0]CPHA (def=0x0) // Serial clock phase
    • [1]CPOL (def=0x0) // Serial clock polarity
    • [8:15]CDIV (def=0x0) // Serial clock DIV value
    • [16:18]FMOD (def=0x0) // Functional mode ( [00] - Std.SPI ; [01] - Reserved ; [10] - QSPI Memory Interface ; [11] - Test Loo
  • 0x20040008DSR// Device status register

    • [0]BUSY (def=0x0) // Flag BUSY
    • [1]TIP (def=0x0) // Transfer In Progress
    • [2]TST (def=0x0) // Transfer Stall
    • [4]TFE (def=0x0) // Tx FIFO Empty
    • [5]TFF (def=0x0) // Tx FIFO Full
    • [6]RFE (def=0x0) // Rx FIFO Empty
    • [7]RFF (def=0x0) // Rx FIFO Full
    • [8:12]TXFCNT (def=0x0) // Curent Tx FIFO Element Count
    • [16:20]RXFCNT (def=0x0) // Curent Rx FIFO Element Count
  • 0x2004000CTCR// Transfer Config register

    • [0:5]LEN (def=0x0) // Size of data
    • [6]LSBF (def=0x0) // LSB First ( 0 - MSB First; 1 - LSB First )
    • [7]DDR (def=0x0) // Double Data Rate ( 0 - SDR ; 1 - DDR )
    • [8]TXE (def=0x0) // Serial Transmitter Enable
    • [9]RXE (def=0x0) // Serial Receiver Enable
    • [10:11]IOM (def=0x0) // IO Mode ( SIO/DIO/QIO ) Single/Double/Quad lines for serial IO
  • 0x20040010TDR// Transfer Data register

    • [0:31]VAL (def=0x0) //
  • 0x20040014TDS// Transfer Data size register

    • [0:31]VAL (def=0x0) //
  • 0x20040018QCC// QSPI Communication Config register

    • [0:7]INST (def=0x0) // Instruction to be sent to the external SPI defice
    • [8:9]IMOD (def=0x0) // Instruction mode
    • [10:11]ADMOD (def=0x0) // Address mode
    • [12:13]ADSIZ (def=0x0) // Address size
    • [14:15]ABMOD (def=0x0) // Alternate bytes mode
    • [16:17]ABSIZ (def=0x0) // Alternate bytes size
    • [18:22]DCYCS (def=0x0) // Number of dummy cycles ( This field defines of the dummy phase. ) It specifies a number of CLK cycl
    • [24:25]DMOD (def=0x0) // Data mode
    • [26:27]DIOD (def=0x0) // QSPI Data IO Direction
    • [31]DDRM (def=0x0) // QSPI Double Data Rate Mode: ( 0 - SDR; 1 - DDR ) This bit sets the DDR mode for address, alt byte
  • 0x2004001CQAD// QSPI Address Register

    • [0:31]VAL (def=0x0) //
  • 0x20040020QAB// QSPI Alternate Bytes Register

    • [0:31]VAL (def=0x0) //
  • 0x20040024IMR// Interrupt Mask Register

    • [1]TCIM (def=0x0) // Transfer Complete Interrupt Mask
    • [2]TSIM (def=0x0) // Transfer Stall Interrupt Mask
    • [4]TEIM (def=0x0) // Tx FIFO Empty Interrupt Mask
    • [5]TFIM (def=0x0) // Tx FIFO Full Interrupt Mask
    • [6]REIM (def=0x0) // Rx FIFO Empty Interrupt Mask
    • [7]RFIM (def=0x0) // Rx FIFO Full Interrupt Mask
    • [8]TWMIM (def=0x0) // Tx FIFO Watermark Interrupt Mask
    • [9]RWMIM (def=0x0) // Rx FIFO Watermark Interrupt Mask
  • 0x20040028ICR// Interrupt Clear Register

    • [1]TCIC (def=0x0) // Transfer Complete Interrupt Clear
    • [2]TSIC (def=0x0) // Transfer Stall Interrupt Clear
    • [4]TEIC (def=0x0) // Tx FIFO Empty Interrupt Clear
    • [5]TFIC (def=0x0) // Tx FIFO Full Interrupt Clear
    • [6]REIC (def=0x0) // Rx FIFO Empty Interrupt Clear
    • [7]RFIC (def=0x0) // Rx FIFO Full Interrupt Clear
    • [8]TWMIC (def=0x0) // Tx FIFO Watermark Interrupt Clear
    • [9]RWMIC (def=0x0) // Rx FIFO Watermark Interrupt Clear
  • 0x2004002CRIS// Raw Interrupt Status Register

    • [1]TCRIS (def=0x0) // Transfer Complete raw interrupt status
    • [2]TSRIS (def=0x0) // Transfer Stall raw interrupt status
    • [4]TERIS (def=0x0) // Tx FIFO Empty raw interrupt status
    • [5]TFRIS (def=0x0) // Tx FIFO Full raw interrupt status
    • [6]RERIS (def=0x0) // Rx FIFO Empty raw interrupt status
    • [7]RFRIS (def=0x0) // Rx FIFO Full raw interrupt status
    • [8]TWMRIS (def=0x0) // Tx FIFO Watermark raw interrupt status
    • [9]RWMRIS (def=0x0) // Rx FIFO Watermark raw interrupt status
  • 0x20040030FWM// Fifo's WaterMarks Register

    • [0:4]TLEC (def=0x0) // Tx FIFO Low Element Count limit ( Low Watermark )
    • [8:12]RHEC (def=0x0) // Rx FIFO High Element Count limit ( High Watermark )
  • 0x20040034MIS// Masked Interrupt Status Register

    • [1]TCMIS (def=0x0) // Transfer Complete masked interrupt status
    • [2]TSMIS (def=0x0) // Transfer Stall masked interrupt status
    • [4]TEMIS (def=0x0) // Tx FIFO Empty masked interrupt status
    • [5]TFMIS (def=0x0) // Tx FIFO Full masked interrupt status
    • [6]REMIS (def=0x0) // Rx FIFO Empty masked interrupt status
    • [7]RFMIS (def=0x0) // Rx FIFO Full masked interrupt status
    • [8]TWMIS (def=0x0) // Tx FIFO Watermark masked interrupt status
    • [9]RWMIS (def=0x0) // Rx FIFO Watermark masked interrupt status
  interrupts:
  • [10] QSPI // QSPI interrupt
• 0x20000000CAN// CAN controller registers

  • 0x20000000CLC// Frequency control register

    • [0]DISR (def=0x0) // OFF module CAN
    • [1]DISS (def=0x0) // State CAN
  • 0x20000008ID// Identity register

    • [0:7]MODREV (def=0x0) //
    • [8:15]MODTYPE (def=0x0) //
    • [16:31]MODNUM (def=0x0) //
  • 0x2000000CFDR// Register divider

    • [0:9]STEP (def=0x0) //
    • [14:15]DM (def=0x0) //
    • [16:25]RESULT (def=0x0) //
    • [30]ENHW (def=0x0) // Control bit synchronization
    • [31]DISCLK (def=0x0) // Disable bit internal clock
  • 0x200001C0MSIMASK// Mask register message index

    • [0:31]IM (def=0x0) //
  • 0x200001C4PANCTR// Register command panel

    • [0:7]PANCMD (def=0x0) //
    • [8]BUSY (def=0x0) // Busy flag panels arguments (waiting to be written at the end of the command)
    • [9]RBUSY (def=0x0) // Busy flag panels arguments (running the command list, the result of which will be recorded in PANAR
    • [16:23]PANAR1 (def=0x0) // Panel argument 8
    • [24:31]PANAR2 (def=0x0) // Panel argument 9
  • 0x200001C8MCR// Control register

    • [12:15]MPSEL (def=0x0) //
  • 0x200001CCMITR// Interrupt register

    • [0:15]IT (def=0x0) //
  interrupts:
  • [2] CAN0 // CAN0 interrupt
  • [3] CAN1 // CAN1 interrupt
• 0x20001000CANMSG// CAN Msg registers
• 0x30005000I2C// I2C controller registers

  • 0x30005000SDA// Data register

    • [0:7]DATA (def=0x0) //
  • 0x30005004ST// Status register

    • [0:5]MODE (def=0x0) //
    • [7]INT (def=0x0) // Interrupt flag
  • 0x30005008CST// Status and control register

    • [0]BB (def=0x0) // Flag employment bus
    • [1:2]TOCDIV (def=0x0) //
    • [3]TOERR (def=0x0) // Flag error simple bus
    • [4]TSDA (def=0x0) // Bit test SDA
    • [5]TGSCL (def=0x0) // Bit switch SCL
    • [6]PECNEXT (def=0x0) // Bit control transmit CRC
    • [7]PECFAULT (def=0x0) // Error flag
  • 0x3000500CCTL0// Control register 0

    • [0]START (def=0x0) // Start bit
    • [1]STOP (def=0x0) // Stop bit
    • [2]INTEN (def=0x0) // Interrupt enable bit
    • [4]ACK (def=0x0) // Acknowledgment bit reception
    • [5]GCMEN (def=0x0) // Control bit part a response to the general call address
    • [6]SMBARE (def=0x0) // Control bit part a response to the response address
    • [7]CLRST (def=0x0) // Bit reset flag interrupt
  • 0x30005010ADDR// Register own address

    • [0:6]ADDR (def=0x0) //
    • [7]SAEN (def=0x0) // Enable bit address recognition
  • 0x30005014CTL1// Control register 1

    • [0]ENABLE (def=0x0) // Enable I2C
    • [1:7]SCLFRQ (def=0x0) //
  • 0x30005018TOPR// Prescaler load register

    • [0:7]SMBTOPR (def=0x0) //
  • 0x3000501CCTL2// Control register 2

    • [0:2]S10ADR (def=0x0) //
    • [3]S10EN (def=0x0) // Bit enabled 10-bit addressing slave
    • [4:7]HSDIV (def=0x0) //
  • 0x30005020CTL3// Control register 3

    • [0:7]SCLFRQ (def=0x0) // Field frequency selection signal at pin SCL in master mode (bits [14:7])
  • 0x30005024CTL4// Control Register 4

    • [0:7]RSDIV (def=0x0) // Field frequency selection signal at pin SCL in HS master mode (bits [11:4])
  • 0x30005028CTL5// Control Register 5

    • [0:7]HSDIV (def=0x0) // Field frequency selection signal at pin SCL in HS master mode (bits [11:4])
  interrupts:
  • [21] I2C // I2C interrupt
• 0x38010000CMP// CMP controller registers

  • 0x38010000DACCTL// DAC control register

    • [0:3]REF0 (def=0x0) //
    • [8:11]REF1 (def=0x0) //
    • [16]EN (def=0x0) //
  • 0x38010004ACMP0CTL// ACMP0 control register

    • [0]EN (def=0x0) //
    • [1]RST (def=0x0) //
    • [2]INV (def=0x0) //
    • [4:5]SELREF (def=0x0) //
    • [8:10]INTSRC (def=0x0) //
    • [12:14]TRIGSRC (def=0x0) //
  • 0x38010008ACMP1CTL// ACMP1 control register

    • [0]EN (def=0x0) //
    • [1]RST (def=0x0) //
    • [2]INV (def=0x0) //
    • [4:5]SELREF (def=0x0) //
    • [8:10]INTSRC (def=0x0) //
    • [12:14]TRIGSRC (def=0x0) //
  • 0x3801000CACSTATUS// ACMP status

    • [0]STATE0 (def=0x0) //
    • [1]STATE1 (def=0x0) //
  • 0x38010010INTEN// Interrupt enable

    • [0]CMP0 (def=0x0) //
    • [1]CMP1 (def=0x0) //
  • 0x38010014RIS// Raw interrupt status

    • [0]CMP0 (def=0x0) //
    • [1]CMP1 (def=0x0) //
  • 0x38010018MIS// Masked interrupt status

    • [0]CMP0 (def=0x0) //
    • [1]CMP1 (def=0x0) //
  • 0x3801001CICLR// Clear interrupt status

    • [0]CMP0 (def=0x0) //
    • [1]CMP1 (def=0x0) //
  interrupts:
  • [30] CMP // CMP interrupt
• 0x38011000PMURTC// RTC controller registers

  • 0x38011000RTC_CFG0// Config0 register

    • [0:2]LPCK (def=0x0) // defines the refresh period of comparators, in LP and ULP
    • [3:4]FC (def=0x0) // (must stay 0) force power mode of the PMU power controller submodule
    • [5]UVDIS (def=0x0) // undervoltage disable (default is 0 - undervoltage detection enable)
    • [6]CD (def=0x0) // lpclk pulse disable (default is 0 - pulse enabled)
    • [10]DE (def=0x0) // clkdiv output enable (defauls is 0, output disabled)
    • [11]EL (def=0x0) // (must stay 0) forced enable levelshifters of LDO0
    • [13]LS (def=0x0) // lpclk == 1 period duration. 0 - 15 us, 1 - 30 us
    • [14:16]AT2 (def=0x0) // 2 - AT2 disabled (default). 001 to 111 - freq limit: 4.7/7.8/10.9/14.1/17.2/20.3/23.4 [%]
    • [17]EXTOSC (def=0x0) // Use external crystal oscillator and disables RC osc. (except if antitamper2 is active)
    • [19:27]FREQDIFF (def=0x0) // Value of the antitamper 2 clock cycles difference relative to expected value
  • 0x38011004RTC_TRIMRC// Trim RC OSC register

    • [0:10]VAL (def=0x0) // Trim for rc osc
  • 0x38011008RTC_HISTORY// History register

    • [0]WAKE0 (def=0x0) // when a wake event occurs, the corresponding bit is set.
    • [1]WAKE1 (def=0x0) // when a wake event occurs, the corresponding bit is set.
    • [2]WAKE2 (def=0x0) // when a wake event occurs, the corresponding bit is set.
    • [3]WKVBATPER (def=0x0) // when a wake event occurs, the corresponding bit is set.
    • [4]WKUVLO (def=0x0) // when a wake event occurs, the corresponding bit is set.
    • [5]WKVFVBAK (def=0x0) // when a wake event occurs, the corresponding bit is set.
    • [6]FREQERR (def=0x0) // frequency error detection history
    • [7]TAMPER0 (def=0x0) // Anti-tamper 0 detection
    • [8]TAMPER1 (def=0x0) // Anti-tamper 1 detection
    • [9]TAMPER2 (def=0x0) // Anti-tamper 1 detection
    • [10]TIMEALARM (def=0x0) // time alarm: time=alarm
  • 0x3801100CRTC_TIME// Time register

    • [0:31]VAL (def=0x0) // Value of Time
  • 0x38011010RTC_ALARM// Alarm register

    • [0:31]VAL (def=0x0) // time value that will set alarm if t=1'b1
  • 0x38011014RTC_TRIM// Trim register

    • [0:10]TRIM1S (def=0x0) // active oscillator (RTC_CFG0.OSCSEL) 1sec trim word (to apply each 64sec)
    • [11:13]ITRIM (def=0x0) // bias current trim word for APC
    • [14:18]VTRIM (def=0x0) // reference voltage offset trim word for APC
    • [19:21]TEMPTRIM (def=0x0) // temperature trim word for APC
    • [22]BYPASS (def=0x0) // Crystal oscillator cmos bypass mode (default is 0 = disabled)
    • [23:26]CXT (def=0x0) // bits reserved (must be 0 unless otherwise advised)
    • [27:31]CLKDIV (def=0x0) // division of clk32 used as anti-tamper source and output at clkdiv
  • 0x38011018RTC_CFG1// Config1 register

    • [0]CLKSEL (def=0x0) // time register clock selection (32kHz if ck=0; 1Hz if ck=1 - default)
    • [1]ALARMZEN (def=0x0) // if z=1, alarmz open drain output is active; if z=0 OD output is not active (default is z=1)
    • [2]ALARMEN (def=0x0) // enable alarm being set by time==alarm (default is 1, set possibility enabled)
    • [9:10]ULP (def=0x0) // when ulp[k]=1, regulator k operates in ultra-low power (default is 00)
    • [11:12]LP (def=0x0) // when lp[k]=1, regulator k operates in low power (default is 00)
    • [13:14]REGEN (def=0x0) // when en[k]=1, regulator k is enabled even with alarm=0 (default is 00)
    • [15:16]REGDIS (def=0x0) // when dis[k]=1, regulator k is disabled even with alarm=1 (default is 00)
    • [17:21]LDOLV (def=0x0) // LDOs low voltage for low power and ultra low power. Default 000101 - 0.9V
    • [23:27]LDOHV (def=0x0) // LDOs high voltage for low power and ultra low power. Default 011010 - 1.32V
    • [30]ALARMRST (def=0x0) // alarm reset (resets alarm if r=1)
  • 0x3801101CRTC_WAKECFG// Wake config register

    • [0:5]WAKEEN (def=0x0) // crystal oscillator cmos bypass mode (default is 0 = disabled)
    • [6:11]WAKEPOL (def=0x0) // if wp[i]=0, wake[i] is active high; if wp[i]=1, wake[i] is active low (default is wp[i]=0)
    • [12:13]DIS5 (def=0x0) // values that are copied to dis[1:0] when wake[5] occurs (default is 00)
    • [14:15]DIS4 (def=0x0) // values that are copied to dis[1:0] when wake[4] occurs (default is 00)
    • [16:17]RST5 (def=0x0) // reset configuration for porz1 and porz0 if wake[5] occurs (default is 00)
    • [18:19]RST4 (def=0x0) // reset configuration for porz1 and porz0 if wake[4] occurs (default is 00)
    • [20]TAMPER0EN (def=0x0) // Anti-tamper input 0 enable bit
    • [21]TAMPER1EN (def=0x0) // Anti-tamper input 1 enable bit
    • [22]TAMPER2EN (def=0x0) // Anti-tamper input 2 enable bit
    • [26:30]VPROG (def=0x0) // programming voltage for high power operation of both LDOs. Default is 010100 - 1.2V
  • 0x38011060RTC_TICKGEN// Tick counter register (used to generate clk1s)

    • [0:20]VAL (def=0x0) // (debug and production test only) Overwrite value of tick counter used for generation of clk1s
  • 0x38011064RTC_TRIM1S_LD// TRIM1S load regiter

    • [0:31]VAL (def=0x0) // RTC_TRIM.TRIM1S will be used after write to this register
  • 0x38011080PMU_WK3EN// PMU WKVBATPER Event Enable register

    • [0]CMP0 (def=0x0) // Comparator 0 event enable for WKVBATPER
    • [1]CMP1 (def=0x0) // Comparator 1 event enable for WKVBATPER
    • [2]IWDG (def=0x0) // Independent WatchDog event enable for WKVBATPER
    • [3]EXTRST (def=0x0) // External reset event enable for WKVBATPER
    • [4]CLK1S (def=0x0) // CLK1S posedge event enable for WKVBATPER
  • 0x38011084PMU_WK3STAT// PMU WKVBATPER Event Status register

    • [0]CMP0 (def=0x0) // Comaparator 0 event status for WKVBATPER
    • [1]CMP1 (def=0x0) // Comaparator 1 event status for WKVBATPER
    • [2]IWDG (def=0x0) // Independent WatchDog event status for WKVBATPER
    • [3]EXTRST (def=0x0) // External reset event status for WKVBATPER
    • [4]CLK1S (def=0x0) // CLK1S posedge event status for WKVBATPER
  • 0x38011088PMU_WCYC// PMU Wait cycles Register Access

    • [0:7]VAL (def=0x0) // Wait cycles value
  • 0x3801108CWFI_PDEN// WFI Powerdown function configuration

    • [0]EN (def=0x0) // Enable powerdown function for WFI command
  • 0x38011090WFI_ENTR// WFI Powerdown Entry configuration

    • [0]LDO0EN (def=0x0) // LDO0 enabled after WFI command
    • [1]LDO1EN (def=0x0) // LDO1 enabled after WFI command
    • [4]LDO0LP (def=0x0) // LDO0 in lowpower mode after WFI command
    • [5]LDO1LP (def=0x0) // LDO1 in lowpower mode after WFI command
    • [8]LDO0ULP (def=0x0) // LDO0 in ultralowpower mode after WFI command
    • [9]LDO1ULP (def=0x0) // LDO1 in ultralowpower mode after WFI command
    • [16:20]VL (def=0x0) // Lower LDO voltage value in LP/ULP mode
    • [24:28]VH (def=0x0) // Upper LDO voltage value in LP/ULP mode
    • [31]ALR (def=0x0) // Automatic alarm reset RTC_CFG1.ALARMRST bit after WFI command
  • 0x38011094WFI_EXIT// WFI Powerdown Exit configuration

    • [0]LDO0EN (def=0x0) // LDO0 enabled after WFI command
    • [1]LDO1EN (def=0x0) // LDO1 enabled after WFI command
    • [4]LDO0LP (def=0x0) // LDO0 in lowpower mode after WFI command
    • [5]LDO1LP (def=0x0) // LDO1 in lowpower mode after WFI command
    • [8]LDO0ULP (def=0x0) // LDO0 in ultralowpower mode after WFI command
    • [9]LDO1ULP (def=0x0) // LDO1 in ultralowpower mode after WFI command
    • [16:20]VL (def=0x0) // Lower LDO voltage value in LP/ULP mode
    • [24:28]VH (def=0x0) // Upper LDO voltage value in LP/ULP mode
    • [31]ALR (def=0x0) // Automatic alarm reset CFG1.ALARMRST bit after WFI command
  • 0x38011098WFI_DELENTR// WFI Delay Entering PD mode register

    • [0:15]VAL (def=0x0) // Value in ticks of REFCLK when entering powerdown mode
  • 0x3801109CWFI_DELEXIT// WFI Delay Exiting PD mode register

    • [0:15]VAL (def=0x0) // Value in ticks of REFCLK when exiting powerdown mode
  • 0x380110A0PMU_IRQEVT// PMU Interrupt event flag

    • [0]IRQEVT (def=0x0) // Flag automatic sets when ALARM, Tamper, WAKE events occurs. Need to clear for resetting request for
  • 0x380110A4PMU_VBATPER_FORCE// PMU vbat domain periph powerdown force register

    • [0]DACPD (def=0x0) // DAC powerdown alltime
    • [1]CMP0PD (def=0x0) // CMP0 powerdown alltime
    • [2]CMP1PD (def=0x0) // CMP1 powerdown alltime
    • [3]SRAM1LO_PD (def=0x0) // Lower 32k SRAM1 powerdown alltime
    • [4]SRAM1HI_PD (def=0x0) // Upper 32k SRAM1 powerdown alltime
    • [5]EXTOSC (def=0x0) // Stop clock generation of external crystal oscillator alltime
    • [6]INTOSC (def=0x0) // Stop clock generation of internal RC oscillator alltime
    • [16]SRAM1LO_RET (def=0x0) // Lower 32k SRAM1 in retention mode
    • [17]SRAM1HI_RET (def=0x0) // Upper 32k SRAM1 in retention mode
  • 0x380110A8PMU_VBATPER_WFI// PMU vbat domain periph powerdown WFI register

    • [0]DACPD (def=0x0) // DAC powerdown after WFI command
    • [1]CMP0PD (def=0x0) // CMP0 powerdown after WFI command
    • [2]CMP1PD (def=0x0) // CMP1 powerdown after WFI command
    • [3]SRAM1LO_PD (def=0x0) // Lower 32k SRAM1 powerdown after WFI command
    • [4]SRAM1HI_PD (def=0x0) // Upper 32k SRAM1 powerdown after WFI command
    • [5]EXTOSC (def=0x0) // Stop clock generation of external crystal oscillator after WFI command
    • [6]INTOSC (def=0x0) // Stop clock generation of internal RC oscillator after WFI command
    • [16]SRAM1LO_RET (def=0x0) // Lower 32k SRAM1 in retention mode after WFI command
    • [17]SRAM1HI_RET (def=0x0) // Upper 32k SRAM1 in retention mode after WFI command
  • 0x380110ACIWDG_CFG// IWDG Clock configuration register

    • [0:1]CLKSRC (def=0x0) // Independent watchdog clock source control
    • [8]RSTDIS (def=0x0) // Disabling reset from IWDG timer counter
  • 0x380110C0VBATRST// VBAT Reset Register

    • [0]RSTEN (def=0x0) // Reset enable
    • [16:31]KEY (def=0x0) // KEY 'C0DE' in hexadecimal for unblocking
  • 0x380110C4CPE_STAT// CPE Status Register

    • [0]CPE (def=0x0) // Status of CPE PAD latched after PowerOn vbat domain
  interrupts:
  • [31] PMURTC // PMURTC interrupt