GD32VW553x
0x40012000ADC// Analog to digital converter
0x40012000STAT// status register
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[5]ROVF (def=0x0) // Regular data register overflow
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[4]STRC (def=0x0) // Start flag of regular channel group
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[3]STIC (def=0x0) // Start flag of inserted channel group
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[2]EOIC (def=0x0) // End of inserted group conversion flag
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[1]EOC (def=0x0) // End of group conversion flag
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[0]WDE (def=0x0) // Analog watchdog event flag
0x40012004CTL0// Control register 0
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[26]ROVFIE (def=0x0) // Interrupt enable for ROVF
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[24:25]DRES (def=0x0) // ADC data resolution
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[23]RWDEN (def=0x0) // Regular channel analog watchdog enable
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[22]IWDEN (def=0x0) // Inserted channel analog watchdog enable
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[13:15]DISNUM (def=0x0) // Number of conversions in discontinuous mode
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[12]DISIC (def=0x0) // Discontinuous mode on inserted channels
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[11]DISRC (def=0x0) // Discontinuous mode on regular channels
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[10]ICA (def=0x0) // Inserted channel group convert automatically
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[9]WDSC (def=0x0) // When in scan mode, analog watchdog is effective on a single channel
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[8]SM (def=0x0) // Scan mode
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[7]EOICIE (def=0x0) // Interrupt enable for EOIC
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[6]WDEIE (def=0x0) // Interrupt enable for WDE
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[5]EOCIE (def=0x0) // Interrupt enable for EOC
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[0:4]WDCHSEL (def=0x0) // Analog watchdog channel select
0x40012008CTL1// Control register 1
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[30]SWRCST (def=0x0) // Software start on regular channel
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[28:29]ETMRC (def=0x0) // External trigger mode for regular channel
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[24:27]ETSRC (def=0x0) // External trigger select for regular channel
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[22]SWICST (def=0x0) // Software start on inserted channel
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[20:21]ETMIC (def=0x0) // External trigger mode for inserted channel
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[16:19]ETSIC (def=0x0) // External trigger select for inserted channel
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[11]DAL (def=0x0) // Data alignment
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[10]EOCM (def=0x0) // End of conversion mode
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[9]DDM (def=0x0) // DMA disable mode
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[8]DMA (def=0x0) // DMA request enable for regular channel
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[1]CTN (def=0x0) // Continuous mode
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[0]ADCON (def=0x0) // ADC ON
0x4001200CSAMPT0// Sample time register 0
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[8:11]SPT10 (def=0x0) // refer to SPT8[3:0] description
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[4:7]SPT9 (def=0x0) // refer to SPT8[3:0] description
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[0:3]SPT8 (def=0x0) // Channel sample time
0x40012010SAMPT1// Sample time register 1
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[28:31]SPT7 (def=0x0) // Refer to SPT0[3:0] description
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[24:27]SPT6 (def=0x0) // Refer to SPT0[3:0] description
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[20:23]SPT5 (def=0x0) // Refer to SPT0[3:0] description
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[16:19]SPT4 (def=0x0) // Refer to SPT0[3:0] description
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[12:15]SPT3 (def=0x0) // Refer to SPT0[3:0] description
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[8:11]SPT2 (def=0x0) // Refer to SPT0[3:0] description
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[4:7]SPT1 (def=0x0) // Refer to SPT0[3:0] description
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[0:3]SPT0 (def=0x0) // Channel sample time
0x40012014IOFF0// Inserted channel data offset register 0
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[0:11]IOFF (def=0x0) // Data offset for inserted channel x
0x40012018IOFF1// Inserted channel data offset register 1
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[0:11]IOFF (def=0x0) // Data offset for inserted channel x
0x4001201CIOFF2// Inserted channel data offset register 2
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[0:11]IOFF (def=0x0) // Data offset for inserted channel x
0x40012020IOFF3// Inserted channel data offset register 3
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[0:11]IOFF (def=0x0) // Data offset for inserted channel x
0x40012024WDHT// Watchdog high threshold register
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[0:11]WDHT (def=0xFFF) // High threshold for analog watchdog
0x40012028WDLT// Watchdog low threshold register
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[0:11]WDLT (def=0x0) // Low threshold for analog watchdog
0x4001202CRSQ0// Regular sequence register 0
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[20:23]RL (def=0x0) // Regular channel group length
0x40012030RSQ1// Regular sequence register 1
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[10:14]RSQ8 (def=0x0) // Refer to RSQ0[4:0] description
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[5:9]RSQ7 (def=0x0) // Refer to RSQ0[4:0] description
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[0:4]RSQ6 (def=0x0) // Refer to RSQ0[4:0] description
0x40012034RSQ2// Regular sequence register 2
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[25:29]RSQ5 (def=0x0) // Refer to RSQ0[4:0] description
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[20:24]RSQ4 (def=0x0) // Refer to RSQ0[4:0] description
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[15:19]RSQ3 (def=0x0) // Refer to RSQ0[4:0] description
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[10:14]RSQ2 (def=0x0) // Refer to RSQ0[4:0] description
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[5:9]RSQ1 (def=0x0) // Refer to RSQ0[4:0] description
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[0:4]RSQ0 (def=0x0) // The channel number (0
0x40012038ISQ// Inserted sequence register
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[20:21]IL (def=0x0) // Inserted channel group length
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[15:19]ISQ3 (def=0x0) // Refer to ISQ0[4:0] description
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[10:14]ISQ2 (def=0x0) // Refer to ISQ0[4:0] description
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[5:9]ISQ1 (def=0x0) // Refer to ISQ0[4:0] description
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[0:4]ISQ0 (def=0x0) // The channel number (0
0x4001203CIDATA0// Inserted data register 0
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x40012040IDATA1// Inserted data register 1
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x40012044IDATA2// Inserted data register 2
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x40012048IDATA3// Inserted data register 3
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x4001204CRDATA// Regular data register
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[0:15]RDATA (def=0x0) // Regular channel data
0x40012080OVSAMPCTL// Oversampling control register
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[9]TOVS (def=0x0) // Triggered Oversampling
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[5:8]OVSS (def=0x0) // Oversampling shift
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[2:4]OVSR (def=0x0) // Oversampling ratio
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[0]OVSEN (def=0x0) // Oversampling enable
0x40012304CCTL// Commom control register
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[23]TSVREN (def=0x0) // Channel 9 (temperature sensor) and 10 (internal reference voltage) enable of ADC
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[16:18]ADCCK (def=0x0) // ADC clock
0x4C060000CAU// Cryptographic Acceleration Unit
0x4C060000CTL// Control register
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[19]ALGM_3 (def=0x0) // Encryption / decryption algorithm mode bit 3
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[16:17]GCM_CCMPH (def=0x0) // GCM CCM phase
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[15]CAUEN (def=0x0) // CAU Enable
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[14]FFLUSH (def=0x0) // Flush FIFO
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[8:9]KEYM (def=0x0) // AES key size mode configuration, must be configured when BUSY = 0
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[6:7]DATAM (def=0x0) // Data swapping type mode configuration, must be configured when BUSY = 0
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[3:5]ALGM (def=0x0) // Encryption / decryption algorithm mode bit 0 to bit 2
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[2]CAUDIR (def=0x0) // CAU direction, must be configured when BUSY = 0
0x4C060004STAT0// Status register 0
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[4]BUSY (def=0x0) // Busy bit
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[3]OFU (def=0x0) // Output FIFO is full
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[2]ONE (def=0x0) // Output FIFO is not empty
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[1]INF (def=0x1) // Input FIFO is not full
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[0]IEM (def=0x1) // Input FIFO is empty
0x4C060008DI// Data input register
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[0:31]DI (def=0x0) // Datainput
0x4C06000CDO// Data output register
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[0:31]DO (def=0x0) // Data output
0x4C060010DMAEN// DMA enable register
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[1]DMAOEN (def=0x0) // DMA output enable
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[0]DMAIEN (def=0x0) // DMA input enable
0x4C060014INTEN// Interrupt enable register
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[1]OINTEN (def=0x0) // OUT FIFO interrupt enable
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[0]IINTEN (def=0x0) // IN FIFO interrupt enable
0x4C060018STAT1// Status register 1
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[1]OSTA (def=0x0) // OUT FIFO interrupt status
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[0]ISTA (def=0x1) // IN FIFO interrupt status
0x4C06001CINTF// Interrupt flag register
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[1]OINTF (def=0x0) // OUT FIFO enabled interrupt flag
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[0]IINTF (def=0x0) // IN FIFO enabled interrupt flag
0x4C060020KEY0H// KEY0 high register
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[0:31]KEY0H (def=0x0) // The key for DES, TDES, AES
0x4C060024KEY0L// KEY0 low register
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[0:31]KEY0L (def=0x0) // The key for DES, TDES, AES
0x4C060028KEY1H// KEY1 high register
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[0:31]KEY1H (def=0x0) // The key for DES, TDES, AES
0x4C06002CKEY1L// KEY1 low register
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[0:31]KEY1L (def=0x0) // The key for DES, TDES, AES
0x4C060030KEY2H// KEY2 high register
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[0:31]KEY2H (def=0x0) // The key for DES, TDES, AES
0x4C060034KEY2L// KEY2 low register
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[0:31]KEY2L (def=0x0) // The key for DES, TDES, AES
0x4C060038KEY3H// KEY3 high register
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[0:31]KEY3H (def=0x0) // The key for DES, TDES, AES
0x4C06003CKEY3L// KEY3 low register
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[0:31]KEY3L (def=0x0) // The key for DES, TDES, AES
0x4C060040IV0H// Initial vector registers 0 high
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[0:31]IV0H (def=0x0) // The initialization vector for DES, TDES, AES
0x4C060044IV0L// Initial vector registers 0 low
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[0:31]IV0L (def=0x0) // The initialization vector for DES, TDES, AES
0x4C060048IV1H// Initial vector registers 1 high
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[0:31]IV1H (def=0x0) // The initialization vector for DES, TDES, AES
0x4C06004CIV1L// Initial vector registers 1 low
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[0:31]IV1L (def=0x0) // The initialization vector for DES, TDES, AES
0x4C060050GCMCCMCTXS0// GCM or CCM mode context switch register 0
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060054GCMCCMCTXS1// GCM or CCM mode context switch register 1
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060058GCMCCMCTXS2// GCM or CCM mode context switch register 2
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C06005CGCMCCMCTXS3// GCM or CCM mode context switch register 3
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060060GCMCCMCTXS4// GCM or CCM mode context switch register 4
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060064GCMCCMCTXS5// GCM or CCM mode context switch register 5
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060068GCMCCMCTXS6// GCM or CCM mode context switch register 6
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C06006CGCMCCMCTXS7// GCM or CCM mode context switch register 7
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060070GCMCTXS0// GCM mode context switch register 0
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060074GCMCTXS1// GCM mode context switch register 1
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060078GCMCTXS2// GCM mode context switch register 2
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C06007CGCMCTXS3// GCM mode context switch register 3
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060080GCMCTXS4// GCM mode context switch register 4
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060084GCMCTXS5// GCM mode context switch register 5
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C060088GCMCTXS6// GCM mode context switch register 6
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0x4C06008CGCMCTXS7// GCM mode context switch register 7
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[0:31]CTXx (def=0x0) // The internal status of the CAU core
0xD1000000CPU_TIMER// cpu timer
0xD1000000MTIME_LO// mtime low register
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[0:31]COUNT (def=0x0) // MTIME count
0xD1000004MTIME_HI// mtime high register
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[0:31]COUNT (def=0x0) // MTIME count
0xD1000008MTIMECMP_LO// mtimecmp low register
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[0:31]COUNT (def=0xFFFFFFFF) // MTIMECMP count
0xD100000CMTIMECMP_HI// mtimecmp high register
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[0:31]COUNT (def=0xFFFFFFFF) // MTIMECMP count
0xD1000FF0MSFTRST// Generate soft-reset request
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[31]MSFTRST (def=0x0) // This bit is used to generate the Soft-Reset Request
0xD1000FF8MTIMECTL// Control some features of the time counter
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[2]CLKSRC (def=0x0) // Select the source of increment frequency
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[1]CMPCLREN (def=0x0) // Control the timer count to clear-to-zero or not
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[0]TIMESTOP (def=0x0) // Control the timer count or pause
0xD1000FFCMSIP// MSIP register
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[0]MSIP (def=0x0) // This bit is used to generate the software interrupt
0x40023000CRC// Cyclic redundancy checks management unit
0x40023000DATA// Data register
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[0:31]DATA (def=0xFFFFFFFF) // CRC calculation result bits
0x40023004FDATA// Free data register
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[0:7]FDATA (def=0x0) // Free Data Register bits
0x40023008CTL// Control register
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[0]RST (def=0x0) // reset the CRC_DATA register
0xE0044000DBG// Debug
0xE0044000ID// ID code register
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[0:31]ID_CODE (def=0x0) // DBG ID code register
0xE0044004CTL0// Control register 0
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[2]STB_HOLD (def=0x0) // Standby mode hold bit
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[1]DSLP_HOLD (def=0x0) // Deep-sleep mode hold bit
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[0]SLP_HOLD (def=0x0) // Sleep mode hold bit
0xE0044008CTL1// Control register 1
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[22]I2C1_HOLD (def=0x0) // I2C1 hold bit
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[21]I2C0_HOLD (def=0x0) // I2C0 hold bit
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[12]FWDGT_HOLD (def=0x0) // FWDGT hold bit
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[11]WWDGT_HOLD (def=0x0) // WWDGT hold bit
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[10]RTC_HOLD (def=0x0) // RTC hold bit
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[4]TIMER5_HOLD (def=0x0) // TIMER5 hold bit
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[1]TIMER2_HOLD (def=0x0) // TIMER2 hold bit
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[0]TIMER1_HOLD (def=0x0) // TIMER1 hold bit
0xE004400CCTL2// Control register 2
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[24]TIMER16_HOLD (def=0x0) // TIMER16 hold bit
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[23]TIMER15_HOLD (def=0x0) // TIMER15 hold bit
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[0]TIMER0_HOLD (def=0x0) // TIMER0 hold bit
0x40026000DMA// DMA controller
0x40026000INTF0// Interrupt flag register 0
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[0]FEEIF0 (def=0x0) // FIFO error and exception of channel 0
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[2]SDEIF0 (def=0x0) // Single data mode exception of channel 0
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[3]TAEIF0 (def=0x0) // Transfer access error flag of channel 0
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[4]HTFIF0 (def=0x0) // Half transfer finish flag of channel 0
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[5]FTFIF0 (def=0x0) // Full Transfer finish flag of channel 0
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[6]FEEIF1 (def=0x0) // FIFO error and exception of channel 1
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[8]SDEIF1 (def=0x0) // Single data mode exception of channel 1
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[9]TAEIF1 (def=0x0) // Transfer access error flag of channel 1
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[10]HTFIF1 (def=0x0) // Half transfer finish flag of channel 1
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[11]FTFIF1 (def=0x0) // Full Transfer finish flag of channel 1
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[16]FEEIF2 (def=0x0) // FIFO error and exception of channel 2
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[18]SDEIF2 (def=0x0) // Single data mode exception of channel 2
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[19]TAEIF2 (def=0x0) // Transfer access error flag of channel 2
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[20]HTFIF2 (def=0x0) // Half transfer finish flag of channel 2
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[21]FTFIF2 (def=0x0) // Full Transfer finish flag of channel 2
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[22]FEEIF3 (def=0x0) // FIFO error and exception of channel 3
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[24]SDEIF3 (def=0x0) // Single data mode exception of channel 3
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[25]TAEIF3 (def=0x0) // Transfer access error flag of channel 3
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[26]HTFIF3 (def=0x0) // Half transfer finish flag of channel 3
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[27]FTFIF3 (def=0x0) // Full Transfer finish flag of channel 3
0x40026004INTF1// Interrupt flag register 1
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[0]FEEIF4 (def=0x0) // FIFO error and exception of channel 4
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[2]SDEIF4 (def=0x0) // Single data mode exception of channel 4
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[3]TAEIF4 (def=0x0) // Transfer access error flag of channel 4
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[4]HTFIF4 (def=0x0) // Half transfer finish flag of channel 4
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[5]FTFIF4 (def=0x0) // Full Transfer finish flag of channel 4
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[6]FEEIF5 (def=0x0) // FIFO error and exception of channel 5
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[8]SDEIF5 (def=0x0) // Single data mode exception of channel 5
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[9]TAEIF5 (def=0x0) // Transfer access error flag of channel 5
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[10]HTFIF5 (def=0x0) // Half transfer finish flag of channel 5
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[11]FTFIF5 (def=0x0) // Full Transfer finish flag of channel 5
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[16]FEEIF6 (def=0x0) // FIFO error and exception of channel 6
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[18]SDEIF6 (def=0x0) // Single data mode exception of channel 6
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[19]TAEIF6 (def=0x0) // Transfer access error flag of channel 6
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[20]HTFIF6 (def=0x0) // Half transfer finish flag of channel 6
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[21]FTFIF6 (def=0x0) // Full Transfer finish flag of channel 6
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[22]FEEIF7 (def=0x0) // FIFO error and exception of channel 7
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[24]SDEIF7 (def=0x0) // Single data mode exception of channel 7
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[25]TAEIF7 (def=0x0) // Transfer access error flag of channel 7
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[26]HTFIF7 (def=0x0) // Half transfer finish flag of channel 7
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[27]FTFIF7 (def=0x0) // Full Transfer finish flag of channel 7
0x40026008INTC0// Interrupt flag clear register 0
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[0]FEEIFC0 (def=0x0) // Clear bit for FIFO error and exception of channel 0
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[2]SDEIFC0 (def=0x0) // Clear bit for single data mode exception of channel 0
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[3]TAEIFC0 (def=0x0) // Clear bit for transfer access error flag of channel 0
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[4]HTFIFC0 (def=0x0) // Clear bit for half transfer finish flag of channel 0
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[5]FTFIFC0 (def=0x0) // Clear bit for Full transfer finish flag of channel 0
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[6]FEEIFC1 (def=0x0) // Clear bit for FIFO error and exception of channel 1
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[8]SDEIFC1 (def=0x0) // Clear bit for single data mode exception of channel 1
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[9]TAEIFC1 (def=0x0) // Clear bit for transfer access error flag of channel 1
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[10]HTFIFC1 (def=0x0) // Clear bit for half transfer finish flag of channel 1
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[11]FTFIFC1 (def=0x0) // Clear bit for Full transfer finish flag of channel 1
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[16]FEEIFC2 (def=0x0) // Clear bit for FIFO error and exception of channel 2
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[18]SDEIFC2 (def=0x0) // Clear bit for single data mode exception of channel 2
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[19]TAEIFC2 (def=0x0) // Clear bit for transfer access error flag of channel 2
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[20]HTFIFC2 (def=0x0) // Clear bit for half transfer finish flag of channel 2
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[21]FTFIFC2 (def=0x0) // Clear bit for Full transfer finish flag of channel 2
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[22]FEEIFC3 (def=0x0) // Clear bit for FIFO error and exception of channel 3
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[24]SDEIFC3 (def=0x0) // Clear bit for single data mode exception of channel 3
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[25]TAEIFC3 (def=0x0) // Clear bit for transfer access error flag of channel 3
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[26]HTFIFC3 (def=0x0) // Clear bit for half transfer finish flag of channel 3
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[27]FTFIFC3 (def=0x0) // Clear bit for Full transfer finish flag of channel 3
0x4002600CINTC1// Interrupt flag clear register 1
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[0]FEEIFC4 (def=0x0) // Clear bit for FIFO error and exception of channel 4
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[2]SDEIFC4 (def=0x0) // Clear bit for single data mode exception of channel 4
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[3]TAEIFC4 (def=0x0) // Clear bit for transfer access error flag of channel 4
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[4]HTFIFC4 (def=0x0) // Clear bit for half transfer finish flag of channel 4
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[5]FTFIFC4 (def=0x0) // Clear bit for Full transfer finish flag of channel 4
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[6]FEEIFC5 (def=0x0) // Clear bit for FIFO error and exception of channel 5
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[8]SDEIFC5 (def=0x0) // Clear bit for single data mode exception of channel 5
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[9]TAEIFC5 (def=0x0) // Clear bit for transfer access error flag of channel 5
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[10]HTFIFC5 (def=0x0) // Clear bit for half transfer finish flag of channel 5
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[11]FTFIFC5 (def=0x0) // Clear bit for Full transfer finish flag of channel 5
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[16]FEEIFC6 (def=0x0) // Clear bit for FIFO error and exception of channel 6
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[18]SDEIFC6 (def=0x0) // Clear bit for single data mode exception of channel 6
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[19]TAEIFC6 (def=0x0) // Clear bit for transfer access error flag of channel 6
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[20]HTFIFC6 (def=0x0) // Clear bit for half transfer finish flag of channel 6
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[21]FTFIFC6 (def=0x0) // Clear bit for Full transfer finish flag of channel 6
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[22]FEEIFC7 (def=0x0) // Clear bit for FIFO error and exception of channel 7
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[24]SDEIFC7 (def=0x0) // Clear bit for single data mode exception of channel 7
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[25]TAEIFC7 (def=0x0) // Clear bit for transfer access error flag of channel 7
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[26]HTFIFC7 (def=0x0) // Clear bit for half transfer finish flag of channel 7
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[27]FTFIFC7 (def=0x0) // Clear bit for Full transfer finish flag of channel 7
0x40026010CH0CTL// Channel 0 control register
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[0]CHEN (def=0x0) // Channel enable
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[1]SDEIE (def=0x0) // Enable bit for single data mode exception interrupt
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[2]TAEIE (def=0x0) // Enable bit for tranfer access error interrupt
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[3]HTFIE (def=0x0) // Enable bit for half transfer finish interrupt
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[4]FTFIE (def=0x0) // Enable bit for full transfer finish interrupt
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[5]TFCS (def=0x0) // Transfer flow controller select
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[6:7]TM (def=0x0) // Transfer mode
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[8]CMEN (def=0x0) // Circulation mode enable
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[9]PNAGA (def=0x0) // Next address generation algorithm of peripheral
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[10]MNAGA (def=0x0) // Next address generation algorithm of memory
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[11:12]PWIDTH (def=0x0) // Transfer width of peripheral
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[13:14]MWIDTH (def=0x0) // Transfer width of memory
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[15]PAIF (def=0x0) // Peripheral address increment fixed
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[16:17]PRIO (def=0x0) // Priority level
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[18]SBMEN (def=0x0) // Switch-buffer mode enable
-
[19]MBS (def=0x0) // Memory buffer select
-
[21:22]PBURST (def=0x0) // Transfer burst type of peripheral
-
[23:24]MBURST (def=0x0) // Transfer burst type of memory
-
[25:27]PERIEN (def=0x0) // Peripheral enable
0x40026014CH0CNT// Channel 0 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40026018CH0PADDR// Channel 0 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x4002601CCH0M0ADDR// Channel 0 memory 0 base address register
-
[0:31]M0ADDR (def=0x0) // Memory 0 base address
0x40026020CH0M1ADDR// Channel 0 memory 1 base address register
-
[0:31]M1ADDR (def=0x0) // Memory 1 base address
0x40026024CH0FCTL// Channel 0 FIFO control register
-
[0:1]FCCV (def=0x0) // FIFO counter critical value
-
[2]MDMEN (def=0x0) // Multi-data mode enable
-
[3:5]FCNT (def=0x0) // FIFO counter
-
[7]FEEIE (def=0x0) // Enable bit for FIFO error and exception interrupt
0x40026028CH1CTL// Channel 1 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]SDEIE (def=0x0) // Enable bit for single data mode exception interrupt
-
[2]TAEIE (def=0x0) // Enable bit for tranfer access error interrupt
-
[3]HTFIE (def=0x0) // Enable bit for half transfer finish interrupt
-
[4]FTFIE (def=0x0) // Enable bit for full transfer finish interrupt
-
[5]TFCS (def=0x0) // Transfer flow controller select
-
[6:7]TM (def=0x0) // Transfer mode
-
[8]CMEN (def=0x0) // Circulation mode enable
-
[9]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[10]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[11:12]PWIDTH (def=0x0) // Transfer width of peripheral
-
[13:14]MWIDTH (def=0x0) // Transfer width of memory
-
[15]PAIF (def=0x0) // Peripheral address increment fixed
-
[16:17]PRIO (def=0x0) // Priority level
-
[18]SBMEN (def=0x0) // Switch-buffer mode enable
-
[19]MBS (def=0x0) // Memory buffer select
-
[21:22]PBURST (def=0x0) // Transfer burst type of peripheral
-
[23:24]MBURST (def=0x0) // Transfer burst type of memory
-
[25:27]PERIEN (def=0x0) // Peripheral enable
0x4002602CCH1CNT// Channel 1 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40026030CH1PADDR// Channel 1 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40026034CH1M0ADDR// Channel 1 memory 0 base address register
-
[0:31]M0ADDR (def=0x0) // Memory 0 base address
0x40026038CH1M1ADDR// Channel 1 memory 1 base address register
-
[0:31]M1ADDR (def=0x0) // Memory 1 base address
0x4002603CCH1FCTL// Channel 1 FIFO control register
-
[0:1]FCCV (def=0x0) // FIFO counter critical value
-
[2]MDMEN (def=0x0) // Multi-data mode enable
-
[3:5]FCNT (def=0x0) // FIFO counter
-
[7]FEEIE (def=0x0) // Enable bit for FIFO error and exception interrupt
0x40026040CH2CTL// Channel 2 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]SDEIE (def=0x0) // Enable bit for single data mode exception interrupt
-
[2]TAEIE (def=0x0) // Enable bit for tranfer access error interrupt
-
[3]HTFIE (def=0x0) // Enable bit for half transfer finish interrupt
-
[4]FTFIE (def=0x0) // Enable bit for full transfer finish interrupt
-
[5]TFCS (def=0x0) // Transfer flow controller select
-
[6:7]TM (def=0x0) // Transfer mode
-
[8]CMEN (def=0x0) // Circulation mode enable
-
[9]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[10]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[11:12]PWIDTH (def=0x0) // Transfer width of peripheral
-
[13:14]MWIDTH (def=0x0) // Transfer width of memory
-
[15]PAIF (def=0x0) // Peripheral address increment fixed
-
[16:17]PRIO (def=0x0) // Priority level
-
[18]SBMEN (def=0x0) // Switch-buffer mode enable
-
[19]MBS (def=0x0) // Memory buffer select
-
[21:22]PBURST (def=0x0) // Transfer burst type of peripheral
-
[23:24]MBURST (def=0x0) // Transfer burst type of memory
-
[25:27]PERIEN (def=0x0) // Peripheral enable
0x40026044CH2CNT// Channel 2 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40026048CH2PADDR// Channel 2 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x4002604CCH2M0ADDR// Channel 2 memory 0 base address register
-
[0:31]M0ADDR (def=0x0) // Memory 0 base address
0x40026050CH2M1ADDR// Channel 2 memory 1 base address register
-
[0:31]M1ADDR (def=0x0) // Memory 1 base address
0x40026054CH2FCTL// Channel 2 FIFO control register
-
[0:1]FCCV (def=0x0) // FIFO counter critical value
-
[2]MDMEN (def=0x0) // Multi-data mode enable
-
[3:5]FCNT (def=0x0) // FIFO counter
-
[7]FEEIE (def=0x0) // Enable bit for FIFO error and exception interrupt
0x40026058CH3CTL// Channel 3 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]SDEIE (def=0x0) // Enable bit for single data mode exception interrupt
-
[2]TAEIE (def=0x0) // Enable bit for tranfer access error interrupt
-
[3]HTFIE (def=0x0) // Enable bit for half transfer finish interrupt
-
[4]FTFIE (def=0x0) // Enable bit for full transfer finish interrupt
-
[5]TFCS (def=0x0) // Transfer flow controller select
-
[6:7]TM (def=0x0) // Transfer mode
-
[8]CMEN (def=0x0) // Circulation mode enable
-
[9]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[10]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[11:12]PWIDTH (def=0x0) // Transfer width of peripheral
-
[13:14]MWIDTH (def=0x0) // Transfer width of memory
-
[15]PAIF (def=0x0) // Peripheral address increment fixed
-
[16:17]PRIO (def=0x0) // Priority level
-
[18]SBMEN (def=0x0) // Switch-buffer mode enable
-
[19]MBS (def=0x0) // Memory buffer select
-
[21:22]PBURST (def=0x0) // Transfer burst type of peripheral
-
[23:24]MBURST (def=0x0) // Transfer burst type of memory
-
[25:27]PERIEN (def=0x0) // Peripheral enable
0x4002605CCH3CNT// Channel 3 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40026060CH3PADDR// Channel 3 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40026064CH3M0ADDR// Channel 3 memory 0 base address register
-
[0:31]M0ADDR (def=0x0) // Memory 0 base address
0x40026068CH3M1ADDR// Channel 3 memory 1 base address register
-
[0:31]M1ADDR (def=0x0) // Memory 1 base address
0x4002606CCH3FCTL// Channel 3 FIFO control register
-
[0:1]FCCV (def=0x0) // FIFO counter critical value
-
[2]MDMEN (def=0x0) // Multi-data mode enable
-
[3:5]FCNT (def=0x0) // FIFO counter
-
[7]FEEIE (def=0x0) // Enable bit for FIFO error and exception interrupt
0x40026070CH4CTL// Channel 4 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]SDEIE (def=0x0) // Enable bit for single data mode exception interrupt
-
[2]TAEIE (def=0x0) // Enable bit for tranfer access error interrupt
-
[3]HTFIE (def=0x0) // Enable bit for half transfer finish interrupt
-
[4]FTFIE (def=0x0) // Enable bit for full transfer finish interrupt
-
[5]TFCS (def=0x0) // Transfer flow controller select
-
[6:7]TM (def=0x0) // Transfer mode
-
[8]CMEN (def=0x0) // Circulation mode enable
-
[9]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[10]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[11:12]PWIDTH (def=0x0) // Transfer width of peripheral
-
[13:14]MWIDTH (def=0x0) // Transfer width of memory
-
[15]PAIF (def=0x0) // Peripheral address increment fixed
-
[16:17]PRIO (def=0x0) // Priority level
-
[18]SBMEN (def=0x0) // Switch-buffer mode enable
-
[19]MBS (def=0x0) // Memory buffer select
-
[21:22]PBURST (def=0x0) // Transfer burst type of peripheral
-
[23:24]MBURST (def=0x0) // Transfer burst type of memory
-
[25:27]PERIEN (def=0x0) // Peripheral enable
0x40026074CH4CNT// Channel 4 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40026078CH4PADDR// Channel 4 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x4002607CCH4M0ADDR// Channel 4 memory 0 base address register
-
[0:31]M0ADDR (def=0x0) // Memory 0 base address
0x40026080CH4M1ADDR// Channel 4 memory 1 base address register
-
[0:31]M1ADDR (def=0x0) // Memory 1 base address
0x40026084CH4FCTL// Channel 4 FIFO control register
-
[0:1]FCCV (def=0x0) // FIFO counter critical value
-
[2]MDMEN (def=0x0) // Multi-data mode enable
-
[3:5]FCNT (def=0x0) // FIFO counter
-
[7]FEEIE (def=0x0) // Enable bit for FIFO error and exception interrupt
0x40026088CH5CTL// Channel 5 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]SDEIE (def=0x0) // Enable bit for single data mode exception interrupt
-
[2]TAEIE (def=0x0) // Enable bit for tranfer access error interrupt
-
[3]HTFIE (def=0x0) // Enable bit for half transfer finish interrupt
-
[4]FTFIE (def=0x0) // Enable bit for full transfer finish interrupt
-
[5]TFCS (def=0x0) // Transfer flow controller select
-
[6:7]TM (def=0x0) // Transfer mode
-
[8]CMEN (def=0x0) // Circulation mode enable
-
[9]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[10]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[11:12]PWIDTH (def=0x0) // Transfer width of peripheral
-
[13:14]MWIDTH (def=0x0) // Transfer width of memory
-
[15]PAIF (def=0x0) // Peripheral address increment fixed
-
[16:17]PRIO (def=0x0) // Priority level
-
[18]SBMEN (def=0x0) // Switch-buffer mode enable
-
[19]MBS (def=0x0) // Memory buffer select
-
[21:22]PBURST (def=0x0) // Transfer burst type of peripheral
-
[23:24]MBURST (def=0x0) // Transfer burst type of memory
-
[25:27]PERIEN (def=0x0) // Peripheral enable
0x4002608CCH5CNT// Channel 5 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40026090CH5PADDR// Channel 5 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40026094CH5M0ADDR// Channel 5 memory 0 base address register
-
[0:31]M0ADDR (def=0x0) // Memory 0 base address
0x40026098CH5M1ADDR// Channel 5 memory 1 base address register
-
[0:31]M1ADDR (def=0x0) // Memory 1 base address
0x4002609CCH5FCTL// Channel 5 FIFO control register
-
[0:1]FCCV (def=0x0) // FIFO counter critical value
-
[2]MDMEN (def=0x0) // Multi-data mode enable
-
[3:5]FCNT (def=0x0) // FIFO counter
-
[7]FEEIE (def=0x0) // Enable bit for FIFO error and exception interrupt
0x400260A0CH6CTL// Channel 6 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]SDEIE (def=0x0) // Enable bit for single data mode exception interrupt
-
[2]TAEIE (def=0x0) // Enable bit for tranfer access error interrupt
-
[3]HTFIE (def=0x0) // Enable bit for half transfer finish interrupt
-
[4]FTFIE (def=0x0) // Enable bit for full transfer finish interrupt
-
[5]TFCS (def=0x0) // Transfer flow controller select
-
[6:7]TM (def=0x0) // Transfer mode
-
[8]CMEN (def=0x0) // Circulation mode enable
-
[9]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[10]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[11:12]PWIDTH (def=0x0) // Transfer width of peripheral
-
[13:14]MWIDTH (def=0x0) // Transfer width of memory
-
[15]PAIF (def=0x0) // Peripheral address increment fixed
-
[16:17]PRIO (def=0x0) // Priority level
-
[18]SBMEN (def=0x0) // Switch-buffer mode enable
-
[19]MBS (def=0x0) // Memory buffer select
-
[21:22]PBURST (def=0x0) // Transfer burst type of peripheral
-
[23:24]MBURST (def=0x0) // Transfer burst type of memory
-
[25:27]PERIEN (def=0x0) // Peripheral enable
0x400260A4CH6CNT// Channel 6 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x400260A8CH6PADDR// Channel 6 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x400260ACCH6M0ADDR// Channel 6 memory 0 base address register
-
[0:31]M0ADDR (def=0x0) // Memory 0 base address
0x400260B0CH6M1ADDR// Channel 6 memory 1 base address register
-
[0:31]M1ADDR (def=0x0) // Memory 1 base address
0x400260B4CH6FCTL// Channel 6 FIFO control register
-
[0:1]FCCV (def=0x0) // FIFO counter critical value
-
[2]MDMEN (def=0x0) // Multi-data mode enable
-
[3:5]FCNT (def=0x0) // FIFO counter
-
[7]FEEIE (def=0x0) // Enable bit for FIFO error and exception interrupt
0x400260B8CH7CTL// Channel 7 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]SDEIE (def=0x0) // Enable bit for single data mode exception interrupt
-
[2]TAEIE (def=0x0) // Enable bit for tranfer access error interrupt
-
[3]HTFIE (def=0x0) // Enable bit for half transfer finish interrupt
-
[4]FTFIE (def=0x0) // Enable bit for full transfer finish interrupt
-
[5]TFCS (def=0x0) // Transfer flow controller select
-
[6:7]TM (def=0x0) // Transfer mode
-
[8]CMEN (def=0x0) // Circulation mode enable
-
[9]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[10]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[11:12]PWIDTH (def=0x0) // Transfer width of peripheral
-
[13:14]MWIDTH (def=0x0) // Transfer width of memory
-
[15]PAIF (def=0x0) // Peripheral address increment fixed
-
[16:17]PRIO (def=0x0) // Priority level
-
[18]SBMEN (def=0x0) // Switch-buffer mode enable
-
[19]MBS (def=0x0) // Memory buffer select
-
[21:22]PBURST (def=0x0) // Transfer burst type of peripheral
-
[23:24]MBURST (def=0x0) // Transfer burst type of memory
-
[25:27]PERIEN (def=0x0) // Peripheral enable
0x400260BCCH7CNT// Channel 7 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x400260C0CH7PADDR// Channel 7 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x400260C4CH7M0ADDR// Channel 7 memory 0 base address register
-
[0:31]M0ADDR (def=0x0) // Memory 0 base address
0x400260C8CH7M1ADDR// Channel 7 memory 1 base address register
-
[0:31]M1ADDR (def=0x0) // Memory 1 base address
0x400260CCCH7FCTL// Channel 7 FIFO control register
-
[0:1]FCCV (def=0x0) // FIFO counter critical value
-
[2]MDMEN (def=0x0) // Multi-data mode enable
-
[3:5]FCNT (def=0x0) // FIFO counter
-
[7]FEEIE (def=0x0) // Enable bit for FIFO error and exception interrupt
- [30] DMA_Channel0 //
- [31] DMA_Channel1 //
- [32] DMA_Channel2 //
- [33] DMA_Channel3 //
- [34] DMA_Channel4 //
- [35] DMA_Channel5 //
- [36] DMA_Channel6 //
- [37] DMA_Channel7 //
0xD2000000ECLIC// Enhanced Core Local Interrupt Controller
0xD2000000CLICCFG// cliccfg Register
-
[1:4]NLBITS (def=0x0) // NLBITS
0xD2000004CLICINFO// clicinfo Register
-
[0:12]NUM_INTERRUPT (def=0x0) // NUM_INTERRUPT
-
[13:20]VERSION (def=0x0) // VERSION
-
[21:24]CLICINTCTLBITS (def=0x0) // CLICINTCTLBITS
0xD200000BMTH// MTH Register
-
[0:7]MTH (def=0x0) // MTH
0xD2001000CLICINTIP_0// clicintip Register
0xD2001004CLICINTIP_1// clicintip Register
0xD2001008CLICINTIP_2// clicintip Register
0xD200100CCLICINTIP_3// clicintip Register
0xD2001010CLICINTIP_4// clicintip Register
0xD2001014CLICINTIP_5// clicintip Register
0xD2001018CLICINTIP_6// clicintip Register
0xD200101CCLICINTIP_7// clicintip Register
0xD2001020CLICINTIP_8// clicintip Register
0xD2001024CLICINTIP_9// clicintip Register
0xD2001028CLICINTIP_10// clicintip Register
0xD200102CCLICINTIP_11// clicintip Register
0xD2001030CLICINTIP_12// clicintip Register
0xD2001034CLICINTIP_13// clicintip Register
0xD2001038CLICINTIP_14// clicintip Register
0xD200103CCLICINTIP_15// clicintip Register
0xD2001040CLICINTIP_16// clicintip Register
0xD2001044CLICINTIP_17// clicintip Register
0xD2001048CLICINTIP_18// clicintip Register
0xD200104CCLICINTIP_19// clicintip Register
0xD2001050CLICINTIP_20// clicintip Register
0xD2001054CLICINTIP_21// clicintip Register
0xD2001058CLICINTIP_22// clicintip Register
0xD200105CCLICINTIP_23// clicintip Register
0xD2001060CLICINTIP_24// clicintip Register
0xD2001064CLICINTIP_25// clicintip Register
0xD2001068CLICINTIP_26// clicintip Register
0xD200106CCLICINTIP_27// clicintip Register
0xD2001070CLICINTIP_28// clicintip Register
0xD2001074CLICINTIP_29// clicintip Register
0xD2001078CLICINTIP_30// clicintip Register
0xD200107CCLICINTIP_31// clicintip Register
0xD2001080CLICINTIP_32// clicintip Register
0xD2001084CLICINTIP_33// clicintip Register
0xD2001088CLICINTIP_34// clicintip Register
0xD200108CCLICINTIP_35// clicintip Register
0xD2001090CLICINTIP_36// clicintip Register
0xD2001094CLICINTIP_37// clicintip Register
0xD2001098CLICINTIP_38// clicintip Register
0xD200109CCLICINTIP_39// clicintip Register
0xD20010A0CLICINTIP_40// clicintip Register
0xD20010A4CLICINTIP_41// clicintip Register
0xD20010A8CLICINTIP_42// clicintip Register
0xD20010ACCLICINTIP_43// clicintip Register
0xD20010B0CLICINTIP_44// clicintip Register
0xD20010B4CLICINTIP_45// clicintip Register
0xD20010B8CLICINTIP_46// clicintip Register
0xD20010BCCLICINTIP_47// clicintip Register
0xD20010C0CLICINTIP_48// clicintip Register
0xD20010C4CLICINTIP_49// clicintip Register
0xD20010C8CLICINTIP_50// clicintip Register
0xD20010CCCLICINTIP_51// clicintip Register
0xD20010D0CLICINTIP_52// clicintip Register
0xD20010D4CLICINTIP_53// clicintip Register
0xD20010D8CLICINTIP_54// clicintip Register
0xD20010DCCLICINTIP_55// clicintip Register
0xD20010E0CLICINTIP_56// clicintip Register
0xD20010E4CLICINTIP_57// clicintip Register
0xD20010E8CLICINTIP_58// clicintip Register
0xD20010ECCLICINTIP_59// clicintip Register
0xD20010F0CLICINTIP_60// clicintip Register
0xD20010F4CLICINTIP_61// clicintip Register
0xD20010F8CLICINTIP_62// clicintip Register
0xD20010FCCLICINTIP_63// clicintip Register
0xD2001100CLICINTIP_64// clicintip Register
0xD2001104CLICINTIP_65// clicintip Register
0xD2001108CLICINTIP_66// clicintip Register
0xD200110CCLICINTIP_67// clicintip Register
0xD2001110CLICINTIP_68// clicintip Register
0xD2001114CLICINTIP_69// clicintip Register
0xD2001118CLICINTIP_70// clicintip Register
0xD200111CCLICINTIP_71// clicintip Register
0xD2001120CLICINTIP_72// clicintip Register
0xD2001124CLICINTIP_73// clicintip Register
0xD2001128CLICINTIP_74// clicintip Register
0xD200112CCLICINTIP_75// clicintip Register
0xD2001130CLICINTIP_76// clicintip Register
0xD2001134CLICINTIP_77// clicintip Register
0xD2001138CLICINTIP_78// clicintip Register
0xD200113CCLICINTIP_79// clicintip Register
0xD2001140CLICINTIP_80// clicintip Register
0xD2001144CLICINTIP_81// clicintip Register
0xD2001148CLICINTIP_82// clicintip Register
0xD200114CCLICINTIP_83// clicintip Register
0xD2001150CLICINTIP_84// clicintip Register
0xD2001154CLICINTIP_85// clicintip Register
0xD2001158CLICINTIP_86// clicintip Register
0xD200115CCLICINTIP_87// clicintip Register
0xD2001160CLICINTIP_88// clicintip Register
0xD2001164CLICINTIP_89// clicintip Register
0xD2001168CLICINTIP_90// clicintip Register
0xD200116CCLICINTIP_91// clicintip Register
0xD2001170CLICINTIP_92// clicintip Register
0xD2001174CLICINTIP_93// clicintip Register
0xD2001178CLICINTIP_94// clicintip Register
0xD200117CCLICINTIP_95// clicintip Register
0xD2001180CLICINTIP_96// clicintip Register
0xD2001184CLICINTIP_97// clicintip Register
0xD2001188CLICINTIP_98// clicintip Register
0xD200118CCLICINTIP_99// clicintip Register
0xD2001190CLICINTIP_100// clicintip Register
0xD2001194CLICINTIP_101// clicintip Register
0xD2001198CLICINTIP_102// clicintip Register
0xD200119CCLICINTIP_103// clicintip Register
0xD20011A0CLICINTIP_104// clicintip Register
0xD20011A4CLICINTIP_105// clicintip Register
0xD20011A8CLICINTIP_106// clicintip Register
0xD20011ACCLICINTIP_107// clicintip Register
0xD20011B0CLICINTIP_108// clicintip Register
0xD20011B4CLICINTIP_109// clicintip Register
0xD20011B8CLICINTIP_110// clicintip Register
0xD20011BCCLICINTIP_111// clicintip Register
0xD20011C0CLICINTIP_112// clicintip Register
0xD20011C4CLICINTIP_113// clicintip Register
0xD20011C8CLICINTIP_114// clicintip Register
0xD20011CCCLICINTIP_115// clicintip Register
0xD2001001CLICINTIE_0// clicintie Register
0xD2001005CLICINTIE_1// clicintie Register
0xD2001009CLICINTIE_2// clicintie Register
0xD200100DCLICINTIE_3// clicintie Register
0xD2001011CLICINTIE_4// clicintie Register
0xD2001015CLICINTIE_5// clicintie Register
0xD2001019CLICINTIE_6// clicintie Register
0xD200101DCLICINTIE_7// clicintie Register
0xD2001021CLICINTIE_8// clicintie Register
0xD2001025CLICINTIE_9// clicintie Register
0xD2001029CLICINTIE_10// clicintie Register
0xD200102DCLICINTIE_11// clicintie Register
0xD2001031CLICINTIE_12// clicintie Register
0xD2001035CLICINTIE_13// clicintie Register
0xD2001039CLICINTIE_14// clicintie Register
0xD200103DCLICINTIE_15// clicintie Register
0xD2001041CLICINTIE_16// clicintie Register
0xD2001045CLICINTIE_17// clicintie Register
0xD2001049CLICINTIE_18// clicintie Register
0xD200104DCLICINTIE_19// clicintie Register
0xD2001051CLICINTIE_20// clicintie Register
0xD2001055CLICINTIE_21// clicintie Register
0xD2001059CLICINTIE_22// clicintie Register
0xD200105DCLICINTIE_23// clicintie Register
0xD2001061CLICINTIE_24// clicintie Register
0xD2001065CLICINTIE_25// clicintie Register
0xD2001069CLICINTIE_26// clicintie Register
0xD200106DCLICINTIE_27// clicintie Register
0xD2001071CLICINTIE_28// clicintie Register
0xD2001075CLICINTIE_29// clicintie Register
0xD2001079CLICINTIE_30// clicintie Register
0xD200107DCLICINTIE_31// clicintie Register
0xD2001081CLICINTIE_32// clicintie Register
0xD2001085CLICINTIE_33// clicintie Register
0xD2001089CLICINTIE_34// clicintie Register
0xD200108DCLICINTIE_35// clicintie Register
0xD2001091CLICINTIE_36// clicintie Register
0xD2001095CLICINTIE_37// clicintie Register
0xD2001099CLICINTIE_38// clicintie Register
0xD200109DCLICINTIE_39// clicintie Register
0xD20010A1CLICINTIE_40// clicintie Register
0xD20010A5CLICINTIE_41// clicintie Register
0xD20010A9CLICINTIE_42// clicintie Register
0xD20010ADCLICINTIE_43// clicintie Register
0xD20010B1CLICINTIE_44// clicintie Register
0xD20010B5CLICINTIE_45// clicintie Register
0xD20010B9CLICINTIE_46// clicintie Register
0xD20010BDCLICINTIE_47// clicintie Register
0xD20010C1CLICINTIE_48// clicintie Register
0xD20010C5CLICINTIE_49// clicintie Register
0xD20010C9CLICINTIE_50// clicintie Register
0xD20010CDCLICINTIE_51// clicintie Register
0xD20010D1CLICINTIE_52// clicintie Register
0xD20010D5CLICINTIE_53// clicintie Register
0xD20010D9CLICINTIE_54// clicintie Register
0xD20010DDCLICINTIE_55// clicintie Register
0xD20010E1CLICINTIE_56// clicintie Register
0xD20010E5CLICINTIE_57// clicintie Register
0xD20010E9CLICINTIE_58// clicintie Register
0xD20010EDCLICINTIE_59// clicintie Register
0xD20010F1CLICINTIE_60// clicintie Register
0xD20010F5CLICINTIE_61// clicintie Register
0xD20010F9CLICINTIE_62// clicintie Register
0xD20010FDCLICINTIE_63// clicintie Register
0xD2001101CLICINTIE_64// clicintie Register
0xD2001105CLICINTIE_65// clicintie Register
0xD2001109CLICINTIE_66// clicintie Register
0xD200110DCLICINTIE_67// clicintie Register
0xD2001111CLICINTIE_68// clicintie Register
0xD2001115CLICINTIE_69// clicintie Register
0xD2001119CLICINTIE_70// clicintie Register
0xD200111DCLICINTIE_71// clicintie Register
0xD2001121CLICINTIE_72// clicintie Register
0xD2001125CLICINTIE_73// clicintie Register
0xD2001129CLICINTIE_74// clicintie Register
0xD200112DCLICINTIE_75// clicintie Register
0xD2001131CLICINTIE_76// clicintie Register
0xD2001135CLICINTIE_77// clicintie Register
0xD2001139CLICINTIE_78// clicintie Register
0xD200113DCLICINTIE_79// clicintie Register
0xD2001141CLICINTIE_80// clicintie Register
0xD2001145CLICINTIE_81// clicintie Register
0xD2001149CLICINTIE_82// clicintie Register
0xD200114DCLICINTIE_83// clicintie Register
0xD2001151CLICINTIE_84// clicintie Register
0xD2001155CLICINTIE_85// clicintie Register
0xD2001159CLICINTIE_86// clicintie Register
0xD200115DCLICINTIE_87// clicintie Register
0xD2001161CLICINTIE_88// clicintie Register
0xD2001165CLICINTIE_89// clicintie Register
0xD2001169CLICINTIE_90// clicintie Register
0xD200116DCLICINTIE_91// clicintie Register
0xD2001171CLICINTIE_92// clicintie Register
0xD2001175CLICINTIE_93// clicintie Register
0xD2001179CLICINTIE_94// clicintie Register
0xD200117DCLICINTIE_95// clicintie Register
0xD2001181CLICINTIE_96// clicintie Register
0xD2001185CLICINTIE_97// clicintie Register
0xD2001189CLICINTIE_98// clicintie Register
0xD200118DCLICINTIE_99// clicintie Register
0xD2001191CLICINTIE_100// clicintie Register
0xD2001195CLICINTIE_101// clicintie Register
0xD2001199CLICINTIE_102// clicintie Register
0xD200119DCLICINTIE_103// clicintie Register
0xD20011A1CLICINTIE_104// clicintie Register
0xD20011A5CLICINTIE_105// clicintie Register
0xD20011A9CLICINTIE_106// clicintie Register
0xD20011ADCLICINTIE_107// clicintie Register
0xD20011B1CLICINTIE_108// clicintie Register
0xD20011B5CLICINTIE_109// clicintie Register
0xD20011B9CLICINTIE_110// clicintie Register
0xD20011BDCLICINTIE_111// clicintie Register
0xD20011C1CLICINTIE_112// clicintie Register
0xD20011C5CLICINTIE_113// clicintie Register
0xD20011C9CLICINTIE_114// clicintie Register
0xD20011CDCLICINTIE_115// clicintie Register
0xD2001002CLICINTATTR_0// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001006CLICINTATTR_1// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200100ACLICINTATTR_2// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200100ECLICINTATTR_3// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001012CLICINTATTR_4// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001016CLICINTATTR_5// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200101ACLICINTATTR_6// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200101ECLICINTATTR_7// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001022CLICINTATTR_8// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001026CLICINTATTR_9// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200102ACLICINTATTR_10// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200102ECLICINTATTR_11// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001032CLICINTATTR_12// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001036CLICINTATTR_13// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200103ACLICINTATTR_14// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200103ECLICINTATTR_15// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001042CLICINTATTR_16// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001046CLICINTATTR_17// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200104ACLICINTATTR_18// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200104ECLICINTATTR_19// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001052CLICINTATTR_20// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001056CLICINTATTR_21// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200105ACLICINTATTR_22// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200105ECLICINTATTR_23// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001062CLICINTATTR_24// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001066CLICINTATTR_25// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200106ACLICINTATTR_26// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200106ECLICINTATTR_27// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001072CLICINTATTR_28// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001076CLICINTATTR_29// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200107ACLICINTATTR_30// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200107ECLICINTATTR_31// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001082CLICINTATTR_32// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001086CLICINTATTR_33// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200108ACLICINTATTR_34// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200108ECLICINTATTR_35// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001092CLICINTATTR_36// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001096CLICINTATTR_37// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200109ACLICINTATTR_38// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200109ECLICINTATTR_39// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010A2CLICINTATTR_40// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010A6CLICINTATTR_41// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010AACLICINTATTR_42// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010AECLICINTATTR_43// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010B2CLICINTATTR_44// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010B6CLICINTATTR_45// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010BACLICINTATTR_46// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010BECLICINTATTR_47// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010C2CLICINTATTR_48// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010C6CLICINTATTR_49// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010CACLICINTATTR_50// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010CECLICINTATTR_51// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010D2CLICINTATTR_52// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010D6CLICINTATTR_53// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010DACLICINTATTR_54// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010DECLICINTATTR_55// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010E2CLICINTATTR_56// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010E6CLICINTATTR_57// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010EACLICINTATTR_58// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010EECLICINTATTR_59// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010F2CLICINTATTR_60// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010F6CLICINTATTR_61// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010FACLICINTATTR_62// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010FECLICINTATTR_63// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001102CLICINTATTR_64// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001106CLICINTATTR_65// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200110ACLICINTATTR_66// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200110ECLICINTATTR_67// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001112CLICINTATTR_68// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001116CLICINTATTR_69// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200111ACLICINTATTR_70// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200111ECLICINTATTR_71// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001122CLICINTATTR_72// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001126CLICINTATTR_73// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200112ACLICINTATTR_74// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200112ECLICINTATTR_75// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001132CLICINTATTR_76// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001136CLICINTATTR_77// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200113ACLICINTATTR_78// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200113ECLICINTATTR_79// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001142CLICINTATTR_80// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001146CLICINTATTR_81// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200114ACLICINTATTR_82// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200114ECLICINTATTR_83// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001152CLICINTATTR_84// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001156CLICINTATTR_85// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200115ACLICINTATTR_86// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200115ECLICINTATTR_87// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001162CLICINTATTR_88// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001166CLICINTATTR_89// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200116ACLICINTATTR_90// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200116ECLICINTATTR_91// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001172CLICINTATTR_92// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001176CLICINTATTR_93// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200117ACLICINTATTR_94// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200117ECLICINTATTR_95// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001182CLICINTATTR_96// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001186CLICINTATTR_97// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200118ACLICINTATTR_98// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200118ECLICINTATTR_99// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001192CLICINTATTR_100// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001196CLICINTATTR_101// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200119ACLICINTATTR_102// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200119ECLICINTATTR_103// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011A2CLICINTATTR_104// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011A6CLICINTATTR_105// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011AACLICINTATTR_106// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011AECLICINTATTR_107// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011B2CLICINTATTR_108// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011B6CLICINTATTR_109// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011BACLICINTATTR_110// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011BECLICINTATTR_111// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011C2CLICINTATTR_112// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011C6CLICINTATTR_113// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011CACLICINTATTR_114// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20011CECLICINTATTR_115// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001003CLICINTCTL_0// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001007CLICINTCTL_1// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200100BCLICINTCTL_2// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200100FCLICINTCTL_3// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001013CLICINTCTL_4// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001017CLICINTCTL_5// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200101BCLICINTCTL_6// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200101FCLICINTCTL_7// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001023CLICINTCTL_8// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001027CLICINTCTL_9// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200102BCLICINTCTL_10// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200102FCLICINTCTL_11// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001033CLICINTCTL_12// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001037CLICINTCTL_13// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200103BCLICINTCTL_14// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200103FCLICINTCTL_15// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001043CLICINTCTL_16// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001047CLICINTCTL_17// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200104BCLICINTCTL_18// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200104FCLICINTCTL_19// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001053CLICINTCTL_20// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001057CLICINTCTL_21// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200105BCLICINTCTL_22// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200105FCLICINTCTL_23// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001063CLICINTCTL_24// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001067CLICINTCTL_25// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200106BCLICINTCTL_26// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200106FCLICINTCTL_27// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001073CLICINTCTL_28// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001077CLICINTCTL_29// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200107BCLICINTCTL_30// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200107FCLICINTCTL_31// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001083CLICINTCTL_32// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001087CLICINTCTL_33// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200108BCLICINTCTL_34// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200108FCLICINTCTL_35// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001093CLICINTCTL_36// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001097CLICINTCTL_37// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200109BCLICINTCTL_38// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200109FCLICINTCTL_39// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010A3CLICINTCTL_40// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010A7CLICINTCTL_41// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010ABCLICINTCTL_42// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010AFCLICINTCTL_43// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010B3CLICINTCTL_44// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010B7CLICINTCTL_45// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010BBCLICINTCTL_46// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010BFCLICINTCTL_47// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010C3CLICINTCTL_48// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010C7CLICINTCTL_49// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010CBCLICINTCTL_50// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010CFCLICINTCTL_51// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010D3CLICINTCTL_52// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010D7CLICINTCTL_53// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010DBCLICINTCTL_54// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010DFCLICINTCTL_55// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010E3CLICINTCTL_56// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010E7CLICINTCTL_57// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010EBCLICINTCTL_58// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010EFCLICINTCTL_59// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010F3CLICINTCTL_60// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010F7CLICINTCTL_61// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010FBCLICINTCTL_62// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010FFCLICINTCTL_63// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001103CLICINTCTL_64// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001107CLICINTCTL_65// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200110BCLICINTCTL_66// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200110FCLICINTCTL_67// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001113CLICINTCTL_68// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001117CLICINTCTL_69// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200111BCLICINTCTL_70// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200111FCLICINTCTL_71// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001123CLICINTCTL_72// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001127CLICINTCTL_73// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200112BCLICINTCTL_74// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200112FCLICINTCTL_75// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001133CLICINTCTL_76// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001137CLICINTCTL_77// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200113BCLICINTCTL_78// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200113FCLICINTCTL_79// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001143CLICINTCTL_80// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001147CLICINTCTL_81// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200114BCLICINTCTL_82// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200114FCLICINTCTL_83// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001153CLICINTCTL_84// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001157CLICINTCTL_85// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200115BCLICINTCTL_86// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200115FCLICINTCTL_87// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001163CLICINTCTL_88// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001167CLICINTCTL_89// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200116BCLICINTCTL_90// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200116FCLICINTCTL_91// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001173CLICINTCTL_92// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001177CLICINTCTL_93// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200117BCLICINTCTL_94// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200117FCLICINTCTL_95// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001183CLICINTCTL_96// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001187CLICINTCTL_97// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200118BCLICINTCTL_98// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200118FCLICINTCTL_99// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001193CLICINTCTL_100// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001197CLICINTCTL_101// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200119BCLICINTCTL_102// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200119FCLICINTCTL_103// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011A3CLICINTCTL_104// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011A7CLICINTCTL_105// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011ABCLICINTCTL_106// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011AFCLICINTCTL_107// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011B3CLICINTCTL_108// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011B7CLICINTCTL_109// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011BBCLICINTCTL_110// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011BFCLICINTCTL_111// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011C3CLICINTCTL_112// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011C7CLICINTCTL_113// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011CBCLICINTCTL_114// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20011CFCLICINTCTL_115// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0x40022800EFUSE// Electronic fuse
0x40022800CS// Control and status register
-
[26]OVBERIC (def=0x0) // Clear bit for overstep boundary error interrupt flag
-
[25]RDIC (def=0x0) // Clear bit for read operation completed interrupt flag
-
[24]PGIC (def=0x0) // Clear bit for program operation completed interrupt flag
-
[22]OVBERIE (def=0x0) // Enable bit for overstep boundary error interrupt
-
[21]RDIE (def=0x0) // Enable bit for read operation completed interrupt
-
[20]PGIE (def=0x0) // Enable bit for program operation completed interrupt
-
[18]OVBERIF (def=0x0) // Overstep boundary error flag
-
[17]RDIF (def=0x0) // Read operation complete flag
-
[16]PGIF (def=0x0) // Program operation completed flag
-
[1]EFRW (def=0x0) // The selection of Efuse operation
-
[0]EFSTR (def=0x0) // Start Efuse operation
0x40022804ADDR// Address register
-
[8:13]EFSIZE (def=0x0) // Read or write Efuse data size
-
[0:6]EFADDR (def=0x0) // Read or write Efuse data start address
0x40022808CTL0// Control register 0
-
[5]SWBOOT0 (def=0x0) // Efuse BOOT0 bit enable
-
[4]EFBOOT0 (def=0x0) // Efuse BOOT0
-
[3]SWBOOT1 (def=0x0) // Efuse BOOT1 bit enable
-
[2]EFBOOT1 (def=0x0) // Efuse BOOT1
-
[1]EFBOOTLK (def=0x0) // EFUSE_CTL0 register bits[5:2] lock bit
-
[0]EFSB (def=0x0) // Startup from secure boot
0x4002280CCTL1// Control register 1
-
[7]VFCERT (def=0x0) // Verify firmware certificate
-
[6]VFIMG (def=0x0) // Verify firmware image
-
[3]OBLK (def=0x0) // Option bytes lock bit
-
[2]ROTLK (def=0x0) // EFUSE_ROTPK_KEY register lock bit
-
[1]NDBG (def=0x0) // Debugging permission setting
0x40022810FPCTL// Flash protection control register
-
[0:2]FP (def=0x0) // Efuse flash protection value
0x40022814USERCTL// User byte control register
-
[6]UDLK (def=0x0) // EFUSE_USER_DATA register lock bit
-
[5]AESEN (def=0x0) // Lock EFUSE_AES_KEY register and enable AES decrypt function
-
[3]EFOPLK (def=0x0) // EFUSE_FPCTL and EFUSE_USERCTL register lock bit
-
[1]LOGUART (def=0x1) // Secure Boot Log UART selection
-
[0]SBCLK (def=0x0) // Secure boot clock source selection
0x40022818RES0// EFUSE reserved register 0
-
[0:31]RES (def=0x0) // Efuse reserved bytes
0x4002281CRES1// EFUSE reserved register 1
-
[0:31]RES (def=0x0) // Efuse reserved bytes
0x40022820RES2// EFUSE reserved register 2
-
[0:31]RES (def=0x0) // Efuse reserved bytes
0x40022824AESKEY0// Firmware AES key register 0
-
[0:31]AESKEY (def=0x0) // Efuse AES key value
0x40022828AESKEY1// Firmware AES key register 1
-
[0:31]AESKEY (def=0x0) // Efuse AES key value
0x4002282CAESKEY2// Firmware AES key register 2
-
[0:31]AESKEY (def=0x0) // Efuse AES key value
0x40022830AESKEY3// Firmware AES key register 3
-
[0:31]AESKEY (def=0x0) // Efuse AES key value
0x40022834ROTPKKEY0// RoTPK key register 0
-
[0:31]RKEY (def=0x0) // Efuse RoTPK or its HASH value
0x40022838ROTPKKEY1// RoTPK key register 1
-
[0:31]RKEY (def=0x0) // Efuse RoTPK or its HASH value
0x4002283CROTPKKEY2// RoTPK key register 2
-
[0:31]RKEY (def=0x0) // Efuse RoTPK or its HASH value
0x40022840ROTPKKEY3// RoTPK key register 3
-
[0:31]RKEY (def=0x0) // Efuse RoTPK or its HASH value
0x40022844ROTPKKEY4// RoTPK key register 4
-
[0:31]RKEY (def=0x0) // Efuse RoTPK or its HASH value
0x40022848ROTPKKEY5// RoTPK key register 5
-
[0:31]RKEY (def=0x0) // Efuse RoTPK or its HASH value
0x4002284CROTPKKEY6// RoTPK key register 6
-
[0:31]RKEY (def=0x0) // Efuse RoTPK or its HASH value
0x40022850ROTPKKEY7// RoTPK key register 7
-
[0:31]RKEY (def=0x0) // Efuse RoTPK or its HASH value
0x40022854PUID0// Product UID register 0
-
[0:31]UID (def=0x0) // Efuse MCU UID value
0x40022858PUID1// Product UID register 1
-
[0:31]UID (def=0x0) // Efuse MCU UID value
0x4002285CPUID2// Product UID register 2
-
[0:31]UID (def=0x0) // Efuse MCU UID value
0x40022860PUID3// Product UID register 3
-
[0:31]UID (def=0x0) // Efuse MCU UID value
0x40022864HUKKEY0// HUK key register 0
-
[0:31]HKEY (def=0x0) // Efuse HUK key value
0x40022868HUKKEY1// HUK key register 1
-
[0:31]HKEY (def=0x0) // Efuse HUK key value
0x4002286CHUKKEY2// HUK key register 2
-
[0:31]HKEY (def=0x0) // Efuse HUK key value
0x40022870HUKKEY3// HUK key register 3
-
[0:31]HKEY (def=0x0) // Efuse HUK key value
0x40022874USER_DATA0// User data register 0
-
[0:31]USERDATA (def=0x0) // Efuse USER_DATA value
0x40022878USER_DATA1// User data register 1
-
[0:31]USERDATA (def=0x0) // Efuse USER_DATA value
0x4002287CUSER_DATA2// User data register 2
-
[0:31]USERDATA (def=0x0) // Efuse USER_DATA value
0x40022880USER_DATA3// User data register 3
-
[0:31]USERDATA (def=0x0) // Efuse USER_DATA value
0x40022884USER_DATA4// User data register 4
-
[0:31]USERDATA (def=0x0) // Efuse USER_DATA value
0x40022888USER_DATA5// User data register 5
-
[0:31]USERDATA (def=0x0) // Efuse USER_DATA value
0x4002288CUSER_DATA6// User data register 6
-
[0:31]USERDATA (def=0x0) // Efuse USER_DATA value
0x40022890USER_DATA7// User data register 7
-
[0:31]USERDATA (def=0x0) // Efuse USER_DATA value
0x40022924BOOTADDR// Boot address register
-
[0:31]BOOTADDR (def=0x0) // Boot from the address
0x40013C00EXTI// External interrupt/event controller
0x40013C00INTEN// Interrupt enable register (EXTI_INTEN)
-
[0]INTEN0 (def=0x0) // Enable Interrupt on line 0
-
[1]INTEN1 (def=0x0) // Enable Interrupt on line 1
-
[2]INTEN2 (def=0x0) // Enable Interrupt on line 2
-
[3]INTEN3 (def=0x0) // Enable Interrupt on line 3
-
[4]INTEN4 (def=0x0) // Enable Interrupt on line 4
-
[5]INTEN5 (def=0x0) // Enable Interrupt on line 5
-
[6]INTEN6 (def=0x0) // Enable Interrupt on line 6
-
[7]INTEN7 (def=0x0) // Enable Interrupt on line 7
-
[8]INTEN8 (def=0x0) // Enable Interrupt on line 8
-
[9]INTEN9 (def=0x0) // Enable Interrupt on line 9
-
[10]INTEN10 (def=0x0) // Enable Interrupt on line 10
-
[11]INTEN11 (def=0x0) // Enable Interrupt on line 11
-
[12]INTEN12 (def=0x0) // Enable Interrupt on line 12
-
[13]INTEN13 (def=0x0) // Enable Interrupt on line 13
-
[14]INTEN14 (def=0x0) // Enable Interrupt on line 14
-
[15]INTEN15 (def=0x0) // Enable Interrupt on line 15
-
[16]INTEN16 (def=0x0) // Enable Interrupt on line 16
-
[17]INTEN17 (def=0x0) // Enable Interrupt on line 17
-
[19]INTEN19 (def=0x0) // Enable Interrupt on line 19
-
[20]INTEN20 (def=0x0) // Enable Interrupt on line 20
-
[21]INTEN21 (def=0x0) // Enable Interrupt on line 21
-
[22]INTEN22 (def=0x0) // Enable Interrupt on line 22
-
[23]INTEN23 (def=0x0) // Enable Interrupt on line 23
-
[24]INTEN24 (def=0x0) // Enable Interrupt on line 24
-
[25]INTEN25 (def=0x0) // Enable Interrupt on line 25
0x40013C04EVEN// Event enable register (EXTI_EVEN)
-
[0]EVEN0 (def=0x0) // Enable Event on line 0
-
[1]EVEN1 (def=0x0) // Enable Event on line 1
-
[2]EVEN2 (def=0x0) // Enable Event on line 2
-
[3]EVEN3 (def=0x0) // Enable Event on line 3
-
[4]EVEN4 (def=0x0) // Enable Event on line 4
-
[5]EVEN5 (def=0x0) // Enable Event on line 5
-
[6]EVEN6 (def=0x0) // Enable Event on line 6
-
[7]EVEN7 (def=0x0) // Enable Event on line 7
-
[8]EVEN8 (def=0x0) // Enable Event on line 8
-
[9]EVEN9 (def=0x0) // Enable Event on line 9
-
[10]EVEN10 (def=0x0) // Enable Event on line 10
-
[11]EVEN11 (def=0x0) // Enable Event on line 11
-
[12]EVEN12 (def=0x0) // Enable Event on line 12
-
[13]EVEN13 (def=0x0) // Enable Event on line 13
-
[14]EVEN14 (def=0x0) // Enable Event on line 14
-
[15]EVEN15 (def=0x0) // Enable Event on line 15
-
[16]EVEN16 (def=0x0) // Enable Event on line 16
-
[17]EVEN17 (def=0x0) // Enable Event on line 17
-
[19]EVEN19 (def=0x0) // Enable Event on line 19
-
[20]EVEN20 (def=0x0) // Enable Event on line 20
-
[21]EVEN21 (def=0x0) // Enable Event on line 21
-
[22]EVEN22 (def=0x0) // Enable Event on line 22
-
[23]EVEN23 (def=0x0) // Enable Event on line 23
-
[24]EVEN24 (def=0x0) // Enable Event on line 24
-
[25]EVEN25 (def=0x0) // Enable Event on line 25
0x40013C08RTEN// Rising Edge Trigger Enable register (EXTI_RTEN)
-
[0]RTEN0 (def=0x0) // Rising edge trigger enable of line 0
-
[1]RTEN1 (def=0x0) // Rising edge trigger enable of line 1
-
[2]RTEN2 (def=0x0) // Rising edge trigger enable of line 2
-
[3]RTEN3 (def=0x0) // Rising edge trigger enable of line 3
-
[4]RTEN4 (def=0x0) // Rising edge trigger enable of line 4
-
[5]RTEN5 (def=0x0) // Rising edge trigger enable of line 5
-
[6]RTEN6 (def=0x0) // Rising edge trigger enable of line 6
-
[7]RTEN7 (def=0x0) // Rising edge trigger enable of line 7
-
[8]RTEN8 (def=0x0) // Rising edge trigger enable of line 8
-
[9]RTEN9 (def=0x0) // Rising edge trigger enable of line 9
-
[10]RTEN10 (def=0x0) // Rising edge trigger enable of line 10
-
[11]RTEN11 (def=0x0) // Rising edge trigger enable of line 11
-
[12]RTEN12 (def=0x0) // Rising edge trigger enable of line 12
-
[13]RTEN13 (def=0x0) // Rising edge trigger enable of line 13
-
[14]RTEN14 (def=0x0) // Rising edge trigger enable of line 14
-
[15]RTEN15 (def=0x0) // Rising edge trigger enable of line 15
-
[16]RTEN16 (def=0x0) // Rising edge trigger enable of line 16
-
[17]RTEN17 (def=0x0) // Rising edge trigger enable of line 17
-
[19]RTEN19 (def=0x0) // Rising edge trigger enable of line 19
-
[20]RTEN20 (def=0x0) // Rising edge trigger enable of line 20
-
[21]RTEN21 (def=0x0) // Rising edge trigger enable of line 21
-
[22]RTEN22 (def=0x0) // Rising edge trigger enable of line 22
-
[23]RTEN23 (def=0x0) // Rising edge trigger enable of line 23
-
[24]RTEN24 (def=0x0) // Rising edge trigger enable of line 24
-
[25]RTEN25 (def=0x0) // Rising edge trigger enable of line 25
0x40013C0CFTEN// Falling Egde Trigger Enable register (EXTI_FTEN)
-
[0]FTEN0 (def=0x0) // Falling edge trigger enable of line 0
-
[1]FTEN1 (def=0x0) // Falling edge trigger enable of line 1
-
[2]FTEN2 (def=0x0) // Falling edge trigger enable of line 2
-
[3]FTEN3 (def=0x0) // Falling edge trigger enable of line 3
-
[4]FTEN4 (def=0x0) // Falling edge trigger enable of line 4
-
[5]FTEN5 (def=0x0) // Falling edge trigger enable of line 5
-
[6]FTEN6 (def=0x0) // Falling edge trigger enable of line 6
-
[7]FTEN7 (def=0x0) // Falling edge trigger enable of line 7
-
[8]FTEN8 (def=0x0) // Falling edge trigger enable of line 8
-
[9]FTEN9 (def=0x0) // Falling edge trigger enable of line 9
-
[10]FTEN10 (def=0x0) // Falling edge trigger enable of line 10
-
[11]FTEN11 (def=0x0) // Falling edge trigger enable of line 11
-
[12]FTEN12 (def=0x0) // Falling edge trigger enable of line 12
-
[13]FTEN13 (def=0x0) // Falling edge trigger enable of line 13
-
[14]FTEN14 (def=0x0) // Falling edge trigger enable of line 14
-
[15]FTEN15 (def=0x0) // Falling edge trigger enable of line 15
-
[16]FTEN16 (def=0x0) // Falling edge trigger enable of line 16
-
[17]FTEN17 (def=0x0) // Falling edge trigger enable of line 17
-
[19]FTEN19 (def=0x0) // Falling edge trigger enable of line 19
-
[20]FTEN20 (def=0x0) // Falling edge trigger enable of line 20
-
[21]FTEN21 (def=0x0) // Falling edge trigger enable of line 21
-
[22]FTEN22 (def=0x0) // Falling edge trigger enable of line 22
-
[23]FTEN23 (def=0x0) // Falling edge trigger enable of line 23
-
[24]FTEN24 (def=0x0) // Falling edge trigger enable of line 24
-
[25]FTEN25 (def=0x0) // Falling edge trigger enable of line 25
0x40013C10SWIEV// Software interrupt event register (EXTI_SWIEV)
-
[0]SWIEV0 (def=0x0) // Interrupt/Event software trigger on line 0
-
[1]SWIEV1 (def=0x0) // Interrupt/Event software trigger on line 1
-
[2]SWIEV2 (def=0x0) // Interrupt/Event software trigger on line 2
-
[3]SWIEV3 (def=0x0) // Interrupt/Event software trigger on line 3
-
[4]SWIEV4 (def=0x0) // Interrupt/Event software trigger on line 4
-
[5]SWIEV5 (def=0x0) // Interrupt/Event software trigger on line 5
-
[6]SWIEV6 (def=0x0) // Interrupt/Event software trigger on line 6
-
[7]SWIEV7 (def=0x0) // Interrupt/Event software trigger on line 7
-
[8]SWIEV8 (def=0x0) // Interrupt/Event software trigger on line 8
-
[9]SWIEV9 (def=0x0) // Interrupt/Event software trigger on line 9
-
[10]SWIEV10 (def=0x0) // Interrupt/Event software trigger on line 10
-
[11]SWIEV11 (def=0x0) // Interrupt/Event software trigger on line 11
-
[12]SWIEV12 (def=0x0) // Interrupt/Event software trigger on line 12
-
[13]SWIEV13 (def=0x0) // Interrupt/Event software trigger on line 13
-
[14]SWIEV14 (def=0x0) // Interrupt/Event software trigger on line 14
-
[15]SWIEV15 (def=0x0) // Interrupt/Event software trigger on line 15
-
[16]SWIEV16 (def=0x0) // Interrupt/Event software trigger on line 16
-
[17]SWIEV17 (def=0x0) // Interrupt/Event software trigger on line 17
-
[19]SWIEV19 (def=0x0) // Interrupt/Event software trigger on line 19
-
[20]SWIEV20 (def=0x0) // Interrupt/Event software trigger on line 20
-
[21]SWIEV21 (def=0x0) // Interrupt/Event software trigger on line 21
-
[22]SWIEV22 (def=0x0) // Interrupt/Event software trigger on line 22
-
[23]SWIEV23 (def=0x0) // Interrupt/Event software trigger on line 23
-
[24]SWIEV24 (def=0x0) // Interrupt/Event software trigger on line 24
-
[25]SWIEV25 (def=0x0) // Interrupt/Event software trigger on line 25
0x40013C14PD// Pending register (EXTI_PD)
-
[0]PD0 (def=0x0) // Interrupt pending status of line 0
-
[1]PD1 (def=0x0) // Interrupt pending status of line 1
-
[2]PD2 (def=0x0) // Interrupt pending status of line 2
-
[3]PD3 (def=0x0) // Interrupt pending status of line 3
-
[4]PD4 (def=0x0) // Interrupt pending status of line 4
-
[5]PD5 (def=0x0) // Interrupt pending status of line 5
-
[6]PD6 (def=0x0) // Interrupt pending status of line 6
-
[7]PD7 (def=0x0) // Interrupt pending status of line 7
-
[8]PD8 (def=0x0) // Interrupt pending status of line 8
-
[9]PD9 (def=0x0) // Interrupt pending status of line 9
-
[10]PD10 (def=0x0) // Interrupt pending status of line 10
-
[11]PD11 (def=0x0) // Interrupt pending status of line 11
-
[12]PD12 (def=0x0) // Interrupt pending status of line 12
-
[13]PD13 (def=0x0) // Interrupt pending status of line 13
-
[14]PD14 (def=0x0) // Interrupt pending status of line 14
-
[15]PD15 (def=0x0) // Interrupt pending status of line 15
-
[16]PD16 (def=0x0) // Interrupt pending status of line 16
-
[17]PD17 (def=0x0) // Interrupt pending status of line 17
-
[19]PD19 (def=0x0) // Interrupt pending status of line 19
-
[20]PD20 (def=0x0) // Interrupt pending status of line 20
-
[21]PD21 (def=0x0) // Interrupt pending status of line 21
-
[22]PD22 (def=0x0) // Interrupt pending status of line 22
-
[23]PD23 (def=0x0) // Interrupt pending status of line 23
-
[24]PD24 (def=0x0) // Interrupt pending status of line 24
-
[25]PD25 (def=0x0) // Interrupt pending status of line 25
- [25] EXTI_Line0 //
- [26] EXTI_Line1 //
- [27] EXTI_Line2 //
- [28] EXTI_Line3 //
- [29] EXTI_Line4 //
- [42] EXTI_line9_5 //
- [59] EXTI_line15_10 //
- [20] LVD //
- [20] LVD //
- [84] WIFI_Wakeup //
- [85] BLE_Wakeup //
- [86] PLF_Wakeup //
0x40022000FMC// Flash memory controller
0x40022004KEY// Unlock key register
-
[0:31]KEY (def=0x0) // FMC_CTL unlock register
0x40022008OBKEY// Option byte unlock key register
-
[0:31]OBKEY (def=0x0) // These bits are only be written by software
0x4002200CSTAT// Status register
-
[5]ENDF (def=0x0) // End of operation flag bit
-
[4]WPERR (def=0x0) // Erase / Program protection error flag bit
-
[0]BUSY (def=0x0) // The flash is busy bit
0x40022010CTL// Control register
-
[15]OBRLD (def=0x0) // Option byte reload bit
-
[14]OBSTART (def=0x0) // Option bytes modification start bit
-
[12]ENDIE (def=0x0) // End of operation interrupt enable bit
-
[10]ERRIE (def=0x0) // Error interrupt enable bit
-
[9]OBWEN (def=0x0) // FMC option byte registers write enable bit
-
[7]LK (def=0x1) // FMC_CTL lock bit
-
[6]START (def=0x0) // Send erase command to FMC
-
[3]WTPG (def=0x0) // WIFI trim program command bit
-
[2]MER (def=0x0) // Main flash mass erase command bit
-
[1]PER (def=0x0) // Main flash page erase command bit
-
[0]PG (def=0x0) // Main flash program command bit
0x40022014ADDR// Address register
-
[0:31]ADDR (def=0x0) // Flash erase / program command address bits
0x4002201COBSTAT// Option byte status register
-
[2]WP (def=0x0) // Write/erase protection state, EFFUSE config 32k write protection
-
[1]SPC (def=0x0) // Security protection level 1 state
0x40022040OBR// Option byte register
-
[12]SRAM1_RST (def=0x0) // SRAM1 reset enable bit
-
[11]NRST_STOP (def=0x0) // Vcore domain Stop entry reset option status bit
-
[10]NRST_STDBY (def=0x0) // Vcore domain Standby entry reset option status bit
-
[9]NWDG_HW (def=0x0) // IWDG option byte
-
[0:7]SPC (def=0x0) // Option byte security protection value
0x40022044OBUSER// Option byte user value register
-
[0:31]USER (def=0x0) // Option byte USER value
0x40022048OBWRP0// Option byte write protection area register 0
-
[16:25]WRP0_EPAGE (def=0x0) // End page of write protection area 0
-
[0:9]WRP0_SPAGE (def=0x0) // Start page of write protection area 0
0x4002204COBWRP1// Option byte write protection area register 1
-
[16:25]WRP1_EPAGE (def=0x0) // End page of write protection area 1
-
[0:9]WRP1_SPAGE (def=0x0) // Start page of write protection area 1
0x40022070NODEC0// NO RTDEC region register 0
-
[16:25]NODEC0_EPAGE (def=0x0) // End page of NODEC region 0
-
[0:9]NODEC0_SPAGE (def=0x3FF) // Start page of NODEC region 0
0x40022074NODEC1// NO RTDEC region register 1
-
[16:25]NODEC1_EPAGE (def=0x0) // End page of NODEC region 1
-
[0:9]NODEC1_SPAGE (def=0x3FF) // Start page of NODEC region 1
0x40022078NODEC2// NO RTDEC region register 2
-
[16:25]NODEC2_EPAGE (def=0x0) // End page of NODEC region 2
-
[0:9]NODEC2_SPAGE (def=0x3FF) // Start page of NODEC region 2
0x4002207CNODEC3// NO RTDEC region register 3
-
[16:25]NODEC3_EPAGE (def=0x0) // End page of NODEC region 3
-
[0:9]NODEC3_SPAGE (def=0x3FF) // Start page of NODEC region 3
0x40022080OFRG// Offset region register
-
[16:28]OF_EPAGE (def=0x0) // End page of offset region
-
[0:12]OF_SPAGE (def=0x1FFF) // Start page of offset region
0x40022084OFVR// Offset value register
-
[0:12]OF_VALUE (def=0x0) // Offset value
0x40022100PID0// Product ID0 register
-
[0:31]PID0 (def=0x0) // Product reserved ID code register
0x40022104PID1// Product ID1 register
-
[0:31]PID1 (def=0x0) // Product reserved ID code register
0x40022108RFT0// RF Trim register 0
-
[24:31]BLETXCAL (def=0x0) // BLE transmit power calibration value
-
[16:23]WIFITXCAL (def=0x0) // WIFI transmit power calibration value
-
[8:15]THECAL (def=0x0) // Thermal meter calibration value
-
[4:7]PABIAST1 (def=0x0) // The PA bias fine tune value
-
[0:3]PABIAST0 (def=0x0) // The PA(Power Amplifier) bias coarse tune value
0x4002210CRFT1// RF Trim register 1
-
[4:7]EFUSEID (def=0x0) // The EFUSE version ID
-
[0:3]WIFIRXGCAL (def=0x0) // The WIFI receive gain calibration value
0x40022200WFT0// WIFI Trim register 0
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022204WFT1// WIFI Trim register 1
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022208WFT2// WIFI Trim register 2
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x4002220CWFT3// WIFI Trim register 3
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022210WFT4// WIFI Trim register 4
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022214WFT5// WIFI Trim register 5
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022218WFT6// WIFI Trim register 6
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x4002221CWFT7// WIFI Trim register 7
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022220WFT8// WIFI Trim register 8
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022224WFT9// WIFI Trim register 9
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022228WFT10// WIFI Trim register 10
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x4002222CWFT11// WIFI Trim register 11
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022230WFT12// WIFI Trim register 12
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022234WFT13// WIFI Trim register 13
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40022238WFT14// WIFI Trim register 14
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x4002223CWFT15// WIFI Trim register 15
-
[0:31]WIFI_TRIM (def=0x0) // After the system is reset, it is loaded from the flash
0x40003000FWDGT// free watchdog timer
0x40003000CTL// Control register
-
[0:15]CMD (def=0x0) // Key value
0x40003004PSC// Prescaler register
-
[0:2]PSC (def=0x0) // Prescaler divider
0x40003008RLD// Reload register
-
[0:11]RLD (def=0xFFF) // Free watchdog timer counter reload value
0x4000300CSTAT// Status register
-
[0]PUD (def=0x0) // Free watchdog timer prescaler value update
-
[1]RUD (def=0x0) // Free watchdog timer counter reload value update
0x40020000GPIOA// General-purpose I/Os
0x40020000CTL// GPIO port control register
-
[30:31]CTL15 (def=0x2) // Port x configuration bits (x = 15)
-
[28:29]CTL14 (def=0x2) // Port x configuration bits (x = 14)
-
[26:27]CTL13 (def=0x2) // Port x configuration bits (x = 13)
-
[24:25]CTL12 (def=0x0) // Port x configuration bits (x = 12)
-
[22:23]CTL11 (def=0x0) // Port x configuration bits (x = 11)
-
[20:21]CTL10 (def=0x0) // Port x configuration bits (x = 10)
-
[18:19]CTL9 (def=0x0) // Port x configuration bits (x = 9)
-
[16:17]CTL8 (def=0x0) // Port x configuration bits (x = 8)
-
[14:15]CTL7 (def=0x0) // Port x configuration bits (x = 7)
-
[12:13]CTL6 (def=0x0) // Port x configuration bits (x = 6 )
-
[10:11]CTL5 (def=0x0) // Port x configuration bits (x = 5)
-
[8:9]CTL4 (def=0x0) // Port x configuration bits (x = 4 )
-
[6:7]CTL3 (def=0x0) // Port x configuration bits (x = 3)
-
[4:5]CTL2 (def=0x0) // Port x configuration bits (x = 2)
-
[2:3]CTL1 (def=0x0) // Port x configuration bits (x = 1)
-
[0:1]CTL0 (def=0x0) // Port x configuration bits (x = 0)
0x40020004OMODE// GPIO port output mode register
-
[15]OM15 (def=0x0) // Port 15 output mode bit
-
[14]OM14 (def=0x0) // Port 14 output mode bit
-
[13]OM13 (def=0x0) // Port 13 output mode bit
-
[12]OM12 (def=0x0) // Port 12 output mode bit
-
[11]OM11 (def=0x0) // Port 11 output mode bit
-
[10]OM10 (def=0x0) // Port 10 output mode bit
-
[9]OM9 (def=0x0) // Port 9 output mode bit
-
[8]OM8 (def=0x0) // Port 8 output mode bit
-
[7]OM7 (def=0x0) // Port 7 output mode bit
-
[6]OM6 (def=0x0) // Port 6 output mode bit
-
[5]OM5 (def=0x0) // Port 5 output mode bit
-
[4]OM4 (def=0x0) // Port 4 output mode bit
-
[3]OM3 (def=0x0) // Port 3 output mode bit
-
[2]OM2 (def=0x0) // Port 2 output mode bit
-
[1]OM1 (def=0x0) // Port 1 output mode bit
-
[0]OM0 (def=0x0) // Port 0 output mode bit
0x40020008OSPD// GPIO port output speed register
-
[30:31]OSPD15 (def=0x0) // Port 15 output max speed bits
-
[28:29]OSPD14 (def=0x0) // Port 14 output max speed bits
-
[26:27]OSPD13 (def=0x3) // Port 13 output max speed bits
-
[24:25]OSPD12 (def=0x0) // Port 12 output max speed bits
-
[22:23]OSPD11 (def=0x0) // Port 11 output max speed bits
-
[20:21]OSPD10 (def=0x0) // Port 10 output max speed bits
-
[18:19]OSPD9 (def=0x0) // Port 9 output max speed bits
-
[16:17]OSPD8 (def=0x0) // Port 8 output max speed bits
-
[14:15]OSPD7 (def=0x0) // Port 7 output max speed bits
-
[12:13]OSPD6 (def=0x0) // Port 6 output max speed bits
-
[10:11]OSPD5 (def=0x0) // Port 5 output max speed bits
-
[8:9]OSPD4 (def=0x0) // Port 4 output max speed bits
-
[6:7]OSPD3 (def=0x0) // Port 3 output max speed bits
-
[4:5]OSPD2 (def=0x0) // Port 2 output max speed bits
-
[2:3]OSPD1 (def=0x0) // Port 1 output max speed bits
-
[0:1]OSPD0 (def=0x0) // Port 0 output max speed bits
0x4002000CPUD// GPIO port pull-up/pull-down register
-
[30:31]PUD15 (def=0x1) // Port 15 pull-up or pull-down bits
-
[28:29]PUD14 (def=0x2) // Port 14 pull-up or pull-down bits
-
[26:27]PUD13 (def=0x1) // Port 13 pull-up or pull-down bits
-
[24:25]PUD12 (def=0x0) // Port 12 pull-up or pull-down bits
-
[22:23]PUD11 (def=0x0) // Port 11 pull-up or pull-down bits
-
[20:21]PUD10 (def=0x0) // Port 10 pull-up or pull-down bits
-
[18:19]PUD9 (def=0x0) // Port 9 pull-up or pull-down bits
-
[16:17]PUD8 (def=0x0) // Port 8 pull-up or pull-down bits
-
[14:15]PUD7 (def=0x0) // Port 7 pull-up or pull-down bits
-
[12:13]PUD6 (def=0x0) // Port 6 pull-up or pull-down bits
-
[10:11]PUD5 (def=0x0) // Port 5 pull-up or pull-down bits
-
[8:9]PUD4 (def=0x0) // Port 4 pull-up or pull-down bits
-
[6:7]PUD3 (def=0x0) // Port 3 pull-up or pull-down bits
-
[4:5]PUD2 (def=0x0) // Port 2 pull-up or pull-down bits
-
[2:3]PUD1 (def=0x0) // Port 1 pull-up or pull-down bits
-
[0:1]PUD0 (def=0x0) // Port 0 pull-up or pull-down bits
0x40020010ISTAT// GPIO port input status register
-
[15]ISTAT15 (def=0x0) // Port input status (y = 15)
-
[14]ISTAT14 (def=0x0) // Port input status (y = 14)
-
[13]ISTAT13 (def=0x0) // Port input status (y = 13)
-
[12]ISTAT12 (def=0x0) // Port input status (y = 12)
-
[11]ISTAT11 (def=0x0) // Port input status (y = 11)
-
[10]ISTAT10 (def=0x0) // Port input status (y = 10)
-
[9]ISTAT9 (def=0x0) // Port input status (y = 9)
-
[8]ISTAT8 (def=0x0) // Port input status (y = 8)
-
[7]ISTAT7 (def=0x0) // Port input status (y = 7)
-
[6]ISTAT6 (def=0x0) // Port input status (y = 6)
-
[5]ISTAT5 (def=0x0) // Port input status (y = 5)
-
[4]ISTAT4 (def=0x0) // Port input status (y = 4)
-
[3]ISTAT3 (def=0x0) // Port input status (y = 3)
-
[2]ISTAT2 (def=0x0) // Port input status (y = 2)
-
[1]ISTAT1 (def=0x0) // Port input status (y = 1)
-
[0]ISTAT0 (def=0x0) // Port input status (y = 0)
0x40020014OCTL// Port output control register
-
[15]OTCL15 (def=0x0) // Pin output control(y=0..15)
-
[14]OTCL14 (def=0x0) // Pin output control(y=0..15)
-
[13]OTCL13 (def=0x0) // Pin output control(y=0..15)
-
[12]OTCL12 (def=0x0) // Pin output control(y=0..15)
-
[11]OTCL11 (def=0x0) // Pin output control(y=0..15)
-
[10]OTCL10 (def=0x0) // Pin output control(y=0..15)
-
[9]OTCL9 (def=0x0) // Pin output control(y=0..15)
-
[8]OTCL8 (def=0x0) // Pin output control(y=0..15)
-
[7]OTCL7 (def=0x0) // Pin output control(y=0..15)
-
[6]OTCL6 (def=0x0) // Pin output control(y=0..15)
-
[5]OTCL5 (def=0x0) // Pin output control(y=0..15)
-
[4]OTCL4 (def=0x0) // Pin output control(y=0..15)
-
[3]OTCL3 (def=0x0) // Pin output control(y=0..15)
-
[2]OTCL2 (def=0x0) // Pin output control(y=0..15)
-
[1]OTC1 (def=0x0) // Pin output control(y=0..15)
-
[0]OTCL0 (def=0x0) // Pin output control(y=0..15)
0x40020018BOP// GPIO port bit operate register
-
[31]CR15 (def=0x0) // Port Clear bit 15
-
[30]CR14 (def=0x0) // Port Clear bit 14
-
[29]CR13 (def=0x0) // Port Clear bit 13
-
[28]CR12 (def=0x0) // Port Clear bit 12
-
[27]CR11 (def=0x0) // Port Clear bit 11
-
[26]CR10 (def=0x0) // Port Clear bit 10
-
[25]CR9 (def=0x0) // Port Clear bit 9
-
[24]CR8 (def=0x0) // Port Clear bit 8
-
[23]CR7 (def=0x0) // Port Clear bit 7
-
[22]CR6 (def=0x0) // Port Clear bit 6
-
[21]CR5 (def=0x0) // Port Clear bit 5
-
[20]CR4 (def=0x0) // Port Clear bit 4
-
[19]CR3 (def=0x0) // Port Clear bit 3
-
[18]CR2 (def=0x0) // Port Clear bit 2
-
[17]CR1 (def=0x0) // Port Clear bit 1
-
[16]CR0 (def=0x0) // Port Clear bit 0
-
[15]BOP15 (def=0x0) // Port Set bit 15
-
[14]BOP14 (def=0x0) // Port Set bit 14
-
[13]BOP13 (def=0x0) // Port Set bit 13
-
[12]BOP12 (def=0x0) // Port Set bit 12
-
[11]BOP11 (def=0x0) // Port Set bit 11
-
[10]BOP10 (def=0x0) // Port Set bit 10
-
[9]BOP9 (def=0x0) // Port Set bit 9
-
[8]BOP8 (def=0x0) // Port Set bit 8
-
[7]BOP7 (def=0x0) // Port Set bit 7
-
[6]BOP6 (def=0x0) // Port Set bit 6
-
[5]BOP5 (def=0x0) // Port Set bit 5
-
[4]BOP4 (def=0x0) // Port Set bit 4
-
[3]BOP3 (def=0x0) // Port Set bit 3
-
[2]BOP2 (def=0x0) // Port Set bit 2
-
[1]BOP1 (def=0x0) // Port Set bit 1
-
[0]BOP0 (def=0x0) // Port Set bit 0
0x4002001CLOCK// GPIO port configuration lock register
-
[16]LKK (def=0x0) // Lock sequence key
-
[15]LK15 (def=0x0) // Port Lock bit 15
-
[14]LK14 (def=0x0) // Port Lock bit 14
-
[13]LK13 (def=0x0) // Port Lock bit 13
-
[12]LK12 (def=0x0) // Port Lock bit 12
-
[11]LK11 (def=0x0) // Port Lock bit 11
-
[10]LK10 (def=0x0) // Port Lock bit 10
-
[9]LK9 (def=0x0) // Port Lock bit 9
-
[8]LK8 (def=0x0) // Port Lock bit 8
-
[7]LK7 (def=0x0) // Port Lock bit 7
-
[6]LK6 (def=0x0) // Port Lock bit 6
-
[5]LK5 (def=0x0) // Port Lock bit 5
-
[4]LK4 (def=0x0) // Port Lock bit 4
-
[3]LK3 (def=0x0) // Port Lock bit 3
-
[2]LK2 (def=0x0) // Port Lock bit 2
-
[1]LK1 (def=0x0) // Port Lock bit 1
-
[0]LK0 (def=0x0) // Port Lock bit 0
0x40020020AFSEL0// GPIO alternate function selected register 0
-
[28:31]SEL7 (def=0x0) // Port 7 alternate function selected
-
[24:27]SEL6 (def=0x0) // Port 6 alternate function selected
-
[20:23]SEL5 (def=0x0) // Port 5 alternate function selected
-
[16:19]SEL4 (def=0x0) // Port 4 alternate function selected
-
[12:15]SEL3 (def=0x0) // Port 3 alternate function selected
-
[8:11]SEL2 (def=0x0) // Port 2 alternate function selected
-
[4:7]SEL1 (def=0x0) // Port 1 alternate function selected
-
[0:3]SEL0 (def=0x0) // Port 0 alternate function selected
0x40020024AFSEL1// GPIO alternate function selected register 1
-
[28:31]SEL15 (def=0x0) // Port 15 alternate function selected
-
[24:27]SEL14 (def=0x0) // Port 14 alternate function selected
-
[20:23]SEL13 (def=0x0) // Port 13 alternate function selected
-
[16:19]SEL12 (def=0x0) // Port 12 alternate function selected
-
[12:15]SEL11 (def=0x0) // Port 11 alternate function selected
-
[8:11]SEL10 (def=0x0) // Port 10 alternate function selected
-
[4:7]SEL9 (def=0x0) // Port 9 alternate function selected
-
[0:3]SEL8 (def=0x0) // Port 8 alternate function selected
0x40020028BC// Bit clear register
-
[0]CR0 (def=0x0) // Port cleat bit
-
[1]CR1 (def=0x0) // Port cleat bit
-
[2]CR2 (def=0x0) // Port cleat bit
-
[3]CR3 (def=0x0) // Port cleat bit
-
[4]CR4 (def=0x0) // Port cleat bit
-
[5]CR5 (def=0x0) // Port cleat bit
-
[6]CR6 (def=0x0) // Port cleat bit
-
[7]CR7 (def=0x0) // Port cleat bit
-
[8]CR8 (def=0x0) // Port cleat bit
-
[9]CR9 (def=0x0) // Port cleat bit
-
[10]CR10 (def=0x0) // Port cleat bit
-
[11]CR11 (def=0x0) // Port cleat bit
-
[12]CR12 (def=0x0) // Port cleat bit
-
[13]CR13 (def=0x0) // Port cleat bit
-
[14]CR14 (def=0x0) // Port cleat bit
-
[15]CR15 (def=0x0) // Port cleat bit
0x4002002CTG// Port bit toggle register
-
[0]TG0 (def=0x0) // Port toggle bit
-
[1]TG1 (def=0x0) // Port toggle bit
-
[2]TG2 (def=0x0) // Port toggle bit
-
[3]TG3 (def=0x0) // Port toggle bit
-
[4]TG4 (def=0x0) // Port toggle bit
-
[5]TG5 (def=0x0) // Port toggle bit
-
[6]TG6 (def=0x0) // Port toggle bit
-
[7]TG7 (def=0x0) // Port toggle bit
-
[8]TG8 (def=0x0) // Port toggle bit
-
[9]TG9 (def=0x0) // Port toggle bit
-
[10]TG10 (def=0x0) // Port toggle bit
-
[11]TG11 (def=0x0) // Port toggle bit
-
[12]TG12 (def=0x0) // Port toggle bit
-
[13]TG13 (def=0x0) // Port toggle bit
-
[14]TG14 (def=0x0) // Port toggle bit
-
[15]TG15 (def=0x0) // Port toggle bit
0x40020400GPIOB//
0x40020400CTL// GPIO port control register
-
[30:31]CTL15 (def=0x2) // Port x configuration bits (x = 15)
-
[28:29]CTL14 (def=0x2) // Port x configuration bits (x = 14)
-
[26:27]CTL13 (def=0x2) // Port x configuration bits (x = 13)
-
[24:25]CTL12 (def=0x0) // Port x configuration bits (x = 12)
-
[22:23]CTL11 (def=0x0) // Port x configuration bits (x = 11)
-
[20:21]CTL10 (def=0x0) // Port x configuration bits (x = 10)
-
[18:19]CTL9 (def=0x0) // Port x configuration bits (x = 9)
-
[16:17]CTL8 (def=0x0) // Port x configuration bits (x = 8)
-
[14:15]CTL7 (def=0x0) // Port x configuration bits (x = 7)
-
[12:13]CTL6 (def=0x0) // Port x configuration bits (x = 6 )
-
[10:11]CTL5 (def=0x0) // Port x configuration bits (x = 5)
-
[8:9]CTL4 (def=0x0) // Port x configuration bits (x = 4 )
-
[6:7]CTL3 (def=0x0) // Port x configuration bits (x = 3)
-
[4:5]CTL2 (def=0x0) // Port x configuration bits (x = 2)
-
[2:3]CTL1 (def=0x0) // Port x configuration bits (x = 1)
-
[0:1]CTL0 (def=0x0) // Port x configuration bits (x = 0)
0x40020404OMODE// GPIO port output mode register
-
[15]OM15 (def=0x0) // Port 15 output mode bit
-
[14]OM14 (def=0x0) // Port 14 output mode bit
-
[13]OM13 (def=0x0) // Port 13 output mode bit
-
[12]OM12 (def=0x0) // Port 12 output mode bit
-
[11]OM11 (def=0x0) // Port 11 output mode bit
-
[10]OM10 (def=0x0) // Port 10 output mode bit
-
[9]OM9 (def=0x0) // Port 9 output mode bit
-
[8]OM8 (def=0x0) // Port 8 output mode bit
-
[7]OM7 (def=0x0) // Port 7 output mode bit
-
[6]OM6 (def=0x0) // Port 6 output mode bit
-
[5]OM5 (def=0x0) // Port 5 output mode bit
-
[4]OM4 (def=0x0) // Port 4 output mode bit
-
[3]OM3 (def=0x0) // Port 3 output mode bit
-
[2]OM2 (def=0x0) // Port 2 output mode bit
-
[1]OM1 (def=0x0) // Port 1 output mode bit
-
[0]OM0 (def=0x0) // Port 0 output mode bit
0x40020408OSPD// GPIO port output speed register
-
[30:31]OSPD15 (def=0x0) // Port 15 output max speed bits
-
[28:29]OSPD14 (def=0x0) // Port 14 output max speed bits
-
[26:27]OSPD13 (def=0x3) // Port 13 output max speed bits
-
[24:25]OSPD12 (def=0x0) // Port 12 output max speed bits
-
[22:23]OSPD11 (def=0x0) // Port 11 output max speed bits
-
[20:21]OSPD10 (def=0x0) // Port 10 output max speed bits
-
[18:19]OSPD9 (def=0x0) // Port 9 output max speed bits
-
[16:17]OSPD8 (def=0x0) // Port 8 output max speed bits
-
[14:15]OSPD7 (def=0x0) // Port 7 output max speed bits
-
[12:13]OSPD6 (def=0x0) // Port 6 output max speed bits
-
[10:11]OSPD5 (def=0x0) // Port 5 output max speed bits
-
[8:9]OSPD4 (def=0x0) // Port 4 output max speed bits
-
[6:7]OSPD3 (def=0x0) // Port 3 output max speed bits
-
[4:5]OSPD2 (def=0x0) // Port 2 output max speed bits
-
[2:3]OSPD1 (def=0x0) // Port 1 output max speed bits
-
[0:1]OSPD0 (def=0x0) // Port 0 output max speed bits
0x4002040CPUD// GPIO port pull-up/pull-down register
-
[30:31]PUD15 (def=0x1) // Port 15 pull-up or pull-down bits
-
[28:29]PUD14 (def=0x2) // Port 14 pull-up or pull-down bits
-
[26:27]PUD13 (def=0x1) // Port 13 pull-up or pull-down bits
-
[24:25]PUD12 (def=0x0) // Port 12 pull-up or pull-down bits
-
[22:23]PUD11 (def=0x0) // Port 11 pull-up or pull-down bits
-
[20:21]PUD10 (def=0x0) // Port 10 pull-up or pull-down bits
-
[18:19]PUD9 (def=0x0) // Port 9 pull-up or pull-down bits
-
[16:17]PUD8 (def=0x0) // Port 8 pull-up or pull-down bits
-
[14:15]PUD7 (def=0x0) // Port 7 pull-up or pull-down bits
-
[12:13]PUD6 (def=0x0) // Port 6 pull-up or pull-down bits
-
[10:11]PUD5 (def=0x0) // Port 5 pull-up or pull-down bits
-
[8:9]PUD4 (def=0x0) // Port 4 pull-up or pull-down bits
-
[6:7]PUD3 (def=0x0) // Port 3 pull-up or pull-down bits
-
[4:5]PUD2 (def=0x0) // Port 2 pull-up or pull-down bits
-
[2:3]PUD1 (def=0x0) // Port 1 pull-up or pull-down bits
-
[0:1]PUD0 (def=0x0) // Port 0 pull-up or pull-down bits
0x40020410ISTAT// GPIO port input status register
-
[15]ISTAT15 (def=0x0) // Port input status (y = 15)
-
[14]ISTAT14 (def=0x0) // Port input status (y = 14)
-
[13]ISTAT13 (def=0x0) // Port input status (y = 13)
-
[12]ISTAT12 (def=0x0) // Port input status (y = 12)
-
[11]ISTAT11 (def=0x0) // Port input status (y = 11)
-
[10]ISTAT10 (def=0x0) // Port input status (y = 10)
-
[9]ISTAT9 (def=0x0) // Port input status (y = 9)
-
[8]ISTAT8 (def=0x0) // Port input status (y = 8)
-
[7]ISTAT7 (def=0x0) // Port input status (y = 7)
-
[6]ISTAT6 (def=0x0) // Port input status (y = 6)
-
[5]ISTAT5 (def=0x0) // Port input status (y = 5)
-
[4]ISTAT4 (def=0x0) // Port input status (y = 4)
-
[3]ISTAT3 (def=0x0) // Port input status (y = 3)
-
[2]ISTAT2 (def=0x0) // Port input status (y = 2)
-
[1]ISTAT1 (def=0x0) // Port input status (y = 1)
-
[0]ISTAT0 (def=0x0) // Port input status (y = 0)
0x40020414OCTL// Port output control register
-
[15]OTCL15 (def=0x0) // Pin output control(y=0..15)
-
[14]OTCL14 (def=0x0) // Pin output control(y=0..15)
-
[13]OTCL13 (def=0x0) // Pin output control(y=0..15)
-
[12]OTCL12 (def=0x0) // Pin output control(y=0..15)
-
[11]OTCL11 (def=0x0) // Pin output control(y=0..15)
-
[10]OTCL10 (def=0x0) // Pin output control(y=0..15)
-
[9]OTCL9 (def=0x0) // Pin output control(y=0..15)
-
[8]OTCL8 (def=0x0) // Pin output control(y=0..15)
-
[7]OTCL7 (def=0x0) // Pin output control(y=0..15)
-
[6]OTCL6 (def=0x0) // Pin output control(y=0..15)
-
[5]OTCL5 (def=0x0) // Pin output control(y=0..15)
-
[4]OTCL4 (def=0x0) // Pin output control(y=0..15)
-
[3]OTCL3 (def=0x0) // Pin output control(y=0..15)
-
[2]OTCL2 (def=0x0) // Pin output control(y=0..15)
-
[1]OTC1 (def=0x0) // Pin output control(y=0..15)
-
[0]OTCL0 (def=0x0) // Pin output control(y=0..15)
0x40020418BOP// GPIO port bit operate register
-
[31]CR15 (def=0x0) // Port Clear bit 15
-
[30]CR14 (def=0x0) // Port Clear bit 14
-
[29]CR13 (def=0x0) // Port Clear bit 13
-
[28]CR12 (def=0x0) // Port Clear bit 12
-
[27]CR11 (def=0x0) // Port Clear bit 11
-
[26]CR10 (def=0x0) // Port Clear bit 10
-
[25]CR9 (def=0x0) // Port Clear bit 9
-
[24]CR8 (def=0x0) // Port Clear bit 8
-
[23]CR7 (def=0x0) // Port Clear bit 7
-
[22]CR6 (def=0x0) // Port Clear bit 6
-
[21]CR5 (def=0x0) // Port Clear bit 5
-
[20]CR4 (def=0x0) // Port Clear bit 4
-
[19]CR3 (def=0x0) // Port Clear bit 3
-
[18]CR2 (def=0x0) // Port Clear bit 2
-
[17]CR1 (def=0x0) // Port Clear bit 1
-
[16]CR0 (def=0x0) // Port Clear bit 0
-
[15]BOP15 (def=0x0) // Port Set bit 15
-
[14]BOP14 (def=0x0) // Port Set bit 14
-
[13]BOP13 (def=0x0) // Port Set bit 13
-
[12]BOP12 (def=0x0) // Port Set bit 12
-
[11]BOP11 (def=0x0) // Port Set bit 11
-
[10]BOP10 (def=0x0) // Port Set bit 10
-
[9]BOP9 (def=0x0) // Port Set bit 9
-
[8]BOP8 (def=0x0) // Port Set bit 8
-
[7]BOP7 (def=0x0) // Port Set bit 7
-
[6]BOP6 (def=0x0) // Port Set bit 6
-
[5]BOP5 (def=0x0) // Port Set bit 5
-
[4]BOP4 (def=0x0) // Port Set bit 4
-
[3]BOP3 (def=0x0) // Port Set bit 3
-
[2]BOP2 (def=0x0) // Port Set bit 2
-
[1]BOP1 (def=0x0) // Port Set bit 1
-
[0]BOP0 (def=0x0) // Port Set bit 0
0x4002041CLOCK// GPIO port configuration lock register
-
[16]LKK (def=0x0) // Lock sequence key
-
[15]LK15 (def=0x0) // Port Lock bit 15
-
[14]LK14 (def=0x0) // Port Lock bit 14
-
[13]LK13 (def=0x0) // Port Lock bit 13
-
[12]LK12 (def=0x0) // Port Lock bit 12
-
[11]LK11 (def=0x0) // Port Lock bit 11
-
[10]LK10 (def=0x0) // Port Lock bit 10
-
[9]LK9 (def=0x0) // Port Lock bit 9
-
[8]LK8 (def=0x0) // Port Lock bit 8
-
[7]LK7 (def=0x0) // Port Lock bit 7
-
[6]LK6 (def=0x0) // Port Lock bit 6
-
[5]LK5 (def=0x0) // Port Lock bit 5
-
[4]LK4 (def=0x0) // Port Lock bit 4
-
[3]LK3 (def=0x0) // Port Lock bit 3
-
[2]LK2 (def=0x0) // Port Lock bit 2
-
[1]LK1 (def=0x0) // Port Lock bit 1
-
[0]LK0 (def=0x0) // Port Lock bit 0
0x40020420AFSEL0// GPIO alternate function selected register 0
-
[28:31]SEL7 (def=0x0) // Port 7 alternate function selected
-
[24:27]SEL6 (def=0x0) // Port 6 alternate function selected
-
[20:23]SEL5 (def=0x0) // Port 5 alternate function selected
-
[16:19]SEL4 (def=0x0) // Port 4 alternate function selected
-
[12:15]SEL3 (def=0x0) // Port 3 alternate function selected
-
[8:11]SEL2 (def=0x0) // Port 2 alternate function selected
-
[4:7]SEL1 (def=0x0) // Port 1 alternate function selected
-
[0:3]SEL0 (def=0x0) // Port 0 alternate function selected
0x40020424AFSEL1// GPIO alternate function selected register 1
-
[28:31]SEL15 (def=0x0) // Port 15 alternate function selected
-
[24:27]SEL14 (def=0x0) // Port 14 alternate function selected
-
[20:23]SEL13 (def=0x0) // Port 13 alternate function selected
-
[16:19]SEL12 (def=0x0) // Port 12 alternate function selected
-
[12:15]SEL11 (def=0x0) // Port 11 alternate function selected
-
[8:11]SEL10 (def=0x0) // Port 10 alternate function selected
-
[4:7]SEL9 (def=0x0) // Port 9 alternate function selected
-
[0:3]SEL8 (def=0x0) // Port 8 alternate function selected
0x40020428BC// Bit clear register
-
[0]CR0 (def=0x0) // Port cleat bit
-
[1]CR1 (def=0x0) // Port cleat bit
-
[2]CR2 (def=0x0) // Port cleat bit
-
[3]CR3 (def=0x0) // Port cleat bit
-
[4]CR4 (def=0x0) // Port cleat bit
-
[5]CR5 (def=0x0) // Port cleat bit
-
[6]CR6 (def=0x0) // Port cleat bit
-
[7]CR7 (def=0x0) // Port cleat bit
-
[8]CR8 (def=0x0) // Port cleat bit
-
[9]CR9 (def=0x0) // Port cleat bit
-
[10]CR10 (def=0x0) // Port cleat bit
-
[11]CR11 (def=0x0) // Port cleat bit
-
[12]CR12 (def=0x0) // Port cleat bit
-
[13]CR13 (def=0x0) // Port cleat bit
-
[14]CR14 (def=0x0) // Port cleat bit
-
[15]CR15 (def=0x0) // Port cleat bit
0x4002042CTG// Port bit toggle register
-
[0]TG0 (def=0x0) // Port toggle bit
-
[1]TG1 (def=0x0) // Port toggle bit
-
[2]TG2 (def=0x0) // Port toggle bit
-
[3]TG3 (def=0x0) // Port toggle bit
-
[4]TG4 (def=0x0) // Port toggle bit
-
[5]TG5 (def=0x0) // Port toggle bit
-
[6]TG6 (def=0x0) // Port toggle bit
-
[7]TG7 (def=0x0) // Port toggle bit
-
[8]TG8 (def=0x0) // Port toggle bit
-
[9]TG9 (def=0x0) // Port toggle bit
-
[10]TG10 (def=0x0) // Port toggle bit
-
[11]TG11 (def=0x0) // Port toggle bit
-
[12]TG12 (def=0x0) // Port toggle bit
-
[13]TG13 (def=0x0) // Port toggle bit
-
[14]TG14 (def=0x0) // Port toggle bit
-
[15]TG15 (def=0x0) // Port toggle bit
0x40020800GPIOC//
0x40020800CTL// GPIO port control register
-
[30:31]CTL15 (def=0x2) // Port x configuration bits (x = 15)
-
[28:29]CTL14 (def=0x2) // Port x configuration bits (x = 14)
-
[26:27]CTL13 (def=0x2) // Port x configuration bits (x = 13)
-
[24:25]CTL12 (def=0x0) // Port x configuration bits (x = 12)
-
[22:23]CTL11 (def=0x0) // Port x configuration bits (x = 11)
-
[20:21]CTL10 (def=0x0) // Port x configuration bits (x = 10)
-
[18:19]CTL9 (def=0x0) // Port x configuration bits (x = 9)
-
[16:17]CTL8 (def=0x0) // Port x configuration bits (x = 8)
-
[14:15]CTL7 (def=0x0) // Port x configuration bits (x = 7)
-
[12:13]CTL6 (def=0x0) // Port x configuration bits (x = 6 )
-
[10:11]CTL5 (def=0x0) // Port x configuration bits (x = 5)
-
[8:9]CTL4 (def=0x0) // Port x configuration bits (x = 4 )
-
[6:7]CTL3 (def=0x0) // Port x configuration bits (x = 3)
-
[4:5]CTL2 (def=0x0) // Port x configuration bits (x = 2)
-
[2:3]CTL1 (def=0x0) // Port x configuration bits (x = 1)
-
[0:1]CTL0 (def=0x0) // Port x configuration bits (x = 0)
0x40020804OMODE// GPIO port output mode register
-
[15]OM15 (def=0x0) // Port 15 output mode bit
-
[14]OM14 (def=0x0) // Port 14 output mode bit
-
[13]OM13 (def=0x0) // Port 13 output mode bit
-
[12]OM12 (def=0x0) // Port 12 output mode bit
-
[11]OM11 (def=0x0) // Port 11 output mode bit
-
[10]OM10 (def=0x0) // Port 10 output mode bit
-
[9]OM9 (def=0x0) // Port 9 output mode bit
-
[8]OM8 (def=0x0) // Port 8 output mode bit
-
[7]OM7 (def=0x0) // Port 7 output mode bit
-
[6]OM6 (def=0x0) // Port 6 output mode bit
-
[5]OM5 (def=0x0) // Port 5 output mode bit
-
[4]OM4 (def=0x0) // Port 4 output mode bit
-
[3]OM3 (def=0x0) // Port 3 output mode bit
-
[2]OM2 (def=0x0) // Port 2 output mode bit
-
[1]OM1 (def=0x0) // Port 1 output mode bit
-
[0]OM0 (def=0x0) // Port 0 output mode bit
0x40020808OSPD// GPIO port output speed register
-
[30:31]OSPD15 (def=0x0) // Port 15 output max speed bits
-
[28:29]OSPD14 (def=0x0) // Port 14 output max speed bits
-
[26:27]OSPD13 (def=0x3) // Port 13 output max speed bits
-
[24:25]OSPD12 (def=0x0) // Port 12 output max speed bits
-
[22:23]OSPD11 (def=0x0) // Port 11 output max speed bits
-
[20:21]OSPD10 (def=0x0) // Port 10 output max speed bits
-
[18:19]OSPD9 (def=0x0) // Port 9 output max speed bits
-
[16:17]OSPD8 (def=0x0) // Port 8 output max speed bits
-
[14:15]OSPD7 (def=0x0) // Port 7 output max speed bits
-
[12:13]OSPD6 (def=0x0) // Port 6 output max speed bits
-
[10:11]OSPD5 (def=0x0) // Port 5 output max speed bits
-
[8:9]OSPD4 (def=0x0) // Port 4 output max speed bits
-
[6:7]OSPD3 (def=0x0) // Port 3 output max speed bits
-
[4:5]OSPD2 (def=0x0) // Port 2 output max speed bits
-
[2:3]OSPD1 (def=0x0) // Port 1 output max speed bits
-
[0:1]OSPD0 (def=0x0) // Port 0 output max speed bits
0x4002080CPUD// GPIO port pull-up/pull-down register
-
[30:31]PUD15 (def=0x1) // Port 15 pull-up or pull-down bits
-
[28:29]PUD14 (def=0x2) // Port 14 pull-up or pull-down bits
-
[26:27]PUD13 (def=0x1) // Port 13 pull-up or pull-down bits
-
[24:25]PUD12 (def=0x0) // Port 12 pull-up or pull-down bits
-
[22:23]PUD11 (def=0x0) // Port 11 pull-up or pull-down bits
-
[20:21]PUD10 (def=0x0) // Port 10 pull-up or pull-down bits
-
[18:19]PUD9 (def=0x0) // Port 9 pull-up or pull-down bits
-
[16:17]PUD8 (def=0x0) // Port 8 pull-up or pull-down bits
-
[14:15]PUD7 (def=0x0) // Port 7 pull-up or pull-down bits
-
[12:13]PUD6 (def=0x0) // Port 6 pull-up or pull-down bits
-
[10:11]PUD5 (def=0x0) // Port 5 pull-up or pull-down bits
-
[8:9]PUD4 (def=0x0) // Port 4 pull-up or pull-down bits
-
[6:7]PUD3 (def=0x0) // Port 3 pull-up or pull-down bits
-
[4:5]PUD2 (def=0x0) // Port 2 pull-up or pull-down bits
-
[2:3]PUD1 (def=0x0) // Port 1 pull-up or pull-down bits
-
[0:1]PUD0 (def=0x0) // Port 0 pull-up or pull-down bits
0x40020810ISTAT// GPIO port input status register
-
[15]ISTAT15 (def=0x0) // Port input status (y = 15)
-
[14]ISTAT14 (def=0x0) // Port input status (y = 14)
-
[13]ISTAT13 (def=0x0) // Port input status (y = 13)
-
[12]ISTAT12 (def=0x0) // Port input status (y = 12)
-
[11]ISTAT11 (def=0x0) // Port input status (y = 11)
-
[10]ISTAT10 (def=0x0) // Port input status (y = 10)
-
[9]ISTAT9 (def=0x0) // Port input status (y = 9)
-
[8]ISTAT8 (def=0x0) // Port input status (y = 8)
-
[7]ISTAT7 (def=0x0) // Port input status (y = 7)
-
[6]ISTAT6 (def=0x0) // Port input status (y = 6)
-
[5]ISTAT5 (def=0x0) // Port input status (y = 5)
-
[4]ISTAT4 (def=0x0) // Port input status (y = 4)
-
[3]ISTAT3 (def=0x0) // Port input status (y = 3)
-
[2]ISTAT2 (def=0x0) // Port input status (y = 2)
-
[1]ISTAT1 (def=0x0) // Port input status (y = 1)
-
[0]ISTAT0 (def=0x0) // Port input status (y = 0)
0x40020814OCTL// Port output control register
-
[15]OTCL15 (def=0x0) // Pin output control(y=0..15)
-
[14]OTCL14 (def=0x0) // Pin output control(y=0..15)
-
[13]OTCL13 (def=0x0) // Pin output control(y=0..15)
-
[12]OTCL12 (def=0x0) // Pin output control(y=0..15)
-
[11]OTCL11 (def=0x0) // Pin output control(y=0..15)
-
[10]OTCL10 (def=0x0) // Pin output control(y=0..15)
-
[9]OTCL9 (def=0x0) // Pin output control(y=0..15)
-
[8]OTCL8 (def=0x0) // Pin output control(y=0..15)
-
[7]OTCL7 (def=0x0) // Pin output control(y=0..15)
-
[6]OTCL6 (def=0x0) // Pin output control(y=0..15)
-
[5]OTCL5 (def=0x0) // Pin output control(y=0..15)
-
[4]OTCL4 (def=0x0) // Pin output control(y=0..15)
-
[3]OTCL3 (def=0x0) // Pin output control(y=0..15)
-
[2]OTCL2 (def=0x0) // Pin output control(y=0..15)
-
[1]OTC1 (def=0x0) // Pin output control(y=0..15)
-
[0]OTCL0 (def=0x0) // Pin output control(y=0..15)
0x40020818BOP// GPIO port bit operate register
-
[31]CR15 (def=0x0) // Port Clear bit 15
-
[30]CR14 (def=0x0) // Port Clear bit 14
-
[29]CR13 (def=0x0) // Port Clear bit 13
-
[28]CR12 (def=0x0) // Port Clear bit 12
-
[27]CR11 (def=0x0) // Port Clear bit 11
-
[26]CR10 (def=0x0) // Port Clear bit 10
-
[25]CR9 (def=0x0) // Port Clear bit 9
-
[24]CR8 (def=0x0) // Port Clear bit 8
-
[23]CR7 (def=0x0) // Port Clear bit 7
-
[22]CR6 (def=0x0) // Port Clear bit 6
-
[21]CR5 (def=0x0) // Port Clear bit 5
-
[20]CR4 (def=0x0) // Port Clear bit 4
-
[19]CR3 (def=0x0) // Port Clear bit 3
-
[18]CR2 (def=0x0) // Port Clear bit 2
-
[17]CR1 (def=0x0) // Port Clear bit 1
-
[16]CR0 (def=0x0) // Port Clear bit 0
-
[15]BOP15 (def=0x0) // Port Set bit 15
-
[14]BOP14 (def=0x0) // Port Set bit 14
-
[13]BOP13 (def=0x0) // Port Set bit 13
-
[12]BOP12 (def=0x0) // Port Set bit 12
-
[11]BOP11 (def=0x0) // Port Set bit 11
-
[10]BOP10 (def=0x0) // Port Set bit 10
-
[9]BOP9 (def=0x0) // Port Set bit 9
-
[8]BOP8 (def=0x0) // Port Set bit 8
-
[7]BOP7 (def=0x0) // Port Set bit 7
-
[6]BOP6 (def=0x0) // Port Set bit 6
-
[5]BOP5 (def=0x0) // Port Set bit 5
-
[4]BOP4 (def=0x0) // Port Set bit 4
-
[3]BOP3 (def=0x0) // Port Set bit 3
-
[2]BOP2 (def=0x0) // Port Set bit 2
-
[1]BOP1 (def=0x0) // Port Set bit 1
-
[0]BOP0 (def=0x0) // Port Set bit 0
0x4002081CLOCK// GPIO port configuration lock register
-
[16]LKK (def=0x0) // Lock sequence key
-
[15]LK15 (def=0x0) // Port Lock bit 15
-
[14]LK14 (def=0x0) // Port Lock bit 14
-
[13]LK13 (def=0x0) // Port Lock bit 13
-
[12]LK12 (def=0x0) // Port Lock bit 12
-
[11]LK11 (def=0x0) // Port Lock bit 11
-
[10]LK10 (def=0x0) // Port Lock bit 10
-
[9]LK9 (def=0x0) // Port Lock bit 9
-
[8]LK8 (def=0x0) // Port Lock bit 8
-
[7]LK7 (def=0x0) // Port Lock bit 7
-
[6]LK6 (def=0x0) // Port Lock bit 6
-
[5]LK5 (def=0x0) // Port Lock bit 5
-
[4]LK4 (def=0x0) // Port Lock bit 4
-
[3]LK3 (def=0x0) // Port Lock bit 3
-
[2]LK2 (def=0x0) // Port Lock bit 2
-
[1]LK1 (def=0x0) // Port Lock bit 1
-
[0]LK0 (def=0x0) // Port Lock bit 0
0x40020820AFSEL0// GPIO alternate function selected register 0
-
[28:31]SEL7 (def=0x0) // Port 7 alternate function selected
-
[24:27]SEL6 (def=0x0) // Port 6 alternate function selected
-
[20:23]SEL5 (def=0x0) // Port 5 alternate function selected
-
[16:19]SEL4 (def=0x0) // Port 4 alternate function selected
-
[12:15]SEL3 (def=0x0) // Port 3 alternate function selected
-
[8:11]SEL2 (def=0x0) // Port 2 alternate function selected
-
[4:7]SEL1 (def=0x0) // Port 1 alternate function selected
-
[0:3]SEL0 (def=0x0) // Port 0 alternate function selected
0x40020824AFSEL1// GPIO alternate function selected register 1
-
[28:31]SEL15 (def=0x0) // Port 15 alternate function selected
-
[24:27]SEL14 (def=0x0) // Port 14 alternate function selected
-
[20:23]SEL13 (def=0x0) // Port 13 alternate function selected
-
[16:19]SEL12 (def=0x0) // Port 12 alternate function selected
-
[12:15]SEL11 (def=0x0) // Port 11 alternate function selected
-
[8:11]SEL10 (def=0x0) // Port 10 alternate function selected
-
[4:7]SEL9 (def=0x0) // Port 9 alternate function selected
-
[0:3]SEL8 (def=0x0) // Port 8 alternate function selected
0x40020828BC// Bit clear register
-
[0]CR0 (def=0x0) // Port cleat bit
-
[1]CR1 (def=0x0) // Port cleat bit
-
[2]CR2 (def=0x0) // Port cleat bit
-
[3]CR3 (def=0x0) // Port cleat bit
-
[4]CR4 (def=0x0) // Port cleat bit
-
[5]CR5 (def=0x0) // Port cleat bit
-
[6]CR6 (def=0x0) // Port cleat bit
-
[7]CR7 (def=0x0) // Port cleat bit
-
[8]CR8 (def=0x0) // Port cleat bit
-
[9]CR9 (def=0x0) // Port cleat bit
-
[10]CR10 (def=0x0) // Port cleat bit
-
[11]CR11 (def=0x0) // Port cleat bit
-
[12]CR12 (def=0x0) // Port cleat bit
-
[13]CR13 (def=0x0) // Port cleat bit
-
[14]CR14 (def=0x0) // Port cleat bit
-
[15]CR15 (def=0x0) // Port cleat bit
0x4002082CTG// Port bit toggle register
-
[0]TG0 (def=0x0) // Port toggle bit
-
[1]TG1 (def=0x0) // Port toggle bit
-
[2]TG2 (def=0x0) // Port toggle bit
-
[3]TG3 (def=0x0) // Port toggle bit
-
[4]TG4 (def=0x0) // Port toggle bit
-
[5]TG5 (def=0x0) // Port toggle bit
-
[6]TG6 (def=0x0) // Port toggle bit
-
[7]TG7 (def=0x0) // Port toggle bit
-
[8]TG8 (def=0x0) // Port toggle bit
-
[9]TG9 (def=0x0) // Port toggle bit
-
[10]TG10 (def=0x0) // Port toggle bit
-
[11]TG11 (def=0x0) // Port toggle bit
-
[12]TG12 (def=0x0) // Port toggle bit
-
[13]TG13 (def=0x0) // Port toggle bit
-
[14]TG14 (def=0x0) // Port toggle bit
-
[15]TG15 (def=0x0) // Port toggle bit
0x4C060400HAU// Hash Acceleration Unit
0x4C060400CTL// HAU control register
-
[18]ALGM1 (def=0x0) // Algorithm selection bit 1
-
[16]KLM (def=0x0) // Key length mode
-
[13]MDS (def=0x0) // Multiple DMA Selection
-
[12]DINE (def=0x0) // DI register not empty
-
[8:11]NWIF (def=0x0) // Number of words in the input FIFO
-
[7]ALGM0 (def=0x0) // Algorithm selection bit 0
-
[6]HMS (def=0x0) // HAU mode selection, must be changed when no computation is processing
-
[4:5]DATAM (def=0x0) // Data type mode
-
[3]DMAE (def=0x0) // DMA enable
-
[2]START (def=0x0) // Start the digest calculation
0x4C060404DI// HAU data input register
-
[0:31]DI (def=0x0) // Message data input
0x4C060408CFG// HAU configuration register
-
[8]CALEN (def=0x0) // Digest calculation enable
-
[0:4]VBL (def=0x0) // Valid bits length in the last word
0x4C06040CDO0// HAU data output register 0
-
[0:31]DO0 (def=0x0) // Messagedigest result of hash algorithm
0x4C060410DO1// HAU data output register 1
-
[0:31]DO1 (def=0x0) // Messagedigest result of hash algorithm
0x4C060414DO2// HAU data output register 2
-
[0:31]DO2 (def=0x0) // Messagedigest result of hash algorithm
0x4C060418DO3// HAU data output register 3
-
[0:31]DO3 (def=0x0) // Messagedigest result of hash algorithm
0x4C06041CDO4// HAU data output register 4
-
[0:31]DO4 (def=0x0) // Messagedigest result of hash algorithm
0x4C060724DO5// HAU data output register 5
-
[0:31]DO5 (def=0x0) // Messagedigest result of hash algorithm
0x4C060728DO6// HAU data output register 6
-
[0:31]DO6 (def=0x0) // Messagedigest result of hash algorithm
0x4C06072CDO7// HAU data output register 7
-
[0:31]DO7 (def=0x0) // Messagedigest result of hash algorithm
0x4C060420INTEN// HAU interrupt enable register
-
[1]CCIE (def=0x0) // Calculation completion interrupt enable
-
[0]DIIE (def=0x0) // Data input interrupt enable
0x4C060424STAT// HAU status and flag register
-
[3]BUSY (def=0x0) // Busy bit
-
[2]DMAS (def=0x0) // DMA status
-
[1]CCF (def=0x0) // Digest calculation completion flag
-
[0]DIF (def=0x1) // Data input flag
0x4C0604F8CTXS0// Context switch register 0
-
[0:31]CTXx (def=0x2) // The complete internal status of the HAU core
0x4C0604FCCTXS1// Context switch register 1
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060500CTXS2// Context switch register 2
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060504CTXS3// Context switch register 3
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060508CTXS4// Context switch register 4
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06050CCTXS5// Context switch register 5
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060510CTXS6// Context switch register 6
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060514CTXS7// Context switch register 7
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060518CTXS8// Context switch register 8
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06051CCTXS9// Context switch register 9
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060520CTXS10// Context switch register 10
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060524CTXS11// Context switch register 11
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060528CTXS12// Context switch register 12
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06052CCTXS13// Context switch register 13
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060530CTXS14// Context switch register 14
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060534CTXS15// Context switch register 15
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060538CTXS16// Context switch register 16
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06053CCTXS17// Context switch register 17
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060540CTXS18// Context switch register 18
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060544CTXS19// Context switch register 19
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060548CTXS20// Context switch register 20
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06054CCTXS21// Context switch register 21
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060550CTXS22// Context switch register 22
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060554CTXS23// Context switch register 23
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060558CTXS24// Context switch register 24
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06055CCTXS25// Context switch register 25
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060560CTXS26// Context switch register 26
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060564CTXS27// Context switch register 27
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060568CTXS28// Context switch register 28
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06056CCTXS29// Context switch register 29
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060570CTXS30// Context switch register 30
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060574CTXS31// Context switch register 31
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060578CTXS32// Context switch register 32
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06057CCTXS33// Context switch register 33
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060580CTXS34// Context switch register 34
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060584CTXS35// Context switch register 35
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060588CTXS36// Context switch register 36
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06058CCTXS37// Context switch register 37
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060590CTXS38// Context switch register 38
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060594CTXS39// Context switch register 39
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C060598CTXS40// Context switch register 40
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C06059CCTXS41// Context switch register 41
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605A0CTXS42// Context switch register 42
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605A4CTXS43// Context switch register 43
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605A8CTXS44// Context switch register 44
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605ACCTXS45// Context switch register 45
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605B0CTXS46// Context switch register 46
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605B4CTXS47// Context switch register 47
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605B8CTXS48// Context switch register 48
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605BCCTXS49// Context switch register 49
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605C0CTXS50// Context switch register 50
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605C4CTXS51// Context switch register 51
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605C8CTXS52// Context switch register 52
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x4C0605CCCTXS53// Context switch register 53
-
[0:31]CTXx (def=0x0) // The complete internal status of the HAU core
0x40005400I2C0// Inter-integrated circuit interface
0x40005400CTL0// Control register 0
-
[23]PECEN (def=0x0) // PEC Calculation Switch
-
[22]SMBALTEN (def=0x0) // SMBus Alert enable
-
[21]SMBDAEN (def=0x0) // SMBus device default address enable
-
[20]SMBHAEN (def=0x0) // SMBus Host address enable
-
[19]GCEN (def=0x0) // Whether or not to response to a General Call (0x00)
-
[18]WUEN (def=0x0) // Wakeup from Deep-sleep mode enable
-
[17]SS (def=0x0) // Whether to stretch SCL low when data is not ready in slave mode
-
[16]SBCTL (def=0x0) // Slave byte control
-
[15]DENR (def=0x0) // DMA enable for reception
-
[14]DENT (def=0x0) // DMA enable for transmission
-
[12]ANOFF (def=0x0) // Analog noise filter disable
-
[8:11]DNF (def=0x0) // Digital noise filter
-
[7]ERRIE (def=0x0) // Error interrupt enable
-
[6]TCIE (def=0x0) // Transfer complete interrupt enable
-
[5]STPDETIE (def=0x0) // Stop detection interrupt enable
-
[4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
-
[3]ADDMIE (def=0x0) // Address match interrupt enable in slave mode
-
[2]RBNEIE (def=0x0) // Receive interrupt enable
-
[1]TIE (def=0x0) // Transmit interrupt enable
-
[0]I2CEN (def=0x0) // I2C peripheral enable
0x40005404CTL1// Control register 1
-
[26]PECTRANS (def=0x0) // PEC Transfer
-
[25]AUTOEND (def=0x0) // Automatic end mode in master mode
-
[24]RELOAD (def=0x0) // Reload mode
-
[16:23]BYTENUM (def=0x0) // Number of bytes to be transferred
-
[15]NACKEN (def=0x0) // Generate NACK in slave mode
-
[14]STOP (def=0x0) // Generate a STOP condition on I2C bus
-
[13]START (def=0x0) // Generate a START condition on I2C bus
-
[12]HEAD10R (def=0x0) // 10-bit address header executes read direction only in master receive mode
-
[11]ADD10EN (def=0x0) // 10-bit addressing mode enable in master mode
-
[10]TRDIR (def=0x0) // Transfer direction in master mode
-
[0:9]SADDRESS (def=0x0) // Slave address to be sent
0x40005408SADDR0// Slave address register 0
-
[15]ADDRESSEN (def=0x0) // I2C address enable
-
[10]ADDFORMAT (def=0x0) // Address mode for the I2C slave
-
[8:9]ADDRESS_8_9 (def=0x0) // Highest two bits of a 10-bit address
-
[1:7]ADDRESS_1_7 (def=0x0) // 7-bit address or bits 7:1 of a 10-bit address
-
[0]ADDRESS_0 (def=0x0) // Bit 0 of a 10-bit address
0x4000540CSADDR1// Slave address register 1
-
[15]ADDRESS2EN (def=0x0) // Second I2C address enable
-
[8:10]ADDMSK2 (def=0x0) // ADDRESS2[7:1] mask
-
[1:7]ADDRESS2 (def=0x0) // Second I2C address for the slave
0x40005410TIMING// Timing register
-
[28:31]PSC (def=0x0) // Timing prescaler
-
[20:23]SCLDELY (def=0x0) // Data setup time
-
[16:19]SDADELY (def=0x0) // Data hold time
-
[8:15]SCLH (def=0x0) // SCL high period
-
[0:7]SCLL (def=0x0) // SCL low period
0x40005414TIMEOUT// Timeout register
-
[31]EXTOEN (def=0x0) // Extended clock timeout detection enable
-
[16:27]BUSTOB (def=0x0) // Bus timeout B
-
[15]TOEN (def=0x0) // Clock timeout detection enable
-
[12]TOIDLE (def=0x0) // Idle clock timeout detection
-
[0:11]BUSTOA (def=0x0) // Bus timeout A
0x40005418STAT// Status register
-
[17:23]READDR (def=0x0) // Received match address in slave mode
-
[16]TR (def=0x0) // Whether the I2C is a transmitter or a receiver in slave mode
-
[15]I2CBSY (def=0x0) // Busy flag
-
[13]SMBALT (def=0x0) // SMBus Alert
-
[12]TIMEOUT (def=0x0) // TIMEOUT flag
-
[11]PECERR (def=0x0) // PEC error
-
[10]OUERR (def=0x0) // Overrun/Underrun error in slave mode
-
[9]LOSTARB (def=0x0) // Arbitration Lost
-
[8]BERR (def=0x0) // Bus error
-
[7]TCR (def=0x0) // Transfer complete reload
-
[6]TC (def=0x0) // Transfer complete in master mode
-
[5]STPDET (def=0x0) // STOP condition detected in slave mode
-
[4]NACK (def=0x0) // Not Acknowledge flag
-
[3]ADDSEND (def=0x0) // Address received matches in slave mode
-
[2]RBNE (def=0x0) // I2C_RDATA is not empty during receiving
-
[1]TI (def=0x0) // Transmit interrupt
-
[0]TBE (def=0x1) // I2C_TDATA is empty during transmitting
0x4000541CSTATC// Status clear register
-
[13]SMBALTC (def=0x0) // SMBus Alert flag clear
-
[12]TIMEOUTC (def=0x0) // TIMEOUT flag clear
-
[11]PECERRC (def=0x0) // PEC error flag clear
-
[10]OUERRC (def=0x0) // Overrun/Underrun flag clear
-
[9]LOSTARBC (def=0x0) // Arbitration Lost flag clear
-
[8]BERRC (def=0x0) // Bus error flag clear
-
[5]STPDETC (def=0x0) // STPDET flag clear
-
[4]NACKC (def=0x0) // Not Acknowledge flag clear
-
[3]ADDSENDC (def=0x0) // ADDSEND flag clear
0x40005420PEC// Packet Error Check register
-
[0:7]PECV (def=0x0) // Packet Error Checking Value that calculated by hardware when PEC is enabled
0x40005424RDATA// Receive data register
-
[0:7]RDATA (def=0x0) // Receive data value
0x40005428TDATA// Transmit data register
-
[0:7]TDATA (def=0x0) // Transmit data value
0x40005490CTL2// Control register 2
-
[9:15]ADDM (def=0x0) // Defines which bits of ADDRESS[7:1] are compared with an incoming address byte, and which bits are i
- [50] I2C0_EV //
- [51] I2C0_ER //
- [70] I2C0_WK //
0x40005800I2C1//
0x40005800CTL0// Control register 0
-
[23]PECEN (def=0x0) // PEC Calculation Switch
-
[22]SMBALTEN (def=0x0) // SMBus Alert enable
-
[21]SMBDAEN (def=0x0) // SMBus device default address enable
-
[20]SMBHAEN (def=0x0) // SMBus Host address enable
-
[19]GCEN (def=0x0) // Whether or not to response to a General Call (0x00)
-
[18]WUEN (def=0x0) // Wakeup from Deep-sleep mode enable
-
[17]SS (def=0x0) // Whether to stretch SCL low when data is not ready in slave mode
-
[16]SBCTL (def=0x0) // Slave byte control
-
[15]DENR (def=0x0) // DMA enable for reception
-
[14]DENT (def=0x0) // DMA enable for transmission
-
[12]ANOFF (def=0x0) // Analog noise filter disable
-
[8:11]DNF (def=0x0) // Digital noise filter
-
[7]ERRIE (def=0x0) // Error interrupt enable
-
[6]TCIE (def=0x0) // Transfer complete interrupt enable
-
[5]STPDETIE (def=0x0) // Stop detection interrupt enable
-
[4]NACKIE (def=0x0) // Not acknowledge received interrupt enable
-
[3]ADDMIE (def=0x0) // Address match interrupt enable in slave mode
-
[2]RBNEIE (def=0x0) // Receive interrupt enable
-
[1]TIE (def=0x0) // Transmit interrupt enable
-
[0]I2CEN (def=0x0) // I2C peripheral enable
0x40005804CTL1// Control register 1
-
[26]PECTRANS (def=0x0) // PEC Transfer
-
[25]AUTOEND (def=0x0) // Automatic end mode in master mode
-
[24]RELOAD (def=0x0) // Reload mode
-
[16:23]BYTENUM (def=0x0) // Number of bytes to be transferred
-
[15]NACKEN (def=0x0) // Generate NACK in slave mode
-
[14]STOP (def=0x0) // Generate a STOP condition on I2C bus
-
[13]START (def=0x0) // Generate a START condition on I2C bus
-
[12]HEAD10R (def=0x0) // 10-bit address header executes read direction only in master receive mode
-
[11]ADD10EN (def=0x0) // 10-bit addressing mode enable in master mode
-
[10]TRDIR (def=0x0) // Transfer direction in master mode
-
[0:9]SADDRESS (def=0x0) // Slave address to be sent
0x40005808SADDR0// Slave address register 0
-
[15]ADDRESSEN (def=0x0) // I2C address enable
-
[10]ADDFORMAT (def=0x0) // Address mode for the I2C slave
-
[8:9]ADDRESS_8_9 (def=0x0) // Highest two bits of a 10-bit address
-
[1:7]ADDRESS_1_7 (def=0x0) // 7-bit address or bits 7:1 of a 10-bit address
-
[0]ADDRESS_0 (def=0x0) // Bit 0 of a 10-bit address
0x4000580CSADDR1// Slave address register 1
-
[15]ADDRESS2EN (def=0x0) // Second I2C address enable
-
[8:10]ADDMSK2 (def=0x0) // ADDRESS2[7:1] mask
-
[1:7]ADDRESS2 (def=0x0) // Second I2C address for the slave
0x40005810TIMING// Timing register
-
[28:31]PSC (def=0x0) // Timing prescaler
-
[20:23]SCLDELY (def=0x0) // Data setup time
-
[16:19]SDADELY (def=0x0) // Data hold time
-
[8:15]SCLH (def=0x0) // SCL high period
-
[0:7]SCLL (def=0x0) // SCL low period
0x40005814TIMEOUT// Timeout register
-
[31]EXTOEN (def=0x0) // Extended clock timeout detection enable
-
[16:27]BUSTOB (def=0x0) // Bus timeout B
-
[15]TOEN (def=0x0) // Clock timeout detection enable
-
[12]TOIDLE (def=0x0) // Idle clock timeout detection
-
[0:11]BUSTOA (def=0x0) // Bus timeout A
0x40005818STAT// Status register
-
[17:23]READDR (def=0x0) // Received match address in slave mode
-
[16]TR (def=0x0) // Whether the I2C is a transmitter or a receiver in slave mode
-
[15]I2CBSY (def=0x0) // Busy flag
-
[13]SMBALT (def=0x0) // SMBus Alert
-
[12]TIMEOUT (def=0x0) // TIMEOUT flag
-
[11]PECERR (def=0x0) // PEC error
-
[10]OUERR (def=0x0) // Overrun/Underrun error in slave mode
-
[9]LOSTARB (def=0x0) // Arbitration Lost
-
[8]BERR (def=0x0) // Bus error
-
[7]TCR (def=0x0) // Transfer complete reload
-
[6]TC (def=0x0) // Transfer complete in master mode
-
[5]STPDET (def=0x0) // STOP condition detected in slave mode
-
[4]NACK (def=0x0) // Not Acknowledge flag
-
[3]ADDSEND (def=0x0) // Address received matches in slave mode
-
[2]RBNE (def=0x0) // I2C_RDATA is not empty during receiving
-
[1]TI (def=0x0) // Transmit interrupt
-
[0]TBE (def=0x1) // I2C_TDATA is empty during transmitting
0x4000581CSTATC// Status clear register
-
[13]SMBALTC (def=0x0) // SMBus Alert flag clear
-
[12]TIMEOUTC (def=0x0) // TIMEOUT flag clear
-
[11]PECERRC (def=0x0) // PEC error flag clear
-
[10]OUERRC (def=0x0) // Overrun/Underrun flag clear
-
[9]LOSTARBC (def=0x0) // Arbitration Lost flag clear
-
[8]BERRC (def=0x0) // Bus error flag clear
-
[5]STPDETC (def=0x0) // STPDET flag clear
-
[4]NACKC (def=0x0) // Not Acknowledge flag clear
-
[3]ADDSENDC (def=0x0) // ADDSEND flag clear
0x40005820PEC// Packet Error Check register
-
[0:7]PECV (def=0x0) // Packet Error Checking Value that calculated by hardware when PEC is enabled
0x40005824RDATA// Receive data register
-
[0:7]RDATA (def=0x0) // Receive data value
0x40005828TDATA// Transmit data register
-
[0:7]TDATA (def=0x0) // Transmit data value
0x40005890CTL2// Control register 2
-
[9:15]ADDM (def=0x0) // Defines which bits of ADDRESS[7:1] are compared with an incoming address byte, and which bits are i
- [52] I2C1_EV //
- [53] I2C1_ER //
0x4C061000PKCAU// Public Key Cryptographic Acceleration Unit
0x4C061000CTL// Control register
-
[20]ADDRERRIE (def=0x0) // Address error interrupt enable
-
[19]RAMERRIE (def=0x0) // RAM error interrupt enable
-
[17]ENDIE (def=0x0) // End of operation interrupt enable
-
[8:13]MODSEL (def=0x0) // PKCAU operation mode selection
-
[1]START (def=0x0) // PKCAU starts operation
-
[0]PKCAUEN (def=0x0) // PKCAU enable
0x4C061004STAT// Status register
-
[20]ADDRERR (def=0x0) // Address error
-
[19]RAMERR (def=0x0) // PKCAU RAM error
-
[17]ENDF (def=0x0) // End of PKCAU operation
-
[16]BUSY (def=0x0) // Busy flag
0x4C061008STATC// Status clear register
-
[20]ADDRERRC (def=0x0) // Address error flag clear
-
[19]RAMERRC (def=0x0) // PKCAU RAM error flag clear
-
[17]ENDFC (def=0x0) // End of PKCAU operation flag clear
0x40007000PMU// Power management unit
0x40007000CTL0// Control register 0
-
[18:19]LDEN (def=0x0) // Low-driver mode enable in Deep-sleep mode
-
[11]LDNP (def=0x0) // Low-driver mode when use normal power LDO
-
[10]LDLP (def=0x0) // Low-driver mode when use low power LDO
-
[8]BKPWEN (def=0x0) // Backup Domain write enable
-
[5:7]LVDT (def=0x0) // Low Voltage Detector Threshold
-
[4]LVDEN (def=0x0) // Low Voltage Detector Enable
-
[3]STBRST (def=0x0) // Standby Flag Reset
-
[2]WURST (def=0x0) // Wakeup Flag Reset
-
[1]STBMOD (def=0x0) // Standby Mode
-
[0]LDOLP (def=0x0) // LDO Low Power Mode
0x40007004CS0// Control and status register 0
-
[18:19]LDRF (def=0x0) // Low-driver mode ready flag
-
[14]LDOVSRF (def=0x0) // LDO voltage select ready flag
-
[11]WUPEN3 (def=0x0) // WKUP Pin3 (PA12) Enable
-
[10]WUPEN2 (def=0x0) // WKUP Pin2 (PB2) Enable
-
[9]WUPEN1 (def=0x0) // WKUP Pin1 (PA15) Enable
-
[8]WUPEN0 (def=0x0) // WKUP Pin0 (PA2) Enable
-
[2]LVDF (def=0x0) // Low Voltage Detector Status Flag
-
[1]STBF (def=0x0) // Standby Flag
-
[0]WUF (def=0x0) // Wakeup Flag
0x40007008CTL1// Control register 1
-
[25]BLE_WAKEUP_REQ (def=0x0) // BLE wakeup request
-
[24]BLEPWAKE (def=0x0) // wakeup BLE
-
[23]BLEPSLEEP (def=0x0) // BLE go to sleep
-
[21]BLE_SRAM_RET (def=0x0) // BLE sram enter retention mode when deepsleep and BLE sleep
-
[20]SRAM0PWAKE (def=0x0) // wakeup SRAM0
-
[19]SRAM0PSLEEP (def=0x0) // SRAM0 go to sleep
-
[18]WIFI_SRAM_RET (def=0x1) // WIFI sram enter retention mode when deepsleep and WIFI sleep
-
[17]WIFI_LPDS_ON (def=0x0) // WIFI auto lpds flow on
-
[16]RETDIS (def=0x0) // No retention register when WIFI power-off
-
[14]SRAM3PWAKE (def=0x0) // wakeup SRAM3
-
[13]SRAM3PSLEEP (def=0x0) // SRAM3 go to sleep
-
[10]SRAM2PWAKE (def=0x0) // wakeup SRAM2
-
[9]SRAM2PSLEEP (def=0x0) // SRAM2 go to sleep
-
[6]SRAM1PWAKE (def=0x0) // wakeup SRAM1
-
[5]SRAM1PSLEEP (def=0x0) // SRAM1 go to sleep
-
[3]WPWAKE (def=0x0) // WIFI wakeup
-
[2]WPSLEEP (def=0x0) // WIFI go to sleep
-
[1]WPEN (def=0x1) // enable WIFI power
0x4000700CCS1// Control and status register 1
-
[17]BLEPS_ACTIVE (def=0x0) // BLE is in active state
-
[16]BLEPS_SLEEP (def=0x1) // BLE is in sleep state
-
[14]SRAM3PS_ACTIVE (def=0x1) // SRAM3 is in active state
-
[13]SRAM3PS_SLEEP (def=0x0) // SRAM3 is in sleep state
-
[10]SRAM2PS_ACTIVE (def=0x1) // SRAM2 is in active state
-
[9]SRAM2PS_SLEEP (def=0x0) // SRAM2 is in sleep state
-
[8]SRAM0PS_ACTIVE (def=0x1) // SRAM0 is in active state
-
[7]SRAM0PS_SLEEP (def=0x0) // SRAM0 is in sleep state
-
[6]SRAM1PS_ACTIVE (def=0x1) // SRAM1 is in active state
-
[5]SRAM1PS_SLEEP (def=0x0) // SRAM1 is in sleep state
-
[4]BLE_POWER_STATE (def=0x1) // BLE power status
-
[3]WPS_ACTIVE (def=0x0) // WIFI is in active state
-
[2]WPS_SLEEP (def=0x1) // WIFI is in sleep state
0x40007010PAR0// Parameter register 0
-
[31]TWKEN (def=0x0) // Wakeup time of WIFI_OFF domain
-
[16:20]TSW_IRCCNT (def=0xA) // When enter deep-sleep, switch to IRC16M clock. Wait the IRC16M COUNTER
-
[8:15]TWK_WL (def=0x20) // Use software value when wake up WIFI_OFF or not
0x40007014PAR1// Parameter register 1
-
[31]TWKSRAM3EN (def=0x0) // Use software value when wake up SRAM3 or not
-
[30]TWKSRAM2EN (def=0x0) // Use software value when wake up SRAM2 or not
-
[29]TWKSRAM1EN (def=0x0) // Use software value when wake up SRAM1 or not
-
[16:23]TWK_SRAM3 (def=0x0) // Wakeup time of SRAM3 domain
-
[8:15]TWK_SRAM2 (def=0x20) // Wakeup time of SRAM2 domain
-
[0:7]TWK_SRAM1 (def=0x20) // Wakeup time of SRAM1 domain
0x40007018PAR2// Parameter register 2
-
[31]TWKBLEEN (def=0x0) // Use software value when wake up BLE or not
-
[30]TWKSRAM0EN (def=0x0) // Use software value when wake up SRAM0 or not
-
[8:15]TWK_BLE (def=0x20) // Wakeup time of BLE domain
-
[0:7]TWK_SRAM0 (def=0x20) // Wakeup time of SRAM0 domain
0x40007020RFCTL// RF Control register
-
[20:22]MCU_STATE (def=0x0) // MCU status
-
[16:19]RF_STATE (def=0x0) // RF status
-
[4]MCU_PLLDOWN (def=0x0) // Software force close, close MCU PLL power
-
[3]MCU_PLLUP (def=0x0) // Software force open, open MCU PLL power
-
[2]RFFC (def=0x0) // Software set or clear (must > 2 IRC16M clock)
-
[1]RFFS (def=0x0) // Software set or clear (must > 2 IRC16M clock)
-
[0]RFSWEN (def=0x0) // RF sequence configured by software or hardware
0x40007024RFPAR// RF timer parameter register
-
[28:30]TIM7_PAR (def=0x4) // RF timer parameter 7
-
[24:27]TIM89_PAR (def=0x7) // RF timer parameter 89
-
[20:21]TIM5_PAR (def=0x2) // RF timer parameter 5
-
[18:19]TIM4_PAR (def=0x2) // RF timer parameter 4
-
[16:17]TIM3_PAR (def=0x2) // RF timer parameter 3
-
[8:11]TIM2_PAR (def=0x1) // RF timer parameter 2
-
[0:6]TIM1_PAR (def=0x64) // RF timer parameter 1
0x4000702CINTF// PMU interrupt flag register
-
[1]BLE_PS_RISEF (def=0x0) // BLE power status rising edge interrupt flag
-
[0]BLE_PS_FALLF (def=0x0) // BLE power status falling edge interrupt flag
0x40007030INTEN// PMU interrupt enable register
-
[1]BLE_PS_RISE_EN (def=0x0) // BLE power status rising edge interrupt enable
-
[0]BLE_PS_FALL_EN (def=0x0) // BLE power status falling edge interrupt enable
0x40007034INTC// PMU interrupt clear register
-
[1]BLE_PS_RISEFC (def=0x0) // clear BLE power status rising edge interrupt flag
-
[0]BLE_PS_FALLFC (def=0x0) // clear BLE power status falling edge interrupt flag
0x40025800QSPI// Quad-SPI interface
0x40025800CTL// Control register
-
[24:31]PSC (def=0x0) // The clock prescaler of AHB clock for generating SCK
-
[23]RPMM (def=0x0) // Read polling match mode
-
[22]RPMS (def=0x0) // Read polling mode stop
-
[20]TMOUTIE (def=0x0) // Timeout interrupt enable
-
[19]RPMFIE (def=0x0) // Read polling mode match interrupt enable
-
[18]FTIE (def=0x0) // FIFO threshold interrupt enable
-
[17]TCIE (def=0x0) // Transfer complete interrupt enable
-
[16]TERRIE (def=0x0) // Transfer error interrupt enable
-
[12:15]SCKDVALUE (def=0x0) // SCK delay value
-
[8:11]FTL (def=0x0) // FIFO threshold level
-
[6]SCKDEN (def=0x0) // SCK delay enable when read data from flash, it is only useful when SSAMPLE is 1
-
[4:5]SSAMPLE (def=0x1) // Sample delay
-
[3]TMOUTEN (def=0x0) // Timeout counter enable
-
[2]DMAEN (def=0x0) // DMA enable
-
[1]ABORT (def=0x0) // Abort request
-
[0]QSPIEN (def=0x0) // the QSPI enable
0x40025804DCFG// Device configuration register
-
[16:20]FMSZ (def=0x1F) // Flash memory size
-
[8:10]CSHC (def=0x0) // Chip select high cycle
-
[0]CKMOD (def=0x0) // This bit indicates the SCK level when QSPI is free
0x40025808STAT// Status register
-
[8:12]FL (def=0x0) // FIFO level
-
[5]BUSY (def=0x0) // Busy flag
-
[4]TMOUT (def=0x0) // Timeout flag
-
[3]RPMF (def=0x0) // Read polling match flag
-
[2]FT (def=0x1) // FIFO threshold flag
-
[1]TC (def=0x0) // Transfer complete flag
-
[0]TERR (def=0x0) // Transfer error flag
0x4002580CSTATC// Status clear register
-
[4]TMOUTC (def=0x0) // Clear timeout flag
-
[3]RPMFC (def=0x0) // Clear read polling mode match flag
-
[1]TCC (def=0x0) // Clear transfer complete flag
-
[0]TERRC (def=0x0) // Clear transfer error flag
0x40025810DTLEN// Data length register
-
[0:31]DTLEN (def=0x0) // Data length
0x40025814TCFG// Transfer configuration register
-
[28]SIOO (def=0x0) // Send instruction only once mode
-
[26:27]FMOD (def=0x0) // Functional mode
-
[24:25]DATAMOD (def=0x0) // Data mode
-
[18:22]DUMYC (def=0x0) // Number of dummy cycles
-
[16:17]ALTESZ (def=0x0) // Alternate bytes size
-
[14:15]ALTEMOD (def=0x0) // Alternate bytes mode
-
[12:13]ADDRSZ (def=0x0) // Address size
-
[10:11]ADDRMOD (def=0x0) // Address mode
-
[8:9]IMOD (def=0x0) // Instruction mode
-
[0:7]INSTRUCTION (def=0x0) // Instruction
0x40025818ADDR// Address register
-
[0:31]ADDR (def=0x0) // Address to be send to the external Flash memory
0x4002581CALTE// Alternate bytes register
-
[0:31]ALTE (def=0x0) // Alternate Bytes
0x40025820DATA// Data register
-
[0:31]DATA (def=0x0) // Data that will be interacting with flash memory
0x40025824STATMK// Status mask register
-
[0:31]MASK (def=0x0) // Status mask in read polling mode
0x40025828STATMATCH// Status match register
-
[0:31]MATCH (def=0x0) // Status match in read polling mode
0x4002582CINTERVAL// Interval register
-
[0:15]INTERVAL (def=0x0) // Interval cycle
0x40025830TMOUT// Timeout register
-
[0:15]TMOUTCYC (def=0x0) // Timeout cycle
0x40025834FLUSH// FIFO flush register
-
[0]FLUSH (def=0x0) // Used to flush all qspi interal fifo
0x40023800RCU// Reset and clock unit
0x40023800CTL// Control register
-
[31]HXTALREADY (def=0x0) // High speed crystal oscillator ready, set by software, which can be written when HXTALEN is off
-
[28]HXTALPU (def=0x0) // High speed crystal oscillator (HXTAL) power up, which can be written when HXTALEN is off
-
[23]PLLDIGSTB (def=0x0) // PLLDIG clock stabilization flag
-
[22]RFCKMEN (def=0x1) // HXTAL clock monitor enable, check RF XTAL
-
[21]PLLDIGEN (def=0x0) // PLLDIG enable, this bit cannot be reset if the PLLDIG clock is used as the system clock
-
[20]PLLDIGPU (def=0x0) // PLLDIG power up, this bit cannot be reset if the PLLDIG clock is used as the system clock
-
[18]HXTALBPS (def=0x0) // High speed crystal oscillator (HXTAL) clock bypass mode enable
-
[17]HXTALSTB (def=0x0) // High speed crystal oscillator (HXTAL) clock stabilization flag
-
[16]HXTALEN (def=0x0) // High speed crystal oscillator (HXTAL) enable
-
[8:15]IRC16MCALIB (def=0x0) // Internal 16 MHz RC Oscillator calibration value register
-
[3:7]IRC16MADJ (def=0x10) // Internal 16 MHz RC oscillator clock trim adjust value
-
[2]IRC16MRFON (def=0x0) // Internal 16 MHz RC RF differential clock signal enable
-
[1]IRC16MSTB (def=0x1) // IRC16M internal 16MHz RC oscillator stabilization flag
-
[0]IRC16MEN (def=0x1) // Internal 16 MHz RC oscillator enable
0x40023804PLL// PLL(Phase Lock Loop) register
-
[15]PLLDIGSEL (def=0x0) // PLLDIG clock source selection
0x40023808CFG0// Clock configuration register 0
-
[30:31]CKOUT1SEL (def=0x0) // CKOUT1 clock source selection
-
[27:29]CKOUT1DIV (def=0x0) // The CK_OUT1 divider which the CK_OUT1 frequency can be reduced
-
[24:26]CKOUT0DIV (def=0x0) // The CK_OUT0 divider which the CK_OUT0 frequency can be reduced
-
[21:23]CKOUT0SEL (def=0x0) // CKOUT0 clock source selection
-
[16:20]RTCDIV (def=0x0) // RTC clock divider factor
-
[13:15]APB2PSC (def=0x0) // APB2 prescaler selection
-
[10:12]APB1PSC (def=0x0) // APB1 prescaler selection
-
[4:7]AHBPSC (def=0x0) // AHB prescaler selection
-
[2:3]SCSS (def=0x0) // System clock switch status
-
[0:1]SCS (def=0x0) // System clock switch
0x4002380CINT// Clock interrupt register
-
[23]CKMIC (def=0x0) // HXTAL clock stuck interrupt clear
-
[22]PLLDIGSTBIC (def=0x0) // PLLDIG stabilization interrupt clear
-
[19]HXTALSTBIC (def=0x0) // HXTAL stabilization interrupt clear
-
[18]IRC16MSTBIC (def=0x0) // IRC16M stabilization interrupt clear
-
[17]LXTALSTBIC (def=0x0) // LXTAL stabilization interrupt clear
-
[16]IRC32KSTBIC (def=0x0) // IRC32K Stabilization interrupt clear
-
[14]PLLDIGSTBIE (def=0x0) // PLLDIG stabilization interrupt enable
-
[11]HXTALSTBIE (def=0x0) // HXTAL stabilization interrupt enable
-
[10]IRC16MSTBIE (def=0x0) // IRC16M stabilization interrupt enable
-
[9]LXTALSTBIE (def=0x0) // LXTAL stabilization interrupt enable
-
[8]IRC32KSTBIE (def=0x0) // IRC32K stabilization interrupt enable
-
[7]CKMIF (def=0x0) // HXTAL clock stuck interrupt flag
-
[6]PLLDIGSTBIF (def=0x0) // PLLDIG stabilization interrupt flag
-
[3]HXTALSTBIF (def=0x0) // HXTAL stabilization interrupt flag
-
[2]IRC16MSTBIF (def=0x0) // IRC16M stabilization interrupt flag
-
[1]LXTALSTBIF (def=0x0) // LXTAL stabilization interrupt flag
-
[0]IRC32KSTBIF (def=0x0) // IRC32K stabilization interrupt flag
0x40023810AHB1RST// AHB1 reset register
-
[31]BLERST (def=0x0) // BLE reset
-
[21]DMARST (def=0x0) // DMA reset
-
[13]WIFIRST (def=0x0) // WIFI reset
-
[12]CRCRST (def=0x0) // CRC reset
-
[2]PCRST (def=0x0) // GPIO port C reset
-
[1]PBRST (def=0x0) // GPIO port B reset
-
[0]PARST (def=0x0) // GPIO port A reset
0x40023814AHB2RST// AHB2 reset register
-
[6]TRNGRST (def=0x0) // TRNG reset
-
[5]HAURST (def=0x0) // HAU reset
-
[4]CAURST (def=0x0) // CAU reset
-
[3]PKCAURST (def=0x0) // PKCAU reset
0x40023818AHB3RST// AHB3 reset register
-
[1]QSPIRST (def=0x0) // QSPI reset
0x40023820APB1RST// APB1 reset register
-
[28]PMURST (def=0x0) // PMU reset
-
[22]I2C1RST (def=0x0) // I2C1 reset
-
[21]I2C0RST (def=0x0) // I2C0 reset
-
[18]USART0RST (def=0x0) // USART0 reset
-
[17]UART1RST (def=0x0) // UART1 reset
-
[15]RFIRST (def=0x0) // RFI reset
-
[11]WWDGTRST (def=0x0) // WWDGT reset
-
[4]TIMER5RST (def=0x0) // TIMER5 reset
-
[1]TIMER2RST (def=0x0) // TIMER2 reset
-
[0]TIMER1RST (def=0x0) // TIMER1 reset
0x40023824APB2RST// APB2 reset register
-
[31]RFRST (def=0x0) // RF reset
-
[18]TIMER16RST (def=0x0) // TIMER16 reset
-
[17]TIMER15RST (def=0x0) // TIMER15 reset
-
[14]SYSCFGRST (def=0x0) // SYSCFG reset
-
[12]SPIRST (def=0x0) // SPI reset
-
[8]ADCRST (def=0x0) // ADC reset
-
[4]UART2RST (def=0x0) // UART2 reset
-
[0]TIMER0RST (def=0x0) // TIMER0 reset
0x40023830AHB1EN// AHB1 enable register
-
[31]BLEEN (def=0x0) // BLE clock enable
-
[21]DMAEN (def=0x0) // DMA clock enable
-
[19]SRAM3EN (def=0x1) // SRAM3 clock enable
-
[18]SRAM2EN (def=0x1) // SRAM2 clock enable
-
[17]SRAM1EN (def=0x1) // SRAM1 clock enable
-
[16]SRAM0EN (def=0x1) // SRAM0 clock enable
-
[14]WIFIRUNEN (def=0x0) // WIFIRUNEN clock enable
-
[13]WIFIEN (def=0x0) // WIFI Module clock enable
-
[12]CRCEN (def=0x0) // CRC clock enable
-
[2]PCEN (def=0x0) // GPIO port C clock enable
-
[1]PBEN (def=0x0) // GPIO port B clock enable
-
[0]PAEN (def=0x0) // GPIO port A clock enable
0x40023834AHB2EN// AHB2 enable register
-
[6]TRNGEN (def=0x0) // TRNG clock enable
-
[5]HAUEN (def=0x0) // HAU clock enable
-
[4]CAUEN (def=0x0) // CAU clock enable
-
[3]PKCAUEN (def=0x0) // PKCAU clock enable
0x40023838AHB3EN// AHB3 enable register
-
[1]QSPIEN (def=0x0) // QSPI clock enable
0x40023840APB1EN// APB1 enable register
-
[28]PMUEN (def=0x0) // PMU clock enable
-
[22]I2C1EN (def=0x0) // I2C1 clock enable
-
[21]I2C0EN (def=0x0) // I2C0 clock enable
-
[18]USART0EN (def=0x0) // USART0 clock enable
-
[17]UART1EN (def=0x0) // UART1 clock enable
-
[15]RFIEN (def=0x0) // RFI clock enable
-
[11]WWDGTEN (def=0x0) // WWDGT clock enable
-
[4]TIMER5EN (def=0x0) // TIMER5 clock enable
-
[1]TIMER2EN (def=0x0) // TIMER2 clock enable
-
[0]TIMER1EN (def=0x0) // TIMER1 clock enable
0x40023844APB2EN// APB2 enable register
-
[31]RFEN (def=0x0) // RF clock enable
-
[18]TIMER16EN (def=0x0) // TIMER16 clock enable
-
[17]TIMER15EN (def=0x0) // TIMER15 clock enable
-
[14]SYSCFGEN (def=0x0) // SYSCFG clock enable
-
[12]SPIEN (def=0x0) // SPI clock enable
-
[8]ADCEN (def=0x0) // ADC clock enable
-
[4]UART2EN (def=0x0) // UART2 clock enable
-
[0]TIMER0EN (def=0x0) // TIMER0 clock enable
0x40023850AHB1SPEN// AHB1 sleep mode enable register
-
[15]FMCSPEN (def=0x1) // FMC clock enable when sleep mode
0x40023870BDCTL// Backup domain control register
-
[16]BKPRST (def=0x0) // Backup domain reset
-
[15]RTCEN (def=0x0) // RTC clock enable
-
[8:9]RTCSRC (def=0x0) // RTC clock entry selection
-
[3:4]LXTALDRI (def=0x3) // LXTAL drive capability
-
[2]LXTALBPS (def=0x0) // LXTAL bypass mode enable
-
[1]LXTALSTB (def=0x0) // Low speed crystal oscillator stabilization flag
-
[0]LXTALEN (def=0x0) // LXTAL enable
0x40023874RSTSCK// Reset source / clock register
-
[31]LPRSTF (def=0x0) // Low-power reset flag
-
[30]WWDGTRSTF (def=0x0) // Window watchdog timer reset flag
-
[29]FWDGTRSTF (def=0x0) // Free watchdog timer reset flag
-
[28]SWRSTF (def=0x0) // Software reset flag
-
[27]PORRSTF (def=0x1) // Power reset flag
-
[26]EPRSTF (def=0x1) // External pin reset flag
-
[24]RSTFC (def=0x0) // Reset flag clear
-
[1]IRC32KSTB (def=0x0) // IRC32K stabilization flag
-
[0]IRC32KEN (def=0x0) // IRC32K enable
0x40023884PLLDIGCFG0// PLLDIG clock configuration register 0
-
[26:31]PLLDIGFSYSDIV (def=0x2) // PLLDIG clock divider factor for system clock
-
[24:25]PLLDIGOSEL (def=0x3) // PLLDIG output frequency select
0x4002388CCFG1// Clock configuration register 1
-
[30:31]USART0SEL (def=0x0) // USART0 Clock Source Selection
-
[26:27]I2C0SEL (def=0x0) // I2C0 Clock Source Selection
-
[24]TIMERSEL (def=0x0) // TIMER clock selection
-
[21]LDO_ANA_LQB (def=0x1) // Analog LDO current bias mode selection
-
[20]LDO_CLK_LQB (def=0x1) // Clock LDO current bias mode selection
-
[19]BGPU (def=0x0) // BandGap power on enable
-
[18]LDOCLKPU (def=0x0) // LDO clock power on enable for RF / ADC / DAC
-
[17]LDOANAPU (def=0x0) // LDO analog power on enable for RF filter
-
[16]RFPLLPU (def=0x0) // RFPLL power on enable
-
[15]RFPLLLOCK (def=0x0) // RF PLL lock
-
[14]RFPLLCALEN (def=0x0) // RF PLL calculation enable
-
[9:11]BGVBIT (def=0x3) // BandGap Power adjust, which can not be written when HXTALEN or PLLDIGEN is on
-
[0:8]IRC16MDIV (def=0x0) // IRC16M clock divider factor for system clock
0x40023890ADDCTL// Additional clock control register
-
[1:5]RNGCKDIV (def=0x0) // PLLDIG clock divider factor for TRNG clock
0x40023894PLLDIGCFG1// PLLDIG clock configuration register 1
-
[21:30]PLLDIGINT (def=0x3C) // Control PLLDIG frequency doubling factor for integer part
-
[0:20]PLLDIGFRAC (def=0x0) // Control PLLDIG frequency doubling factor for fractional part
0x40023900VKEY// Voltage key register
-
[0:31]KEY (def=0x0) // The key of RCU_DSV register
0x40023934DSV// Deep-sleep mode voltage register
-
[0:1]DSLPVS (def=0x0) // Deep-sleep mode voltage selection
0x40002800RTC// Real time clock
0x40002800TIME// Time register
-
[22]PM (def=0x0) // AM / PM mark
-
[20:21]HRT (def=0x0) // Hour tens in BCD code
-
[16:19]HRU (def=0x0) // Hour units in BCD code
-
[12:14]MNT (def=0x0) // Minute tens in BCD code
-
[8:11]MNU (def=0x0) // Minute units in BCD code
-
[4:6]SCT (def=0x0) // Second tens in BCD code
-
[0:3]SCU (def=0x0) // Second units in BCD code
0x40002804DATE// Date register
-
[20:23]YRT (def=0x0) // Year tens in BCD code
-
[16:19]YRU (def=0x0) // Year units in BCD code
-
[13:15]DOW (def=0x1) // Days of the week
-
[12]MONT (def=0x0) // Month tens in BCD code
-
[8:11]MONU (def=0x1) // Month units in BCD code
-
[4:5]DAYT (def=0x0) // Day tens in BCD code
-
[0:3]DAYU (def=0x1) // Day units in BCD code
0x40002808CTL// Control register
-
[31]OUT2EN (def=0x0) // RTC_OUT pin select
-
[23]COEN (def=0x0) // Calibration output enable
-
[21:22]OS (def=0x0) // Output selection
-
[20]OPOL (def=0x0) // Output polarity
-
[19]COS (def=0x0) // Calibration output selection
-
[18]DSM (def=0x0) // Daylight saving mark
-
[17]S1H (def=0x0) // Subtract 1 hour(winter time change)
-
[16]A1H (def=0x0) // Add 1 hour(summer time change)
-
[15]TSIE (def=0x0) // Time-stamp interrupt enable
-
[14]WTIE (def=0x0) // Auto-wakeup timer interrupt enable
-
[13]ALRM1IE (def=0x0) // RTC alarm-1 interrupt enable
-
[12]ALRM0IE (def=0x0) // RTC alarm-0 interrupt enable
-
[11]TSEN (def=0x0) // Time-stamp function enable
-
[10]WTEN (def=0x0) // Auto-wakeup timer function enable
-
[9]ALRM1EN (def=0x0) // Alarm-1 function enable
-
[8]ALRM0EN (def=0x0) // Alarm-0 function enable
-
[7]CCEN (def=0x0) // Coarse calibration function enable
-
[6]CS (def=0x0) // Clock System
-
[5]BPSHAD (def=0x0) // Shadow registers bypass control
-
[4]REFEN (def=0x0) // Reference clock detection function enable
-
[3]TSEG (def=0x0) // Valid event edge of time-stamp
-
[0:2]WTCS (def=0x0) // Auto-wakeup timer clock selection
0x4000280CSTAT// Status register
-
[16]SCPF (def=0x0) // Smooth calibration pending flag
-
[14]TP1F (def=0x0) // RTC_TAMP1 detected flag
-
[13]TP0F (def=0x0) // RTC_TAMP0 detected flag
-
[12]TSOVRF (def=0x0) // Time-stamp overflow flag
-
[11]TSF (def=0x0) // Time-stamp flag
-
[10]WTF (def=0x0) // Wakeup timer flag
-
[9]ALRM1F (def=0x0) // Alarm-1 occurs flag
-
[8]ALRM0F (def=0x0) // Alarm-0 occurs flag
-
[7]INITM (def=0x0) // Enter initialization mode
-
[6]INITF (def=0x0) // Initialization state flag
-
[5]RSYNF (def=0x0) // Register synchronization flag
-
[4]YCM (def=0x0) // Year configuration mark
-
[3]SOPF (def=0x0) // Shift function operation pending flag
-
[2]WTWF (def=0x1) // Wakeup timer write enable flag
-
[1]ALRM1WF (def=0x1) // Alarm 1 configuration can be write flag
-
[0]ALRM0WF (def=0x1) // Alarm 0 configuration can be write flag
0x40002810PSC// Prescaler register
-
[16:22]FACTOR_A (def=0x7F) // Asynchronous prescaler factor
-
[0:14]FACTOR_S (def=0xFF) // Synchronous prescaler factor
0x40002814WUT// Wakeup timer register
-
[0:15]WTRV (def=0xFFFF) // Auto-wakeup timer reloads value
0x40002818COSC// Coarse calibration register
-
[7]COSD (def=0x0) // Coarse calibration direction
-
[0:4]COSS (def=0x0) // Coarse calibration step
0x4000281CALRM0TD// Alarm 0 time and date register
-
[31]MSKD (def=0x0) // Alarm date mask bit
-
[30]DOWS (def=0x0) // Day of the week selected
-
[28:29]DAYT (def=0x0) // Date tens in BCD code
-
[24:27]DAYU (def=0x0) // Date units or week day in BCD code
-
[23]MSKH (def=0x0) // Alarm hour mask bit
-
[22]PM (def=0x0) // AM / PM flag
-
[20:21]HRT (def=0x0) // Hour tens in BCD code
-
[16:19]HRU (def=0x0) // Hour units in BCD code
-
[15]MSKM (def=0x0) // Alarm minutes mask bit
-
[12:14]MNT (def=0x0) // Minutes tens in BCD code
-
[8:11]MNU (def=0x0) // Minutes units in BCD code
-
[7]MSKS (def=0x0) // Alarm second mask bit
-
[4:6]SCT (def=0x0) // Second tens in BCD code
-
[0:3]SCU (def=0x0) // Second units in BCD code
0x40002820ALRM1TD// Alarm 1 time and date register
-
[31]MSKD (def=0x0) // Alarm date mask bit
-
[30]DOWS (def=0x0) // Day of the week selected
-
[28:29]DAYT (def=0x0) // Day tens in BCD code
-
[24:27]DAYU (def=0x0) // Day units or week day in BCD code
-
[23]MSKH (def=0x0) // Alarm hour mask bit
-
[22]PM (def=0x0) // AM / PM flag
-
[20:21]HRT (def=0x0) // Hour tens in BCD code
-
[16:19]HRU (def=0x0) // Hour units in BCD code
-
[15]MSKM (def=0x0) // Alarm minutes mask bit
-
[12:14]MNT (def=0x0) // Minutes tens in BCD code
-
[8:11]MNU (def=0x0) // Minutes units in BCD code
-
[7]MSKS (def=0x0) // Alarm second mask bit
-
[4:6]SCT (def=0x0) // Second tens in BCD code
-
[0:3]SCU (def=0x0) // Second units in BCD code
0x40002824WPK// Write protection key register
-
[0:7]WPK (def=0x0) // Key for write protection
0x40002828SS// Sub second register
-
[0:15]SSC (def=0x0) // Sub second value
0x4000282CSHIFTCTL// Shift function control register
-
[31]A1S (def=0x0) // One second add
-
[0:14]SFS (def=0x0) // Subtract a fraction of a second
0x40002830TTS// Time of time stamp register
-
[22]PM (def=0x0) // AM / PM mark
-
[20:21]HRT (def=0x0) // Hour tens in BCD code
-
[16:19]HRU (def=0x0) // Hour units in BCD code
-
[12:14]MNT (def=0x0) // Minute tens in BCD code
-
[8:11]MNU (def=0x0) // Minute units in BCD code
-
[4:6]SCT (def=0x0) // Second tens in BCD code
-
[0:3]SCU (def=0x0) // Second units in BCD code
0x40002834DTS// Date of time stamp register
-
[13:15]DOW (def=0x0) // Days of the week
-
[12]MONT (def=0x0) // Month tens in BCD code
-
[8:11]MONU (def=0x0) // Month units in BCD code
-
[4:5]DAYT (def=0x0) // Day tens in BCD code
-
[0:3]DAYU (def=0x0) // Day units in BCD code
0x40002838SSTS// Sub second of time stamp register
-
[0:15]SSC (def=0x0) // Sub second value
0x4000283CHRFC// High resolution frequency compensation register
-
[15]FREQI (def=0x0) // Increase RTC frequency by 488
-
[14]CWND8 (def=0x0) // Frequency compensation window 8 second selected
-
[13]CWND16 (def=0x0) // Frequency compensation window 16 second selected
-
[0:8]CMSK (def=0x0) // Calibration mask number
0x40002840TAMP// Tamper register
-
[31]BKERASE (def=0x0) // Backup registers erase
-
[20]TP1NOER (def=0x0) // Tamper 1 no erase
-
[19]TP0NOER (def=0x0) // Tamper 0 no erase
-
[18]AOT (def=0x0) // RTC_ALARM output type
-
[15]DISPU (def=0x0) // RTC_TAMPx pull up disable bit
-
[13:14]PRCH (def=0x0) // Pre-charge duration time of RTC_TAMPx
-
[11:12]FLT (def=0x0) // RTC_TAMPx filter count setting
-
[8:10]FREQ (def=0x0) // Sampling frequency of tamper event detection
-
[7]TPTS (def=0x0) // Make tamper function used for timestamp function
-
[4]TP1EG (def=0x0) // Tamper 1 event trigger edge
-
[3]TP1EN (def=0x0) // Tamper 1 detection enable
-
[2]TPIE (def=0x0) // Tamper detection interrupt enable
-
[1]TP0EG (def=0x0) // Tamper 0 event trigger edge
-
[0]TP0EN (def=0x0) // Tamper 0 detection enable
0x40002844ALRM0SS// Alarm 0 sub second register
-
[24:27]MSKSSC (def=0x0) // Mask control bit of SSC
-
[0:14]SSC (def=0x0) // Alarm sub second value
0x40002848ALRM1SS// Alarm 1 sub second register
-
[24:27]MSKSSC (def=0x0) // Mask control bit of SSC
-
[0:14]SSC (def=0x0) // Alarm sub second value
0x40002870BKP0// Backup registe 0
-
[0:31]DATA (def=0x0) // Data
0x40002874BKP1// Backup registe 1
-
[0:31]DATA (def=0x0) // Data
0x40002878BKP2// Backup registe 2
-
[0:31]DATA (def=0x0) // Data
0x4000287CBKP3// Backup registe 3
-
[0:31]DATA (def=0x0) // Data
0x40002880BKP4// Backup registe 4
-
[0:31]DATA (def=0x0) // Data
0x40002884BKP5// Backup registe 5
-
[0:31]DATA (def=0x0) // Data
0x40002888BKP6// Backup registe 6
-
[0:31]DATA (def=0x0) // Data
0x4000288CBKP7// Backup registe 7
-
[0:31]DATA (def=0x0) // Data
0x40002890BKP8// Backup registe 8
-
[0:31]DATA (def=0x0) // Data
0x40002894BKP9// Backup registe 9
-
[0:31]DATA (def=0x0) // Data
0x40002898BKP10// Backup registe 10
-
[0:31]DATA (def=0x0) // Data
0x4000289CBKP11// Backup registe 11
-
[0:31]DATA (def=0x0) // Data
0x400028A0BKP12// Backup registe 12
-
[0:31]DATA (def=0x0) // Data
0x400028A4BKP13// Backup registe 13
-
[0:31]DATA (def=0x0) // Data
0x400028A8BKP14// Backup registe 14
-
[0:31]DATA (def=0x0) // Data
0x400028ACBKP15// Backup registe 15
-
[0:31]DATA (def=0x0) // Data
0x400028B0BKP16// Backup registe 16
-
[0:31]DATA (def=0x0) // Data
0x400028B4BKP17// Backup registe 17
-
[0:31]DATA (def=0x0) // Data
0x400028B8BKP18// Backup registe 18
-
[0:31]DATA (def=0x0) // Data
0x400028BCBKP19// Backup registe 19
-
[0:31]DATA (def=0x0) // Data
- [21] RTC_Tamper_TimeStamp //
- [22] RTC_WKUP //
- [60] RTC_Alarm //
0x40013000SPI// Serial peripheral interface
0x40013000CTL0// Control register 0
-
[15]BDEN (def=0x0) // Bidirectional enable
-
[14]BDOEN (def=0x0) // Bidirectional transmit output enable
-
[13]CRCEN (def=0x0) // CRC calculation enable
-
[12]CRCNT (def=0x0) // CRC next transfer
-
[11]FF16 (def=0x0) // Data frame format
-
[10]RO (def=0x0) // Receive only mode
-
[9]SWNSSEN (def=0x0) // NSS software mode enable
-
[8]SWNSS (def=0x0) // NSS pin selection in NSS software mode
-
[7]LF (def=0x0) // LSB first mode
-
[6]SPIEN (def=0x0) // SPI enable
-
[3:5]PSC (def=0x0) // Master clock prescaler selection
-
[2]MSTMOD (def=0x0) // Master mode enable
-
[1]CKPL (def=0x0) // Clock polarity selection
-
[0]CKPH (def=0x0) // Clock phase selection
0x40013004CTL1// Control register 1
-
[7]TBEIE (def=0x0) // Transmit buffer empty interrupt enable
-
[6]RBNEIE (def=0x0) // Receive buffer not empty interrupt enable
-
[5]ERRIE (def=0x0) // Errors interrupt enable
-
[4]TMOD (def=0x0) // SPI TI mode enable
-
[2]NSSDRV (def=0x0) // Drive NSS output
-
[1]DMATEN (def=0x0) // Transmit buffer DMA enable
-
[0]DMAREN (def=0x0) // Receive buffer DMA enable
0x40013008STAT// Status register
-
[8]FERR (def=0x0) // Format error
-
[7]TRANS (def=0x0) // Transmitting ongoing bit
-
[6]RXORERR (def=0x0) // Reception overrun error bit
-
[5]CONFERR (def=0x0) // SPI Configuration error
-
[4]CRCERR (def=0x0) // SPI CRC error bit
-
[3]TXURERR (def=0x0) // Transmission underrun error bit
-
[1]TBE (def=0x1) // Transmit buffer empty
-
[0]RBNE (def=0x0) // Receive buffer not empty
0x4001300CDATA// Data register
-
[0:15]SPI_DATA (def=0x0) // Data transfer register
0x40013010CRCPOLY// CRC polynomial register
-
[0:15]CRCPOLY (def=0x7) // CRC polynomial value
0x40013014RCRC// RX CRC register
-
[0:15]RCRC (def=0x0) // RX CRC value
0x40013018TCRC// TX CRC register
-
[0:15]TCRC (def=0x0) // TX CRC value
0x40013800SYSCFG// System configuration registers
0x40013800CFG0// Configuration register 0
-
[0:1]BOOT_MODE (def=0x0) // Boot mode (Refer to Boot configuration for details)
0x40013808EXTISS0// EXTI sources selection register 0
-
[12:15]EXTI3_SS (def=0x0) // EXTI 3 sources selection
-
[8:11]EXTI2_SS (def=0x0) // EXTI 2 sources selection
-
[4:7]EXTI1_SS (def=0x0) // EXTI 1 sources selection
-
[0:3]EXTI0_SS (def=0x0) // EXTI 0 sources selection
0x4001380CEXTISS1// EXTI sources selection register 1
-
[12:15]EXTI7_SS (def=0x0) // EXTI 7 sources selection
-
[8:11]EXTI6_SS (def=0x0) // EXTI 6 sources selection
-
[4:7]EXTI5_SS (def=0x0) // EXTI 5 sources selection
-
[0:3]EXTI4_SS (def=0x0) // EXTI 4 sources selection
0x40013810EXTISS2// EXTI sources selection register 2
-
[12:15]EXTI11_SS (def=0x0) // EXTI 11 sources selection
-
[8:11]EXTI10_SS (def=0x0) // EXTI 10 sources selection
-
[4:7]EXTI9_SS (def=0x0) // EXTI 9 sources selection
-
[0:3]EXTI8_SS (def=0x0) // EXTI 8 sources selection
0x40013814EXTISS3// EXTI sources selection register 3
-
[12:15]EXTI15_SS (def=0x0) // EXTI 15 sources selection
-
[8:11]EXTI14_SS (def=0x0) // EXTI 14 sources selection
-
[4:7]EXTI13_SS (def=0x0) // EXTI 13 sources selection
-
[0:3]EXTI12_SS (def=0x0) // EXTI 12 sources selection
0x40013820CPSCTL// I/O compensation control register
-
[8]CPS_RDY (def=0x0) // Compensation cell ready flag
-
[0]CPS_EN (def=0x0) // Compensation cell power-down
0x40013854CFG1// SYSCFG configuration register 1
-
[2]LVD_LOCK (def=0x0) // LVD lockup bit
0x40013868SCFG// SYSCFG shared SRAM configuration register
-
[0]SOWNSEL (def=0x1) // Shared SRAM ownership select
0x40013900TIMER0CFG// TIMER trigger selection regist 0
-
[28:31]TSCFG7 (def=0x0) // Trigger selection 7
-
[24:27]TSCFG6 (def=0x0) // Trigger selection 6
-
[20:23]TSCFG5 (def=0x0) // Trigger selection 5
-
[16:19]TSCFG4 (def=0x0) // Trigger selection 4
-
[12:15]TSCFG3 (def=0x0) // Trigger selection 3
-
[8:11]TSCFG2 (def=0x0) // Trigger selection 2
-
[4:7]TSCFG1 (def=0x0) // Trigger selection 1
-
[0:3]TSCFG0 (def=0x0) // Trigger selection 0
0x40013904TIMER1CFG// TIMER trigger selection regist 1
-
[28:31]TSCFG7 (def=0x0) // Trigger selection 7
-
[24:27]TSCFG6 (def=0x0) // Trigger selection 6
-
[20:23]TSCFG5 (def=0x0) // Trigger selection 5
-
[16:19]TSCFG4 (def=0x0) // Trigger selection 4
-
[12:15]TSCFG3 (def=0x0) // Trigger selection 3
-
[8:11]TSCFG2 (def=0x0) // Trigger selection 2
-
[4:7]TSCFG1 (def=0x0) // Trigger selection 1
-
[0:3]TSCFG0 (def=0x0) // Trigger selection 0
0x40013908TIMER2CFG// TIMER trigger selection regist 2
-
[28:31]TSCFG7 (def=0x0) // Trigger selection 7
-
[24:27]TSCFG6 (def=0x0) // Trigger selection 6
-
[20:23]TSCFG5 (def=0x0) // Trigger selection 5
-
[16:19]TSCFG4 (def=0x0) // Trigger selection 4
-
[12:15]TSCFG3 (def=0x0) // Trigger selection 3
-
[8:11]TSCFG2 (def=0x0) // Trigger selection 2
-
[4:7]TSCFG1 (def=0x0) // Trigger selection 1
-
[0:3]TSCFG0 (def=0x0) // Trigger selection 0
0x40010000TIMER0// Advanced-timers
0x40010000CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload preload enable
-
[5:6]CAM (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]SPM (def=0x0) // One-pulse mode
-
[2]UPS (def=0x0) // Update request source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40010004CTL1// control register 1
-
[14]ISO3 (def=0x0) // Idle state of channel 3 output
-
[13]ISO2N (def=0x0) // Idle state of channel 2 complementary output
-
[12]ISO2 (def=0x0) // Idle state of channel 2 output
-
[11]ISO1N (def=0x0) // Idle state of channel 1 complementary output
-
[10]ISO1 (def=0x0) // Idle state of channel 1 output
-
[9]ISO0N (def=0x0) // Idle state of channel 0 complementary output
-
[8]ISO0 (def=0x0) // Idle state of channel 0 output
-
[7]TI0S (def=0x0) // Channel 0 trigger input selection
-
[4:6]MMC (def=0x0) // Master mode control
-
[3]DMAS (def=0x0) // DMA request source selection
-
[2]CCUC (def=0x0) // Commutation control shadow register update control
-
[0]CCSE (def=0x0) // Commutation control shadow enable
0x40010008SMCFG// slave mode configuration register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]SCM1 (def=0x0) // Part of SMC for enable External clock mode1
-
[12:13]ETPSC (def=0x0) // External trigger prescaler
-
[8:11]ETFC (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
0x4001000CDMAINTEN// DMA/Interrupt enable register
-
[14]TRGDEN (def=0x0) // Trigger DMA request enable
-
[13]CMTDEN (def=0x0) // Commutation DMA request enable
-
[12]CH3DEN (def=0x0) // Capture/Compare 3 DMA request enable
-
[11]CH2DEN (def=0x0) // Capture/Compare 2 DMA request enable
-
[10]CH1DEN (def=0x0) // Capture/Compare 1 DMA request enable
-
[9]CH0DEN (def=0x0) // Capture/Compare 0 DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[7]BRKIE (def=0x0) // Break interrupt enable
-
[6]TRGIE (def=0x0) // Trigger interrupt enable
-
[5]CMTIE (def=0x0) // COM interrupt enable
-
[4]CH3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[3]CH2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[2]CH1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[1]CH0IE (def=0x0) // Capture/Compare 0 interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40010010INTF// status register
-
[12]CH3OF (def=0x0) // Channel 3 over capture flag
-
[11]CH2OF (def=0x0) // Channel 2 over capture flag
-
[10]CH1OF (def=0x0) // Channel 1 over capture flag
-
[9]CH0OF (def=0x0) // Channel 0 over capture flag
-
[7]BRKIF (def=0x0) // Break interrupt flag
-
[6]TRGIF (def=0x0) // Trigger interrupt flag
-
[5]CMTIF (def=0x0) // COM interrupt flag
-
[4]CH3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[3]CH2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[2]CH1IF (def=0x0) // Capture/Compare 1 interrupt flag
-
[1]CH0IF (def=0x0) // Capture/compare 0 interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40010014SWEVG// Software event generation register
-
[7]BRKG (def=0x0) // Break event generation
-
[6]TRGG (def=0x0) // Trigger event generation
-
[5]CMTG (def=0x0) // Channel commutation event generation
-
[4]CH3G (def=0x0) // Channel 3's capture or compare event generation
-
[3]CH2G (def=0x0) // Channel 2's capture or compare event generation
-
[2]CH1G (def=0x0) // Channel 1's capture or compare event generation
-
[1]CH0G (def=0x0) // Channel 0's capture or compare event generation
-
[0]UPG (def=0x0) // Update event generation
0x40010018CHCTL0_Output// capture/compare mode register (output mode)
-
[15]CH1COMCEN (def=0x0) // Channel 1 output compare clear enable
-
[12:14]CH1COMCTL (def=0x0) // Channel 1 compare output control
-
[11]CH1COMSEN (def=0x0) // Channel 1 output compare shadow enable
-
[10]CH1COMFEN (def=0x0) // Channel 1 output compare fast enable
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[7]CH0COMCEN (def=0x0) // Channel 0 output compare clear enable
-
[4:6]CH0COMCTL (def=0x0) // Channel 0 compare output control
-
[3]CH0COMSEN (def=0x0) // Channel 0 compare output shadow enable
-
[2]CH0COMFEN (def=0x0) // Channel 0 output compare fast enable
-
[0:1]CH0MS (def=0x0) // Channel 0 I/O mode selection
0x40010018CHCTL0_Input// capture/compare mode register 0 (input mode)
-
[12:15]CH1CAPFLT (def=0x0) // Channel 1 input capture filter control
-
[10:11]CH1CAPPSC (def=0x0) // Channel 1 input capture prescaler
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[4:7]CH0CAPFLT (def=0x0) // Channel 0 input capture filter control
-
[2:3]CH0CAPPSC (def=0x0) // Channel 0 input capture prescaler
-
[0:1]CH0MS (def=0x0) // Channel 0 mode selection
0x4001001CCHCTL1_Output// capture/compare mode register (output mode)
-
[15]CH3COMCEN (def=0x0) // Channel 3 output compare clear enable
-
[12:14]CH3COMCTL (def=0x0) // Channel 3 compare output control
-
[11]CH3COMSEN (def=0x0) // Channel 3 output compare shadow enable
-
[10]CH3COMFEN (def=0x0) // Channel 3 output compare fast enable
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[7]CH2COMCEN (def=0x0) // Channel 2 output compare clear enable
-
[4:6]CH2COMCTL (def=0x0) // Channel 2 compare output control
-
[3]CH2COMSEN (def=0x0) // Channel 2 compare output shadow enable
-
[2]CH2COMFEN (def=0x0) // Channel 2 output compare fast enable
-
[0:1]CH2MS (def=0x0) // Channel 2 I/O mode selection
0x4001001CCHCTL1_Input// capture/compare mode register 1 (input mode)
-
[12:15]CH3CAPFLT (def=0x0) // Channel 3 input capture filter control
-
[10:11]CH3CAPPSC (def=0x0) // Channel 3 input capture prescaler
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[4:7]CH2CAPFLT (def=0x0) // Input capture 2 filter
-
[2:3]CH2CAPPSC (def=0x0) // Input capture 2 prescaler
-
[0:1]CH2MS (def=0x0) // Capture/compare 2 selection
0x40010020CHCTL2// capture/compare enable register
-
[13]CH3P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CH3EN (def=0x0) // Capture/Compare 3 output enable
-
[11]CH2NP (def=0x0) // Capture/Compare 2 output Polarity
-
[10]CH2NEN (def=0x0) // Capture/Compare 2 complementary output enable
-
[9]CH2P (def=0x0) // Capture/Compare 2 output Polarity
-
[8]CH2EN (def=0x0) // Capture/Compare 2 output enable
-
[7]CH1NP (def=0x0) // Capture/Compare 1 output Polarity
-
[6]CH1NEN (def=0x0) // Capture/Compare 1 complementary output enable
-
[5]CH1P (def=0x0) // Capture/Compare 1 output Polarity
-
[4]CH1EN (def=0x0) // Capture/Compare 1 output enable
-
[3]CH0NP (def=0x0) // Capture/Compare 0 output Polarity
-
[2]CH0NEN (def=0x0) // Capture/Compare 0 complementary output enable
-
[1]CH0P (def=0x0) // Capture/Compare 0 output Polarity
-
[0]CH0EN (def=0x0) // Capture/Compare 1 output enable
0x40010024CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40010028PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4001002CCAR// auto-reload register
-
[0:15]CARL (def=0x0) // Counter auto reload value
0x40010030CREP// repetition counter register
-
[0:7]CREP (def=0x0) // Repetition counter value
0x40010034CH0CV// capture/compare register 0
-
[0:15]CH0VAL (def=0x0) // Capture/Compare 0 value
0x40010038CH1CV// capture/compare register 1
-
[0:15]CH1VAL (def=0x0) // Capture/Compare 1 value
0x4001003CCH2CV// capture/compare register 2
-
[0:15]CH2VAL (def=0x0) // Capture/Compare 2 value
0x40010040CH3CV// capture/compare register 3
-
[0:15]CH3VAL (def=0x0) // Capture/Compare 3 value
0x40010044CCHP// channel complementary protection register
-
[15]POEN (def=0x0) // Primary output enable
-
[14]OAEN (def=0x0) // Automatic output enable
-
[13]BRKP (def=0x0) // Break polarity
-
[12]BRKEN (def=0x0) // Break enable
-
[11]ROS (def=0x0) // Off-state selection for Run mode
-
[10]IOS (def=0x0) // Off-state selection for Idle mode
-
[8:9]PROT (def=0x0) // Lock configuration
-
[0:7]DTCFG (def=0x0) // Dead-time generator setup
0x40010048DMACFG// DMA configuration register
-
[8:12]DMATC (def=0x0) // DMA transfer count
-
[0:4]DMATA (def=0x0) // DMA transfer access start address
0x4001004CDMATB// DMA transfer buffer register
-
[0:15]DMATB (def=0x0) // DMA transfer buffer
0x400100FCCFG// Configuration register
-
[1]CHVSEL (def=0x0) // Write CHxVAL register selection
-
[0]OUTSEL (def=0x0) // The output value selection
- [43] TIMER0_BRK //
- [44] TIMER0_UP //
- [45] TIMER0COM //
- [46] TIMER0_CC //
0x40000000TIMER1// General-level0-timer
0x40000000CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload preload enable
-
[5:6]CAM (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]SPM (def=0x0) // One-pulse mode
-
[2]UPS (def=0x0) // Update request source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000004CTL1// control register 1
-
[7]TI0S (def=0x0) // TI0 selection
-
[4:6]MMC (def=0x0) // Master mode selection
-
[3]DMAS (def=0x0) // Capture/compare DMA selection
0x40000008SMCFG// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]SMC1 (def=0x0) // External clock enable
-
[12:13]ETPSC (def=0x0) // External trigger prescaler
-
[8:11]ETFC (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
0x4000000CDMAINTEN// DMA/Interrupt enable register
-
[14]TRGDEN (def=0x0) // Trigger DMA request enable
-
[12]CH3DEN (def=0x0) // Capture/Compare 3 DMA request enable
-
[11]CH2DEN (def=0x0) // Capture/Compare 2 DMA request enable
-
[10]CH1DEN (def=0x0) // Capture/Compare 1 DMA request enable
-
[9]CH0DEN (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[6]TRGIE (def=0x0) // Trigger interrupt enable
-
[4]CH3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[3]CH2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[2]CH1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[1]CH0IE (def=0x0) // Capture/Compare 0 interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40000010INTF// interrupt flag register
-
[12]CH3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[11]CH2OF (def=0x0) // Capture/Compare 2 overcapture flag
-
[10]CH1OF (def=0x0) // Capture/compare 1 overcapture flag
-
[9]CH0OF (def=0x0) // Capture/Compare 0 overcapture flag
-
[6]TRGIF (def=0x0) // Trigger interrupt flag
-
[4]CH3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[3]CH2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[2]CH1IF (def=0x0) // Capture/Compare 1 interrupt flag
-
[1]CH0IF (def=0x0) // Capture/compare 0 interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40000014SWEVG// event generation register
-
[6]TRGG (def=0x0) // Trigger generation
-
[4]CH3G (def=0x0) // Capture/compare 3 generation
-
[3]CH2G (def=0x0) // Capture/compare 2 generation
-
[2]CH1G (def=0x0) // Capture/compare 1 generation
-
[1]CH0G (def=0x0) // Capture/compare 0 generation
-
[0]UPG (def=0x0) // Update generation
0x40000018CHCTL0_Output// capture/compare mode register 0 (output mode)
-
[15]CH1COMCEN (def=0x0) // Output compare 1 clear enable
-
[12:14]CH1COMCTL (def=0x0) // Output compare 1 mode
-
[11]CH1COMSEN (def=0x0) // Output compare 1 preload enable
-
[10]CH1COMFEN (def=0x0) // Output compare 1 fast enable
-
[8:9]CH1MS (def=0x0) // Capture/Compare 1 selection
-
[7]CH0COMCEN (def=0x0) // Output compare 0 clear enable
-
[4:6]CH0COMCTL (def=0x0) // Output compare 0 mode
-
[3]CH0COMSEN (def=0x0) // Output compare 0 preload enable
-
[2]CH0COMFEN (def=0x0) // Output compare 0 fast enable
-
[0:1]CH0MS (def=0x0) // Capture/Compare 0 selection
0x40000018CHCTL0_Input// capture/compare mode register 0 (input mode)
-
[12:15]CH1CAPFLT (def=0x0) // Input capture 1 filter
-
[10:11]CH1CAPPSC (def=0x0) // Input capture 1 prescaler
-
[8:9]CH1MS (def=0x0) // Capture/compare 1 selection
-
[4:7]CH0CAPFLT (def=0x0) // Input capture 0 filter
-
[2:3]CH0CAPPSC (def=0x0) // Input capture 0 prescaler
-
[0:1]CH0MS (def=0x0) // Capture/Compare 0 selection
0x4000001CCHCTL1_Output// capture/compare mode register 1 (output mode)
-
[15]CH3COMCEN (def=0x0) // Output compare 3 clear enable
-
[12:14]CH3COMCTL (def=0x0) // Output compare 3 mode
-
[11]CH3COMSEN (def=0x0) // Output compare 3 preload enable
-
[10]CH3COMFEN (def=0x0) // Output compare 3 fast enable
-
[8:9]CH3MS (def=0x0) // Capture/Compare 3 selection
-
[7]CH2COMCEN (def=0x0) // Output compare 2 clear enable
-
[4:6]CH2COMCTL (def=0x0) // Output compare 2 mode
-
[3]CH2COMSEN (def=0x0) // Output compare 2 preload enable
-
[2]CH2COMFEN (def=0x0) // Output compare 2 fast enable
-
[0:1]CH2MS (def=0x0) // Capture/Compare 2 selection
0x4000001CCHCTL1_Input// capture/compare mode register 1 (input mode)
-
[12:15]CH3CAPFLT (def=0x0) // Input capture 3 filter
-
[10:11]CH3CAPPSC (def=0x0) // Input capture 3 prescaler
-
[8:9]CH3MS (def=0x0) // Capture/Compare 3 selection
-
[4:7]CH2CAPFLT (def=0x0) // Input capture 2 filter
-
[2:3]CH2CAPPSC (def=0x0) // Input capture 2 prescaler
-
[0:1]CH2MS (def=0x0) // Capture/Compare 2 selection
0x40000020CHCTL2// capture/compare enable register
-
[15]CH3NP (def=0x0) // Capture/Compare 3 output Polarity
-
[13]CH3P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CH3EN (def=0x0) // Capture/Compare 3 output enable
-
[11]CH2NP (def=0x0) // Capture/Compare 2 output Polarity
-
[9]CH2P (def=0x0) // Capture/Compare 2 output Polarity
-
[8]CH2EN (def=0x0) // Capture/Compare 2 output enable
-
[7]CH1NP (def=0x0) // Capture/Compare 1 output Polarity
-
[5]CH1P (def=0x0) // Capture/Compare 1 output Polarity
-
[4]CH1EN (def=0x0) // Capture/Compare 1 output enable
-
[3]CH0NP (def=0x0) // Capture/Compare 0 output Polarity
-
[1]CH0P (def=0x0) // Capture/Compare 0 output Polarity
-
[0]CH0EN (def=0x0) // Capture/Compare 0 output enable
0x40000024CNT// counter
-
[0:31]CNT (def=0x0) // counter value
0x40000028PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4000002CCAR// auto-reload register
-
[0:31]CARL (def=0x0) // Low Auto-reload value
0x40000034CH0CV// capture/compare register 1
-
[0:31]CH0VAL (def=0x0) // Low Capture/Compare 1 value
0x40000038CH1CV// capture/compare register 2
-
[0:31]CH1VAL (def=0x0) // Low Capture/Compare 2 value
0x4000003CCH2CV// capture/compare register 2
-
[0:31]CH2VAL (def=0x0) // High Capture/Compare value (TIM2 only)
0x40000040CH3CV// capture/compare register 3
-
[0:31]CH3VAL (def=0x0) // High Capture/Compare value (TIM2 only)
0x40000048DMACFG// DMA control register
-
[8:12]DMATC (def=0x0) // DMA burst length
-
[0:4]DMATA (def=0x0) // DMA base address
0x4000004CDMATB// DMA address for full transfer
-
[0:15]DMATB (def=0x0) // DMA register for burst accesses
0x400000FCCFG// Configuration
-
[1]CHVSEL (def=0x0) // Write CHxVAL register selection
0x40018000TIMER15// General-purpose-timers
0x40018000CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload preload enable
-
[3]SPM (def=0x0) // One-pulse mode
-
[2]UPS (def=0x0) // Update request source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40018004CTL1// control register 1
-
[9]ISO0N (def=0x0) // Output Idle state 0
-
[8]ISO0 (def=0x0) // Output Idle state 0
-
[3]DMAS (def=0x0) // Capture/compare DMA selection
-
[2]CCUC (def=0x0) // Capture/compare control update selection
-
[0]CCSE (def=0x0) // Capture/compare preloaded control
0x4001800CDMAINTEN// DMA/Interrupt enable register
-
[9]CH0DEN (def=0x0) // Capture/Compare 0 DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[7]BRKIE (def=0x0) // Break interrupt enable
-
[5]CMTIE (def=0x0) // COM interrupt enable
-
[1]CH0IE (def=0x0) // Capture/Compare 0 interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40018010INTF// interrupt flag register
-
[9]CH0OF (def=0x0) // Capture/Compare 0 overcapture flag
-
[7]BRKIF (def=0x0) // Break interrupt flag
-
[5]CMTIF (def=0x0) // COM interrupt flag
-
[1]CH0IF (def=0x0) // Capture/compare 0 interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40018014SWEVG// event generation register
-
[7]BRKG (def=0x0) // Break generation
-
[5]CMTG (def=0x0) // Capture/Compare control update generation
-
[1]CH0G (def=0x0) // Capture/compare 0 generation
-
[0]UPG (def=0x0) // Update generation
0x40018018CHCTL0_Output// capture/compare mode register (output mode)
-
[4:6]CH0COMCTL (def=0x0) // Output Compare 0 mode
-
[3]CH0COMSEN (def=0x0) // Output Compare 0 preload enable
-
[2]CH0COMFEN (def=0x0) // Output Compare 0 fast enable
-
[0:1]CH0MS (def=0x0) // Capture/Compare 0 selection
0x40018018CHCTL0_Input// capture/compare mode register 0 (input mode)
-
[4:7]CH0CAPFLT (def=0x0) // Input capture 0 filter
-
[2:3]CH0CAPPSC (def=0x0) // Input capture 0 prescaler
-
[0:1]CH0MS (def=0x0) // Capture/Compare 0 selection
0x40018020CHCTL2// capture/compare enable register
-
[3]CH0NP (def=0x0) // Capture/Compare 0 output Polarity
-
[2]CH0NEN (def=0x0) // Capture/Compare 0 complementary output enable
-
[1]CH0P (def=0x0) // Capture/Compare 0 output Polarity
-
[0]CH0EN (def=0x0) // Capture/Compare 0 output enable
0x40018024CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40018028PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4001802CCAR// auto-reload register
-
[0:15]CARL (def=0x0) // Auto-reload value
0x40018030CREP// repetition counter register
-
[0:7]CREP (def=0x0) // Repetition counter value
0x40018034CH0CV// capture/compare register 0
-
[0:15]CH0VAL (def=0x0) // Capture/Compare 0 value
0x40018044CCHP// break and dead-time register
-
[15]POEN (def=0x0) // Main output enable
-
[14]OAEN (def=0x0) // Automatic output enable
-
[13]BRKP (def=0x0) // Break polarity
-
[12]BRKEN (def=0x0) // Break enable
-
[11]ROS (def=0x0) // Off-state selection for Run mode
-
[10]IOS (def=0x0) // Off-state selection for Idle mode
-
[8:9]PROT (def=0x0) // complementary register protect control
-
[0:7]DTCFG (def=0x0) // Dead-time generator setup
0x40018048DMACFG// DMA configuration register
-
[8:12]DMATC (def=0x0) // DMA transfer count
-
[0:4]DMATA (def=0x0) // DMA transfer access start address
0x4001804CDMATB// DMA transfer buffer register
-
[0:15]DMATB (def=0x0) // DMA register for burst accesses
0x400180FCCFG// configuration register
-
[0]OUTSEL (def=0x0) // The output value selection
-
[1]CHVSEL (def=0x0) // Write CHxVAL register selection
0x40018400TIMER16// General-purpose-timers
0x40018400CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload preload enable
-
[3]SPM (def=0x0) // One-pulse mode
-
[2]UPS (def=0x0) // Update request source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40018404CTL1// control register 1
-
[9]ISO0N (def=0x0) // Output Idle state 0
-
[8]ISO0 (def=0x0) // Output Idle state 0
-
[3]DMAS (def=0x0) // Capture/compare DMA selection
-
[2]CCUC (def=0x0) // Capture/compare control update selection
-
[0]CCSE (def=0x0) // Capture/compare preloaded control
0x4001840CDMAINTEN// DMA/Interrupt enable register
-
[9]CH0DEN (def=0x0) // Capture/Compare 0 DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[7]BRKIE (def=0x0) // Break interrupt enable
-
[5]CMTIE (def=0x0) // COM interrupt enable
-
[1]CH0IE (def=0x0) // Capture/Compare 0 interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40018410INTF// interrupt flag register
-
[9]CH0OF (def=0x0) // Capture/Compare 0 overcapture flag
-
[7]BRKIF (def=0x0) // Break interrupt flag
-
[5]CMTIF (def=0x0) // COM interrupt flag
-
[1]CH0IF (def=0x0) // Capture/compare 0 interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40018414SWEVG// event generation register
-
[7]BRKG (def=0x0) // Break generation
-
[5]CMTG (def=0x0) // Capture/Compare control update generation
-
[1]CH0G (def=0x0) // Capture/compare 0 generation
-
[0]UPG (def=0x0) // Update generation
0x40018418CHCTL0_Output// capture/compare mode register (output mode)
-
[4:6]CH0COMCTL (def=0x0) // Output Compare 0 mode
-
[3]CH0COMSEN (def=0x0) // Output Compare 0 preload enable
-
[2]CH0COMFEN (def=0x0) // Output Compare 0 fast enable
-
[0:1]CH0MS (def=0x0) // Capture/Compare 0 selection
0x40018418CHCTL0_Input// capture/compare mode register 0 (input mode)
-
[4:7]CH0CAPFLT (def=0x0) // Input capture 0 filter
-
[2:3]CH0CAPPSC (def=0x0) // Input capture 0 prescaler
-
[0:1]CH0MS (def=0x0) // Capture/Compare 0 selection
0x40018420CHCTL2// capture/compare enable register
-
[3]CH0NP (def=0x0) // Capture/Compare 0 output Polarity
-
[2]CH0NEN (def=0x0) // Capture/Compare 0 complementary output enable
-
[1]CH0P (def=0x0) // Capture/Compare 0 output Polarity
-
[0]CH0EN (def=0x0) // Capture/Compare 0 output enable
0x40018424CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40018428PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4001842CCAR// auto-reload register
-
[0:15]CARL (def=0x0) // Auto-reload value
0x40018430CREP// repetition counter register
-
[0:7]CREP (def=0x0) // Repetition counter value
0x40018434CH0CV// capture/compare register 0
-
[0:15]CH0VAL (def=0x0) // Capture/Compare 0 value
0x40018444CCHP// break and dead-time register
-
[15]POEN (def=0x0) // Main output enable
-
[14]OAEN (def=0x0) // Automatic output enable
-
[13]BRKP (def=0x0) // Break polarity
-
[12]BRKEN (def=0x0) // Break enable
-
[11]ROS (def=0x0) // Off-state selection for Run mode
-
[10]IOS (def=0x0) // Off-state selection for Idle mode
-
[8:9]PROT (def=0x0) // complementary register protect control
-
[0:7]DTCFG (def=0x0) // Dead-time generator setup
0x40018448DMACFG// DMA configuration register
-
[8:12]DMATC (def=0x0) // DMA transfer count
-
[0:4]DMATA (def=0x0) // DMA transfer access start address
0x4001844CDMATB// DMA transfer buffer register
-
[0:15]DMATB (def=0x0) // DMA register for burst accesses
0x400184FCCFG// configuration register
-
[0]OUTSEL (def=0x0) // The output value selection
-
[1]CHVSEL (def=0x0) // Write CHxVAL register selection
0x40000400TIMER2// General-purpose-timers
0x40000400CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload preload enable
-
[5:6]CAM (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]SPM (def=0x0) // One-pulse mode
-
[2]UPS (def=0x0) // Update request source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000404CTL1// control register 1
-
[7]TI0S (def=0x0) // TI0 selection
-
[4:6]MMC (def=0x0) // Master mode selection
-
[3]DMAS (def=0x0) // Capture/compare DMA selection
0x40000408SMCFG// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]SMC1 (def=0x0) // External clock enable
-
[12:13]ETPSC (def=0x0) // External trigger prescaler
-
[8:11]ETFC (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
0x4000040CDMAINTEN// DMA/Interrupt enable register
-
[14]TRGDEN (def=0x0) // Trigger DMA request enable
-
[12]CH3DEN (def=0x0) // Capture/Compare 3 DMA request enable
-
[11]CH2DEN (def=0x0) // Capture/Compare 2 DMA request enable
-
[10]CH1DEN (def=0x0) // Capture/Compare 1 DMA request enable
-
[9]CH0DEN (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[6]TRGIE (def=0x0) // Trigger interrupt enable
-
[4]CH3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[3]CH2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[2]CH1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[1]CH0IE (def=0x0) // Capture/Compare 0 interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40000410INTF// interrupt flag register
-
[12]CH3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[11]CH2OF (def=0x0) // Capture/Compare 2 overcapture flag
-
[10]CH1OF (def=0x0) // Capture/compare 1 overcapture flag
-
[9]CH0OF (def=0x0) // Capture/Compare 0 overcapture flag
-
[6]TRGIF (def=0x0) // Trigger interrupt flag
-
[4]CH3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[3]CH2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[2]CH1IF (def=0x0) // Capture/Compare 1 interrupt flag
-
[1]CH0IF (def=0x0) // Capture/compare 0 interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40000414SWEVG// event generation register
-
[6]TRGG (def=0x0) // Trigger generation
-
[4]CH3G (def=0x0) // Capture/compare 3 generation
-
[3]CH2G (def=0x0) // Capture/compare 2 generation
-
[2]CH1G (def=0x0) // Capture/compare 1 generation
-
[1]CH0G (def=0x0) // Capture/compare 0 generation
-
[0]UPG (def=0x0) // Update generation
0x40000418CHCTL0_Output// capture/compare mode register 0 (output mode)
-
[15]CH1COMCEN (def=0x0) // Output compare 1 clear enable
-
[12:14]CH1COMCTL (def=0x0) // Output compare 1 mode
-
[11]CH1COMSEN (def=0x0) // Output compare 1 preload enable
-
[10]CH1COMFEN (def=0x0) // Output compare 1 fast enable
-
[8:9]CH1MS (def=0x0) // Capture/Compare 1 selection
-
[7]CH0COMCEN (def=0x0) // Output compare 0 clear enable
-
[4:6]CH0COMCTL (def=0x0) // Output compare 0 mode
-
[3]CH0COMSEN (def=0x0) // Output compare 0 preload enable
-
[2]CH0COMFEN (def=0x0) // Output compare 0 fast enable
-
[0:1]CH0MS (def=0x0) // Capture/Compare 0 selection
0x40000418CHCTL0_Input// capture/compare mode register 0 (input mode)
-
[12:15]CH1CAPFLT (def=0x0) // Input capture 1 filter
-
[10:11]CH1CAPPSC (def=0x0) // Input capture 1 prescaler
-
[8:9]CH1MS (def=0x0) // Capture/compare 1 selection
-
[4:7]CH0CAPFLT (def=0x0) // Input capture 0 filter
-
[2:3]CH0CAPPSC (def=0x0) // Input capture 0 prescaler
-
[0:1]CH0MS (def=0x0) // Capture/Compare 0 selection
0x4000041CCHCTL1_Output// capture/compare mode register 1 (output mode)
-
[15]CH3COMCEN (def=0x0) // Output compare 3 clear enable
-
[12:14]CH3COMCTL (def=0x0) // Output compare 3 mode
-
[11]CH3COMSEN (def=0x0) // Output compare 3 preload enable
-
[10]CH3COMFEN (def=0x0) // Output compare 3 fast enable
-
[8:9]CH3MS (def=0x0) // Capture/Compare 3 selection
-
[7]CH2COMCEN (def=0x0) // Output compare 2 clear enable
-
[4:6]CH2COMCTL (def=0x0) // Output compare 2 mode
-
[3]CH2COMSEN (def=0x0) // Output compare 2 preload enable
-
[2]CH2COMFEN (def=0x0) // Output compare 2 fast enable
-
[0:1]CH2MS (def=0x0) // Capture/Compare 2 selection
0x4000041CCHCTL1_Input// capture/compare mode register 1 (input mode)
-
[12:15]CH3CAPFLT (def=0x0) // Input capture 3 filter
-
[10:11]CH3CAPPSC (def=0x0) // Input capture 3 prescaler
-
[8:9]CH3MS (def=0x0) // Capture/Compare 3 selection
-
[4:7]CH2CAPFLT (def=0x0) // Input capture 2 filter
-
[2:3]CH2CAPPSC (def=0x0) // Input capture 2 prescaler
-
[0:1]CH2MS (def=0x0) // Capture/Compare 2 selection
0x40000420CHCTL2// capture/compare enable register
-
[15]CH3NP (def=0x0) // Capture/Compare 3 output Polarity
-
[13]CH3P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CH3EN (def=0x0) // Capture/Compare 3 output enable
-
[11]CH2NP (def=0x0) // Capture/Compare 2 output Polarity
-
[9]CH2P (def=0x0) // Capture/Compare 2 output Polarity
-
[8]CH2EN (def=0x0) // Capture/Compare 2 output enable
-
[7]CH1NP (def=0x0) // Capture/Compare 1 output Polarity
-
[5]CH1P (def=0x0) // Capture/Compare 1 output Polarity
-
[4]CH1EN (def=0x0) // Capture/Compare 1 output enable
-
[3]CH0NP (def=0x0) // Capture/Compare 0 output Polarity
-
[1]CH0P (def=0x0) // Capture/Compare 0 output Polarity
-
[0]CH0EN (def=0x0) // Capture/Compare 0 output enable
0x40000424CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40000428PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4000042CCAR// auto-reload register
-
[0:15]CARL (def=0x0) // Low Auto-reload value
0x40000434CH0CV// capture/compare register 1
-
[0:15]CH0VAL (def=0x0) // Low Capture/Compare 1 value
0x40000438CH1CV// capture/compare register 2
-
[0:15]CH1VAL (def=0x0) // Low Capture/Compare 2 value
0x4000043CCH2CV// capture/compare register 2
-
[0:15]CH2VAL (def=0x0) // High Capture/Compare value (TIM2 only)
0x40000440CH3CV// capture/compare register 3
-
[0:15]CH3VAL (def=0x0) // High Capture/Compare value (TIM2 only)
0x40000448DMACFG// DMA control register
-
[8:12]DMATC (def=0x0) // DMA burst length
-
[0:4]DMATA (def=0x0) // DMA base address
0x4000044CDMATB// DMA address for full transfer
-
[0:15]DMATB (def=0x0) // DMA register for burst accesses
0x40000450IRMP// Channel input remap register
-
[6:7]CI3_RMP (def=0x0) // Channel 3 input remap
0x400004FCCFG// Configuration
-
[1]CHVSEL (def=0x0) // Write CHxVAL register selection
0x40001000TIMER5// Basic-timers
0x40001000CTL0// control register 0
-
[7]ARSE (def=0x0) // Auto-reload preload enable
-
[3]SPM (def=0x0) // One-pulse mode
-
[2]UPS (def=0x0) // Update request source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40001004CTL1// control register 1
-
[4:6]MMC (def=0x0) // Master mode selection
0x4000100CDMAINTEN// DMA/Interrupt enable register
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40001010INTF// status register
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40001014SWEVG// event generation register
-
[0]UPG (def=0x0) // Update generation
0x40001024CNT// counter
-
[0:15]CNT (def=0x0) // Low counter value
0x40001028PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4000102CCAR// auto-reload register
-
[0:15]CARL (def=0x0) // Low Auto-reload value
0x4C060800TRNG// True random number generator
0x4C060800CTL// Control register
-
[3]IE (def=0x0) // Interrupt enabled bit
-
[2]TRNGEN (def=0x0) // TRNG enabled bit
0x4C060804STAT// Status register
-
[6]SEIF (def=0x0) // Seed error interrupt flag
-
[5]CEIF (def=0x0) // Clock error interrupt flag
-
[2]SECS (def=0x0) // Seed error current status
-
[1]CECS (def=0x0) // Clock error current status
-
[0]DRDY (def=0x0) // Random data ready status bit
0x4C060808DATA// Data register
-
[0:31]TRNDATA (def=0x0) // 32-bit random data
0x40004400UART1// Universal asynchronous receiver /transmitter
0x40004400CTL0// Control register 0
-
[21:25]DEA (def=0x0) // Driver enable assertion time
-
[16:20]DED (def=0x0) // Driver enable de-assertion time
-
[15]OVSMOD (def=0x0) // Oversample mode
-
[14]AMIE (def=0x0) // ADDR match interrupt enable
-
[13]MEN (def=0x0) // Mute mode enable
-
[12]WL (def=0x0) // Word length
-
[11]WM (def=0x0) // Wakeup method in mute mode
-
[10]PCEN (def=0x0) // Parity control enable
-
[9]PM (def=0x0) // Parity mode
-
[8]PERRIE (def=0x0) // Parity error interrupt enable
-
[7]TBEIE (def=0x0) // Transmitter register empty interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RBNEIE (def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE line detected interrupt enable
-
[3]TEN (def=0x0) // Transmitter enable
-
[2]REN (def=0x0) // Receiver enable
-
[0]UEN (def=0x0) // USART enable
0x40004404CTL1// Control register 1
-
[24:31]ADDR (def=0x0) // Address of the USART terminal
-
[19]MSBF (def=0x0) // Most significant bit first
-
[18]DINV (def=0x0) // Data bit level inversion
-
[17]TINV (def=0x0) // TX pin level inversion
-
[16]RINV (def=0x0) // RX pin level inversion
-
[15]STRP (def=0x0) // Swap TX/RX pins
-
[12:13]STB (def=0x0) // STOP bits length
-
[10]CPL (def=0x0) // Clock polarity
-
[9]CPH (def=0x0) // Clock phase
-
[8]CLEN (def=0x0) // CK length
-
[4]ADDM (def=0x0) // Address detection mode
0x40004408CTL2// Control register 2
-
[15]DEP (def=0x0) // Driver enable polarity mode
-
[14]DEM (def=0x0) // Driver enable mode
-
[13]DDRE (def=0x0) // Disable DMA on reception error
-
[12]OVRD (def=0x0) // Overrun disable
-
[11]OSB (def=0x0) // One sample bit method
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSEN (def=0x0) // CTS enable
-
[8]RTSEN (def=0x0) // RTS enable
-
[7]DENT (def=0x0) // DMA enable for transmission
-
[6]DENR (def=0x0) // DMA enable for reception
-
[3]HDEN (def=0x0) // Half-duplex enable
-
[2]IRLP (def=0x0) // IrDA low-power
-
[0]ERRIE (def=0x0) // Error interrupt enable
0x4000440CBAUD// Baud rate generator register
-
[4:15]BRR_INT (def=0x0) // Integer of baud-rate divider
-
[0:3]BRR_FRA (def=0x0) // Fraction of baud-rate divider
0x40004418CMD// Command register
-
[3]RXFCMD (def=0x0) // Receive data flush command
-
[2]MMCMD (def=0x0) // Mute mode command
-
[1]SBKCMD (def=0x0) // Send break command
0x4000441CSTAT// Status register
-
[22]REA (def=0x0) // Receive enable acknowledge flag
-
[21]TEA (def=0x0) // Transmit enable acknowledge flag
-
[19]RWU (def=0x0) // Receiver wakeup from mute mode
-
[18]SBF (def=0x0) // Send break flag
-
[17]AMF (def=0x0) // ADDR match flag
-
[16]BSY (def=0x0) // Busy flag
-
[10]CTS (def=0x0) // CTS level
-
[9]CTSF (def=0x0) // CTS change flag
-
[7]TBE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission completed
-
[5]RBNE (def=0x0) // Read data buffer not empty
-
[4]IDLEF (def=0x0) // IDLE line detected flag
-
[3]ORERR (def=0x0) // Overrun error
-
[2]NERR (def=0x0) // Noise error flag
-
[1]FERR (def=0x0) // Frame error flag
-
[0]PERR (def=0x0) // Parity error flag
0x40004420INTC// Interrupt status clear register
-
[17]AMC (def=0x0) // ADDR match clear
-
[9]CTSC (def=0x0) // CTS change clear
-
[6]TCC (def=0x0) // Transmission complete clear
-
[4]IDLEC (def=0x0) // Idle line detected clear
-
[3]OREC (def=0x0) // Overrun error clear
-
[2]NEC (def=0x0) // Noise detected clear
-
[1]FEC (def=0x0) // Frame error flag clear
-
[0]PEC (def=0x0) // Parity error clear
0x40004424RDATA// Receive data register
-
[0:8]RDATA (def=0x0) // Receive data value
0x40004428TDATA// Transmit data register
-
[0:8]TDATA (def=0x0) // Transmit data value
0x400044C0CHC// USART coherence control register
-
[8]EPERR (def=0x0) // Early parity error flag
-
[0]HCM (def=0x0) // Hardware flow control coherence mode
0x400044D0RFCS// USART receive FIFO control and status register
-
[15]RFFINT (def=0x0) // Receive FIFO full interrupt flag
-
[12:14]RFCNT (def=0x0) // Receive FIFO counter number
-
[11]RFF (def=0x0) // Receive FIFO full flag
-
[10]RFE (def=0x1) // Receive FIFO empty flag
-
[9]RFFIE (def=0x0) // Receive FIFO full interrupt enable
-
[8]RFEN (def=0x0) // Receive FIFO enable
0x40011000UART2//
0x40011000CTL0// Control register 0
-
[21:25]DEA (def=0x0) // Driver enable assertion time
-
[16:20]DED (def=0x0) // Driver enable de-assertion time
-
[15]OVSMOD (def=0x0) // Oversample mode
-
[14]AMIE (def=0x0) // ADDR match interrupt enable
-
[13]MEN (def=0x0) // Mute mode enable
-
[12]WL (def=0x0) // Word length
-
[11]WM (def=0x0) // Wakeup method in mute mode
-
[10]PCEN (def=0x0) // Parity control enable
-
[9]PM (def=0x0) // Parity mode
-
[8]PERRIE (def=0x0) // Parity error interrupt enable
-
[7]TBEIE (def=0x0) // Transmitter register empty interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RBNEIE (def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE line detected interrupt enable
-
[3]TEN (def=0x0) // Transmitter enable
-
[2]REN (def=0x0) // Receiver enable
-
[0]UEN (def=0x0) // USART enable
0x40011004CTL1// Control register 1
-
[24:31]ADDR (def=0x0) // Address of the USART terminal
-
[19]MSBF (def=0x0) // Most significant bit first
-
[18]DINV (def=0x0) // Data bit level inversion
-
[17]TINV (def=0x0) // TX pin level inversion
-
[16]RINV (def=0x0) // RX pin level inversion
-
[15]STRP (def=0x0) // Swap TX/RX pins
-
[12:13]STB (def=0x0) // STOP bits length
-
[10]CPL (def=0x0) // Clock polarity
-
[9]CPH (def=0x0) // Clock phase
-
[8]CLEN (def=0x0) // CK length
-
[4]ADDM (def=0x0) // Address detection mode
0x40011008CTL2// Control register 2
-
[15]DEP (def=0x0) // Driver enable polarity mode
-
[14]DEM (def=0x0) // Driver enable mode
-
[13]DDRE (def=0x0) // Disable DMA on reception error
-
[12]OVRD (def=0x0) // Overrun disable
-
[11]OSB (def=0x0) // One sample bit method
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSEN (def=0x0) // CTS enable
-
[8]RTSEN (def=0x0) // RTS enable
-
[7]DENT (def=0x0) // DMA enable for transmission
-
[6]DENR (def=0x0) // DMA enable for reception
-
[3]HDEN (def=0x0) // Half-duplex enable
-
[2]IRLP (def=0x0) // IrDA low-power
-
[0]ERRIE (def=0x0) // Error interrupt enable
0x4001100CBAUD// Baud rate generator register
-
[4:15]BRR_INT (def=0x0) // Integer of baud-rate divider
-
[0:3]BRR_FRA (def=0x0) // Fraction of baud-rate divider
0x40011018CMD// Command register
-
[3]RXFCMD (def=0x0) // Receive data flush command
-
[2]MMCMD (def=0x0) // Mute mode command
-
[1]SBKCMD (def=0x0) // Send break command
0x4001101CSTAT// Status register
-
[22]REA (def=0x0) // Receive enable acknowledge flag
-
[21]TEA (def=0x0) // Transmit enable acknowledge flag
-
[19]RWU (def=0x0) // Receiver wakeup from mute mode
-
[18]SBF (def=0x0) // Send break flag
-
[17]AMF (def=0x0) // ADDR match flag
-
[16]BSY (def=0x0) // Busy flag
-
[10]CTS (def=0x0) // CTS level
-
[9]CTSF (def=0x0) // CTS change flag
-
[7]TBE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission completed
-
[5]RBNE (def=0x0) // Read data buffer not empty
-
[4]IDLEF (def=0x0) // IDLE line detected flag
-
[3]ORERR (def=0x0) // Overrun error
-
[2]NERR (def=0x0) // Noise error flag
-
[1]FERR (def=0x0) // Frame error flag
-
[0]PERR (def=0x0) // Parity error flag
0x40011020INTC// Interrupt status clear register
-
[17]AMC (def=0x0) // ADDR match clear
-
[9]CTSC (def=0x0) // CTS change clear
-
[6]TCC (def=0x0) // Transmission complete clear
-
[4]IDLEC (def=0x0) // Idle line detected clear
-
[3]OREC (def=0x0) // Overrun error clear
-
[2]NEC (def=0x0) // Noise detected clear
-
[1]FEC (def=0x0) // Frame error flag clear
-
[0]PEC (def=0x0) // Parity error clear
0x40011024RDATA// Receive data register
-
[0:8]RDATA (def=0x0) // Receive data value
0x40011028TDATA// Transmit data register
-
[0:8]TDATA (def=0x0) // Transmit data value
0x400110C0CHC// USART coherence control register
-
[8]EPERR (def=0x0) // Early parity error flag
-
[0]HCM (def=0x0) // Hardware flow control coherence mode
0x400110D0RFCS// USART receive FIFO control and status register
-
[15]RFFINT (def=0x0) // Receive FIFO full interrupt flag
-
[12:14]RFCNT (def=0x0) // Receive FIFO counter number
-
[11]RFF (def=0x0) // Receive FIFO full flag
-
[10]RFE (def=0x1) // Receive FIFO empty flag
-
[9]RFFIE (def=0x0) // Receive FIFO full interrupt enable
-
[8]RFEN (def=0x0) // Receive FIFO enable
0x40004800USART0// Universal synchronous/asynchronous receiver /transmitter
0x40004800CTL0// Control register 0
-
[27]EBIE (def=0x0) // End of Block interrupt enable
-
[26]RTIE (def=0x0) // Receiver timeout interrupt enable
-
[21:25]DEA (def=0x0) // Driver enable assertion time
-
[16:20]DED (def=0x0) // Driver enable de-assertion time
-
[15]OVSMOD (def=0x0) // Oversample mode
-
[14]AMIE (def=0x0) // ADDR match interrupt enable
-
[13]MEN (def=0x0) // Mute mode enable
-
[12]WL (def=0x0) // Word length
-
[11]WM (def=0x0) // Wakeup method in mute mode
-
[10]PCEN (def=0x0) // Parity control enable
-
[9]PM (def=0x0) // Parity mode
-
[8]PERRIE (def=0x0) // Parity error interrupt enable
-
[7]TBEIE (def=0x0) // Transmitter register empty interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RBNEIE (def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE line detected interrupt enable
-
[3]TEN (def=0x0) // Transmitter enable
-
[2]REN (def=0x0) // Receiver enable
-
[1]UESM (def=0x0) // USART enable in Deep-sleep mode
-
[0]UEN (def=0x0) // USART enable
0x40004804CTL1// Control register 1
-
[24:31]ADDR (def=0x0) // Address of the USART terminal
-
[23]RTEN (def=0x0) // Receiver timeout enable
-
[19]MSBF (def=0x0) // Most significant bit first
-
[18]DINV (def=0x0) // Data bit level inversion
-
[17]TINV (def=0x0) // TX pin level inversion
-
[16]RINV (def=0x0) // RX pin level inversion
-
[15]STRP (def=0x0) // Swap TX/RX pins
-
[14]LMEN (def=0x0) // LIN mode enable
-
[12:13]STB (def=0x0) // STOP bits length
-
[11]CKEN (def=0x0) // CK pin enable
-
[10]CPL (def=0x0) // Clock polarity
-
[9]CPH (def=0x0) // Clock phase
-
[8]CLEN (def=0x0) // CK length
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBLEN (def=0x0) // LIN break frame length
-
[4]ADDM (def=0x0) // Address detection mode
0x40004808CTL2// Control register 2
-
[22]WUIE (def=0x0) // Wakeup from deep-sleep mode interrupt enable
-
[20:21]WUM (def=0x0) // Wakeup mode from deep-sleep mode
-
[17:19]SCRTNUM (def=0x0) // Smartcard auto-retry number
-
[15]DEP (def=0x0) // Driver enable polarity mode
-
[14]DEM (def=0x0) // Driver enable mode
-
[13]DDRE (def=0x0) // Disable DMA on reception error
-
[12]OVRD (def=0x0) // Overrun disable
-
[11]OSB (def=0x0) // One sample bit method
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSEN (def=0x0) // CTS enable
-
[8]RTSEN (def=0x0) // RTS enable
-
[7]DENT (def=0x0) // DMA enable for transmission
-
[6]DENR (def=0x0) // DMA enable for reception
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NKEN (def=0x0) // NACK enable in Smartcard mode
-
[3]HDEN (def=0x0) // Half-duplex enable
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]ERRIE (def=0x0) // Error interrupt enable
0x4000480CBAUD// Baud rate generator register
-
[4:15]BRR_INT (def=0x0) // Integer of baud-rate divider
-
[0:3]BRR_FRA (def=0x0) // Fraction of baud-rate divider
0x40004810GP// Prescaler and guard time configuration register
-
[8:15]GUAT (def=0x0) // Guard time value in smartcard mode
-
[0:7]PSC (def=0x0) // Prescaler value for dividing the system clock
0x40004814RT// Receiver timeout register
-
[24:31]BL (def=0x0) // Block Length
-
[0:23]RT (def=0x0) // Receiver timeout threshold
0x40004818CMD// Command register
-
[4]TXFCMD (def=0x0) // Transmit data flush request
-
[3]RXFCMD (def=0x0) // Receive data flush command
-
[2]MMCMD (def=0x0) // Mute mode command
-
[1]SBKCMD (def=0x0) // Send break command
0x4000481CSTAT// Status register
-
[22]REA (def=0x0) // Receive enable acknowledge flag
-
[21]TEA (def=0x0) // Transmit enable acknowledge flag
-
[20]WUF (def=0x0) // Wakeup from deep-sleep mode flag
-
[19]RWU (def=0x0) // Receiver wakeup from mute mode
-
[18]SBF (def=0x0) // Send break flag
-
[17]AMF (def=0x0) // ADDR match flag
-
[16]BSY (def=0x0) // Busy flag
-
[12]EBF (def=0x0) // End of block flag
-
[11]RTF (def=0x0) // Receiver timeout flag
-
[10]CTS (def=0x0) // CTS level
-
[9]CTSF (def=0x0) // CTS change flag
-
[8]LBDF (def=0x0) // LIN break detected flag
-
[7]TBE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission completed
-
[5]RBNE (def=0x0) // Read data buffer not empty
-
[4]IDLEF (def=0x0) // IDLE line detected flag
-
[3]ORERR (def=0x0) // Overrun error
-
[2]NERR (def=0x0) // Noise error flag
-
[1]FERR (def=0x0) // Frame error flag
-
[0]PERR (def=0x0) // Parity error flag
0x40004820INTC// Interrupt status clear register
-
[20]WUC (def=0x0) // Wakeup from deep-sleep mode clear
-
[17]AMC (def=0x0) // ADDR match clear
-
[12]EBC (def=0x0) // End of block clear
-
[11]RTC (def=0x0) // Receiver timeout clear
-
[9]CTSC (def=0x0) // CTS change clear
-
[8]LBDC (def=0x0) // LIN break detected clear
-
[6]TCC (def=0x0) // Transmission complete clear
-
[4]IDLEC (def=0x0) // Idle line detected clear
-
[3]OREC (def=0x0) // Overrun error clear
-
[2]NEC (def=0x0) // Noise detected clear
-
[1]FEC (def=0x0) // Frame error flag clear
-
[0]PEC (def=0x0) // Parity error clear
0x40004824RDATA// Receive data register
-
[0:8]RDATA (def=0x0) // Receive data value
0x40004828TDATA// Transmit data register
-
[0:8]TDATA (def=0x0) // Transmit data value
0x400048C0CHC// USART coherence control register
-
[8]EPERR (def=0x0) // Early parity error flag
-
[0]HCM (def=0x0) // Hardware flow control coherence mode
0x400048D0RFCS// USART receive FIFO control and status register
-
[15]RFFINT (def=0x0) // Receive FIFO full interrupt flag
-
[12:14]RFCNT (def=0x0) // Receive FIFO counter number
-
[11]RFF (def=0x0) // Receive FIFO full flag
-
[10]RFE (def=0x1) // Receive FIFO empty flag
-
[9]RFFIE (def=0x0) // Receive FIFO full interrupt enable
-
[8]RFEN (def=0x0) // Receive FIFO enable
-
[0]ELNACK (def=0x0) // Early NACK when smartcard mode is selected
- [56] USART0 //
- [71] USART0_WK //
0x40002C00WWDGT// Window watchdog timer
0x40002C00CTL// Control register
-
[7]WDGTEN (def=0x0) // Activation bit
-
[0:6]CNT (def=0x7F) // 7-bit counter
0x40002C04CFG// Configuration register
-
[9]EWIE (def=0x0) // Early wakeup interrupt
-
[7:8]PSC (def=0x0) // Prescaler
-
[0:6]WIN (def=0x7F) // 7-bit window value
0x40002C08STAT// Status register
-
[0]EWIF (def=0x0) // Early wakeup interrupt flag