CH32V208xx
0x40005C00USB// Universal serial bus full-speed device interface
0x40005C00EPR0// endpoint 0 register
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[0:3]EA (def=0x0) // Endpoint address
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[4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
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[6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
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[7]CTR_TX (def=0x0) // Correct Transfer for transmission
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[8]EP_KIND (def=0x0) // Endpoint kind
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[9:10]EP_TYPE (def=0x0) // Endpoint type
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[11]SETUP (def=0x0) // Setup transaction completed
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[12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
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[14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
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[15]CTR_RX (def=0x0) // Correct transfer for reception
0x40005C04EPR1// endpoint 1 register
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[0:3]EA (def=0x0) // Endpoint address
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[4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
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[6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
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[7]CTR_TX (def=0x0) // Correct Transfer for transmission
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[8]EP_KIND (def=0x0) // Endpoint kind
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[9:10]EP_TYPE (def=0x0) // Endpoint type
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[11]SETUP (def=0x0) // Setup transaction completed
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[12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
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[14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
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[15]CTR_RX (def=0x0) // Correct transfer for reception
0x40005C08EPR2// endpoint 2 register
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[0:3]EA (def=0x0) // Endpoint address
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[4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
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[6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
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[7]CTR_TX (def=0x0) // Correct Transfer for transmission
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[8]EP_KIND (def=0x0) // Endpoint kind
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[9:10]EP_TYPE (def=0x0) // Endpoint type
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[11]SETUP (def=0x0) // Setup transaction completed
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[12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
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[14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
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[15]CTR_RX (def=0x0) // Correct transfer for reception
0x40005C0CEPR3// endpoint 3 register
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[0:3]EA (def=0x0) // Endpoint address
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[4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
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[6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
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[7]CTR_TX (def=0x0) // Correct Transfer for transmission
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[8]EP_KIND (def=0x0) // Endpoint kind
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[9:10]EP_TYPE (def=0x0) // Endpoint type
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[11]SETUP (def=0x0) // Setup transaction completed
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[12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
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[14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
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[15]CTR_RX (def=0x0) // Correct transfer for reception
0x40005C10EPR4// endpoint 4 register
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[0:3]EA (def=0x0) // Endpoint address
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[4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
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[6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
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[7]CTR_TX (def=0x0) // Correct Transfer for transmission
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[8]EP_KIND (def=0x0) // Endpoint kind
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[9:10]EP_TYPE (def=0x0) // Endpoint type
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[11]SETUP (def=0x0) // Setup transaction completed
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[12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
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[14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
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[15]CTR_RX (def=0x0) // Correct transfer for reception
0x40005C14EPR5// endpoint 5 register
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[0:3]EA (def=0x0) // Endpoint address
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[4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
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[6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
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[7]CTR_TX (def=0x0) // Correct Transfer for transmission
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[8]EP_KIND (def=0x0) // Endpoint kind
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[9:10]EP_TYPE (def=0x0) // Endpoint type
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[11]SETUP (def=0x0) // Setup transaction completed
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[12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
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[14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
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[15]CTR_RX (def=0x0) // Correct transfer for reception
0x40005C18EPR6// endpoint 6 register
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[0:3]EA (def=0x0) // Endpoint address
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[4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
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[6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
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[7]CTR_TX (def=0x0) // Correct Transfer for transmission
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[8]EP_KIND (def=0x0) // Endpoint kind
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[9:10]EP_TYPE (def=0x0) // Endpoint type
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[11]SETUP (def=0x0) // Setup transaction completed
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[12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
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[14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
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[15]CTR_RX (def=0x0) // Correct transfer for reception
0x40005C1CEPR7// endpoint 7 register
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[0:3]EA (def=0x0) // Endpoint address
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[4:5]STAT_TX (def=0x0) // Status bits, for transmission transfers
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[6]DTOG_TX (def=0x0) // Data Toggle, for transmission transfers
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[7]CTR_TX (def=0x0) // Correct Transfer for transmission
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[8]EP_KIND (def=0x0) // Endpoint kind
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[9:10]EP_TYPE (def=0x0) // Endpoint type
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[11]SETUP (def=0x0) // Setup transaction completed
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[12:13]STAT_RX (def=0x0) // Status bits, for reception transfers
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[14]DTOG_RX (def=0x0) // Data Toggle, for reception transfers
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[15]CTR_RX (def=0x0) // Correct transfer for reception
0x40005C40CNTR// control register
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[0]FRES (def=0x1) // Force USB Reset
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[1]PDWN (def=0x1) // Power down
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[2]LPMODE (def=0x0) // Low-power mode
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[3]FSUSP (def=0x0) // Force suspend
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[4]RESUME (def=0x0) // Resume request
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[8]ESOFM (def=0x0) // Expected start of frame interrupt mask
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[9]SOFM (def=0x0) // Start of frame interrupt mask
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[10]RESETM (def=0x0) // USB reset interrupt mask
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[11]SUSPM (def=0x0) // Suspend mode interrupt mask
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[12]WKUPM (def=0x0) // Wakeup interrupt mask
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[13]ERRM (def=0x0) // Error interrupt mask
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[14]PMAOVRM (def=0x0) // Packet memory area over / underrun interrupt mask
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[15]CTRM (def=0x0) // Correct transfer interrupt mask
0x40005C44ISTR// interrupt status register
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[0:3]EP_ID (def=0x0) // Endpoint Identifier
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[4]DIR (def=0x0) // Direction of transaction
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[8]ESOF (def=0x0) // Expected start frame
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[9]SOF (def=0x0) // start of frame
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[10]RST (def=0x0) // reset request
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[11]SUSP (def=0x0) // Suspend mode request
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[12]WKUP (def=0x0) // Wakeup
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[13]ERR (def=0x0) // Error
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[14]PMAOVR (def=0x0) // Packet memory area over / underrun
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[15]CTR (def=0x0) // Correct transfer
0x40005C48FNR// frame number register
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[0:10]FN (def=0x0) // Frame number
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[11:12]LSOF (def=0x0) // Lost SOF
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[13]LCK (def=0x0) // Locked
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[14]RXDM (def=0x0) // Receive data - line status
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[15]RXDP (def=0x0) // Receive data + line status
0x40005C4CDADDR// device address
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[0:6]ADD (def=0x0) // Device address
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[7]EF (def=0x0) // Enable function
0x40005C50BTABLE// Buffer table address
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[3:15]BTABLE (def=0x0) // Buffer table
- [58] USBWakeUp // USB Device WakeUp from suspend through EXTI Line Interrupt
0x40006400CAN1// Controller area network
0x40006400CTLR// CAN Master control register
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[16]DBF (def=0x1) // Debug freeze
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[15]RST (def=0x0) // Software master reset
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[7]TTCM (def=0x0) // Time triggered communication mode
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[6]ABOM (def=0x0) // Automatic bus-off management
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[5]AWUM (def=0x0) // Automatic wakeup mode
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[4]NART (def=0x0) // No automatic retransmission
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[3]RFLM (def=0x0) // Receive FIFO locked mode
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[2]TXFP (def=0x0) // Transmit FIFO priority
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[1]SLEEP (def=0x1) // Sleep mode request
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[0]INRQ (def=0x0) // Initialization request
0x40006404STATR// CAN master status register
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[11]RX (def=0x1) // Rx signal
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[10]SAMP (def=0x1) // Last sample point
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[9]RXM (def=0x0) // Receive mode
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[8]TXM (def=0x0) // Transmit mode
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[4]SLAKI (def=0x0) // Sleep acknowledge interrupt
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[3]WKUI (def=0x0) // Wakeup interrupt
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[2]ERRI (def=0x0) // Error interrupt
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[1]SLAK (def=0x1) // Sleep acknowledge
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[0]INAK (def=0x0) // Initialization acknowledge
0x40006408TSTATR// CAN transmit status register
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[31]LOW2 (def=0x0) // Lowest priority flag for mailbox 2
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[30]LOW1 (def=0x0) // Lowest priority flag for mailbox 1
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[29]LOW0 (def=0x0) // Lowest priority flag for mailbox 0
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[28]TME2 (def=0x1) // Transmit mailbox 2 empty
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[27]TME1 (def=0x1) // Transmit mailbox 1 empty
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[26]TME0 (def=0x1) // Transmit mailbox 0 empty
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[24:25]CODE (def=0x0) // Mailbox code
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[23]ABRQ2 (def=0x0) // Abort request for mailbox 2
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[19]TERR2 (def=0x0) // Transmission error of mailbox 2
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[18]ALST2 (def=0x0) // Arbitration lost for mailbox 2
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[17]TXOK2 (def=0x0) // Transmission OK of mailbox 2
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[16]RQCP2 (def=0x0) // Request completed mailbox2
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[15]ABRQ1 (def=0x0) // Abort request for mailbox 1
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[11]TERR1 (def=0x0) // Transmission error of mailbox1
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[10]ALST1 (def=0x0) // Arbitration lost for mailbox1
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[9]TXOK1 (def=0x0) // Transmission OK of mailbox1
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[8]RQCP1 (def=0x0) // Request completed mailbox1
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[7]ABRQ0 (def=0x0) // Abort request for mailbox0
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[3]TERR0 (def=0x0) // Transmission error of mailbox0
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[2]ALST0 (def=0x0) // Arbitration lost for mailbox0
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[1]TXOK0 (def=0x0) // Transmission OK of mailbox0
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[0]RQCP0 (def=0x0) // Request completed mailbox0
0x4000640CRFIFO0// CAN receive FIFO 0 register
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[5]RFOM0 (def=0x0) // Release FIFO 0 output mailbox
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[4]FOVR0 (def=0x0) // FIFO 0 overrun
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[3]FULL0 (def=0x0) // FIFO 0 full
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[0:1]FMP0 (def=0x0) // FIFO 0 message pending
0x40006410RFIFO1// CAN receive FIFO 1 register
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[5]RFOM1 (def=0x0) // Release FIFO 1 output mailbox
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[4]FOVR1 (def=0x0) // FIFO 1 overrun
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[3]FULL1 (def=0x0) // FIFO 1 full
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[0:1]FMP1 (def=0x0) // FIFO 1 message pending
0x40006414INTENR// CAN interrupt enable register
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[17]SLKIE (def=0x0) // Sleep interrupt enable
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[16]WKUIE (def=0x0) // Wakeup interrupt enable
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[15]ERRIE (def=0x0) // Error interrupt enable
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[11]LECIE (def=0x0) // Last error code interrupt enable
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[10]BOFIE (def=0x0) // Bus-off interrupt enable
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[9]EPVIE (def=0x0) // Error passive interrupt enable
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[8]EWGIE (def=0x0) // Error warning interrupt enable
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[6]FOVIE1 (def=0x0) // FIFO overrun interrupt enable
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[5]FFIE1 (def=0x0) // FIFO full interrupt enable
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[4]FMPIE1 (def=0x0) // FIFO message pending interrupt enable
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[3]FOVIE0 (def=0x0) // FIFO overrun interrupt enable
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[2]FFIE0 (def=0x0) // FIFO full interrupt enable
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[1]FMPIE0 (def=0x0) // FIFO message pending interrupt enable
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[0]TMEIE (def=0x0) // Transmit mailbox empty interrupt enable
0x40006418ERRSR// CAN error status register
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[24:31]REC (def=0x0) // Receive error counter
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[16:23]TEC (def=0x0) // Least significant byte of the 9-bit transmit error counter
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[4:6]LEC (def=0x0) // Last error code
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[2]BOFF (def=0x0) // Bus-off flag
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[1]EPVF (def=0x0) // Error passive flag
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[0]EWGF (def=0x0) // Error warning flag
0x4000641CBTIMR// CAN bit timing register
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[31]SILM (def=0x0) // Silent mode (debug)
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[30]LBKM (def=0x0) // Loop back mode (debug)
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[24:25]SJW (def=0x1) // Resynchronization jump width
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[20:22]TS2 (def=0x2) // Time segment 2
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[16:19]TS1 (def=0x3) // Time segment 1
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[0:9]BRP (def=0x0) // Baud rate prescaler
0x40006580TXMIR0// CAN TX mailbox identifier register
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[21:31]STID (def=0x0) // Standard identifier
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[3:20]EXID (def=0x0) // extended identifier
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[2]IDE (def=0x0) // Identifier extension
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[1]RTR (def=0x0) // Remote transmission request
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[0]TXRQ (def=0x0) // Transmit mailbox request
0x40006584TXMDTR0// CAN mailbox data length control and time stamp register
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[16:31]TIME (def=0x0) // Message time stamp
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[8]TGT (def=0x0) // Transmit global time
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[0:3]DLC (def=0x0) // Data length code
0x40006588TXMDLR0// CAN mailbox data low register
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[24:31]DATA3 (def=0x0) // Data byte 3
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[16:23]DATA2 (def=0x0) // Data byte 2
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[8:15]DATA1 (def=0x0) // Data byte 1
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[0:7]DATA0 (def=0x0) // Data byte 0
0x4000658CTXMDHR0// CAN mailbox data high register
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[24:31]DATA7 (def=0x0) // Data byte 7
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[16:23]DATA6 (def=0x0) // Data byte 6
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[8:15]DATA5 (def=0x0) // Data byte 5
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[0:7]DATA4 (def=0x0) // Data byte 4
0x40006590TXMIR1// CAN TX mailbox identifier register
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[21:31]STID (def=0x0) // Standard identifier
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[3:20]EXID (def=0x0) // extended identifier
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[2]IDE (def=0x0) // Identifier extension
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[1]RTR (def=0x0) // Remote transmission request
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[0]TXRQ (def=0x0) // Transmit mailbox request
0x40006594TXMDTR1// CAN mailbox data length control and time stamp register
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[16:31]TIME (def=0x0) // Message time stamp
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[8]TGT (def=0x0) // Transmit global time
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[0:3]DLC (def=0x0) // Data length code
0x40006598TXMDLR1// CAN mailbox data low register
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[24:31]DATA3 (def=0x0) // Data byte 3
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[16:23]DATA2 (def=0x0) // Data byte 2
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[8:15]DATA1 (def=0x0) // Data byte 1
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[0:7]DATA0 (def=0x0) // Data byte 0
0x4000659CTXMDHR1// CAN mailbox data high register
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[24:31]DATA7 (def=0x0) // Data byte 7
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[16:23]DATA6 (def=0x0) // Data byte 6
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[8:15]DATA5 (def=0x0) // Data byte 5
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[0:7]DATA4 (def=0x0) // Data byte 4
0x400065A0TXMIR2// CAN TX mailbox identifier register
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[21:31]STID (def=0x0) // Standard identifier
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[3:20]EXID (def=0x0) // extended identifier
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[2]IDE (def=0x0) // Identifier extension
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[1]RTR (def=0x0) // Remote transmission request
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[0]TXRQ (def=0x0) // Transmit mailbox request
0x400065A4TXMDTR2// CAN mailbox data length control and time stamp register
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[16:31]TIME (def=0x0) // Message time stamp
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[8]TGT (def=0x0) // Transmit global time
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[0:3]DLC (def=0x0) // Data length code
0x400065A8TXMDLR2// CAN mailbox data low register
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[24:31]DATA3 (def=0x0) // Data byte 3
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[16:23]DATA2 (def=0x0) // Data byte 2
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[8:15]DATA1 (def=0x0) // Data byte 1
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[0:7]DATA0 (def=0x0) // Data byte 0
0x400065ACTXMDHR2// CAN mailbox data high register
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[24:31]DATA7 (def=0x0) // Data byte 7
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[16:23]DATA6 (def=0x0) // Data byte 6
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[8:15]DATA5 (def=0x0) // Data byte 5
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[0:7]DATA4 (def=0x0) // Data byte 4
0x400065B0RXMIR0// CAN receive FIFO mailbox identifier register
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[21:31]STID (def=0x0) // Standard identifier
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[3:20]EXID (def=0x0) // extended identifier
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[2]IDE (def=0x0) // Identifier extension
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[1]RTR (def=0x0) // Remote transmission request
0x400065B4RXMDTR0// CAN receive FIFO mailbox data length control and time stamp register
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[16:31]TIME (def=0x0) // Message time stamp
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[8:15]FMI (def=0x0) // Filter match index
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[0:3]DLC (def=0x0) // Data length code
0x400065B8RXMDLR0// CAN receive FIFO mailbox data low register
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[24:31]DATA3 (def=0x0) // Data Byte 3
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[16:23]DATA2 (def=0x0) // Data Byte 2
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[8:15]DATA1 (def=0x0) // Data Byte 1
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[0:7]DATA0 (def=0x0) // Data Byte 0
0x400065BCRXMDHR0// CAN receive FIFO mailbox data high register
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[24:31]DATA7 (def=0x0) // DATA7
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[16:23]DATA6 (def=0x0) // DATA6
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[8:15]DATA5 (def=0x0) // DATA5
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[0:7]DATA4 (def=0x0) // DATA4
0x400065C0RXMIR1// CAN receive FIFO mailbox identifier register
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[21:31]STID (def=0x0) // Standard identifier
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[3:20]EXID (def=0x0) // extended identifier
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[2]IDE (def=0x0) // Identifier extension
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[1]RTR (def=0x0) // Remote transmission request
0x400065C4RXMDTR1// CAN receive FIFO mailbox data length control and time stamp register
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[16:31]TIME (def=0x0) // Message time stamp
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[8:15]FMI (def=0x0) // Filter match index
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[0:3]DLC (def=0x0) // Data length code
0x400065C8RXMDLR1// CAN receive FIFO mailbox data low register
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[24:31]DATA3 (def=0x0) // Data Byte 3
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[16:23]DATA2 (def=0x0) // Data Byte 2
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[8:15]DATA1 (def=0x0) // Data Byte 1
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[0:7]DATA0 (def=0x0) // Data Byte 0
0x400065CCRXMDHR1// CAN receive FIFO mailbox data high register
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[24:31]DATA7 (def=0x0) // DATA7
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[16:23]DATA6 (def=0x0) // DATA6
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[8:15]DATA5 (def=0x0) // DATA5
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[0:7]DATA4 (def=0x0) // DATA4
0x40006600FCTLR// CAN filter master register
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[0]FINIT (def=0x1) // Filter init mode
0x40006604FMCFGR// CAN filter mode register
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[0]FBM0 (def=0x0) // Filter mode
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[1]FBM1 (def=0x0) // Filter mode
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[2]FBM2 (def=0x0) // Filter mode
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[3]FBM3 (def=0x0) // Filter mode
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[4]FBM4 (def=0x0) // Filter mode
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[5]FBM5 (def=0x0) // Filter mode
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[6]FBM6 (def=0x0) // Filter mode
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[7]FBM7 (def=0x0) // Filter mode
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[8]FBM8 (def=0x0) // Filter mode
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[9]FBM9 (def=0x0) // Filter mode
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[10]FBM10 (def=0x0) // Filter mode
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[11]FBM11 (def=0x0) // Filter mode
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[12]FBM12 (def=0x0) // Filter mode
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[13]FBM13 (def=0x0) // Filter mode
0x4000660CFSCFGR// CAN filter scale register
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[0]FSC0 (def=0x0) // Filter scale configuration
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[1]FSC1 (def=0x0) // Filter scale configuration
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[2]FSC2 (def=0x0) // Filter scale configuration
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[3]FSC3 (def=0x0) // Filter scale configuration
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[4]FSC4 (def=0x0) // Filter scale configuration
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[5]FSC5 (def=0x0) // Filter scale configuration
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[6]FSC6 (def=0x0) // Filter scale configuration
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[7]FSC7 (def=0x0) // Filter scale configuration
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[8]FSC8 (def=0x0) // Filter scale configuration
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[9]FSC9 (def=0x0) // Filter scale configuration
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[10]FSC10 (def=0x0) // Filter scale configuration
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[11]FSC11 (def=0x0) // Filter scale configuration
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[12]FSC12 (def=0x0) // Filter scale configuration
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[13]FSC13 (def=0x0) // Filter scale configuration
0x40006614FAFIFOR// CAN filter FIFO assignment register
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[0]FFA0 (def=0x0) // Filter FIFO assignment for filter 0
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[1]FFA1 (def=0x0) // Filter FIFO assignment for filter 1
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[2]FFA2 (def=0x0) // Filter FIFO assignment for filter 2
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[3]FFA3 (def=0x0) // Filter FIFO assignment for filter 3
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[4]FFA4 (def=0x0) // Filter FIFO assignment for filter 4
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[5]FFA5 (def=0x0) // Filter FIFO assignment for filter 5
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[6]FFA6 (def=0x0) // Filter FIFO assignment for filter 6
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[7]FFA7 (def=0x0) // Filter FIFO assignment for filter 7
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[8]FFA8 (def=0x0) // Filter FIFO assignment for filter 8
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[9]FFA9 (def=0x0) // Filter FIFO assignment for filter 9
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[10]FFA10 (def=0x0) // Filter FIFO assignment for filter 10
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[11]FFA11 (def=0x0) // Filter FIFO assignment for filter 11
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[12]FFA12 (def=0x0) // Filter FIFO assignment for filter 12
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[13]FFA13 (def=0x0) // Filter FIFO assignment for filter 13
0x4000661CFWR// CAN filter activation register
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[0]FACT0 (def=0x0) // Filter active
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[1]FACT1 (def=0x0) // Filter active
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[2]FACT2 (def=0x0) // Filter active
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[3]FACT3 (def=0x0) // Filter active
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[4]FACT4 (def=0x0) // Filter active
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[5]FACT5 (def=0x0) // Filter active
-
[6]FACT6 (def=0x0) // Filter active
-
[7]FACT7 (def=0x0) // Filter active
-
[8]FACT8 (def=0x0) // Filter active
-
[9]FACT9 (def=0x0) // Filter active
-
[10]FACT10 (def=0x0) // Filter active
-
[11]FACT11 (def=0x0) // Filter active
-
[12]FACT12 (def=0x0) // Filter active
-
[13]FACT13 (def=0x0) // Filter active
0x40006640F0R1// Filter bank 0 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006644F0R2// Filter bank 0 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006648F1R1// Filter bank 1 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x4000664CF1R2// Filter bank 1 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006650F2R1// Filter bank 2 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006654F2R2// Filter bank 2 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006658F3R1// Filter bank 3 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x4000665CF3R2// Filter bank 3 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006660F4R1// Filter bank 4 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006664F4R2// Filter bank 4 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006668F5R1// Filter bank 5 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x4000666CF5R2// Filter bank 5 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006670F6R1// Filter bank 6 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006674F6R2// Filter bank 6 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006678F7R1// Filter bank 7 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x4000667CF7R2// Filter bank 7 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006680F8R1// Filter bank 8 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006684F8R2// Filter bank 8 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006688F9R1// Filter bank 9 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x4000668CF9R2// Filter bank 9 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006690F10R1// Filter bank 10 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006694F10R2// Filter bank 10 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006698F11R1// Filter bank 11 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x4000669CF11R2// Filter bank 11 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066A0F12R1// Filter bank 4 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066A4F12R2// Filter bank 12 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066A8F13R1// Filter bank 13 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066ACF13R2// Filter bank 13 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066B0F14R1// Filter bank 14 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066B4F14R2// Filter bank 14 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066B8F15R1// Filter bank 15 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066BCF15R2// Filter bank 15 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066C0F16R1// Filter bank 16 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066C4F16R2// Filter bank 16 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066C8F17R1// Filter bank 17 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066CCF17R2// Filter bank 17 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066D0F18R1// Filter bank 18 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066D4F18R2// Filter bank 18 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066D8F19R1// Filter bank 19 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066DCF19R2// Filter bank 19 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066E0F20R1// Filter bank 20 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066E4F20R2// Filter bank 20 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066E8F21R1// Filter bank 21 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066ECF21R2// Filter bank 21 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066F0F22R1// Filter bank 22 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066F4F22R2// Filter bank 22 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066F8F23R1// Filter bank 23 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x400066FCF23R2// Filter bank 23 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006700F24R1// Filter bank 24 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006704F24R2// Filter bank 24 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006708F25R1// Filter bank 25 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x4000670CF25R2// Filter bank 25 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006710F26R1// Filter bank 26 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006714F26R2// Filter bank 26 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x40006718F27R1// Filter bank 27 register 1
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
0x4000671CF27R2// Filter bank 27 register 2
-
[0]FB0 (def=0x0) // Filter bits
-
[1]FB1 (def=0x0) // Filter bits
-
[2]FB2 (def=0x0) // Filter bits
-
[3]FB3 (def=0x0) // Filter bits
-
[4]FB4 (def=0x0) // Filter bits
-
[5]FB5 (def=0x0) // Filter bits
-
[6]FB6 (def=0x0) // Filter bits
-
[7]FB7 (def=0x0) // Filter bits
-
[8]FB8 (def=0x0) // Filter bits
-
[9]FB9 (def=0x0) // Filter bits
-
[10]FB10 (def=0x0) // Filter bits
-
[11]FB11 (def=0x0) // Filter bits
-
[12]FB12 (def=0x0) // Filter bits
-
[13]FB13 (def=0x0) // Filter bits
-
[14]FB14 (def=0x0) // Filter bits
-
[15]FB15 (def=0x0) // Filter bits
-
[16]FB16 (def=0x0) // Filter bits
-
[17]FB17 (def=0x0) // Filter bits
-
[18]FB18 (def=0x0) // Filter bits
-
[19]FB19 (def=0x0) // Filter bits
-
[20]FB20 (def=0x0) // Filter bits
-
[21]FB21 (def=0x0) // Filter bits
-
[22]FB22 (def=0x0) // Filter bits
-
[23]FB23 (def=0x0) // Filter bits
-
[24]FB24 (def=0x0) // Filter bits
-
[25]FB25 (def=0x0) // Filter bits
-
[26]FB26 (def=0x0) // Filter bits
-
[27]FB27 (def=0x0) // Filter bits
-
[28]FB28 (def=0x0) // Filter bits
-
[29]FB29 (def=0x0) // Filter bits
-
[30]FB30 (def=0x0) // Filter bits
-
[31]FB31 (def=0x0) // Filter bits
- [35] USB_HP_CAN1_TX // CAN1 TX interrupts
- [36] USB_LP_CAN1_RX0 // CAN1 RX0 interrupts
- [37] CAN1_RX1 // CAN1 RX1 interrupt
- [38] CAN1_SCE // CAN1 SCE interrupt
0x40028000ETHERNET_MAC// Ethernet: media access control
0x40028000MACCR// Ethernet MAC configuration register (ETH_MACCR)
-
[0]TCES (def=0x0) // Send clock selection bit
-
[1]TCF (def=0x0) // Send clock reversal
-
[2]RE (def=0x0) // Receiver enable
-
[3]TE (def=0x0) // Transmitter enable
-
[4]DC (def=0x0) // Deferral check
-
[5:6]BL (def=0x0) // Back-off limit
-
[7]APCS (def=0x0) // Automatic pad/CRC stripping
-
[9]RD (def=0x0) // Retry disable
-
[10]IPCO (def=0x0) // IPv4 checksum offload
-
[11]DM (def=0x0) // Duplex mode
-
[12]LM (def=0x0) // Loopback mode
-
[13]ROD (def=0x0) // Receive own disable
-
[14]FES (def=0x0) // Fast Ethernet speed
-
[16]CSD (def=0x0) // Carrier sense disable
-
[17:19]IFG (def=0x0) // Interframe gap
-
[20]PR (def=0x0) // 10MPHY 50 Ohm set
-
[21]PI (def=0x0) // 10MPHY TX DRIVER bisa current
-
[22]JD (def=0x0) // Jabber disable
-
[23]WD (def=0x0) // Watchdog disable
-
[29:31]TCD (def=0x0) // SEND clock delay
0x40028004MACFFR// Ethernet MAC frame filter register (ETH_MACCFFR)
-
[0]PM (def=0x0) // Promiscuous mode
-
[1]HU (def=0x0) // Hash unicast
-
[2]HM (def=0x0) // Hash multicast
-
[3]DAIF (def=0x0) // Destination address inverse filtering
-
[4]PAM (def=0x0) // Pass all multicast
-
[5]BFD (def=0x0) // Broadcast frames disable
-
[6:7]PCF (def=0x0) // Pass control frames
-
[8]SAIF (def=0x0) // Source address inverse filtering
-
[9]SAF (def=0x0) // Source address filter
-
[10]HPF (def=0x0) // Hash or perfect filter
-
[31]RA (def=0x0) // Receive all
0x40028008MACHTHR// Ethernet MAC hash table high register
-
[0:31]HTH (def=0x0) // Hash table high
0x4002800CMACHTLR// Ethernet MAC hash table low register
-
[0:31]HTL (def=0x0) // Hash table low
0x40028010MACMIIAR// Ethernet MAC MII address register (ETH_MACMIIAR)
-
[0]MB (def=0x0) // MII busy
-
[1]MW (def=0x0) // MII write
-
[2:4]CR (def=0x0) // Clock range
-
[6:10]MR (def=0x0) // MII register
-
[11:15]PA (def=0x0) // PHY address
0x40028014MACMIIDR// Ethernet MAC MII data register (ETH_MACMIIDR)
-
[0:15]MD (def=0x0) // MII data
0x40028018MACFCR// Ethernet MAC flow control register (ETH_MACFCR)
-
[0]FCB_BPA (def=0x0) // Flow control busy/back pressure activate
-
[1]TFCE (def=0x0) // Transmit flow control enable
-
[2]RFCE (def=0x0) // Receive flow control enable
-
[3]UPFD (def=0x0) // Unicast pause frame detect
-
[16:31]PT (def=0x0) // Pass control frames
0x4002801CMACVLANTR// Ethernet MAC VLAN tag register (ETH_MACVLANTR)
-
[0:15]VLANTI (def=0x0) // VLAN tag identifier (for receive frames)
-
[16]VLANTC (def=0x0) // 12-bit VLAN tag comparison
0x40028028MACRWUFFR// Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)
0x4002802CMACPMTCSR// Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
-
[0]PD (def=0x0) // Power down
-
[1]MPE (def=0x0) // Magic Packet enable
-
[2]WFE (def=0x0) // Wakeup frame enable
-
[5]MPR (def=0x0) // Magic packet received
-
[6]WFR (def=0x0) // Wakeup frame received
-
[9]GU (def=0x0) // Global unicast
-
[31]WFFRPR (def=0x0) // Wakeup frame filter register pointer reset
0x40028038MACSR// Ethernet MAC interrupt status register (ETH_MACSR)
-
[3]PMTS (def=0x0) // PMT status
-
[4]MMCS (def=0x0) // MMC status
-
[5]MMCRS (def=0x0) // MMC receive status
-
[6]MMCTS (def=0x0) // MMC transmit status
-
[9]TSTS (def=0x0) // Time stamp trigger status
0x4002803CMACIMR// Ethernet MAC interrupt mask register (ETH_MACIMR)
-
[3]PMTIM (def=0x0) // PMT interrupt mask
-
[9]TSTIM (def=0x0) // Time stamp trigger interrupt mask
0x40028040MACA0HR// Ethernet MAC address 0 high register (ETH_MACA0HR)
-
[0:15]MACA0H (def=0xFFFF) // MAC address0 high
-
[31]MO (def=0x1) // Always 1
0x40028044MACA0LR// Ethernet MAC address 0 low register
-
[0:31]MACA0L (def=0xFFFFFFFF) // MAC address0 low
0x40028048MACA1HR// Ethernet MAC address 1 high register (ETH_MACA1HR)
-
[0:15]MACA1H (def=0xFFFF) // MAC address1 high
-
[24:29]MBC (def=0x0) // Mask byte control
-
[30]SA (def=0x0) // Source address
-
[31]AE (def=0x0) // Address enable
0x4002804CMACA1LR// Ethernet MAC address1 low register
-
[0:31]MACA1L (def=0xFFFFFFFF) // MAC address1 low
0x40028050MACA2HR// Ethernet MAC address 2 high register (ETH_MACA2HR)
-
[0:15]ETH_MACA2HR (def=0xFFFF) // Ethernet MAC address 2 high register
-
[24:29]MBC (def=0x0) // Mask byte control
-
[30]SA (def=0x0) // Source address
-
[31]AE (def=0x0) // Address enable
0x40028054MACA2LR// Ethernet MAC address 2 low register
-
[0:30]MACA2L (def=0x7FFFFFFF) // MAC address2 low
0x40028058MACA3HR// Ethernet MAC address 3 high register (ETH_MACA3HR)
-
[0:15]MACA3H (def=0xFFFF) // MAC address3 high
-
[24:29]MBC (def=0x0) // Mask byte control
-
[30]SA (def=0x0) // Source address
-
[31]AE (def=0x0) // Address enable
0x4002805CMACA3LR// Ethernet MAC address 3 low register
-
[0:31]MBCA3L (def=0xFFFFFFFF) // MAC address3 low
- [77] ETH // Ethernet global interrupt
- [78] ETH_WKUP // Ethernet Wakeup through EXTI line interrupt
0x40028100ETHERNET_MMC// Ethernet: MAC management counters
0x40028100MMCCR// Ethernet MMC control register (ETH_MMCCR)
-
[0]CR (def=0x0) // Counter reset
-
[1]CSR (def=0x0) // Counter stop rollover
-
[2]ROR (def=0x0) // Reset on read
-
[31]MCF (def=0x0) // MMC counter freeze
0x40028104MMCRIR// Ethernet MMC receive interrupt register (ETH_MMCRIR)
-
[5]RFCES (def=0x0) // Received frames CRC error status
-
[6]RFAES (def=0x0) // Received frames alignment error status
-
[17]RGUFS (def=0x0) // Received Good Unicast Frames Status
0x40028108MMCTIR// Ethernet MMC transmit interrupt register (ETH_MMCTIR)
-
[14]TGFSCS (def=0x0) // Transmitted good frames single collision status
-
[15]TGFMSCS (def=0x0) // Transmitted good frames more single collision status
-
[21]TGFS (def=0x0) // Transmitted good frames status
0x4002810CMMCRIMR// Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
-
[5]RFCEM (def=0x0) // Received frame CRC error mask
-
[6]RFAEM (def=0x0) // Received frames alignment error mask
-
[17]RGUFM (def=0x0) // Received good unicast frames mask
0x40028110MMCTIMR// Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
-
[14]TGFSCM (def=0x0) // Transmitted good frames single collision mask
-
[15]TGFMSCM (def=0x0) // Transmitted good frames more single collision mask
-
[21]TGFM (def=0x0) // Transmitted good frames mask
0x4002814CMMCTGFSCCR// Ethernet MMC transmitted good frames after a single collision counter
-
[0:31]TGFSCC (def=0x0) // Transmitted good frames after a single collision counter
0x40028150MMCTGFMSCCR// Ethernet MMC transmitted good frames after more than a single collision
-
[0:31]TGFMSCC (def=0x0) // Transmitted good frames after more than a single collision counter
0x40028168MMCTGFCR// Ethernet MMC transmitted good frames counter register
-
[0:31]TGFC (def=0x0) // Transmitted good frames counter
0x40028194MMCRFCECR// Ethernet MMC received frames with CRC error counter register
-
[0:31]RFCFC (def=0x0) // Received frames with CRC error counter
0x40028198MMCRFAECR// Ethernet MMC received frames with alignment error counter register
-
[0:31]RFAEC (def=0x0) // Received frames with alignment error counter
0x400281C4MMCRGUFCR// MMC received good unicast frames counter register
-
[0:31]RGUFC (def=0x0) // Received good unicast frames counter
0x40028700ETHERNET_PTP// Ethernet: Precision time protocol
0x40028700PTPTSCR// Ethernet PTP time stamp control register (ETH_PTPTSCR)
-
[0]TSE (def=0x0) // Time stamp enable
-
[1]TSFCU (def=0x0) // Time stamp fine or coarse update
-
[2]TSSTI (def=0x0) // Time stamp system time initialize
-
[3]TSSTU (def=0x0) // Time stamp system time update
-
[4]TSITE (def=0x0) // Time stamp interrupt trigger enable
-
[5]TSARU (def=0x0) // Time stamp addend register update
0x40028704PTPSSIR// Ethernet PTP subsecond increment register
-
[0:7]STSSI (def=0x0) // System time subsecond increment
0x40028708PTPTSHR// Ethernet PTP time stamp high register
-
[0:31]STS (def=0x0) // System time second
0x4002870CPTPTSLR// Ethernet PTP time stamp low register (ETH_PTPTSLR)
-
[0:30]STSS (def=0x0) // System time subseconds
-
[31]STPNS (def=0x0) // System time positive or negative sign
0x40028710PTPTSHUR// Ethernet PTP time stamp high update register
-
[0:31]TSUS (def=0x0) // Time stamp update second
0x40028714PTPTSLUR// Ethernet PTP time stamp low update register (ETH_PTPTSLUR)
-
[0:30]TSUSS (def=0x0) // Time stamp update subseconds
-
[31]TSUPNS (def=0x0) // Time stamp update positive or negative sign
0x40028718PTPTSAR// Ethernet PTP time stamp addend register
-
[0:31]TSA (def=0x0) // Time stamp addend
0x4002871CPTPTTHR// Ethernet PTP target time high register
-
[0:31]TTSH (def=0x0) // Target time stamp high
0x40028720PTPTTLR// Ethernet PTP target time low register
-
[0:31]TTSL (def=0x0) // Target time stamp low
0x40029000ETHERNET_DMA// Ethernet: DMA controller operation
0x40029000DMABMR// Ethernet DMA bus mode register
-
[0]SR (def=0x0) // Software reset
-
[1]DA (def=0x0) // DMA Arbitration
-
[2:6]DSL (def=0x0) // Descriptor skip length
-
[8:13]PBL (def=0x0) // Programmable burst length
-
[14:15]RTPR (def=0x0) // Rx Tx priority ratio
-
[16]FB (def=0x0) // Fixed burst
-
[17:22]RDP (def=0x0) // Rx DMA PBL
-
[23]USP (def=0x0) // Use separate PBL
-
[24]FPM (def=0x0) // 4xPBL mode
-
[25]AAB (def=0x0) // Address-aligned beats
0x40029004DMATPDR// Ethernet DMA transmit poll demand register
-
[0:31]TPD (def=0x0) // Transmit poll demand
0x40029008DMARPDR// EHERNET DMA receive poll demand register
-
[0:31]RPD (def=0x0) // Receive poll demand
0x4002900CDMARDLAR// Ethernet DMA receive descriptor list address register
-
[0:31]SRL (def=0x0) // Start of receive list
0x40029010DMATDLAR// Ethernet DMA transmit descriptor list address register
-
[0:31]STL (def=0x0) // Start of transmit list
0x40029014DMASR// Ethernet DMA status register
-
[0]TS (def=0x0) // Transmit status
-
[1]TPSS (def=0x0) // Transmit process stopped status
-
[2]TBUS (def=0x0) // Transmit buffer unavailable status
-
[3]TJTS (def=0x0) // Transmit jabber timeout status
-
[4]ROS (def=0x0) // Receive overflow status
-
[5]TUS (def=0x0) // Transmit underflow status
-
[6]RS (def=0x0) // Receive status
-
[7]RBUS (def=0x0) // Receive buffer unavailable status
-
[8]RPSS (def=0x0) // Receive process stopped status
-
[9]PWTS (def=0x0) // Receive watchdog timeout status
-
[10]ETS (def=0x0) // Early transmit status
-
[13]FBES (def=0x0) // Fatal bus error status
-
[14]ERS (def=0x0) // Early receive status
-
[15]AIS (def=0x0) // Abnormal interrupt summary
-
[16]NIS (def=0x0) // Normal interrupt summary
-
[17:19]RPS (def=0x0) // Receive process state
-
[20:22]TPS (def=0x0) // Transmit process state
-
[23:25]EBS (def=0x0) // Error bits status
-
[27]MMCS (def=0x0) // MMC status
-
[28]PMTS (def=0x0) // PMT status
-
[29]TSTS (def=0x0) // Time stamp trigger status
-
[31]IPLS (def=0x0) // 10MPHY Physical layer variation
0x40029018DMAOMR// Ethernet DMA operation mode register
-
[1]SR (def=0x0) // SR
-
[2]OSF (def=0x0) // OSF
-
[3:4]RTC (def=0x0) // RTC
-
[6]FUGF (def=0x0) // FUGF
-
[7]FEF (def=0x0) // FEF
-
[13]ST (def=0x0) // ST
-
[14:16]TTC (def=0x0) // TTC
-
[20]FTF (def=0x0) // FTF
-
[21]TSF (def=0x0) // TSF
-
[24]DFRF (def=0x0) // DFRF
-
[25]RSF (def=0x0) // RSF
-
[26]DTCEFD (def=0x0) // DTCEFD
0x4002901CDMAIER// Ethernet DMA interrupt enable register
-
[0]TIE (def=0x0) // Transmit interrupt enable
-
[1]TPSIE (def=0x0) // Transmit process stopped interrupt enable
-
[2]TBUIE (def=0x0) // Transmit buffer unavailable interrupt enable
-
[3]TJTIE (def=0x0) // Transmit jabber timeout interrupt enable
-
[4]ROIE (def=0x0) // Overflow interrupt enable
-
[5]TUIE (def=0x0) // Underflow interrupt enable
-
[6]RIE (def=0x0) // Receive interrupt enable
-
[7]RBUIE (def=0x0) // Receive buffer unavailable interrupt enable
-
[8]RPSIE (def=0x0) // Receive process stopped interrupt enable
-
[9]RWTIE (def=0x0) // receive watchdog timeout interrupt enable
-
[10]ETIE (def=0x0) // Early transmit interrupt enable
-
[13]FBEIE (def=0x0) // Fatal bus error interrupt enable
-
[14]ERIE (def=0x0) // Early receive interrupt enable
-
[15]AISE (def=0x0) // Abnormal interrupt summary enable
-
[16]NISE (def=0x0) // Normal interrupt summary enable
-
[31]IPLE (def=0x0) // 10M Physical layer connection
0x40029020DMAMFBOCR// Ethernet DMA missed frame and buffer overflow counter register
-
[0:15]MFC (def=0x0) // Missed frames by the controller
-
[16]OMFC (def=0x0) // Overflow bit for missed frame counter
-
[17:27]MFA (def=0x0) // Missed frames by the application
-
[28]OFOC (def=0x0) // Overflow bit for FIFO overflow counter
0x40029048DMACHTDR// Ethernet DMA current host transmit descriptor register
-
[0:31]HTDAP (def=0x0) // Host transmit descriptor address pointer
0x4002904CDMACHRDR// Ethernet DMA current host receive descriptor register
-
[0:31]HRDAP (def=0x0) // Host receive descriptor address pointer
0x40029050DMACHTBAR// Ethernet DMA current host transmit buffer address register
-
[0:31]HTBAP (def=0x0) // Host transmit buffer address pointer
0x40029054DMACHRBAR// Ethernet DMA current host receive buffer address register
-
[0:31]HRBAP (def=0x0) // Host receive buffer address pointer
0x40007400DAC// Digital to analog converter
0x40007400CTLR// Control register (DAC_CR)
-
[0]EN1 (def=0x0) // DAC channel1 enable
-
[1]BOFF1 (def=0x0) // DAC channel1 output buffer disable
-
[2]TEN1 (def=0x0) // DAC channel1 trigger enable
-
[3:5]TSEL1 (def=0x0) // DAC channel1 trigger selection
-
[6:7]WAVE1 (def=0x0) // DAC channel1 noise/triangle wave generation enable
-
[8:11]MAMP1 (def=0x0) // DAC channel1 mask/amplitude selector
-
[12]DMAEN1 (def=0x0) // DAC channel1 DMA enable
-
[16]EN2 (def=0x0) // DAC channel2 enable
-
[17]BOFF2 (def=0x0) // DAC channel2 output buffer disable
-
[18]TEN2 (def=0x0) // DAC channel2 trigger enable
-
[19:21]TSEL2 (def=0x0) // DAC channel2 trigger selection
-
[22:23]WAVE2 (def=0x0) // DAC channel2 noise/triangle wave generation enable
-
[24:27]MAMP2 (def=0x0) // DAC channel2 mask/amplitude selector
-
[28]DMAEN2 (def=0x0) // DAC channel2 DMA enable
0x40007404SWTR// DAC software trigger register (DAC_SWTRIGR)
-
[0]SWTRIG1 (def=0x0) // DAC channel1 software trigger
-
[1]SWTRIG2 (def=0x0) // DAC channel2 software trigger
0x40007408R12BDHR1// DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
-
[0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
0x4000740CL12BDHR1// DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
-
[4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
0x40007410R8BDHR1// DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
-
[0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
0x40007414R12BDHR2// DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
-
[0:11]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
0x40007418L12BDHR2// DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
-
[4:15]DACC2DHR (def=0x0) // DAC channel2 12-bit left-aligned data
0x4000741CR8BDHR2// DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
-
[0:7]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
0x40007420RD12BDHR// Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, B
-
[0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
-
[16:27]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
0x40007424LD12BDHR// DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bi
-
[4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
-
[20:31]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
0x40007428RD8BDHR// DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
-
[0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
-
[8:15]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
0x4000742CDOR1// DAC channel1 data output register (DAC_DOR1)
-
[0:11]DACC1DOR (def=0x0) // DAC channel1 data output
0x40007430DOR2// DAC channel2 data output register (DAC_DOR2)
-
[0:11]DACC2DOR (def=0x0) // DAC channel2 data output
0x40007000PWR// Power control
0x40007000CTLR// Power control register (PWR_CTRL)
-
[0]LPDS (def=0x0) // Low Power Deep Sleep
-
[1]PDDS (def=0x0) // Power Down Deep Sleep
-
[2]CWUF (def=0x0) // Clear Wake-up Flag
-
[3]CSBF (def=0x0) // Clear STANDBY Flag
-
[4]PVDE (def=0x0) // Power Voltage Detector Enable
-
[5:7]PLS (def=0x0) // PVD Level Selection
-
[8]DBP (def=0x0) // Disable Backup Domain write protection
-
[16]R2K_STYEN (def=0x0) // standby 2k ram enable
-
[17]R30K_STYEN (def=0x0) // standby 30k ram enable
-
[18]R2K_VBATEN (def=0x0) // VBAT 30k ram enable
-
[19]R30K_VBATEN (def=0x0) // VBAT 30k ram enable
-
[20]RAM_LVEN (def=0x0) // Ram LV Enable
0x40007004CSR// Power control register (PWR_CSR)
-
[0]WUF (def=0x0) // Wake-Up Flag
-
[1]SBF (def=0x0) // STANDBY Flag
-
[2]PVDO (def=0x0) // PVD Output
-
[8]EWUP (def=0x0) // Enable WKUP pin
- [17] PVD // PVD through EXTI line detection interrupt
0x40021000RCC// Reset and clock control
0x40021000CTLR// Clock control register
-
[0]HSION (def=0x1) // Internal High Speed clock enable
-
[1]HSIRDY (def=0x1) // Internal High Speed clock ready flag
-
[3:7]HSITRIM (def=0x10) // Internal High Speed clock trimming
-
[8:15]HSICAL (def=0x0) // Internal High Speed clock Calibration
-
[16]HSEON (def=0x0) // External High Speed clock enable
-
[17]HSERDY (def=0x0) // External High Speed clock ready flag
-
[18]HSEBYP (def=0x0) // External High Speed clock Bypass
-
[19]CSSON (def=0x0) // Clock Security System enable
-
[24]PLLON (def=0x0) // PLL enable
-
[25]PLLRDY (def=0x0) // PLL clock ready flag
0x40021004CFGR0// Clock configuration register (RCC_CFGR0)
-
[0:1]SW (def=0x0) // System clock Switch
-
[2:3]SWS (def=0x0) // System Clock Switch Status
-
[4:7]HPRE (def=0x0) // HB prescaler
-
[8:10]PPRE1 (def=0x0) // PB Low speed prescaler (PB1)
-
[11:13]PPRE2 (def=0x0) // PB High speed prescaler (PB2)
-
[14:15]ADCPRE (def=0x0) // ADC prescaler
-
[16]PLLSRC (def=0x0) // PLL entry clock source
-
[17]PLLXTPRE (def=0x0) // HSE divider for PLL entry
-
[18:21]PLLMUL (def=0x0) // PLL Multiplication Factor
-
[22:23]USBPRE (def=0x0) // USB prescaler
-
[24:27]MCO (def=0x0) // Microcontroller clock output
-
[28]ETHPRE (def=0x0) // ETH prescaler
-
[31]ADCDUTY (def=0x0) // ADC clock duty cycle adjustment
0x40021008INTR// Clock interrupt register (RCC_INTR)
-
[0]LSIRDYF (def=0x0) // LSI Ready Interrupt flag
-
[1]LSERDYF (def=0x0) // LSE Ready Interrupt flag
-
[2]HSIRDYF (def=0x0) // HSI Ready Interrupt flag
-
[3]HSERDYF (def=0x0) // HSE Ready Interrupt flag
-
[4]PLLRDYF (def=0x0) // PLL Ready Interrupt flag
-
[7]CSSF (def=0x0) // Clock Security System Interrupt flag
-
[8]LSIRDYIE (def=0x0) // LSI Ready Interrupt Enable
-
[9]LSERDYIE (def=0x0) // LSE Ready Interrupt Enable
-
[10]HSIRDYIE (def=0x0) // HSI Ready Interrupt Enable
-
[11]HSERDYIE (def=0x0) // HSE Ready Interrupt Enable
-
[12]PLLRDYIE (def=0x0) // PLL Ready Interrupt Enable
-
[16]LSIRDYC (def=0x0) // LSI Ready Interrupt Clear
-
[17]LSERDYC (def=0x0) // LSE Ready Interrupt Clear
-
[18]HSIRDYC (def=0x0) // HSI Ready Interrupt Clear
-
[19]HSERDYC (def=0x0) // HSE Ready Interrupt Clear
-
[20]PLLRDYC (def=0x0) // PLL Ready Interrupt Clear
-
[23]CSSC (def=0x0) // Clock security system interrupt clear
0x4002100CAPB2PRSTR// PB2 peripheral reset register (RCC_APB2PRSTR)
-
[0]AFIORST (def=0x0) // Alternate function I/O reset
-
[2]IOPARST (def=0x0) // IO port A reset
-
[3]IOPBRST (def=0x0) // IO port B reset
-
[4]IOPCRST (def=0x0) // IO port C reset
-
[5]IOPDRST (def=0x0) // IO port D reset
-
[6]IOPERST (def=0x0) // IO port E reset
-
[9]ADC1RST (def=0x0) // ADC 1 interface reset
-
[10]ADC2RST (def=0x0) // ADC 2 interface reset
-
[11]TIM1RST (def=0x0) // TIM1 timer reset
-
[12]SPI1RST (def=0x0) // SPI 1 reset
-
[13]TIM8RST (def=0x0) // TIM8 timer reset
-
[14]USART1RST (def=0x0) // USART1 reset
-
[19]TIM9RST (def=0x0) // TIM9 timer reset
-
[20]TIM10RST (def=0x0) // TIM10 timer reset
0x40021010APB1PRSTR// PB1 peripheral reset register (RCC_APB1PRSTR)
-
[0]TIM2RST (def=0x0) // Timer 2 reset
-
[1]TIM3RST (def=0x0) // Timer 3 reset
-
[2]TIM4RST (def=0x0) // Timer 4 reset
-
[3]TIM5RST (def=0x0) // Timer 5 reset
-
[4]TIM6RST (def=0x0) // Timer 6 reset
-
[5]TIM7RST (def=0x0) // Timer 7 reset
-
[6]UART6RST (def=0x0) // UART 6 reset
-
[7]UART7RST (def=0x0) // UART 7 reset
-
[8]UART8RST (def=0x0) // UART 8 reset
-
[11]WWDGRST (def=0x0) // Window watchdog reset
-
[14]SPI2RST (def=0x0) // SPI2 reset
-
[15]SPI3RST (def=0x0) // SPI3 reset
-
[17]USART2RST (def=0x0) // USART 2 reset
-
[18]USART3RST (def=0x0) // USART 3 reset
-
[19]USART4RST (def=0x0) // USART 4 reset
-
[20]USART5RST (def=0x0) // USART 5 reset
-
[21]I2C1RST (def=0x0) // I2C1 reset
-
[22]I2C2RST (def=0x0) // I2C2 reset
-
[23]USBDRST (def=0x0) // USBD reset
-
[25]CAN1RST (def=0x0) // CAN1 reset
-
[26]CAN2RST (def=0x0) // CAN2 reset
-
[27]BKPRST (def=0x0) // Backup interface reset
-
[28]PWRRST (def=0x0) // Power interface reset
-
[29]DACRST (def=0x0) // DAC interface reset
0x40021014AHBPCENR// HB Peripheral Clock enable register (RCC_AHBPCENR)
-
[0]DMA1EN (def=0x0) // DMA clock enable
-
[1]DMA2EN (def=0x0) // DMA2 clock enable
-
[2]SRAMEN (def=0x1) // SRAM interface clock enable
-
[4]FLITFEN (def=0x1) // FLITF clock enable
-
[6]CRCEN (def=0x0) // CRC clock enable
-
[8]FSMCEN (def=0x0) // FSMC clock enable
-
[9]TRNG_EN (def=0x0) // TRNG clock enable
-
[10]SDIOEN (def=0x0) // SDIO clock enable
-
[11]USBHS_EN (def=0x0) // USBHS clock enable
-
[12]OTG_EN (def=0x0) // OTG clock enable
-
[13]DVP_EN (def=0x0) // DVP clock enable
-
[14]ETHMACEN (def=0x0) // Ethernet MAC clock enable
-
[15]ETHMACTXEN (def=0x0) // Ethernet MAC TX clock enable
-
[16]ETHMACRXEN (def=0x0) // Ethernet MAC RX clock enable
0x40021018APB2PCENR// PB2 peripheral clock enable register (RCC_APB2PCENR)
-
[0]AFIOEN (def=0x0) // Alternate function I/O clock enable
-
[2]IOPAEN (def=0x0) // I/O port A clock enable
-
[3]IOPBEN (def=0x0) // I/O port B clock enable
-
[4]IOPCEN (def=0x0) // I/O port C clock enable
-
[5]IOPDEN (def=0x0) // I/O port D clock enable
-
[6]IOPEEN (def=0x0) // I/O port E clock enable
-
[9]ADC1EN (def=0x0) // ADC1 interface clock enable
-
[10]ADC2EN (def=0x0) // ADC 2 interface clock enable
-
[11]TIM1EN (def=0x0) // TIM1 Timer clock enable
-
[12]SPI1EN (def=0x0) // SPI 1 clock enable
-
[13]TIM8EN (def=0x0) // TIM8 Timer clock enable
-
[14]USART1EN (def=0x0) // USART1 clock enable
-
[19]TIM9_EN (def=0x0) // TIM9 Timer clock enable
-
[20]TIM10_EN (def=0x0) // TIM10 Timer clock enable
0x4002101CAPB1PCENR// PB1 peripheral clock enable register (RCC_APB1PCENR)
-
[0]TIM2EN (def=0x0) // Timer 2 clock enable
-
[1]TIM3EN (def=0x0) // Timer 3 clock enable
-
[2]TIM4EN (def=0x0) // Timer 4 clock enable
-
[3]TIM5EN (def=0x0) // Timer 5 clock enable
-
[4]TIM6EN (def=0x0) // Timer 6 clock enable
-
[5]TIM7EN (def=0x0) // Timer 7 clock enable
-
[6]USART6_EN (def=0x0) // USART 6 clock enable
-
[7]USART7_EN (def=0x0) // USART 7 clock enable
-
[8]USART8_EN (def=0x0) // USART 8 clock enable
-
[11]WWDGEN (def=0x0) // Window watchdog clock enable
-
[14]SPI2EN (def=0x0) // SPI 2 clock enable
-
[15]SPI3EN (def=0x0) // SPI 3 clock enable
-
[17]USART2EN (def=0x0) // USART 2 clock enable
-
[18]USART3EN (def=0x0) // USART 3 clock enable
-
[19]UART4EN (def=0x0) // UART 4 clock enable
-
[20]UART5EN (def=0x0) // UART 5 clock enable
-
[21]I2C1EN (def=0x0) // I2C 1 clock enable
-
[22]I2C2EN (def=0x0) // I2C 2 clock enable
-
[23]USBDEN (def=0x0) // USBD clock enable
-
[25]CAN1EN (def=0x0) // CAN1 clock enable
-
[26]CAN2EN (def=0x0) // CAN2 clock enable
-
[27]BKPEN (def=0x0) // Backup interface clock enable
-
[28]PWREN (def=0x0) // Power interface clock enable
-
[29]DACEN (def=0x0) // DAC interface clock enable
0x40021020BDCTLR// Backup domain control register (RCC_BDCTLR)
-
[0]LSEON (def=0x0) // External Low Speed oscillator enable
-
[1]LSERDY (def=0x0) // External Low Speed oscillator ready
-
[2]LSEBYP (def=0x0) // External Low Speed oscillator bypass
-
[8:9]RTCSEL (def=0x0) // RTC clock source selection
-
[15]RTCEN (def=0x0) // RTC clock enable
-
[16]BDRST (def=0x0) // Backup domain software reset
0x40021024RSTSCKR// Control/status register (RCC_RSTSCKR)
-
[0]LSION (def=0x0) // Internal low speed oscillator enable
-
[1]LSIRDY (def=0x0) // Internal low speed oscillator ready
-
[24]RMVF (def=0x0) // Remove reset flag
-
[26]PINRSTF (def=0x1) // PIN reset flag
-
[27]PORRSTF (def=0x1) // POR/PDR reset flag
-
[28]SFTRSTF (def=0x0) // Software reset flag
-
[29]IWDGRSTF (def=0x0) // Independent watchdog reset flag
-
[30]WWDGRSTF (def=0x0) // Window watchdog reset flag
-
[31]LPWRRSTF (def=0x0) // Low-power reset flag
0x40021028AHBRSTR// HB reset register (RCC_APHBRSTR)
-
[12]USBHDRST (def=0x0) // USBHD reset
-
[13]DVPRST (def=0x0) // DVP reset
-
[14]ETHMACRST (def=0x0) // Ethernet MAC reset
0x4002102CCFGR2// Clock configuration register2 (RCC_CFGR2)
-
[0:3]PREDIV1 (def=0x0) // PREDIV1 division factor
-
[4:7]PREDIV2 (def=0x0) // PREDIV2 division factor
-
[8:11]PLL2MUL (def=0x0) // PLL2 Multiplication Factor
-
[12:15]PLL3MUL (def=0x0) // PLL3 Multiplication Factor
-
[16]PREDIV1SRC (def=0x0) // PREDIV1 entry clock source
-
[17]I2S2SRC (def=0x0) // I2S2 clock source
-
[18]I2S3SRC (def=0x0) // I2S3 clock source
-
[19]TRNGSRC (def=0x0) // TRNG clock source
-
[20:21]ETH1GSRC (def=0x0) // ETH1G clock source
-
[22]ETH1GEN (def=0x0) // ETH1G _125M clock enable
-
[24:26]USBHSDIV (def=0x0) // USB HS PREDIV division factor
-
[27]USBHSPLLSRC (def=0x0) // USB HS Multiplication Factor clock source
-
[28:29]USBHSCLK (def=0x0) // USB HS Peference Clock source
-
[30]USBHSPLL (def=0x0) // USB HS Multiplication control
-
[31]USBFSSRC (def=0x0) // USB FS clock source
- [21] RCC // RCC global interrupt
0x40023800EXTEND// Extend configuration
0x40023800EXTEND_CTR// EXTEND register
-
[0]USBDLS (def=0x0) // USBD Lowspeed Enable
-
[1]USBDPU (def=0x0) // USBD pullup Enable
-
[2]ETH10M (def=0x0) // ETH 10M Enable
-
[3]ETHRGMII (def=0x0) // ETH RGMII Enable
-
[4]HSIPRE (def=0x0) // Whether HSI is divided
-
[6]LKUPEN (def=0x1) // LOCKUP_Eable
-
[7]LOCKUP_RSTF (def=0x0) // LOCKUP RESET
-
[8:9]ULLDOTRIM (def=0x2) // ULLDO_TRIM
-
[10:11]LDOTRIM (def=0x2) // LDO_TRIM
-
[12]HSEKPLP (def=0x0) // HSE_KEEP_LP
0x40023804CR// OPA Control register
-
[0]EN1 (def=0x0) // OPA Enable1
-
[1]MODE1 (def=0x0) // OPA MODE1
-
[2]NSEL1 (def=0x0) // OPA NSEL1
-
[3]PSEL1 (def=0x0) // OPA PSEL1
-
[4]EN2 (def=0x0) // OPA Enable2
-
[5]MODE2 (def=0x0) // OPA MODE2
-
[6]NSEL2 (def=0x0) // OPA NSEL2
-
[7]PSEL2 (def=0x0) // OPA PSEL2
-
[8]EN3 (def=0x0) // OPA Eable3
-
[9]MODE3 (def=0x0) // OPA MODE3
-
[10]NSEL3 (def=0x0) // OPA NSEL3
-
[11]PSEL3 (def=0x0) // OPA PSEL3
-
[12]EN4 (def=0x0) // OPA Enable4
-
[13]MODE4 (def=0x0) // OPA MODE4
-
[14]NSEL4 (def=0x0) // OPA NSEL4
-
[15]PSEL4 (def=0x0) // OPA PSEL4
0x40010800GPIOA// General purpose I/O
0x40010800CFGLR// Port configuration register low (GPIOn_CFGLR)
-
[0:1]MODE0 (def=0x0) // Port n.0 mode bits
-
[2:3]CNF0 (def=0x1) // Port n.0 configuration bits
-
[4:5]MODE1 (def=0x0) // Port n.1 mode bits
-
[6:7]CNF1 (def=0x1) // Port n.1 configuration bits
-
[8:9]MODE2 (def=0x0) // Port n.2 mode bits
-
[10:11]CNF2 (def=0x1) // Port n.2 configuration bits
-
[12:13]MODE3 (def=0x0) // Port n.3 mode bits
-
[14:15]CNF3 (def=0x1) // Port n.3 configuration bits
-
[16:17]MODE4 (def=0x0) // Port n.4 mode bits
-
[18:19]CNF4 (def=0x1) // Port n.4 configuration bits
-
[20:21]MODE5 (def=0x0) // Port n.5 mode bits
-
[22:23]CNF5 (def=0x1) // Port n.5 configuration bits
-
[24:25]MODE6 (def=0x0) // Port n.6 mode bits
-
[26:27]CNF6 (def=0x1) // Port n.6 configuration bits
-
[28:29]MODE7 (def=0x0) // Port n.7 mode bits
-
[30:31]CNF7 (def=0x1) // Port n.7 configuration bits
0x40010804CFGHR// Port configuration register high (GPIOn_CFGHR)
-
[0:1]MODE8 (def=0x0) // Port n.8 mode bits
-
[2:3]CNF8 (def=0x1) // Port n.8 configuration bits
-
[4:5]MODE9 (def=0x0) // Port n.9 mode bits
-
[6:7]CNF9 (def=0x1) // Port n.9 configuration bits
-
[8:9]MODE10 (def=0x0) // Port n.10 mode bits
-
[10:11]CNF10 (def=0x1) // Port n.10 configuration bits
-
[12:13]MODE11 (def=0x0) // Port n.11 mode bits
-
[14:15]CNF11 (def=0x1) // Port n.11 configuration bits
-
[16:17]MODE12 (def=0x0) // Port n.12 mode bits
-
[18:19]CNF12 (def=0x1) // Port n.12 configuration bits
-
[20:21]MODE13 (def=0x0) // Port n.13 mode bits
-
[22:23]CNF13 (def=0x1) // Port n.13 configuration bits
-
[24:25]MODE14 (def=0x0) // Port n.14 mode bits
-
[26:27]CNF14 (def=0x1) // Port n.14 configuration bits
-
[28:29]MODE15 (def=0x0) // Port n.15 mode bits
-
[30:31]CNF15 (def=0x1) // Port n.15 configuration bits
0x40010808INDR// Port input data register (GPIOn_INDR)
-
[0]IDR0 (def=0x0) // Port input data
-
[1]IDR1 (def=0x0) // Port input data
-
[2]IDR2 (def=0x0) // Port input data
-
[3]IDR3 (def=0x0) // Port input data
-
[4]IDR4 (def=0x0) // Port input data
-
[5]IDR5 (def=0x0) // Port input data
-
[6]IDR6 (def=0x0) // Port input data
-
[7]IDR7 (def=0x0) // Port input data
-
[8]IDR8 (def=0x0) // Port input data
-
[9]IDR9 (def=0x0) // Port input data
-
[10]IDR10 (def=0x0) // Port input data
-
[11]IDR11 (def=0x0) // Port input data
-
[12]IDR12 (def=0x0) // Port input data
-
[13]IDR13 (def=0x0) // Port input data
-
[14]IDR14 (def=0x0) // Port input data
-
[15]IDR15 (def=0x0) // Port input data
0x4001080COUTDR// Port output data register (GPIOn_OUTDR)
-
[0]ODR0 (def=0x0) // Port output data
-
[1]ODR1 (def=0x0) // Port output data
-
[2]ODR2 (def=0x0) // Port output data
-
[3]ODR3 (def=0x0) // Port output data
-
[4]ODR4 (def=0x0) // Port output data
-
[5]ODR5 (def=0x0) // Port output data
-
[6]ODR6 (def=0x0) // Port output data
-
[7]ODR7 (def=0x0) // Port output data
-
[8]ODR8 (def=0x0) // Port output data
-
[9]ODR9 (def=0x0) // Port output data
-
[10]ODR10 (def=0x0) // Port output data
-
[11]ODR11 (def=0x0) // Port output data
-
[12]ODR12 (def=0x0) // Port output data
-
[13]ODR13 (def=0x0) // Port output data
-
[14]ODR14 (def=0x0) // Port output data
-
[15]ODR15 (def=0x0) // Port output data
0x40010810BSHR// Port bit set/reset register (GPIOn_BSHR)
-
[0]BS0 (def=0x0) // Set bit 0
-
[1]BS1 (def=0x0) // Set bit 1
-
[2]BS2 (def=0x0) // Set bit 1
-
[3]BS3 (def=0x0) // Set bit 3
-
[4]BS4 (def=0x0) // Set bit 4
-
[5]BS5 (def=0x0) // Set bit 5
-
[6]BS6 (def=0x0) // Set bit 6
-
[7]BS7 (def=0x0) // Set bit 7
-
[8]BS8 (def=0x0) // Set bit 8
-
[9]BS9 (def=0x0) // Set bit 9
-
[10]BS10 (def=0x0) // Set bit 10
-
[11]BS11 (def=0x0) // Set bit 11
-
[12]BS12 (def=0x0) // Set bit 12
-
[13]BS13 (def=0x0) // Set bit 13
-
[14]BS14 (def=0x0) // Set bit 14
-
[15]BS15 (def=0x0) // Set bit 15
-
[16]BR0 (def=0x0) // Reset bit 0
-
[17]BR1 (def=0x0) // Reset bit 1
-
[18]BR2 (def=0x0) // Reset bit 2
-
[19]BR3 (def=0x0) // Reset bit 3
-
[20]BR4 (def=0x0) // Reset bit 4
-
[21]BR5 (def=0x0) // Reset bit 5
-
[22]BR6 (def=0x0) // Reset bit 6
-
[23]BR7 (def=0x0) // Reset bit 7
-
[24]BR8 (def=0x0) // Reset bit 8
-
[25]BR9 (def=0x0) // Reset bit 9
-
[26]BR10 (def=0x0) // Reset bit 10
-
[27]BR11 (def=0x0) // Reset bit 11
-
[28]BR12 (def=0x0) // Reset bit 12
-
[29]BR13 (def=0x0) // Reset bit 13
-
[30]BR14 (def=0x0) // Reset bit 14
-
[31]BR15 (def=0x0) // Reset bit 15
0x40010814BCR// Port bit reset register (GPIOn_BCR)
-
[0]BR0 (def=0x0) // Reset bit 0
-
[1]BR1 (def=0x0) // Reset bit 1
-
[2]BR2 (def=0x0) // Reset bit 1
-
[3]BR3 (def=0x0) // Reset bit 3
-
[4]BR4 (def=0x0) // Reset bit 4
-
[5]BR5 (def=0x0) // Reset bit 5
-
[6]BR6 (def=0x0) // Reset bit 6
-
[7]BR7 (def=0x0) // Reset bit 7
-
[8]BR8 (def=0x0) // Reset bit 8
-
[9]BR9 (def=0x0) // Reset bit 9
-
[10]BR10 (def=0x0) // Reset bit 10
-
[11]BR11 (def=0x0) // Reset bit 11
-
[12]BR12 (def=0x0) // Reset bit 12
-
[13]BR13 (def=0x0) // Reset bit 13
-
[14]BR14 (def=0x0) // Reset bit 14
-
[15]BR15 (def=0x0) // Reset bit 15
0x40010818LCKR// Port configuration lock register
-
[0]LCK0 (def=0x0) // Port A Lock bit 0
-
[1]LCK1 (def=0x0) // Port A Lock bit 1
-
[2]LCK2 (def=0x0) // Port A Lock bit 2
-
[3]LCK3 (def=0x0) // Port A Lock bit 3
-
[4]LCK4 (def=0x0) // Port A Lock bit 4
-
[5]LCK5 (def=0x0) // Port A Lock bit 5
-
[6]LCK6 (def=0x0) // Port A Lock bit 6
-
[7]LCK7 (def=0x0) // Port A Lock bit 7
-
[8]LCK8 (def=0x0) // Port A Lock bit 8
-
[9]LCK9 (def=0x0) // Port A Lock bit 9
-
[10]LCK10 (def=0x0) // Port A Lock bit 10
-
[11]LCK11 (def=0x0) // Port A Lock bit 11
-
[12]LCK12 (def=0x0) // Port A Lock bit 12
-
[13]LCK13 (def=0x0) // Port A Lock bit 13
-
[14]LCK14 (def=0x0) // Port A Lock bit 14
-
[15]LCK15 (def=0x0) // Port A Lock bit 15
-
[16]LCKK (def=0x0) // Lock key
0x40010C00GPIOB//
0x40010C00CFGLR// Port configuration register low (GPIOn_CFGLR)
-
[0:1]MODE0 (def=0x0) // Port n.0 mode bits
-
[2:3]CNF0 (def=0x1) // Port n.0 configuration bits
-
[4:5]MODE1 (def=0x0) // Port n.1 mode bits
-
[6:7]CNF1 (def=0x1) // Port n.1 configuration bits
-
[8:9]MODE2 (def=0x0) // Port n.2 mode bits
-
[10:11]CNF2 (def=0x1) // Port n.2 configuration bits
-
[12:13]MODE3 (def=0x0) // Port n.3 mode bits
-
[14:15]CNF3 (def=0x1) // Port n.3 configuration bits
-
[16:17]MODE4 (def=0x0) // Port n.4 mode bits
-
[18:19]CNF4 (def=0x1) // Port n.4 configuration bits
-
[20:21]MODE5 (def=0x0) // Port n.5 mode bits
-
[22:23]CNF5 (def=0x1) // Port n.5 configuration bits
-
[24:25]MODE6 (def=0x0) // Port n.6 mode bits
-
[26:27]CNF6 (def=0x1) // Port n.6 configuration bits
-
[28:29]MODE7 (def=0x0) // Port n.7 mode bits
-
[30:31]CNF7 (def=0x1) // Port n.7 configuration bits
0x40010C04CFGHR// Port configuration register high (GPIOn_CFGHR)
-
[0:1]MODE8 (def=0x0) // Port n.8 mode bits
-
[2:3]CNF8 (def=0x1) // Port n.8 configuration bits
-
[4:5]MODE9 (def=0x0) // Port n.9 mode bits
-
[6:7]CNF9 (def=0x1) // Port n.9 configuration bits
-
[8:9]MODE10 (def=0x0) // Port n.10 mode bits
-
[10:11]CNF10 (def=0x1) // Port n.10 configuration bits
-
[12:13]MODE11 (def=0x0) // Port n.11 mode bits
-
[14:15]CNF11 (def=0x1) // Port n.11 configuration bits
-
[16:17]MODE12 (def=0x0) // Port n.12 mode bits
-
[18:19]CNF12 (def=0x1) // Port n.12 configuration bits
-
[20:21]MODE13 (def=0x0) // Port n.13 mode bits
-
[22:23]CNF13 (def=0x1) // Port n.13 configuration bits
-
[24:25]MODE14 (def=0x0) // Port n.14 mode bits
-
[26:27]CNF14 (def=0x1) // Port n.14 configuration bits
-
[28:29]MODE15 (def=0x0) // Port n.15 mode bits
-
[30:31]CNF15 (def=0x1) // Port n.15 configuration bits
0x40010C08INDR// Port input data register (GPIOn_INDR)
-
[0]IDR0 (def=0x0) // Port input data
-
[1]IDR1 (def=0x0) // Port input data
-
[2]IDR2 (def=0x0) // Port input data
-
[3]IDR3 (def=0x0) // Port input data
-
[4]IDR4 (def=0x0) // Port input data
-
[5]IDR5 (def=0x0) // Port input data
-
[6]IDR6 (def=0x0) // Port input data
-
[7]IDR7 (def=0x0) // Port input data
-
[8]IDR8 (def=0x0) // Port input data
-
[9]IDR9 (def=0x0) // Port input data
-
[10]IDR10 (def=0x0) // Port input data
-
[11]IDR11 (def=0x0) // Port input data
-
[12]IDR12 (def=0x0) // Port input data
-
[13]IDR13 (def=0x0) // Port input data
-
[14]IDR14 (def=0x0) // Port input data
-
[15]IDR15 (def=0x0) // Port input data
0x40010C0COUTDR// Port output data register (GPIOn_OUTDR)
-
[0]ODR0 (def=0x0) // Port output data
-
[1]ODR1 (def=0x0) // Port output data
-
[2]ODR2 (def=0x0) // Port output data
-
[3]ODR3 (def=0x0) // Port output data
-
[4]ODR4 (def=0x0) // Port output data
-
[5]ODR5 (def=0x0) // Port output data
-
[6]ODR6 (def=0x0) // Port output data
-
[7]ODR7 (def=0x0) // Port output data
-
[8]ODR8 (def=0x0) // Port output data
-
[9]ODR9 (def=0x0) // Port output data
-
[10]ODR10 (def=0x0) // Port output data
-
[11]ODR11 (def=0x0) // Port output data
-
[12]ODR12 (def=0x0) // Port output data
-
[13]ODR13 (def=0x0) // Port output data
-
[14]ODR14 (def=0x0) // Port output data
-
[15]ODR15 (def=0x0) // Port output data
0x40010C10BSHR// Port bit set/reset register (GPIOn_BSHR)
-
[0]BS0 (def=0x0) // Set bit 0
-
[1]BS1 (def=0x0) // Set bit 1
-
[2]BS2 (def=0x0) // Set bit 1
-
[3]BS3 (def=0x0) // Set bit 3
-
[4]BS4 (def=0x0) // Set bit 4
-
[5]BS5 (def=0x0) // Set bit 5
-
[6]BS6 (def=0x0) // Set bit 6
-
[7]BS7 (def=0x0) // Set bit 7
-
[8]BS8 (def=0x0) // Set bit 8
-
[9]BS9 (def=0x0) // Set bit 9
-
[10]BS10 (def=0x0) // Set bit 10
-
[11]BS11 (def=0x0) // Set bit 11
-
[12]BS12 (def=0x0) // Set bit 12
-
[13]BS13 (def=0x0) // Set bit 13
-
[14]BS14 (def=0x0) // Set bit 14
-
[15]BS15 (def=0x0) // Set bit 15
-
[16]BR0 (def=0x0) // Reset bit 0
-
[17]BR1 (def=0x0) // Reset bit 1
-
[18]BR2 (def=0x0) // Reset bit 2
-
[19]BR3 (def=0x0) // Reset bit 3
-
[20]BR4 (def=0x0) // Reset bit 4
-
[21]BR5 (def=0x0) // Reset bit 5
-
[22]BR6 (def=0x0) // Reset bit 6
-
[23]BR7 (def=0x0) // Reset bit 7
-
[24]BR8 (def=0x0) // Reset bit 8
-
[25]BR9 (def=0x0) // Reset bit 9
-
[26]BR10 (def=0x0) // Reset bit 10
-
[27]BR11 (def=0x0) // Reset bit 11
-
[28]BR12 (def=0x0) // Reset bit 12
-
[29]BR13 (def=0x0) // Reset bit 13
-
[30]BR14 (def=0x0) // Reset bit 14
-
[31]BR15 (def=0x0) // Reset bit 15
0x40010C14BCR// Port bit reset register (GPIOn_BCR)
-
[0]BR0 (def=0x0) // Reset bit 0
-
[1]BR1 (def=0x0) // Reset bit 1
-
[2]BR2 (def=0x0) // Reset bit 1
-
[3]BR3 (def=0x0) // Reset bit 3
-
[4]BR4 (def=0x0) // Reset bit 4
-
[5]BR5 (def=0x0) // Reset bit 5
-
[6]BR6 (def=0x0) // Reset bit 6
-
[7]BR7 (def=0x0) // Reset bit 7
-
[8]BR8 (def=0x0) // Reset bit 8
-
[9]BR9 (def=0x0) // Reset bit 9
-
[10]BR10 (def=0x0) // Reset bit 10
-
[11]BR11 (def=0x0) // Reset bit 11
-
[12]BR12 (def=0x0) // Reset bit 12
-
[13]BR13 (def=0x0) // Reset bit 13
-
[14]BR14 (def=0x0) // Reset bit 14
-
[15]BR15 (def=0x0) // Reset bit 15
0x40010C18LCKR// Port configuration lock register
-
[0]LCK0 (def=0x0) // Port A Lock bit 0
-
[1]LCK1 (def=0x0) // Port A Lock bit 1
-
[2]LCK2 (def=0x0) // Port A Lock bit 2
-
[3]LCK3 (def=0x0) // Port A Lock bit 3
-
[4]LCK4 (def=0x0) // Port A Lock bit 4
-
[5]LCK5 (def=0x0) // Port A Lock bit 5
-
[6]LCK6 (def=0x0) // Port A Lock bit 6
-
[7]LCK7 (def=0x0) // Port A Lock bit 7
-
[8]LCK8 (def=0x0) // Port A Lock bit 8
-
[9]LCK9 (def=0x0) // Port A Lock bit 9
-
[10]LCK10 (def=0x0) // Port A Lock bit 10
-
[11]LCK11 (def=0x0) // Port A Lock bit 11
-
[12]LCK12 (def=0x0) // Port A Lock bit 12
-
[13]LCK13 (def=0x0) // Port A Lock bit 13
-
[14]LCK14 (def=0x0) // Port A Lock bit 14
-
[15]LCK15 (def=0x0) // Port A Lock bit 15
-
[16]LCKK (def=0x0) // Lock key
0x40011000GPIOC//
0x40011000CFGLR// Port configuration register low (GPIOn_CFGLR)
-
[0:1]MODE0 (def=0x0) // Port n.0 mode bits
-
[2:3]CNF0 (def=0x1) // Port n.0 configuration bits
-
[4:5]MODE1 (def=0x0) // Port n.1 mode bits
-
[6:7]CNF1 (def=0x1) // Port n.1 configuration bits
-
[8:9]MODE2 (def=0x0) // Port n.2 mode bits
-
[10:11]CNF2 (def=0x1) // Port n.2 configuration bits
-
[12:13]MODE3 (def=0x0) // Port n.3 mode bits
-
[14:15]CNF3 (def=0x1) // Port n.3 configuration bits
-
[16:17]MODE4 (def=0x0) // Port n.4 mode bits
-
[18:19]CNF4 (def=0x1) // Port n.4 configuration bits
-
[20:21]MODE5 (def=0x0) // Port n.5 mode bits
-
[22:23]CNF5 (def=0x1) // Port n.5 configuration bits
-
[24:25]MODE6 (def=0x0) // Port n.6 mode bits
-
[26:27]CNF6 (def=0x1) // Port n.6 configuration bits
-
[28:29]MODE7 (def=0x0) // Port n.7 mode bits
-
[30:31]CNF7 (def=0x1) // Port n.7 configuration bits
0x40011004CFGHR// Port configuration register high (GPIOn_CFGHR)
-
[0:1]MODE8 (def=0x0) // Port n.8 mode bits
-
[2:3]CNF8 (def=0x1) // Port n.8 configuration bits
-
[4:5]MODE9 (def=0x0) // Port n.9 mode bits
-
[6:7]CNF9 (def=0x1) // Port n.9 configuration bits
-
[8:9]MODE10 (def=0x0) // Port n.10 mode bits
-
[10:11]CNF10 (def=0x1) // Port n.10 configuration bits
-
[12:13]MODE11 (def=0x0) // Port n.11 mode bits
-
[14:15]CNF11 (def=0x1) // Port n.11 configuration bits
-
[16:17]MODE12 (def=0x0) // Port n.12 mode bits
-
[18:19]CNF12 (def=0x1) // Port n.12 configuration bits
-
[20:21]MODE13 (def=0x0) // Port n.13 mode bits
-
[22:23]CNF13 (def=0x1) // Port n.13 configuration bits
-
[24:25]MODE14 (def=0x0) // Port n.14 mode bits
-
[26:27]CNF14 (def=0x1) // Port n.14 configuration bits
-
[28:29]MODE15 (def=0x0) // Port n.15 mode bits
-
[30:31]CNF15 (def=0x1) // Port n.15 configuration bits
0x40011008INDR// Port input data register (GPIOn_INDR)
-
[0]IDR0 (def=0x0) // Port input data
-
[1]IDR1 (def=0x0) // Port input data
-
[2]IDR2 (def=0x0) // Port input data
-
[3]IDR3 (def=0x0) // Port input data
-
[4]IDR4 (def=0x0) // Port input data
-
[5]IDR5 (def=0x0) // Port input data
-
[6]IDR6 (def=0x0) // Port input data
-
[7]IDR7 (def=0x0) // Port input data
-
[8]IDR8 (def=0x0) // Port input data
-
[9]IDR9 (def=0x0) // Port input data
-
[10]IDR10 (def=0x0) // Port input data
-
[11]IDR11 (def=0x0) // Port input data
-
[12]IDR12 (def=0x0) // Port input data
-
[13]IDR13 (def=0x0) // Port input data
-
[14]IDR14 (def=0x0) // Port input data
-
[15]IDR15 (def=0x0) // Port input data
0x4001100COUTDR// Port output data register (GPIOn_OUTDR)
-
[0]ODR0 (def=0x0) // Port output data
-
[1]ODR1 (def=0x0) // Port output data
-
[2]ODR2 (def=0x0) // Port output data
-
[3]ODR3 (def=0x0) // Port output data
-
[4]ODR4 (def=0x0) // Port output data
-
[5]ODR5 (def=0x0) // Port output data
-
[6]ODR6 (def=0x0) // Port output data
-
[7]ODR7 (def=0x0) // Port output data
-
[8]ODR8 (def=0x0) // Port output data
-
[9]ODR9 (def=0x0) // Port output data
-
[10]ODR10 (def=0x0) // Port output data
-
[11]ODR11 (def=0x0) // Port output data
-
[12]ODR12 (def=0x0) // Port output data
-
[13]ODR13 (def=0x0) // Port output data
-
[14]ODR14 (def=0x0) // Port output data
-
[15]ODR15 (def=0x0) // Port output data
0x40011010BSHR// Port bit set/reset register (GPIOn_BSHR)
-
[0]BS0 (def=0x0) // Set bit 0
-
[1]BS1 (def=0x0) // Set bit 1
-
[2]BS2 (def=0x0) // Set bit 1
-
[3]BS3 (def=0x0) // Set bit 3
-
[4]BS4 (def=0x0) // Set bit 4
-
[5]BS5 (def=0x0) // Set bit 5
-
[6]BS6 (def=0x0) // Set bit 6
-
[7]BS7 (def=0x0) // Set bit 7
-
[8]BS8 (def=0x0) // Set bit 8
-
[9]BS9 (def=0x0) // Set bit 9
-
[10]BS10 (def=0x0) // Set bit 10
-
[11]BS11 (def=0x0) // Set bit 11
-
[12]BS12 (def=0x0) // Set bit 12
-
[13]BS13 (def=0x0) // Set bit 13
-
[14]BS14 (def=0x0) // Set bit 14
-
[15]BS15 (def=0x0) // Set bit 15
-
[16]BR0 (def=0x0) // Reset bit 0
-
[17]BR1 (def=0x0) // Reset bit 1
-
[18]BR2 (def=0x0) // Reset bit 2
-
[19]BR3 (def=0x0) // Reset bit 3
-
[20]BR4 (def=0x0) // Reset bit 4
-
[21]BR5 (def=0x0) // Reset bit 5
-
[22]BR6 (def=0x0) // Reset bit 6
-
[23]BR7 (def=0x0) // Reset bit 7
-
[24]BR8 (def=0x0) // Reset bit 8
-
[25]BR9 (def=0x0) // Reset bit 9
-
[26]BR10 (def=0x0) // Reset bit 10
-
[27]BR11 (def=0x0) // Reset bit 11
-
[28]BR12 (def=0x0) // Reset bit 12
-
[29]BR13 (def=0x0) // Reset bit 13
-
[30]BR14 (def=0x0) // Reset bit 14
-
[31]BR15 (def=0x0) // Reset bit 15
0x40011014BCR// Port bit reset register (GPIOn_BCR)
-
[0]BR0 (def=0x0) // Reset bit 0
-
[1]BR1 (def=0x0) // Reset bit 1
-
[2]BR2 (def=0x0) // Reset bit 1
-
[3]BR3 (def=0x0) // Reset bit 3
-
[4]BR4 (def=0x0) // Reset bit 4
-
[5]BR5 (def=0x0) // Reset bit 5
-
[6]BR6 (def=0x0) // Reset bit 6
-
[7]BR7 (def=0x0) // Reset bit 7
-
[8]BR8 (def=0x0) // Reset bit 8
-
[9]BR9 (def=0x0) // Reset bit 9
-
[10]BR10 (def=0x0) // Reset bit 10
-
[11]BR11 (def=0x0) // Reset bit 11
-
[12]BR12 (def=0x0) // Reset bit 12
-
[13]BR13 (def=0x0) // Reset bit 13
-
[14]BR14 (def=0x0) // Reset bit 14
-
[15]BR15 (def=0x0) // Reset bit 15
0x40011018LCKR// Port configuration lock register
-
[0]LCK0 (def=0x0) // Port A Lock bit 0
-
[1]LCK1 (def=0x0) // Port A Lock bit 1
-
[2]LCK2 (def=0x0) // Port A Lock bit 2
-
[3]LCK3 (def=0x0) // Port A Lock bit 3
-
[4]LCK4 (def=0x0) // Port A Lock bit 4
-
[5]LCK5 (def=0x0) // Port A Lock bit 5
-
[6]LCK6 (def=0x0) // Port A Lock bit 6
-
[7]LCK7 (def=0x0) // Port A Lock bit 7
-
[8]LCK8 (def=0x0) // Port A Lock bit 8
-
[9]LCK9 (def=0x0) // Port A Lock bit 9
-
[10]LCK10 (def=0x0) // Port A Lock bit 10
-
[11]LCK11 (def=0x0) // Port A Lock bit 11
-
[12]LCK12 (def=0x0) // Port A Lock bit 12
-
[13]LCK13 (def=0x0) // Port A Lock bit 13
-
[14]LCK14 (def=0x0) // Port A Lock bit 14
-
[15]LCK15 (def=0x0) // Port A Lock bit 15
-
[16]LCKK (def=0x0) // Lock key
0x40011400GPIOD//
0x40011400CFGLR// Port configuration register low (GPIOn_CFGLR)
-
[0:1]MODE0 (def=0x0) // Port n.0 mode bits
-
[2:3]CNF0 (def=0x1) // Port n.0 configuration bits
-
[4:5]MODE1 (def=0x0) // Port n.1 mode bits
-
[6:7]CNF1 (def=0x1) // Port n.1 configuration bits
-
[8:9]MODE2 (def=0x0) // Port n.2 mode bits
-
[10:11]CNF2 (def=0x1) // Port n.2 configuration bits
-
[12:13]MODE3 (def=0x0) // Port n.3 mode bits
-
[14:15]CNF3 (def=0x1) // Port n.3 configuration bits
-
[16:17]MODE4 (def=0x0) // Port n.4 mode bits
-
[18:19]CNF4 (def=0x1) // Port n.4 configuration bits
-
[20:21]MODE5 (def=0x0) // Port n.5 mode bits
-
[22:23]CNF5 (def=0x1) // Port n.5 configuration bits
-
[24:25]MODE6 (def=0x0) // Port n.6 mode bits
-
[26:27]CNF6 (def=0x1) // Port n.6 configuration bits
-
[28:29]MODE7 (def=0x0) // Port n.7 mode bits
-
[30:31]CNF7 (def=0x1) // Port n.7 configuration bits
0x40011404CFGHR// Port configuration register high (GPIOn_CFGHR)
-
[0:1]MODE8 (def=0x0) // Port n.8 mode bits
-
[2:3]CNF8 (def=0x1) // Port n.8 configuration bits
-
[4:5]MODE9 (def=0x0) // Port n.9 mode bits
-
[6:7]CNF9 (def=0x1) // Port n.9 configuration bits
-
[8:9]MODE10 (def=0x0) // Port n.10 mode bits
-
[10:11]CNF10 (def=0x1) // Port n.10 configuration bits
-
[12:13]MODE11 (def=0x0) // Port n.11 mode bits
-
[14:15]CNF11 (def=0x1) // Port n.11 configuration bits
-
[16:17]MODE12 (def=0x0) // Port n.12 mode bits
-
[18:19]CNF12 (def=0x1) // Port n.12 configuration bits
-
[20:21]MODE13 (def=0x0) // Port n.13 mode bits
-
[22:23]CNF13 (def=0x1) // Port n.13 configuration bits
-
[24:25]MODE14 (def=0x0) // Port n.14 mode bits
-
[26:27]CNF14 (def=0x1) // Port n.14 configuration bits
-
[28:29]MODE15 (def=0x0) // Port n.15 mode bits
-
[30:31]CNF15 (def=0x1) // Port n.15 configuration bits
0x40011408INDR// Port input data register (GPIOn_INDR)
-
[0]IDR0 (def=0x0) // Port input data
-
[1]IDR1 (def=0x0) // Port input data
-
[2]IDR2 (def=0x0) // Port input data
-
[3]IDR3 (def=0x0) // Port input data
-
[4]IDR4 (def=0x0) // Port input data
-
[5]IDR5 (def=0x0) // Port input data
-
[6]IDR6 (def=0x0) // Port input data
-
[7]IDR7 (def=0x0) // Port input data
-
[8]IDR8 (def=0x0) // Port input data
-
[9]IDR9 (def=0x0) // Port input data
-
[10]IDR10 (def=0x0) // Port input data
-
[11]IDR11 (def=0x0) // Port input data
-
[12]IDR12 (def=0x0) // Port input data
-
[13]IDR13 (def=0x0) // Port input data
-
[14]IDR14 (def=0x0) // Port input data
-
[15]IDR15 (def=0x0) // Port input data
0x4001140COUTDR// Port output data register (GPIOn_OUTDR)
-
[0]ODR0 (def=0x0) // Port output data
-
[1]ODR1 (def=0x0) // Port output data
-
[2]ODR2 (def=0x0) // Port output data
-
[3]ODR3 (def=0x0) // Port output data
-
[4]ODR4 (def=0x0) // Port output data
-
[5]ODR5 (def=0x0) // Port output data
-
[6]ODR6 (def=0x0) // Port output data
-
[7]ODR7 (def=0x0) // Port output data
-
[8]ODR8 (def=0x0) // Port output data
-
[9]ODR9 (def=0x0) // Port output data
-
[10]ODR10 (def=0x0) // Port output data
-
[11]ODR11 (def=0x0) // Port output data
-
[12]ODR12 (def=0x0) // Port output data
-
[13]ODR13 (def=0x0) // Port output data
-
[14]ODR14 (def=0x0) // Port output data
-
[15]ODR15 (def=0x0) // Port output data
0x40011410BSHR// Port bit set/reset register (GPIOn_BSHR)
-
[0]BS0 (def=0x0) // Set bit 0
-
[1]BS1 (def=0x0) // Set bit 1
-
[2]BS2 (def=0x0) // Set bit 1
-
[3]BS3 (def=0x0) // Set bit 3
-
[4]BS4 (def=0x0) // Set bit 4
-
[5]BS5 (def=0x0) // Set bit 5
-
[6]BS6 (def=0x0) // Set bit 6
-
[7]BS7 (def=0x0) // Set bit 7
-
[8]BS8 (def=0x0) // Set bit 8
-
[9]BS9 (def=0x0) // Set bit 9
-
[10]BS10 (def=0x0) // Set bit 10
-
[11]BS11 (def=0x0) // Set bit 11
-
[12]BS12 (def=0x0) // Set bit 12
-
[13]BS13 (def=0x0) // Set bit 13
-
[14]BS14 (def=0x0) // Set bit 14
-
[15]BS15 (def=0x0) // Set bit 15
-
[16]BR0 (def=0x0) // Reset bit 0
-
[17]BR1 (def=0x0) // Reset bit 1
-
[18]BR2 (def=0x0) // Reset bit 2
-
[19]BR3 (def=0x0) // Reset bit 3
-
[20]BR4 (def=0x0) // Reset bit 4
-
[21]BR5 (def=0x0) // Reset bit 5
-
[22]BR6 (def=0x0) // Reset bit 6
-
[23]BR7 (def=0x0) // Reset bit 7
-
[24]BR8 (def=0x0) // Reset bit 8
-
[25]BR9 (def=0x0) // Reset bit 9
-
[26]BR10 (def=0x0) // Reset bit 10
-
[27]BR11 (def=0x0) // Reset bit 11
-
[28]BR12 (def=0x0) // Reset bit 12
-
[29]BR13 (def=0x0) // Reset bit 13
-
[30]BR14 (def=0x0) // Reset bit 14
-
[31]BR15 (def=0x0) // Reset bit 15
0x40011414BCR// Port bit reset register (GPIOn_BCR)
-
[0]BR0 (def=0x0) // Reset bit 0
-
[1]BR1 (def=0x0) // Reset bit 1
-
[2]BR2 (def=0x0) // Reset bit 1
-
[3]BR3 (def=0x0) // Reset bit 3
-
[4]BR4 (def=0x0) // Reset bit 4
-
[5]BR5 (def=0x0) // Reset bit 5
-
[6]BR6 (def=0x0) // Reset bit 6
-
[7]BR7 (def=0x0) // Reset bit 7
-
[8]BR8 (def=0x0) // Reset bit 8
-
[9]BR9 (def=0x0) // Reset bit 9
-
[10]BR10 (def=0x0) // Reset bit 10
-
[11]BR11 (def=0x0) // Reset bit 11
-
[12]BR12 (def=0x0) // Reset bit 12
-
[13]BR13 (def=0x0) // Reset bit 13
-
[14]BR14 (def=0x0) // Reset bit 14
-
[15]BR15 (def=0x0) // Reset bit 15
0x40011418LCKR// Port configuration lock register
-
[0]LCK0 (def=0x0) // Port A Lock bit 0
-
[1]LCK1 (def=0x0) // Port A Lock bit 1
-
[2]LCK2 (def=0x0) // Port A Lock bit 2
-
[3]LCK3 (def=0x0) // Port A Lock bit 3
-
[4]LCK4 (def=0x0) // Port A Lock bit 4
-
[5]LCK5 (def=0x0) // Port A Lock bit 5
-
[6]LCK6 (def=0x0) // Port A Lock bit 6
-
[7]LCK7 (def=0x0) // Port A Lock bit 7
-
[8]LCK8 (def=0x0) // Port A Lock bit 8
-
[9]LCK9 (def=0x0) // Port A Lock bit 9
-
[10]LCK10 (def=0x0) // Port A Lock bit 10
-
[11]LCK11 (def=0x0) // Port A Lock bit 11
-
[12]LCK12 (def=0x0) // Port A Lock bit 12
-
[13]LCK13 (def=0x0) // Port A Lock bit 13
-
[14]LCK14 (def=0x0) // Port A Lock bit 14
-
[15]LCK15 (def=0x0) // Port A Lock bit 15
-
[16]LCKK (def=0x0) // Lock key
0x40011800GPIOE//
0x40011800CFGLR// Port configuration register low (GPIOn_CFGLR)
-
[0:1]MODE0 (def=0x0) // Port n.0 mode bits
-
[2:3]CNF0 (def=0x1) // Port n.0 configuration bits
-
[4:5]MODE1 (def=0x0) // Port n.1 mode bits
-
[6:7]CNF1 (def=0x1) // Port n.1 configuration bits
-
[8:9]MODE2 (def=0x0) // Port n.2 mode bits
-
[10:11]CNF2 (def=0x1) // Port n.2 configuration bits
-
[12:13]MODE3 (def=0x0) // Port n.3 mode bits
-
[14:15]CNF3 (def=0x1) // Port n.3 configuration bits
-
[16:17]MODE4 (def=0x0) // Port n.4 mode bits
-
[18:19]CNF4 (def=0x1) // Port n.4 configuration bits
-
[20:21]MODE5 (def=0x0) // Port n.5 mode bits
-
[22:23]CNF5 (def=0x1) // Port n.5 configuration bits
-
[24:25]MODE6 (def=0x0) // Port n.6 mode bits
-
[26:27]CNF6 (def=0x1) // Port n.6 configuration bits
-
[28:29]MODE7 (def=0x0) // Port n.7 mode bits
-
[30:31]CNF7 (def=0x1) // Port n.7 configuration bits
0x40011804CFGHR// Port configuration register high (GPIOn_CFGHR)
-
[0:1]MODE8 (def=0x0) // Port n.8 mode bits
-
[2:3]CNF8 (def=0x1) // Port n.8 configuration bits
-
[4:5]MODE9 (def=0x0) // Port n.9 mode bits
-
[6:7]CNF9 (def=0x1) // Port n.9 configuration bits
-
[8:9]MODE10 (def=0x0) // Port n.10 mode bits
-
[10:11]CNF10 (def=0x1) // Port n.10 configuration bits
-
[12:13]MODE11 (def=0x0) // Port n.11 mode bits
-
[14:15]CNF11 (def=0x1) // Port n.11 configuration bits
-
[16:17]MODE12 (def=0x0) // Port n.12 mode bits
-
[18:19]CNF12 (def=0x1) // Port n.12 configuration bits
-
[20:21]MODE13 (def=0x0) // Port n.13 mode bits
-
[22:23]CNF13 (def=0x1) // Port n.13 configuration bits
-
[24:25]MODE14 (def=0x0) // Port n.14 mode bits
-
[26:27]CNF14 (def=0x1) // Port n.14 configuration bits
-
[28:29]MODE15 (def=0x0) // Port n.15 mode bits
-
[30:31]CNF15 (def=0x1) // Port n.15 configuration bits
0x40011808INDR// Port input data register (GPIOn_INDR)
-
[0]IDR0 (def=0x0) // Port input data
-
[1]IDR1 (def=0x0) // Port input data
-
[2]IDR2 (def=0x0) // Port input data
-
[3]IDR3 (def=0x0) // Port input data
-
[4]IDR4 (def=0x0) // Port input data
-
[5]IDR5 (def=0x0) // Port input data
-
[6]IDR6 (def=0x0) // Port input data
-
[7]IDR7 (def=0x0) // Port input data
-
[8]IDR8 (def=0x0) // Port input data
-
[9]IDR9 (def=0x0) // Port input data
-
[10]IDR10 (def=0x0) // Port input data
-
[11]IDR11 (def=0x0) // Port input data
-
[12]IDR12 (def=0x0) // Port input data
-
[13]IDR13 (def=0x0) // Port input data
-
[14]IDR14 (def=0x0) // Port input data
-
[15]IDR15 (def=0x0) // Port input data
0x4001180COUTDR// Port output data register (GPIOn_OUTDR)
-
[0]ODR0 (def=0x0) // Port output data
-
[1]ODR1 (def=0x0) // Port output data
-
[2]ODR2 (def=0x0) // Port output data
-
[3]ODR3 (def=0x0) // Port output data
-
[4]ODR4 (def=0x0) // Port output data
-
[5]ODR5 (def=0x0) // Port output data
-
[6]ODR6 (def=0x0) // Port output data
-
[7]ODR7 (def=0x0) // Port output data
-
[8]ODR8 (def=0x0) // Port output data
-
[9]ODR9 (def=0x0) // Port output data
-
[10]ODR10 (def=0x0) // Port output data
-
[11]ODR11 (def=0x0) // Port output data
-
[12]ODR12 (def=0x0) // Port output data
-
[13]ODR13 (def=0x0) // Port output data
-
[14]ODR14 (def=0x0) // Port output data
-
[15]ODR15 (def=0x0) // Port output data
0x40011810BSHR// Port bit set/reset register (GPIOn_BSHR)
-
[0]BS0 (def=0x0) // Set bit 0
-
[1]BS1 (def=0x0) // Set bit 1
-
[2]BS2 (def=0x0) // Set bit 1
-
[3]BS3 (def=0x0) // Set bit 3
-
[4]BS4 (def=0x0) // Set bit 4
-
[5]BS5 (def=0x0) // Set bit 5
-
[6]BS6 (def=0x0) // Set bit 6
-
[7]BS7 (def=0x0) // Set bit 7
-
[8]BS8 (def=0x0) // Set bit 8
-
[9]BS9 (def=0x0) // Set bit 9
-
[10]BS10 (def=0x0) // Set bit 10
-
[11]BS11 (def=0x0) // Set bit 11
-
[12]BS12 (def=0x0) // Set bit 12
-
[13]BS13 (def=0x0) // Set bit 13
-
[14]BS14 (def=0x0) // Set bit 14
-
[15]BS15 (def=0x0) // Set bit 15
-
[16]BR0 (def=0x0) // Reset bit 0
-
[17]BR1 (def=0x0) // Reset bit 1
-
[18]BR2 (def=0x0) // Reset bit 2
-
[19]BR3 (def=0x0) // Reset bit 3
-
[20]BR4 (def=0x0) // Reset bit 4
-
[21]BR5 (def=0x0) // Reset bit 5
-
[22]BR6 (def=0x0) // Reset bit 6
-
[23]BR7 (def=0x0) // Reset bit 7
-
[24]BR8 (def=0x0) // Reset bit 8
-
[25]BR9 (def=0x0) // Reset bit 9
-
[26]BR10 (def=0x0) // Reset bit 10
-
[27]BR11 (def=0x0) // Reset bit 11
-
[28]BR12 (def=0x0) // Reset bit 12
-
[29]BR13 (def=0x0) // Reset bit 13
-
[30]BR14 (def=0x0) // Reset bit 14
-
[31]BR15 (def=0x0) // Reset bit 15
0x40011814BCR// Port bit reset register (GPIOn_BCR)
-
[0]BR0 (def=0x0) // Reset bit 0
-
[1]BR1 (def=0x0) // Reset bit 1
-
[2]BR2 (def=0x0) // Reset bit 1
-
[3]BR3 (def=0x0) // Reset bit 3
-
[4]BR4 (def=0x0) // Reset bit 4
-
[5]BR5 (def=0x0) // Reset bit 5
-
[6]BR6 (def=0x0) // Reset bit 6
-
[7]BR7 (def=0x0) // Reset bit 7
-
[8]BR8 (def=0x0) // Reset bit 8
-
[9]BR9 (def=0x0) // Reset bit 9
-
[10]BR10 (def=0x0) // Reset bit 10
-
[11]BR11 (def=0x0) // Reset bit 11
-
[12]BR12 (def=0x0) // Reset bit 12
-
[13]BR13 (def=0x0) // Reset bit 13
-
[14]BR14 (def=0x0) // Reset bit 14
-
[15]BR15 (def=0x0) // Reset bit 15
0x40011818LCKR// Port configuration lock register
-
[0]LCK0 (def=0x0) // Port A Lock bit 0
-
[1]LCK1 (def=0x0) // Port A Lock bit 1
-
[2]LCK2 (def=0x0) // Port A Lock bit 2
-
[3]LCK3 (def=0x0) // Port A Lock bit 3
-
[4]LCK4 (def=0x0) // Port A Lock bit 4
-
[5]LCK5 (def=0x0) // Port A Lock bit 5
-
[6]LCK6 (def=0x0) // Port A Lock bit 6
-
[7]LCK7 (def=0x0) // Port A Lock bit 7
-
[8]LCK8 (def=0x0) // Port A Lock bit 8
-
[9]LCK9 (def=0x0) // Port A Lock bit 9
-
[10]LCK10 (def=0x0) // Port A Lock bit 10
-
[11]LCK11 (def=0x0) // Port A Lock bit 11
-
[12]LCK12 (def=0x0) // Port A Lock bit 12
-
[13]LCK13 (def=0x0) // Port A Lock bit 13
-
[14]LCK14 (def=0x0) // Port A Lock bit 14
-
[15]LCK15 (def=0x0) // Port A Lock bit 15
-
[16]LCKK (def=0x0) // Lock key
0x40010000AFIO// Alternate function I/O
0x40010000ECR// Event Control Register (AFIO_ECR)
-
[0:3]PIN (def=0x0) // Pin selection
-
[4:6]PORT (def=0x0) // Port selection
-
[7]EVOE (def=0x0) // Event Output Enable
0x40010004PCFR1// AF remap and debug I/O configuration register (AFIO_PCFR1)
-
[0]SPI1_RM (def=0x0) // SPI1 remapping
-
[1]I2C1_RM (def=0x0) // I2C1 remapping
-
[2]USART1_RM (def=0x0) // USART1 remapping
-
[3]USART2_RM (def=0x0) // USART2 remapping
-
[4:5]USART3_RM (def=0x0) // USART3 remapping
-
[6:7]TIM1_RM (def=0x0) // TIM1 remapping
-
[8:9]TIM2_RM (def=0x0) // TIM2 remapping
-
[10:11]TIM3_RM (def=0x0) // TIM3 remapping
-
[12]TIM4_RM (def=0x0) // TIM4 remapping
-
[13:14]CAN1_RM (def=0x0) // CAN1 remapping
-
[15]PD0PD1_RM (def=0x0) // Port D0/Port D1 mapping on OSCIN/OSCOUT
-
[16]TIM5CH4_RM (def=0x0) // TIM5 channel4 internal remap
-
[17]ADC1_ETRGINJ_RM (def=0x0) // ADC 1 External trigger injected conversion remapping
-
[18]ADC1_ETRGREG_RM (def=0x0) // ADC 1 external trigger regular conversion remapping
-
[19]ADC2_ETRGINJ_RM (def=0x0) // ADC 2 External trigger injected conversion remapping
-
[20]ADC2_ETRGREG_RM (def=0x0) // ADC 2 external trigger regular conversion remapping
-
[21]ETH_RM (def=0x0) // Ethernet remapping
-
[22]CAN2_RM (def=0x0) // CAN2 remapping
-
[23]MII_RMII_SEL (def=0x0) // MII_RMII_SEL
-
[24:26]SW_CFG (def=0x0) // Serial wire JTAG configuration
-
[28]SPI3_RM (def=0x0) // SPI3 remapping
-
[29]TIM2ITR1_RM (def=0x0) // TIM2 internally triggers 1 remapping
-
[30]PTP_PPS_RM (def=0x0) // Ethernet PTP_PPS remapping
0x40010008EXTICR1// External interrupt configuration register 1 (AFIO_EXTICR1)
-
[0:3]EXTI0 (def=0x0) // EXTI0 configuration
-
[4:7]EXTI1 (def=0x0) // EXTI1 configuration
-
[8:11]EXTI2 (def=0x0) // EXTI2 configuration
-
[12:15]EXTI3 (def=0x0) // EXTI3 configuration
0x4001000CEXTICR2// External interrupt configuration register 2 (AFIO_EXTICR2)
-
[0:3]EXTI4 (def=0x0) // EXTI4 configuration
-
[4:7]EXTI5 (def=0x0) // EXTI5 configuration
-
[8:11]EXTI6 (def=0x0) // EXTI6 configuration
-
[12:15]EXTI7 (def=0x0) // EXTI7 configuration
0x40010010EXTICR3// External interrupt configuration register 3 (AFIO_EXTICR3)
-
[0:3]EXTI8 (def=0x0) // EXTI8 configuration
-
[4:7]EXTI9 (def=0x0) // EXTI9 configuration
-
[8:11]EXTI10 (def=0x0) // EXTI10 configuration
-
[12:15]EXTI11 (def=0x0) // EXTI11 configuration
0x40010014EXTICR4// External interrupt configuration register 4 (AFIO_EXTICR4)
-
[0:3]EXTI12 (def=0x0) // EXTI12 configuration
-
[4:7]EXTI13 (def=0x0) // EXTI13 configuration
-
[8:11]EXTI14 (def=0x0) // EXTI14 configuration
-
[12:15]EXTI15 (def=0x0) // EXTI15 configuration
0x4001001CPCFR2// AF remap and debug I/O configuration register (AFIO_PCFR2)
-
[2]TIM8_RM (def=0x0) // TIM8 remapping
-
[3:4]TIM9_RM (def=0x0) // TIM9 remapping
-
[5:6]TIM10_RM (def=0x0) // TIM10 remapping
-
[10]FSMC_NADV (def=0x0) // FSMC_NADV
-
[16:17]UART4_RM (def=0x0) // UART4 remapping
-
[18:19]UART5_RM (def=0x0) // UART5 remapping
-
[20:21]UART6_RM (def=0x0) // UART6 remapping
-
[22:23]UART7_RM (def=0x0) // UART7 remapping
-
[24:25]UART8_RM (def=0x0) // UART8 remapping
-
[26]UART1_RM1 (def=0x0) // UART1 remapping
0x40010400EXTI// EXTI
0x40010400INTENR// Interrupt mask register (EXTI_INTENR)
-
[0]MR0 (def=0x0) // Interrupt Mask on line 0
-
[1]MR1 (def=0x0) // Interrupt Mask on line 1
-
[2]MR2 (def=0x0) // Interrupt Mask on line 2
-
[3]MR3 (def=0x0) // Interrupt Mask on line 3
-
[4]MR4 (def=0x0) // Interrupt Mask on line 4
-
[5]MR5 (def=0x0) // Interrupt Mask on line 5
-
[6]MR6 (def=0x0) // Interrupt Mask on line 6
-
[7]MR7 (def=0x0) // Interrupt Mask on line 7
-
[8]MR8 (def=0x0) // Interrupt Mask on line 8
-
[9]MR9 (def=0x0) // Interrupt Mask on line 9
-
[10]MR10 (def=0x0) // Interrupt Mask on line 10
-
[11]MR11 (def=0x0) // Interrupt Mask on line 11
-
[12]MR12 (def=0x0) // Interrupt Mask on line 12
-
[13]MR13 (def=0x0) // Interrupt Mask on line 13
-
[14]MR14 (def=0x0) // Interrupt Mask on line 14
-
[15]MR15 (def=0x0) // Interrupt Mask on line 15
-
[16]MR16 (def=0x0) // Interrupt Mask on line 16
-
[17]MR17 (def=0x0) // Interrupt Mask on line 17
-
[18]MR18 (def=0x0) // Interrupt Mask on line 18
-
[19]MR19 (def=0x0) // Interrupt Mask on line 19
0x40010404EVENR// Event mask register (EXTI_EVENR)
-
[0]MR0 (def=0x0) // Event Mask on line 0
-
[1]MR1 (def=0x0) // Event Mask on line 1
-
[2]MR2 (def=0x0) // Event Mask on line 2
-
[3]MR3 (def=0x0) // Event Mask on line 3
-
[4]MR4 (def=0x0) // Event Mask on line 4
-
[5]MR5 (def=0x0) // Event Mask on line 5
-
[6]MR6 (def=0x0) // Event Mask on line 6
-
[7]MR7 (def=0x0) // Event Mask on line 7
-
[8]MR8 (def=0x0) // Event Mask on line 8
-
[9]MR9 (def=0x0) // Event Mask on line 9
-
[10]MR10 (def=0x0) // Event Mask on line 10
-
[11]MR11 (def=0x0) // Event Mask on line 11
-
[12]MR12 (def=0x0) // Event Mask on line 12
-
[13]MR13 (def=0x0) // Event Mask on line 13
-
[14]MR14 (def=0x0) // Event Mask on line 14
-
[15]MR15 (def=0x0) // Event Mask on line 15
-
[16]MR16 (def=0x0) // Event Mask on line 16
-
[17]MR17 (def=0x0) // Event Mask on line 17
-
[18]MR18 (def=0x0) // Event Mask on line 18
-
[19]MR19 (def=0x0) // Event Mask on line 19
0x40010408RTENR// Rising Trigger selection register (EXTI_RTENR)
-
[0]TR0 (def=0x0) // Rising trigger event configuration of line 0
-
[1]TR1 (def=0x0) // Rising trigger event configuration of line 1
-
[2]TR2 (def=0x0) // Rising trigger event configuration of line 2
-
[3]TR3 (def=0x0) // Rising trigger event configuration of line 3
-
[4]TR4 (def=0x0) // Rising trigger event configuration of line 4
-
[5]TR5 (def=0x0) // Rising trigger event configuration of line 5
-
[6]TR6 (def=0x0) // Rising trigger event configuration of line 6
-
[7]TR7 (def=0x0) // Rising trigger event configuration of line 7
-
[8]TR8 (def=0x0) // Rising trigger event configuration of line 8
-
[9]TR9 (def=0x0) // Rising trigger event configuration of line 9
-
[10]TR10 (def=0x0) // Rising trigger event configuration of line 10
-
[11]TR11 (def=0x0) // Rising trigger event configuration of line 11
-
[12]TR12 (def=0x0) // Rising trigger event configuration of line 12
-
[13]TR13 (def=0x0) // Rising trigger event configuration of line 13
-
[14]TR14 (def=0x0) // Rising trigger event configuration of line 14
-
[15]TR15 (def=0x0) // Rising trigger event configuration of line 15
-
[16]TR16 (def=0x0) // Rising trigger event configuration of line 16
-
[17]TR17 (def=0x0) // Rising trigger event configuration of line 17
-
[18]TR18 (def=0x0) // Rising trigger event configuration of line 18
-
[19]TR19 (def=0x0) // Rising trigger event configuration of line 19
0x4001040CFTENR// Falling Trigger selection register (EXTI_FTENR)
-
[0]TR0 (def=0x0) // Falling trigger event configuration of line 0
-
[1]TR1 (def=0x0) // Falling trigger event configuration of line 1
-
[2]TR2 (def=0x0) // Falling trigger event configuration of line 2
-
[3]TR3 (def=0x0) // Falling trigger event configuration of line 3
-
[4]TR4 (def=0x0) // Falling trigger event configuration of line 4
-
[5]TR5 (def=0x0) // Falling trigger event configuration of line 5
-
[6]TR6 (def=0x0) // Falling trigger event configuration of line 6
-
[7]TR7 (def=0x0) // Falling trigger event configuration of line 7
-
[8]TR8 (def=0x0) // Falling trigger event configuration of line 8
-
[9]TR9 (def=0x0) // Falling trigger event configuration of line 9
-
[10]TR10 (def=0x0) // Falling trigger event configuration of line 10
-
[11]TR11 (def=0x0) // Falling trigger event configuration of line 11
-
[12]TR12 (def=0x0) // Falling trigger event configuration of line 12
-
[13]TR13 (def=0x0) // Falling trigger event configuration of line 13
-
[14]TR14 (def=0x0) // Falling trigger event configuration of line 14
-
[15]TR15 (def=0x0) // Falling trigger event configuration of line 15
-
[16]TR16 (def=0x0) // Falling trigger event configuration of line 16
-
[17]TR17 (def=0x0) // Falling trigger event configuration of line 17
-
[18]TR18 (def=0x0) // Falling trigger event configuration of line 18
-
[19]TR19 (def=0x0) // Falling trigger event configuration of line 19
0x40010410SWIEVR// Software interrupt event register (EXTI_SWIEVR)
-
[0]SWIER0 (def=0x0) // Software Interrupt on line 0
-
[1]SWIER1 (def=0x0) // Software Interrupt on line 1
-
[2]SWIER2 (def=0x0) // Software Interrupt on line 2
-
[3]SWIER3 (def=0x0) // Software Interrupt on line 3
-
[4]SWIER4 (def=0x0) // Software Interrupt on line 4
-
[5]SWIER5 (def=0x0) // Software Interrupt on line 5
-
[6]SWIER6 (def=0x0) // Software Interrupt on line 6
-
[7]SWIER7 (def=0x0) // Software Interrupt on line 7
-
[8]SWIER8 (def=0x0) // Software Interrupt on line 8
-
[9]SWIER9 (def=0x0) // Software Interrupt on line 9
-
[10]SWIER10 (def=0x0) // Software Interrupt on line 10
-
[11]SWIER11 (def=0x0) // Software Interrupt on line 11
-
[12]SWIER12 (def=0x0) // Software Interrupt on line 12
-
[13]SWIER13 (def=0x0) // Software Interrupt on line 13
-
[14]SWIER14 (def=0x0) // Software Interrupt on line 14
-
[15]SWIER15 (def=0x0) // Software Interrupt on line 15
-
[16]SWIER16 (def=0x0) // Software Interrupt on line 16
-
[17]SWIER17 (def=0x0) // Software Interrupt on line 17
-
[18]SWIER18 (def=0x0) // Software Interrupt on line 18
-
[19]SWIER19 (def=0x0) // Software Interrupt on line 19
0x40010414INTFR// Pending register (EXTI_INTFR)
-
[0]PR0 (def=0x0) // Pending bit 0
-
[1]PR1 (def=0x0) // Pending bit 1
-
[2]PR2 (def=0x0) // Pending bit 2
-
[3]PR3 (def=0x0) // Pending bit 3
-
[4]PR4 (def=0x0) // Pending bit 4
-
[5]PR5 (def=0x0) // Pending bit 5
-
[6]PR6 (def=0x0) // Pending bit 6
-
[7]PR7 (def=0x0) // Pending bit 7
-
[8]PR8 (def=0x0) // Pending bit 8
-
[9]PR9 (def=0x0) // Pending bit 9
-
[10]PR10 (def=0x0) // Pending bit 10
-
[11]PR11 (def=0x0) // Pending bit 11
-
[12]PR12 (def=0x0) // Pending bit 12
-
[13]PR13 (def=0x0) // Pending bit 13
-
[14]PR14 (def=0x0) // Pending bit 14
-
[15]PR15 (def=0x0) // Pending bit 15
-
[16]PR16 (def=0x0) // Pending bit 16
-
[17]PR17 (def=0x0) // Pending bit 17
-
[18]PR18 (def=0x0) // Pending bit 18
-
[19]PR19 (def=0x0) // Pending bit 19
- [18] TAMPER // Tamper interrupt
- [22] EXTI0 // EXTI Line0 interrupt
- [23] EXTI1 // EXTI Line1 interrupt
- [24] EXTI2 // EXTI Line2 interrupt
- [25] EXTI3 // EXTI Line3 interrupt
- [26] EXTI4 // EXTI Line4 interrupt
- [39] EXTI9_5 // EXTI Line[9:5] interrupts
- [56] EXTI15_10 // EXTI Line[15:10] interrupts
0x40020000DMA1// DMA1 controller
0x40020000INTFR// DMA interrupt status register (DMA_INTFR)
-
[0]GIF1 (def=0x0) // Channel 1 Global interrupt flag
-
[1]TCIF1 (def=0x0) // Channel 1 Transfer Complete flag
-
[2]HTIF1 (def=0x0) // Channel 1 Half Transfer Complete flag
-
[3]TEIF1 (def=0x0) // Channel 1 Transfer Error flag
-
[4]GIF2 (def=0x0) // Channel 2 Global interrupt flag
-
[5]TCIF2 (def=0x0) // Channel 2 Transfer Complete flag
-
[6]HTIF2 (def=0x0) // Channel 2 Half Transfer Complete flag
-
[7]TEIF2 (def=0x0) // Channel 2 Transfer Error flag
-
[8]GIF3 (def=0x0) // Channel 3 Global interrupt flag
-
[9]TCIF3 (def=0x0) // Channel 3 Transfer Complete flag
-
[10]HTIF3 (def=0x0) // Channel 3 Half Transfer Complete flag
-
[11]TEIF3 (def=0x0) // Channel 3 Transfer Error flag
-
[12]GIF4 (def=0x0) // Channel 4 Global interrupt flag
-
[13]TCIF4 (def=0x0) // Channel 4 Transfer Complete flag
-
[14]HTIF4 (def=0x0) // Channel 4 Half Transfer Complete flag
-
[15]TEIF4 (def=0x0) // Channel 4 Transfer Error flag
-
[16]GIF5 (def=0x0) // Channel 5 Global interrupt flag
-
[17]TCIF5 (def=0x0) // Channel 5 Transfer Complete flag
-
[18]HTIF5 (def=0x0) // Channel 5 Half Transfer Complete flag
-
[19]TEIF5 (def=0x0) // Channel 5 Transfer Error flag
-
[20]GIF6 (def=0x0) // Channel 6 Global interrupt flag
-
[21]TCIF6 (def=0x0) // Channel 6 Transfer Complete flag
-
[22]HTIF6 (def=0x0) // Channel 6 Half Transfer Complete flag
-
[23]TEIF6 (def=0x0) // Channel 6 Transfer Error flag
-
[24]GIF7 (def=0x0) // Channel 7 Global interrupt flag
-
[25]TCIF7 (def=0x0) // Channel 7 Transfer Complete flag
-
[26]HTIF7 (def=0x0) // Channel 7 Half Transfer Complete flag
-
[27]TEIF7 (def=0x0) // Channel 7 Transfer Error flag
-
[28]GIF8 (def=0x0) // Channel 8 Global interrupt flag use in ch32v20_D8/D8W/D6
-
[29]TCIF8 (def=0x0) // Channel 8 Transfer Complete flag use in ch32v20_D8/D8W/D6
-
[30]HTIF8 (def=0x0) // Channel 8 Half Transfer Complete flag use in ch32v20_D8/D8W/D6
-
[31]TEIF8 (def=0x0) // Channel 8 Transfer Error flag use in ch32v20_D8/D8W/D6
0x40020004INTFCR// DMA interrupt flag clear register (DMA_INTFCR)
-
[0]CGIF1 (def=0x0) // Channel 1 Global interrupt clear
-
[4]CGIF2 (def=0x0) // Channel 2 Global interrupt clear
-
[8]CGIF3 (def=0x0) // Channel 3 Global interrupt clear
-
[12]CGIF4 (def=0x0) // Channel 4 Global interrupt clear
-
[16]CGIF5 (def=0x0) // Channel 5 Global interrupt clear
-
[20]CGIF6 (def=0x0) // Channel 6 Global interrupt clear
-
[24]CGIF7 (def=0x0) // Channel 7 Global interrupt clear
-
[28]CGIF8 (def=0x0) // Channel 8 Global interrupt clear use in ch32v20_D8/D8W/D6
-
[1]CTCIF1 (def=0x0) // Channel 1 Transfer Complete clear
-
[5]CTCIF2 (def=0x0) // Channel 2 Transfer Complete clear
-
[9]CTCIF3 (def=0x0) // Channel 3 Transfer Complete clear
-
[13]CTCIF4 (def=0x0) // Channel 4 Transfer Complete clear
-
[17]CTCIF5 (def=0x0) // Channel 5 Transfer Complete clear
-
[21]CTCIF6 (def=0x0) // Channel 6 Transfer Complete clear
-
[25]CTCIF7 (def=0x0) // Channel 7 Transfer Complete clear
-
[29]CTCIF8 (def=0x0) // Channel 8 Transfer Complete clear use in ch32v20_D8/D8W/D6
-
[2]CHTIF1 (def=0x0) // Channel 1 Half Transfer clear
-
[6]CHTIF2 (def=0x0) // Channel 2 Half Transfer clear
-
[10]CHTIF3 (def=0x0) // Channel 3 Half Transfer clear
-
[14]CHTIF4 (def=0x0) // Channel 4 Half Transfer clear
-
[18]CHTIF5 (def=0x0) // Channel 5 Half Transfer clear
-
[22]CHTIF6 (def=0x0) // Channel 6 Half Transfer clear
-
[26]CHTIF7 (def=0x0) // Channel 7 Half Transfer clear
-
[30]CHTIF8 (def=0x0) // Channel 8 Half Transfer clear use in ch32v20_D8/D8W/D6
-
[3]CTEIF1 (def=0x0) // Channel 1 Transfer Error clear
-
[7]CTEIF2 (def=0x0) // Channel 2 Transfer Error clear
-
[11]CTEIF3 (def=0x0) // Channel 3 Transfer Error clear
-
[15]CTEIF4 (def=0x0) // Channel 4 Transfer Error clear
-
[19]CTEIF5 (def=0x0) // Channel 5 Transfer Error clear
-
[23]CTEIF6 (def=0x0) // Channel 6 Transfer Error clear
-
[27]CTEIF7 (def=0x0) // Channel 7 Transfer Error clear
-
[31]CTEIF8 (def=0x0) // Channel 8 Transfer Error clear use in ch32v20_D8/D8W/D6
0x40020008CFGR1// DMA channel configuration register (DMA_CFGR)
-
[0]EN (def=0x0) // Channel enable
-
[1]TCIE (def=0x0) // Transfer complete interrupt enable
-
[2]HTIE (def=0x0) // Half Transfer interrupt enable
-
[3]TEIE (def=0x0) // Transfer error interrupt enable
-
[4]DIR (def=0x0) // Data transfer direction
-
[5]CIRC (def=0x0) // Circular mode
-
[6]PINC (def=0x0) // Peripheral increment mode
-
[7]MINC (def=0x0) // Memory increment mode
-
[8:9]PSIZE (def=0x0) // Peripheral size
-
[10:11]MSIZE (def=0x0) // Memory size
-
[12:13]PL (def=0x0) // Channel Priority level
-
[14]MEM2MEM (def=0x0) // Memory to memory mode
0x4002000CCNTR1// DMA channel 1 number of data register
-
[0:15]NDT (def=0x0) // Number of data to transfer
0x40020010PADDR1// DMA channel 1 peripheral address register
-
[0:31]PA (def=0x0) // Peripheral address
0x40020014MADDR1// DMA channel 1 memory address register
-
[0:31]MA (def=0x0) // Memory address
0x4002001CCFGR2// DMA channel configuration register (DMA_CFGR)
-
[0]EN (def=0x0) // Channel enable
-
[1]TCIE (def=0x0) // Transfer complete interrupt enable
-
[2]HTIE (def=0x0) // Half Transfer interrupt enable
-
[3]TEIE (def=0x0) // Transfer error interrupt enable
-
[4]DIR (def=0x0) // Data transfer direction
-
[5]CIRC (def=0x0) // Circular mode
-
[6]PINC (def=0x0) // Peripheral increment mode
-
[7]MINC (def=0x0) // Memory increment mode
-
[8:9]PSIZE (def=0x0) // Peripheral size
-
[10:11]MSIZE (def=0x0) // Memory size
-
[12:13]PL (def=0x0) // Channel Priority level
-
[14]MEM2MEM (def=0x0) // Memory to memory mode
0x40020020CNTR2// DMA channel 2 number of data register
-
[0:15]NDT (def=0x0) // Number of data to transfer
0x40020024PADDR2// DMA channel 2 peripheral address register
-
[0:31]PA (def=0x0) // Peripheral address
0x40020028MADDR2// DMA channel 2 memory address register
-
[0:31]MA (def=0x0) // Memory address
0x40020030CFGR3// DMA channel configuration register (DMA_CFGR)
-
[0]EN (def=0x0) // Channel enable
-
[1]TCIE (def=0x0) // Transfer complete interrupt enable
-
[2]HTIE (def=0x0) // Half Transfer interrupt enable
-
[3]TEIE (def=0x0) // Transfer error interrupt enable
-
[4]DIR (def=0x0) // Data transfer direction
-
[5]CIRC (def=0x0) // Circular mode
-
[6]PINC (def=0x0) // Peripheral increment mode
-
[7]MINC (def=0x0) // Memory increment mode
-
[8:9]PSIZE (def=0x0) // Peripheral size
-
[10:11]MSIZE (def=0x0) // Memory size
-
[12:13]PL (def=0x0) // Channel Priority level
-
[14]MEM2MEM (def=0x0) // Memory to memory mode
0x40020034CNTR3// DMA channel 3 number of data register
-
[0:15]NDT (def=0x0) // Number of data to transfer
0x40020038PADDR3// DMA channel 3 peripheral address register
-
[0:31]PA (def=0x0) // Peripheral address
0x4002003CMADDR3// DMA channel 3 memory address register
-
[0:31]MA (def=0x0) // Memory address
0x40020044CFGR4// DMA channel configuration register (DMA_CFGR)
-
[0]EN (def=0x0) // Channel enable
-
[1]TCIE (def=0x0) // Transfer complete interrupt enable
-
[2]HTIE (def=0x0) // Half Transfer interrupt enable
-
[3]TEIE (def=0x0) // Transfer error interrupt enable
-
[4]DIR (def=0x0) // Data transfer direction
-
[5]CIRC (def=0x0) // Circular mode
-
[6]PINC (def=0x0) // Peripheral increment mode
-
[7]MINC (def=0x0) // Memory increment mode
-
[8:9]PSIZE (def=0x0) // Peripheral size
-
[10:11]MSIZE (def=0x0) // Memory size
-
[12:13]PL (def=0x0) // Channel Priority level
-
[14]MEM2MEM (def=0x0) // Memory to memory mode
0x40020048CNTR4// DMA channel 4 number of data register
-
[0:15]NDT (def=0x0) // Number of data to transfer
0x4002004CPADDR4// DMA channel 4 peripheral address register
-
[0:31]PA (def=0x0) // Peripheral address
0x40020050MADDR4// DMA channel 4 memory address register
-
[0:31]MA (def=0x0) // Memory address
0x40020058CFGR5// DMA channel configuration register (DMA_CFGR)
-
[0]EN (def=0x0) // Channel enable
-
[1]TCIE (def=0x0) // Transfer complete interrupt enable
-
[2]HTIE (def=0x0) // Half Transfer interrupt enable
-
[3]TEIE (def=0x0) // Transfer error interrupt enable
-
[4]DIR (def=0x0) // Data transfer direction
-
[5]CIRC (def=0x0) // Circular mode
-
[6]PINC (def=0x0) // Peripheral increment mode
-
[7]MINC (def=0x0) // Memory increment mode
-
[8:9]PSIZE (def=0x0) // Peripheral size
-
[10:11]MSIZE (def=0x0) // Memory size
-
[12:13]PL (def=0x0) // Channel Priority level
-
[14]MEM2MEM (def=0x0) // Memory to memory mode
0x4002005CCNTR5// DMA channel 5 number of data register
-
[0:15]NDT (def=0x0) // Number of data to transfer
0x40020060PADDR5// DMA channel 5 peripheral address register
-
[0:31]PA (def=0x0) // Peripheral address
0x40020064MADDR5// DMA channel 5 memory address register
-
[0:31]MA (def=0x0) // Memory address
0x4002006CCFGR6// DMA channel configuration register (DMA_CFGR)
-
[0]EN (def=0x0) // Channel enable
-
[1]TCIE (def=0x0) // Transfer complete interrupt enable
-
[2]HTIE (def=0x0) // Half Transfer interrupt enable
-
[3]TEIE (def=0x0) // Transfer error interrupt enable
-
[4]DIR (def=0x0) // Data transfer direction
-
[5]CIRC (def=0x0) // Circular mode
-
[6]PINC (def=0x0) // Peripheral increment mode
-
[7]MINC (def=0x0) // Memory increment mode
-
[8:9]PSIZE (def=0x0) // Peripheral size
-
[10:11]MSIZE (def=0x0) // Memory size
-
[12:13]PL (def=0x0) // Channel Priority level
-
[14]MEM2MEM (def=0x0) // Memory to memory mode
0x40020070CNTR6// DMA channel 6 number of data register
-
[0:15]NDT (def=0x0) // Number of data to transfer
0x40020074PADDR6// DMA channel 6 peripheral address register
-
[0:31]PA (def=0x0) // Peripheral address
0x40020078MADDR6// DMA channel 6 memory address register
-
[0:31]MA (def=0x0) // Memory address
0x40020080CFGR7// DMA channel configuration register (DMA_CFGR)
-
[0]EN (def=0x0) // Channel enable
-
[1]TCIE (def=0x0) // Transfer complete interrupt enable
-
[2]HTIE (def=0x0) // Half Transfer interrupt enable
-
[3]TEIE (def=0x0) // Transfer error interrupt enable
-
[4]DIR (def=0x0) // Data transfer direction
-
[5]CIRC (def=0x0) // Circular mode
-
[6]PINC (def=0x0) // Peripheral increment mode
-
[7]MINC (def=0x0) // Memory increment mode
-
[8:9]PSIZE (def=0x0) // Peripheral size
-
[10:11]MSIZE (def=0x0) // Memory size
-
[12:13]PL (def=0x0) // Channel Priority level
-
[14]MEM2MEM (def=0x0) // Memory to memory mode
0x40020084CNTR7// DMA channel 7 number of data register
-
[0:15]NDT (def=0x0) // Number of data to transfer
0x40020088PADDR7// DMA channel 7 peripheral address register
-
[0:31]PA (def=0x0) // Peripheral address
0x4002008CMADDR7// DMA channel 7 memory address register
-
[0:31]MA (def=0x0) // Memory address
0x40020094CFGR8// DMA channel configuration register (DMA_CFGR) use in ch32v20_D8/D8W/D6
-
[0]EN (def=0x0) // Channel enable
-
[1]TCIE (def=0x0) // Transfer complete interrupt enable
-
[2]HTIE (def=0x0) // Half Transfer interrupt enable
-
[3]TEIE (def=0x0) // Transfer error interrupt enable
-
[4]DIR (def=0x0) // Data transfer direction
-
[5]CIRC (def=0x0) // Circular mode
-
[6]PINC (def=0x0) // Peripheral increment mode
-
[7]MINC (def=0x0) // Memory increment mode
-
[8:9]PSIZE (def=0x0) // Peripheral size
-
[10:11]MSIZE (def=0x0) // Memory size
-
[12:13]PL (def=0x0) // Channel Priority level
-
[14]MEM2MEM (def=0x0) // Memory to memory mode
0x40020098CNTR8// DMA channel 8 number of data register use in ch32v20_D8/D8W/D6
-
[0:15]NDT (def=0x0) // Number of data to transfer
0x4002009CPADDR8// DMA channel 8 peripheral address register use in ch32v20_D8/D8W/D6
-
[0:31]PA (def=0x0) // Peripheral address
0x400200A0MADDR8// DMA channel 8 memory address register use in ch32v20_D8/D8W/D6
-
[0:31]MA (def=0x0) // Memory address
- [27] DMA1_Channel1 // DMA1 Channel1 global interrupt
- [28] DMA1_Channel2 // DMA1 Channel2 global interrupt
- [29] DMA1_Channel3 // DMA1 Channel3 global interrupt
- [30] DMA1_Channel4 // DMA1 Channel4 global interrupt
- [31] DMA1_Channel5 // DMA1 Channel5 global interrupt
- [32] DMA1_Channel6 // DMA1 Channel6 global interrupt
- [33] DMA1_Channel7 // DMA1 Channel7 global interrupt
0x40002800RTC// Real time clock
0x40002800CTLRH// RTC Control Register High
-
[0]SECIE (def=0x0) // Second interrupt Enable
-
[1]ALRIE (def=0x0) // Alarm interrupt Enable
-
[2]OWIE (def=0x0) // Overflow interrupt Enable
0x40002804CTLRL// RTC Control Register Low
-
[0]SECF (def=0x0) // Second Flag
-
[1]ALRF (def=0x0) // Alarm Flag
-
[2]OWF (def=0x0) // Overflow Flag
-
[3]RSF (def=0x0) // Registers Synchronized Flag
-
[4]CNF (def=0x0) // Configuration Flag
-
[5]RTOFF (def=0x1) // RTC operation OFF
0x40002808PSCRH// RTC Prescaler Load Register High
-
[0:3]PRL (def=0x0) // RTC Prescaler Load Register High
0x4000280CPSCRL// RTC Prescaler Load Register Low
-
[0:15]PRL (def=0x8000) // RTC Prescaler Divider Register Low
0x40002810DIVH// RTC Prescaler Divider Register High
-
[0:3]DIV (def=0x0) // RTC prescaler divider register high
0x40002814DIVL// RTC Prescaler Divider Register Low
-
[0:15]DIV (def=0x8000) // RTC prescaler divider register Low
0x40002818CNTH// RTC Counter Register High
-
[0:15]CNT (def=0x0) // RTC counter register high
0x4000281CCNTL// RTC Counter Register Low
-
[0:15]CNT (def=0x0) // RTC counter register Low
0x40002820ALRMH// RTC Alarm Register High
-
[0:15]ALR (def=0xFFFF) // RTC alarm register high
0x40002824ALRML// RTC Alarm Register Low
-
[0:15]ALR (def=0xFFFF) // RTC alarm register low
- [19] RTC // RTC global interrupt
- [57] RTCAlarm // RTC Alarms through EXTI line interrupt
0x40006C00BKP// Backup registers
0x40006C04DATAR1// Backup data register (BKP_DR)
-
[0:15]D1 (def=0x0) // Backup data
0x40006C08DATAR2// Backup data register (BKP_DR)
-
[0:15]D2 (def=0x0) // Backup data
0x40006C0CDATAR3// Backup data register (BKP_DR)
-
[0:15]D3 (def=0x0) // Backup data
0x40006C10DATAR4// Backup data register (BKP_DR)
-
[0:15]D4 (def=0x0) // Backup data
0x40006C14DATAR5// Backup data register (BKP_DR)
-
[0:15]D5 (def=0x0) // Backup data
0x40006C18DATAR6// Backup data register (BKP_DR)
-
[0:15]D6 (def=0x0) // Backup data
0x40006C1CDATAR7// Backup data register (BKP_DR)
-
[0:15]D7 (def=0x0) // Backup data
0x40006C20DATAR8// Backup data register (BKP_DR)
-
[0:15]D8 (def=0x0) // Backup data
0x40006C24DATAR9// Backup data register (BKP_DR)
-
[0:15]D9 (def=0x0) // Backup data
0x40006C28DATAR10// Backup data register (BKP_DR)
-
[0:15]D10 (def=0x0) // Backup data
0x40006C40DATAR11// Backup data register (BKP_DR)
-
[0:15]DR11 (def=0x0) // Backup data
0x40006C44DATAR12// Backup data register (BKP_DR)
-
[0:15]DR12 (def=0x0) // Backup data
0x40006C48DATAR13// Backup data register (BKP_DR)
-
[0:15]DR13 (def=0x0) // Backup data
0x40006C4CDATAR14// Backup data register (BKP_DR)
-
[0:15]D14 (def=0x0) // Backup data
0x40006C50DATAR15// Backup data register (BKP_DR)
-
[0:15]D15 (def=0x0) // Backup data
0x40006C54DATAR16// Backup data register (BKP_DR)
-
[0:15]D16 (def=0x0) // Backup data
0x40006C58DATAR17// Backup data register (BKP_DR)
-
[0:15]D17 (def=0x0) // Backup data
0x40006C5CDATAR18// Backup data register (BKP_DR)
-
[0:15]D18 (def=0x0) // Backup data
0x40006C60DATAR19// Backup data register (BKP_DR)
-
[0:15]D19 (def=0x0) // Backup data
0x40006C64DATAR20// Backup data register (BKP_DR)
-
[0:15]D20 (def=0x0) // Backup data
0x40006C68DATAR21// Backup data register (BKP_DR)
-
[0:15]D21 (def=0x0) // Backup data
0x40006C6CDATAR22// Backup data register (BKP_DR)
-
[0:15]D22 (def=0x0) // Backup data
0x40006C70DATAR23// Backup data register (BKP_DR)
-
[0:15]D23 (def=0x0) // Backup data
0x40006C74DATAR24// Backup data register (BKP_DR)
-
[0:15]D24 (def=0x0) // Backup data
0x40006C78DATAR25// Backup data register (BKP_DR)
-
[0:15]D25 (def=0x0) // Backup data
0x40006C7CDATAR26// Backup data register (BKP_DR)
-
[0:15]D26 (def=0x0) // Backup data
0x40006C80DATAR27// Backup data register (BKP_DR)
-
[0:15]D27 (def=0x0) // Backup data
0x40006C84DATAR28// Backup data register (BKP_DR)
-
[0:15]D28 (def=0x0) // Backup data
0x40006C88DATAR29// Backup data register (BKP_DR)
-
[0:15]D29 (def=0x0) // Backup data
0x40006C8CDATAR30// Backup data register (BKP_DR)
-
[0:15]D30 (def=0x0) // Backup data
0x40006C90DATAR31// Backup data register (BKP_DR)
-
[0:15]D31 (def=0x0) // Backup data
0x40006C94DATAR32// Backup data register (BKP_DR)
-
[0:15]D32 (def=0x0) // Backup data
0x40006C98DATAR33// Backup data register (BKP_DR)
-
[0:15]D33 (def=0x0) // Backup data
0x40006C9CDATAR34// Backup data register (BKP_DR)
-
[0:15]D34 (def=0x0) // Backup data
0x40006CA0DATAR35// Backup data register (BKP_DR)
-
[0:15]D35 (def=0x0) // Backup data
0x40006CA4DATAR36// Backup data register (BKP_DR)
-
[0:15]D36 (def=0x0) // Backup data
0x40006CA8DATAR37// Backup data register (BKP_DR)
-
[0:15]D37 (def=0x0) // Backup data
0x40006CACDATAR38// Backup data register (BKP_DR)
-
[0:15]D38 (def=0x0) // Backup data
0x40006CB0DATAR39// Backup data register (BKP_DR)
-
[0:15]D39 (def=0x0) // Backup data
0x40006CB4DATAR40// Backup data register (BKP_DR)
-
[0:15]D40 (def=0x0) // Backup data
0x40006CB8DATAR41// Backup data register (BKP_DR)
-
[0:15]D41 (def=0x0) // Backup data
0x40006CBCDATAR42// Backup data register (BKP_DR)
-
[0:15]D42 (def=0x0) // Backup data
0x40006C2COCTLR// RTC clock calibration register (BKP_OCTLR)
-
[0:6]CAL (def=0x0) // Calibration value
-
[7]CCO (def=0x0) // Calibration Clock Output
-
[8]ASOE (def=0x0) // Alarm or second output enable
-
[9]ASOS (def=0x0) // Alarm or second output selection
0x40006C30TPCTLR// Backup control register (BKP_TPCTLR)
-
[0]TPE (def=0x0) // Tamper pin enable
-
[1]TPAL (def=0x0) // Tamper pin active level
0x40006C34TPCSR// BKP_TPCSR control/status register (BKP_CSR)
-
[0]CTE (def=0x0) // Clear Tamper event
-
[1]CTI (def=0x0) // Clear Tamper Interrupt
-
[2]TPIE (def=0x0) // Tamper Pin interrupt enable
-
[8]TEF (def=0x0) // Tamper Event Flag
-
[9]TIF (def=0x0) // Tamper Interrupt Flag
0x40003000IWDG// Independent watchdog
0x40003000CTLR// Key register (IWDG_CTLR)
-
[0:15]KEY (def=0x0) // Key value
0x40003004PSCR// Prescaler register (IWDG_PSCR)
-
[0:2]PR (def=0x0) // Prescaler divider
0x40003008RLDR// Reload register (IWDG_RLDR)
-
[0:11]RL (def=0xFFF) // Watchdog counter reload value
0x4000300CSTATR// Status register (IWDG_SR)
-
[0]PVU (def=0x0) // Watchdog prescaler value update
-
[1]RVU (def=0x0) // Watchdog counter reload value update
0x40002C00WWDG// Window watchdog
0x40002C00CTLR// Control register (WWDG_CR)
-
[0:6]T (def=0x7F) // 7-bit counter (MSB to LSB)
-
[7]WDGA (def=0x0) // Activation bit
0x40002C04CFGR// Configuration register (WWDG_CFGR)
-
[0:6]W (def=0x7F) // 7-bit window value
-
[7:8]WDGTB (def=0x0) // Timer Base
-
[9]EWI (def=0x0) // Early Wakeup Interrupt
0x40002C08STATR// Status register (WWDG_SR)
-
[0]WEIF (def=0x0) // Early Wakeup Interrupt Flag
- [16] WWDG // Window Watchdog interrupt
0x40012C00TIM1// Advanced timer
0x40012C00CTLR1// control register 1
-
[8:9]CKD (def=0x0) // Clock division
-
[7]ARPE (def=0x0) // Auto-reload preload enable
-
[5:6]CMS (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]OPM (def=0x0) // One-pulse mode
-
[2]URS (def=0x0) // Update request source
-
[1]UDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40012C04CTLR2// control register 2
-
[14]OIS4 (def=0x0) // Output Idle state 4
-
[13]OIS3N (def=0x0) // Output Idle state 3
-
[12]OIS3 (def=0x0) // Output Idle state 3
-
[11]OIS2N (def=0x0) // Output Idle state 2
-
[10]OIS2 (def=0x0) // Output Idle state 2
-
[9]OIS1N (def=0x0) // Output Idle state 1
-
[8]OIS1 (def=0x0) // Output Idle state 1
-
[7]TI1S (def=0x0) // TI1 selection
-
[4:6]MMS (def=0x0) // Master mode selection
-
[3]CCDS (def=0x0) // Capture/compare DMA selection
-
[2]CCUS (def=0x0) // Capture/compare control update selection
-
[0]CCPC (def=0x0) // Capture/compare preloaded control
0x40012C08SMCFGR// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]ECE (def=0x0) // External clock enable
-
[12:13]ETPS (def=0x0) // External trigger prescaler
-
[8:11]ETF (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
-
[4:6]TS (def=0x0) // Trigger selection
-
[0:2]SMS (def=0x0) // Slave mode selection
0x40012C0CDMAINTENR// DMA/Interrupt enable register
-
[14]TDE (def=0x0) // Trigger DMA request enable
-
[13]COMDE (def=0x0) // COM DMA request enable
-
[12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
-
[11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
-
[10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
-
[9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UDE (def=0x0) // Update DMA request enable
-
[7]BIE (def=0x0) // Break interrupt enable
-
[6]TIE (def=0x0) // Trigger interrupt enable
-
[5]COMIE (def=0x0) // COM interrupt enable
-
[4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
-
[3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[0]UIE (def=0x0) // Update interrupt enable
0x40012C10INTFR// status register
-
[12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
-
[11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
-
[9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
-
[7]BIF (def=0x0) // Break interrupt flag
-
[6]TIF (def=0x0) // Trigger interrupt flag
-
[5]COMIF (def=0x0) // COM interrupt flag
-
[4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
-
[3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
-
[0]UIF (def=0x0) // Update interrupt flag
0x40012C14SWEVGR// event generation register
-
[7]BG (def=0x0) // Break generation
-
[6]TG (def=0x0) // Trigger generation
-
[5]COMG (def=0x0) // Capture/Compare control update generation
-
[4]CC4G (def=0x0) // Capture/compare 4 generation
-
[3]CC3G (def=0x0) // Capture/compare 3 generation
-
[2]CC2G (def=0x0) // Capture/compare 2 generation
-
[1]CC1G (def=0x0) // Capture/compare 1 generation
-
[0]UG (def=0x0) // Update generation
0x40012C18CHCTLR1_Output// capture/compare mode register (output mode)
-
[15]OC2CE (def=0x0) // Output Compare 2 clear enable
-
[12:14]OC2M (def=0x0) // Output Compare 2 mode
-
[11]OC2PE (def=0x0) // Output Compare 2 preload enable
-
[10]OC2FE (def=0x0) // Output Compare 2 fast enable
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[7]OC1CE (def=0x0) // Output Compare 1 clear enable
-
[4:6]OC1M (def=0x0) // Output Compare 1 mode
-
[3]OC1PE (def=0x0) // Output Compare 1 preload enable
-
[2]OC1FE (def=0x0) // Output Compare 1 fast enable
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40012C18CHCTLR1_Input// capture/compare mode register 1 (input mode)
-
[12:15]IC2F (def=0x0) // Input capture 2 filter
-
[10:11]IC2PCS (def=0x0) // Input capture 2 prescaler
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[4:7]IC1F (def=0x0) // Input capture 1 filter
-
[2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40012C1CCHCTLR2_Output// capture/compare mode register (output mode)
-
[15]OC4CE (def=0x0) // Output compare 4 clear enable
-
[12:14]OC4M (def=0x0) // Output compare 4 mode
-
[11]OC4PE (def=0x0) // Output compare 4 preload enable
-
[10]OC4FE (def=0x0) // Output compare 4 fast enable
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[7]OC3CE (def=0x0) // Output compare 3 clear enable
-
[4:6]OC3M (def=0x0) // Output compare 3 mode
-
[3]OC3PE (def=0x0) // Output compare 3 preload enable
-
[2]OC3FE (def=0x0) // Output compare 3 fast enable
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x40012C1CCHCTLR2_Input// capture/compare mode register 2 (input mode)
-
[12:15]IC4F (def=0x0) // Input capture 4 filter
-
[10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[4:7]IC3F (def=0x0) // Input capture 3 filter
-
[2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
-
[0:1]CC3S (def=0x0) // Capture/compare 3 selection
0x40012C20CCER// capture/compare enable register
-
[13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CC4E (def=0x0) // Capture/Compare 4 output enable
-
[11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
-
[10]CC3NE (def=0x0) // Capture/Compare 3 complementary output enable
-
[9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
-
[8]CC3E (def=0x0) // Capture/Compare 3 output enable
-
[7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
-
[6]CC2NE (def=0x0) // Capture/Compare 2 complementary output enable
-
[5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
-
[4]CC2E (def=0x0) // Capture/Compare 2 output enable
-
[3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
-
[2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
-
[1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
-
[0]CC1E (def=0x0) // Capture/Compare 1 output enable
0x40012C24CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40012C28PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x40012C2CATRLR// auto-reload register
-
[0:15]ATRLR (def=0xFFFF) // Auto-reload value
0x40012C30RPTCR// repetition counter register
-
[0:7]RPTCR (def=0x0) // Repetition counter value
0x40012C34CH1CVR// capture/compare register 1
-
[0:15]CCR1 (def=0x0) // Capture/Compare 1 value
0x40012C38CH2CVR// capture/compare register 2
-
[0:15]CCR2 (def=0x0) // Capture/Compare 2 value
0x40012C3CCH3CVR// capture/compare register 3
-
[0:15]CCR3 (def=0x0) // Capture/Compare value
0x40012C40CH4CVR// capture/compare register 4
-
[0:15]CCR4 (def=0x0) // Capture/Compare value
0x40012C44BDTR// break and dead-time register
-
[15]MOE (def=0x0) // Main output enable
-
[14]AOE (def=0x0) // Automatic output enable
-
[13]BKP (def=0x0) // Break polarity
-
[12]BKE (def=0x0) // Break enable
-
[11]OSSR (def=0x0) // Off-state selection for Run mode
-
[10]OSSI (def=0x0) // Off-state selection for Idle mode
-
[8:9]LOCK (def=0x0) // Lock configuration
-
[0:7]DTG (def=0x0) // Dead-time generator setup
0x40012C48DMACFGR// DMA control register
-
[8:12]DBL (def=0x0) // DMA burst length
-
[0:4]DBA (def=0x0) // DMA base address
0x40012C4CDMAADR// DMA address for full transfer
-
[0:15]DMAADR (def=0x0) // DMA register for burst accesses
- [40] TIM1_BRK // TIM1 Break interrupt
- [41] TIM1_UP_ // TIM1 Update interrupt
- [42] TIM1_TRG_COM // TIM1 Trigger and Commutation interrupts
- [43] TIM1_CC // TIM1 Capture Compare interrupt
0x40013400TIM8//
0x40013400CTLR1// control register 1
-
[8:9]CKD (def=0x0) // Clock division
-
[7]ARPE (def=0x0) // Auto-reload preload enable
-
[5:6]CMS (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]OPM (def=0x0) // One-pulse mode
-
[2]URS (def=0x0) // Update request source
-
[1]UDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40013404CTLR2// control register 2
-
[14]OIS4 (def=0x0) // Output Idle state 4
-
[13]OIS3N (def=0x0) // Output Idle state 3
-
[12]OIS3 (def=0x0) // Output Idle state 3
-
[11]OIS2N (def=0x0) // Output Idle state 2
-
[10]OIS2 (def=0x0) // Output Idle state 2
-
[9]OIS1N (def=0x0) // Output Idle state 1
-
[8]OIS1 (def=0x0) // Output Idle state 1
-
[7]TI1S (def=0x0) // TI1 selection
-
[4:6]MMS (def=0x0) // Master mode selection
-
[3]CCDS (def=0x0) // Capture/compare DMA selection
-
[2]CCUS (def=0x0) // Capture/compare control update selection
-
[0]CCPC (def=0x0) // Capture/compare preloaded control
0x40013408SMCFGR// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]ECE (def=0x0) // External clock enable
-
[12:13]ETPS (def=0x0) // External trigger prescaler
-
[8:11]ETF (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
-
[4:6]TS (def=0x0) // Trigger selection
-
[0:2]SMS (def=0x0) // Slave mode selection
0x4001340CDMAINTENR// DMA/Interrupt enable register
-
[14]TDE (def=0x0) // Trigger DMA request enable
-
[13]COMDE (def=0x0) // COM DMA request enable
-
[12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
-
[11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
-
[10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
-
[9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UDE (def=0x0) // Update DMA request enable
-
[7]BIE (def=0x0) // Break interrupt enable
-
[6]TIE (def=0x0) // Trigger interrupt enable
-
[5]COMIE (def=0x0) // COM interrupt enable
-
[4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
-
[3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[0]UIE (def=0x0) // Update interrupt enable
0x40013410INTFR// status register
-
[12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
-
[11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
-
[9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
-
[7]BIF (def=0x0) // Break interrupt flag
-
[6]TIF (def=0x0) // Trigger interrupt flag
-
[5]COMIF (def=0x0) // COM interrupt flag
-
[4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
-
[3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
-
[0]UIF (def=0x0) // Update interrupt flag
0x40013414SWEVGR// event generation register
-
[7]BG (def=0x0) // Break generation
-
[6]TG (def=0x0) // Trigger generation
-
[5]COMG (def=0x0) // Capture/Compare control update generation
-
[4]CC4G (def=0x0) // Capture/compare 4 generation
-
[3]CC3G (def=0x0) // Capture/compare 3 generation
-
[2]CC2G (def=0x0) // Capture/compare 2 generation
-
[1]CC1G (def=0x0) // Capture/compare 1 generation
-
[0]UG (def=0x0) // Update generation
0x40013418CHCTLR1_Output// capture/compare mode register (output mode)
-
[15]OC2CE (def=0x0) // Output Compare 2 clear enable
-
[12:14]OC2M (def=0x0) // Output Compare 2 mode
-
[11]OC2PE (def=0x0) // Output Compare 2 preload enable
-
[10]OC2FE (def=0x0) // Output Compare 2 fast enable
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[7]OC1CE (def=0x0) // Output Compare 1 clear enable
-
[4:6]OC1M (def=0x0) // Output Compare 1 mode
-
[3]OC1PE (def=0x0) // Output Compare 1 preload enable
-
[2]OC1FE (def=0x0) // Output Compare 1 fast enable
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40013418CHCTLR1_Input// capture/compare mode register 1 (input mode)
-
[12:15]IC2F (def=0x0) // Input capture 2 filter
-
[10:11]IC2PCS (def=0x0) // Input capture 2 prescaler
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[4:7]IC1F (def=0x0) // Input capture 1 filter
-
[2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x4001341CCHCTLR2_Output// capture/compare mode register (output mode)
-
[15]OC4CE (def=0x0) // Output compare 4 clear enable
-
[12:14]OC4M (def=0x0) // Output compare 4 mode
-
[11]OC4PE (def=0x0) // Output compare 4 preload enable
-
[10]OC4FE (def=0x0) // Output compare 4 fast enable
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[7]OC3CE (def=0x0) // Output compare 3 clear enable
-
[4:6]OC3M (def=0x0) // Output compare 3 mode
-
[3]OC3PE (def=0x0) // Output compare 3 preload enable
-
[2]OC3FE (def=0x0) // Output compare 3 fast enable
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x4001341CCHCTLR2_Input// capture/compare mode register 2 (input mode)
-
[12:15]IC4F (def=0x0) // Input capture 4 filter
-
[10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[4:7]IC3F (def=0x0) // Input capture 3 filter
-
[2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
-
[0:1]CC3S (def=0x0) // Capture/compare 3 selection
0x40013420CCER// capture/compare enable register
-
[13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CC4E (def=0x0) // Capture/Compare 4 output enable
-
[11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
-
[10]CC3NE (def=0x0) // Capture/Compare 3 complementary output enable
-
[9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
-
[8]CC3E (def=0x0) // Capture/Compare 3 output enable
-
[7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
-
[6]CC2NE (def=0x0) // Capture/Compare 2 complementary output enable
-
[5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
-
[4]CC2E (def=0x0) // Capture/Compare 2 output enable
-
[3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
-
[2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
-
[1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
-
[0]CC1E (def=0x0) // Capture/Compare 1 output enable
0x40013424CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40013428PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4001342CATRLR// auto-reload register
-
[0:15]ATRLR (def=0xFFFF) // Auto-reload value
0x40013430RPTCR// repetition counter register
-
[0:7]RPTCR (def=0x0) // Repetition counter value
0x40013434CH1CVR// capture/compare register 1
-
[0:15]CCR1 (def=0x0) // Capture/Compare 1 value
0x40013438CH2CVR// capture/compare register 2
-
[0:15]CCR2 (def=0x0) // Capture/Compare 2 value
0x4001343CCH3CVR// capture/compare register 3
-
[0:15]CCR3 (def=0x0) // Capture/Compare value
0x40013440CH4CVR// capture/compare register 4
-
[0:15]CCR4 (def=0x0) // Capture/Compare value
0x40013444BDTR// break and dead-time register
-
[15]MOE (def=0x0) // Main output enable
-
[14]AOE (def=0x0) // Automatic output enable
-
[13]BKP (def=0x0) // Break polarity
-
[12]BKE (def=0x0) // Break enable
-
[11]OSSR (def=0x0) // Off-state selection for Run mode
-
[10]OSSI (def=0x0) // Off-state selection for Idle mode
-
[8:9]LOCK (def=0x0) // Lock configuration
-
[0:7]DTG (def=0x0) // Dead-time generator setup
0x40013448DMACFGR// DMA control register
-
[8:12]DBL (def=0x0) // DMA burst length
-
[0:4]DBA (def=0x0) // DMA base address
0x4001344CDMAADR// DMA address for full transfer
-
[0:15]DMAADR (def=0x0) // DMA register for burst accesses
- [59] TIM8_BRK // TIM8 Break interrupt
- [60] TIM8_UP_ // TIM8 Update interrupt
- [61] TIM8_TRG_COM // TIM8 Trigger and Commutation interrupts
- [62] TIM8_CC // TIM8 Capture Compare interrupt
0x40014C00TIM9//
0x40014C00CTLR1// control register 1
-
[8:9]CKD (def=0x0) // Clock division
-
[7]ARPE (def=0x0) // Auto-reload preload enable
-
[5:6]CMS (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]OPM (def=0x0) // One-pulse mode
-
[2]URS (def=0x0) // Update request source
-
[1]UDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40014C04CTLR2// control register 2
-
[14]OIS4 (def=0x0) // Output Idle state 4
-
[13]OIS3N (def=0x0) // Output Idle state 3
-
[12]OIS3 (def=0x0) // Output Idle state 3
-
[11]OIS2N (def=0x0) // Output Idle state 2
-
[10]OIS2 (def=0x0) // Output Idle state 2
-
[9]OIS1N (def=0x0) // Output Idle state 1
-
[8]OIS1 (def=0x0) // Output Idle state 1
-
[7]TI1S (def=0x0) // TI1 selection
-
[4:6]MMS (def=0x0) // Master mode selection
-
[3]CCDS (def=0x0) // Capture/compare DMA selection
-
[2]CCUS (def=0x0) // Capture/compare control update selection
-
[0]CCPC (def=0x0) // Capture/compare preloaded control
0x40014C08SMCFGR// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]ECE (def=0x0) // External clock enable
-
[12:13]ETPS (def=0x0) // External trigger prescaler
-
[8:11]ETF (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
-
[4:6]TS (def=0x0) // Trigger selection
-
[0:2]SMS (def=0x0) // Slave mode selection
0x40014C0CDMAINTENR// DMA/Interrupt enable register
-
[14]TDE (def=0x0) // Trigger DMA request enable
-
[13]COMDE (def=0x0) // COM DMA request enable
-
[12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
-
[11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
-
[10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
-
[9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UDE (def=0x0) // Update DMA request enable
-
[7]BIE (def=0x0) // Break interrupt enable
-
[6]TIE (def=0x0) // Trigger interrupt enable
-
[5]COMIE (def=0x0) // COM interrupt enable
-
[4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
-
[3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[0]UIE (def=0x0) // Update interrupt enable
0x40014C10INTFR// status register
-
[12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
-
[11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
-
[9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
-
[7]BIF (def=0x0) // Break interrupt flag
-
[6]TIF (def=0x0) // Trigger interrupt flag
-
[5]COMIF (def=0x0) // COM interrupt flag
-
[4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
-
[3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
-
[0]UIF (def=0x0) // Update interrupt flag
0x40014C14SWEVGR// event generation register
-
[7]BG (def=0x0) // Break generation
-
[6]TG (def=0x0) // Trigger generation
-
[5]COMG (def=0x0) // Capture/Compare control update generation
-
[4]CC4G (def=0x0) // Capture/compare 4 generation
-
[3]CC3G (def=0x0) // Capture/compare 3 generation
-
[2]CC2G (def=0x0) // Capture/compare 2 generation
-
[1]CC1G (def=0x0) // Capture/compare 1 generation
-
[0]UG (def=0x0) // Update generation
0x40014C18CHCTLR1_Output// capture/compare mode register (output mode)
-
[15]OC2CE (def=0x0) // Output Compare 2 clear enable
-
[12:14]OC2M (def=0x0) // Output Compare 2 mode
-
[11]OC2PE (def=0x0) // Output Compare 2 preload enable
-
[10]OC2FE (def=0x0) // Output Compare 2 fast enable
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[7]OC1CE (def=0x0) // Output Compare 1 clear enable
-
[4:6]OC1M (def=0x0) // Output Compare 1 mode
-
[3]OC1PE (def=0x0) // Output Compare 1 preload enable
-
[2]OC1FE (def=0x0) // Output Compare 1 fast enable
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40014C18CHCTLR1_Input// capture/compare mode register 1 (input mode)
-
[12:15]IC2F (def=0x0) // Input capture 2 filter
-
[10:11]IC2PCS (def=0x0) // Input capture 2 prescaler
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[4:7]IC1F (def=0x0) // Input capture 1 filter
-
[2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40014C1CCHCTLR2_Output// capture/compare mode register (output mode)
-
[15]OC4CE (def=0x0) // Output compare 4 clear enable
-
[12:14]OC4M (def=0x0) // Output compare 4 mode
-
[11]OC4PE (def=0x0) // Output compare 4 preload enable
-
[10]OC4FE (def=0x0) // Output compare 4 fast enable
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[7]OC3CE (def=0x0) // Output compare 3 clear enable
-
[4:6]OC3M (def=0x0) // Output compare 3 mode
-
[3]OC3PE (def=0x0) // Output compare 3 preload enable
-
[2]OC3FE (def=0x0) // Output compare 3 fast enable
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x40014C1CCHCTLR2_Input// capture/compare mode register 2 (input mode)
-
[12:15]IC4F (def=0x0) // Input capture 4 filter
-
[10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[4:7]IC3F (def=0x0) // Input capture 3 filter
-
[2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
-
[0:1]CC3S (def=0x0) // Capture/compare 3 selection
0x40014C20CCER// capture/compare enable register
-
[13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CC4E (def=0x0) // Capture/Compare 4 output enable
-
[11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
-
[10]CC3NE (def=0x0) // Capture/Compare 3 complementary output enable
-
[9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
-
[8]CC3E (def=0x0) // Capture/Compare 3 output enable
-
[7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
-
[6]CC2NE (def=0x0) // Capture/Compare 2 complementary output enable
-
[5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
-
[4]CC2E (def=0x0) // Capture/Compare 2 output enable
-
[3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
-
[2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
-
[1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
-
[0]CC1E (def=0x0) // Capture/Compare 1 output enable
0x40014C24CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40014C28PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x40014C2CATRLR// auto-reload register
-
[0:15]ATRLR (def=0xFFFF) // Auto-reload value
0x40014C30RPTCR// repetition counter register
-
[0:7]RPTCR (def=0x0) // Repetition counter value
0x40014C34CH1CVR// capture/compare register 1
-
[0:15]CCR1 (def=0x0) // Capture/Compare 1 value
0x40014C38CH2CVR// capture/compare register 2
-
[0:15]CCR2 (def=0x0) // Capture/Compare 2 value
0x40014C3CCH3CVR// capture/compare register 3
-
[0:15]CCR3 (def=0x0) // Capture/Compare value
0x40014C40CH4CVR// capture/compare register 4
-
[0:15]CCR4 (def=0x0) // Capture/Compare value
0x40014C44BDTR// break and dead-time register
-
[15]MOE (def=0x0) // Main output enable
-
[14]AOE (def=0x0) // Automatic output enable
-
[13]BKP (def=0x0) // Break polarity
-
[12]BKE (def=0x0) // Break enable
-
[11]OSSR (def=0x0) // Off-state selection for Run mode
-
[10]OSSI (def=0x0) // Off-state selection for Idle mode
-
[8:9]LOCK (def=0x0) // Lock configuration
-
[0:7]DTG (def=0x0) // Dead-time generator setup
0x40014C48DMACFGR// DMA control register
-
[8:12]DBL (def=0x0) // DMA burst length
-
[0:4]DBA (def=0x0) // DMA base address
0x40014C4CDMAADR// DMA address for full transfer
-
[0:15]DMAADR (def=0x0) // DMA register for burst accesses
- [90] TIM9_BRK // TIM9 Break interrupt
- [91] TIM9_UP_ // TIM9 Update interrupt
- [92] TIM9_TRG_COM // TIM9 Trigger and Commutation interrupts
- [93] TIM9_CC // TIM9 Capture Compare interrupt
0x40015000TIM10//
0x40015000CTLR1// control register 1
-
[8:9]CKD (def=0x0) // Clock division
-
[7]ARPE (def=0x0) // Auto-reload preload enable
-
[5:6]CMS (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]OPM (def=0x0) // One-pulse mode
-
[2]URS (def=0x0) // Update request source
-
[1]UDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40015004CTLR2// control register 2
-
[14]OIS4 (def=0x0) // Output Idle state 4
-
[13]OIS3N (def=0x0) // Output Idle state 3
-
[12]OIS3 (def=0x0) // Output Idle state 3
-
[11]OIS2N (def=0x0) // Output Idle state 2
-
[10]OIS2 (def=0x0) // Output Idle state 2
-
[9]OIS1N (def=0x0) // Output Idle state 1
-
[8]OIS1 (def=0x0) // Output Idle state 1
-
[7]TI1S (def=0x0) // TI1 selection
-
[4:6]MMS (def=0x0) // Master mode selection
-
[3]CCDS (def=0x0) // Capture/compare DMA selection
-
[2]CCUS (def=0x0) // Capture/compare control update selection
-
[0]CCPC (def=0x0) // Capture/compare preloaded control
0x40015008SMCFGR// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]ECE (def=0x0) // External clock enable
-
[12:13]ETPS (def=0x0) // External trigger prescaler
-
[8:11]ETF (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
-
[4:6]TS (def=0x0) // Trigger selection
-
[0:2]SMS (def=0x0) // Slave mode selection
0x4001500CDMAINTENR// DMA/Interrupt enable register
-
[14]TDE (def=0x0) // Trigger DMA request enable
-
[13]COMDE (def=0x0) // COM DMA request enable
-
[12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
-
[11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
-
[10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
-
[9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UDE (def=0x0) // Update DMA request enable
-
[7]BIE (def=0x0) // Break interrupt enable
-
[6]TIE (def=0x0) // Trigger interrupt enable
-
[5]COMIE (def=0x0) // COM interrupt enable
-
[4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
-
[3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[0]UIE (def=0x0) // Update interrupt enable
0x40015010INTFR// status register
-
[12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
-
[11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
-
[9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
-
[7]BIF (def=0x0) // Break interrupt flag
-
[6]TIF (def=0x0) // Trigger interrupt flag
-
[5]COMIF (def=0x0) // COM interrupt flag
-
[4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
-
[3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
-
[0]UIF (def=0x0) // Update interrupt flag
0x40015014SWEVGR// event generation register
-
[7]BG (def=0x0) // Break generation
-
[6]TG (def=0x0) // Trigger generation
-
[5]COMG (def=0x0) // Capture/Compare control update generation
-
[4]CC4G (def=0x0) // Capture/compare 4 generation
-
[3]CC3G (def=0x0) // Capture/compare 3 generation
-
[2]CC2G (def=0x0) // Capture/compare 2 generation
-
[1]CC1G (def=0x0) // Capture/compare 1 generation
-
[0]UG (def=0x0) // Update generation
0x40015018CHCTLR1_Output// capture/compare mode register (output mode)
-
[15]OC2CE (def=0x0) // Output Compare 2 clear enable
-
[12:14]OC2M (def=0x0) // Output Compare 2 mode
-
[11]OC2PE (def=0x0) // Output Compare 2 preload enable
-
[10]OC2FE (def=0x0) // Output Compare 2 fast enable
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[7]OC1CE (def=0x0) // Output Compare 1 clear enable
-
[4:6]OC1M (def=0x0) // Output Compare 1 mode
-
[3]OC1PE (def=0x0) // Output Compare 1 preload enable
-
[2]OC1FE (def=0x0) // Output Compare 1 fast enable
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40015018CHCTLR1_Input// capture/compare mode register 1 (input mode)
-
[12:15]IC2F (def=0x0) // Input capture 2 filter
-
[10:11]IC2PCS (def=0x0) // Input capture 2 prescaler
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[4:7]IC1F (def=0x0) // Input capture 1 filter
-
[2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x4001501CCHCTLR2_Output// capture/compare mode register (output mode)
-
[15]OC4CE (def=0x0) // Output compare 4 clear enable
-
[12:14]OC4M (def=0x0) // Output compare 4 mode
-
[11]OC4PE (def=0x0) // Output compare 4 preload enable
-
[10]OC4FE (def=0x0) // Output compare 4 fast enable
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[7]OC3CE (def=0x0) // Output compare 3 clear enable
-
[4:6]OC3M (def=0x0) // Output compare 3 mode
-
[3]OC3PE (def=0x0) // Output compare 3 preload enable
-
[2]OC3FE (def=0x0) // Output compare 3 fast enable
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x4001501CCHCTLR2_Input// capture/compare mode register 2 (input mode)
-
[12:15]IC4F (def=0x0) // Input capture 4 filter
-
[10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[4:7]IC3F (def=0x0) // Input capture 3 filter
-
[2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
-
[0:1]CC3S (def=0x0) // Capture/compare 3 selection
0x40015020CCER// capture/compare enable register
-
[13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CC4E (def=0x0) // Capture/Compare 4 output enable
-
[11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
-
[10]CC3NE (def=0x0) // Capture/Compare 3 complementary output enable
-
[9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
-
[8]CC3E (def=0x0) // Capture/Compare 3 output enable
-
[7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
-
[6]CC2NE (def=0x0) // Capture/Compare 2 complementary output enable
-
[5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
-
[4]CC2E (def=0x0) // Capture/Compare 2 output enable
-
[3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
-
[2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
-
[1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
-
[0]CC1E (def=0x0) // Capture/Compare 1 output enable
0x40015024CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40015028PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4001502CATRLR// auto-reload register
-
[0:15]ATRLR (def=0xFFFF) // Auto-reload value
0x40015030RPTCR// repetition counter register
-
[0:7]RPTCR (def=0x0) // Repetition counter value
0x40015034CH1CVR// capture/compare register 1
-
[0:15]CCR1 (def=0x0) // Capture/Compare 1 value
0x40015038CH2CVR// capture/compare register 2
-
[0:15]CCR2 (def=0x0) // Capture/Compare 2 value
0x4001503CCH3CVR// capture/compare register 3
-
[0:15]CCR3 (def=0x0) // Capture/Compare value
0x40015040CH4CVR// capture/compare register 4
-
[0:15]CCR4 (def=0x0) // Capture/Compare value
0x40015044BDTR// break and dead-time register
-
[15]MOE (def=0x0) // Main output enable
-
[14]AOE (def=0x0) // Automatic output enable
-
[13]BKP (def=0x0) // Break polarity
-
[12]BKE (def=0x0) // Break enable
-
[11]OSSR (def=0x0) // Off-state selection for Run mode
-
[10]OSSI (def=0x0) // Off-state selection for Idle mode
-
[8:9]LOCK (def=0x0) // Lock configuration
-
[0:7]DTG (def=0x0) // Dead-time generator setup
0x40015048DMACFGR// DMA control register
-
[8:12]DBL (def=0x0) // DMA burst length
-
[0:4]DBA (def=0x0) // DMA base address
0x4001504CDMAADR// DMA address for full transfer
-
[0:15]DMAADR (def=0x0) // DMA register for burst accesses
- [94] TIM10_BRK // TIM10 Break interrupt
- [95] TIM10_UP_ // TIM10 Update interrupt
- [96] TIM10_TRG_COM // TIM10 Trigger and Commutation interrupts
- [97] TIM10_CC // TIM10 Capture Compare interrupt
0x40000000TIM2// General purpose timer
0x40000000CTLR1// control register 1
-
[8:9]CKD (def=0x0) // Clock division
-
[7]ARPE (def=0x0) // Auto-reload preload enable
-
[5:6]CMS (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]OPM (def=0x0) // One-pulse mode
-
[2]URS (def=0x0) // Update request source
-
[1]UDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000004CTLR2// control register 2
-
[7]TI1S (def=0x0) // TI1 selection
-
[4:6]MMS (def=0x0) // Master mode selection
-
[3]CCDS (def=0x0) // Capture/compare DMA selection
-
[2]CCUS (def=0x0) // Update selection
-
[0]CCPC (def=0x0) // Compare selection
0x40000008SMCFGR// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]ECE (def=0x0) // External clock enable
-
[12:13]ETPS (def=0x0) // External trigger prescaler
-
[8:11]ETF (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
-
[4:6]TS (def=0x0) // Trigger selection
-
[0:2]SMS (def=0x0) // Slave mode selection
0x4000000CDMAINTENR// DMA/Interrupt enable register
-
[14]TDE (def=0x0) // Trigger DMA request enable
-
[13]COMDE (def=0x0) // COM DMA request enable
-
[12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
-
[11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
-
[10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
-
[9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UDE (def=0x0) // Update DMA request enable
-
[6]TIE (def=0x0) // Trigger interrupt enable
-
[4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
-
[3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[0]UIE (def=0x0) // Update interrupt enable
0x40000010INTFR// status register
-
[12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
-
[11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
-
[9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
-
[6]TIF (def=0x0) // Trigger interrupt flag
-
[4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
-
[3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
-
[0]UIF (def=0x0) // Update interrupt flag
0x40000014SWEVGR// event generation register
-
[7]BG (def=0x0) // Brake generation
-
[6]TG (def=0x0) // Trigger generation
-
[5]COMG (def=0x0) // Capture/compare generation
-
[4]CC4G (def=0x0) // Capture/compare 4 generation
-
[3]CC3G (def=0x0) // Capture/compare 3 generation
-
[2]CC2G (def=0x0) // Capture/compare 2 generation
-
[1]CC1G (def=0x0) // Capture/compare 1 generation
-
[0]UG (def=0x0) // Update generation
0x40000018CHCTLR1_Output// capture/compare mode register 1 (output mode)
-
[15]OC2CE (def=0x0) // Output compare 2 clear enable
-
[12:14]OC2M (def=0x0) // Output compare 2 mode
-
[11]OC2PE (def=0x0) // Output compare 2 preload enable
-
[10]OC2FE (def=0x0) // Output compare 2 fast enable
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[7]OC1CE (def=0x0) // Output compare 1 clear enable
-
[4:6]OC1M (def=0x0) // Output compare 1 mode
-
[3]OC1PE (def=0x0) // Output compare 1 preload enable
-
[2]OC1FE (def=0x0) // Output compare 1 fast enable
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40000018CHCTLR1_Input// capture/compare mode register 1 (input mode)
-
[12:15]IC2F (def=0x0) // Input capture 2 filter
-
[10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
-
[8:9]CC2S (def=0x0) // Capture/compare 2 selection
-
[4:7]IC1F (def=0x0) // Input capture 1 filter
-
[2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x4000001CCHCTLR2_Output// capture/compare mode register 2 (output mode)
-
[15]OC4CE (def=0x0) // Output compare 4 clear enable
-
[12:14]OC4M (def=0x0) // Output compare 4 mode
-
[11]OC4PE (def=0x0) // Output compare 4 preload enable
-
[10]OC4FE (def=0x0) // Output compare 4 fast enable
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[7]OC3CE (def=0x0) // Output compare 3 clear enable
-
[4:6]OC3M (def=0x0) // Output compare 3 mode
-
[3]OC3PE (def=0x0) // Output compare 3 preload enable
-
[2]OC3FE (def=0x0) // Output compare 3 fast enable
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x4000001CCHCTLR2_Input// capture/compare mode register 2 (input mode)
-
[12:15]IC4F (def=0x0) // Input capture 4 filter
-
[10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[4:7]IC3F (def=0x0) // Input capture 3 filter
-
[2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x40000020CCER// capture/compare enable register
-
[13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CC4E (def=0x0) // Capture/Compare 4 output enable
-
[9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
-
[8]CC3E (def=0x0) // Capture/Compare 3 output enable
-
[5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
-
[4]CC2E (def=0x0) // Capture/Compare 2 output enable
-
[1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
-
[0]CC1E (def=0x0) // Capture/Compare 1 output enable
0x40000024CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40000028PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4000002CATRLR// auto-reload register
-
[0:15]ARR (def=0xFFFF) // Auto-reload value
0x40000034CH1CVR// capture/compare register 1
-
[0:15]CCR1 (def=0x0) // Capture/Compare 1 value
0x40000038CH2CVR// capture/compare register 2
-
[0:15]CCR2 (def=0x0) // Capture/Compare 2 value
0x4000003CCH3CVR// capture/compare register 3
-
[0:15]CCR3 (def=0x0) // Capture/Compare value
0x40000040CH4CVR// capture/compare register 4
-
[0:15]CCR4 (def=0x0) // Capture/Compare value
0x40000048DMACFGR// DMA control register
-
[8:12]DBL (def=0x0) // DMA burst length
-
[0:4]DBA (def=0x0) // DMA base address
0x4000004CDMAADR// DMA address for full transfer
-
[0:15]DMAADR (def=0x0) // DMA register for burst accesses
- [44] TIM2 // TIM2 global interrupt
0x40000400TIM3//
0x40000400CTLR1// control register 1
-
[8:9]CKD (def=0x0) // Clock division
-
[7]ARPE (def=0x0) // Auto-reload preload enable
-
[5:6]CMS (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]OPM (def=0x0) // One-pulse mode
-
[2]URS (def=0x0) // Update request source
-
[1]UDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000404CTLR2// control register 2
-
[7]TI1S (def=0x0) // TI1 selection
-
[4:6]MMS (def=0x0) // Master mode selection
-
[3]CCDS (def=0x0) // Capture/compare DMA selection
-
[2]CCUS (def=0x0) // Update selection
-
[0]CCPC (def=0x0) // Compare selection
0x40000408SMCFGR// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]ECE (def=0x0) // External clock enable
-
[12:13]ETPS (def=0x0) // External trigger prescaler
-
[8:11]ETF (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
-
[4:6]TS (def=0x0) // Trigger selection
-
[0:2]SMS (def=0x0) // Slave mode selection
0x4000040CDMAINTENR// DMA/Interrupt enable register
-
[14]TDE (def=0x0) // Trigger DMA request enable
-
[13]COMDE (def=0x0) // COM DMA request enable
-
[12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
-
[11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
-
[10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
-
[9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UDE (def=0x0) // Update DMA request enable
-
[6]TIE (def=0x0) // Trigger interrupt enable
-
[4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
-
[3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[0]UIE (def=0x0) // Update interrupt enable
0x40000410INTFR// status register
-
[12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
-
[11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
-
[9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
-
[6]TIF (def=0x0) // Trigger interrupt flag
-
[4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
-
[3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
-
[0]UIF (def=0x0) // Update interrupt flag
0x40000414SWEVGR// event generation register
-
[7]BG (def=0x0) // Brake generation
-
[6]TG (def=0x0) // Trigger generation
-
[5]COMG (def=0x0) // Capture/compare generation
-
[4]CC4G (def=0x0) // Capture/compare 4 generation
-
[3]CC3G (def=0x0) // Capture/compare 3 generation
-
[2]CC2G (def=0x0) // Capture/compare 2 generation
-
[1]CC1G (def=0x0) // Capture/compare 1 generation
-
[0]UG (def=0x0) // Update generation
0x40000418CHCTLR1_Output// capture/compare mode register 1 (output mode)
-
[15]OC2CE (def=0x0) // Output compare 2 clear enable
-
[12:14]OC2M (def=0x0) // Output compare 2 mode
-
[11]OC2PE (def=0x0) // Output compare 2 preload enable
-
[10]OC2FE (def=0x0) // Output compare 2 fast enable
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[7]OC1CE (def=0x0) // Output compare 1 clear enable
-
[4:6]OC1M (def=0x0) // Output compare 1 mode
-
[3]OC1PE (def=0x0) // Output compare 1 preload enable
-
[2]OC1FE (def=0x0) // Output compare 1 fast enable
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40000418CHCTLR1_Input// capture/compare mode register 1 (input mode)
-
[12:15]IC2F (def=0x0) // Input capture 2 filter
-
[10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
-
[8:9]CC2S (def=0x0) // Capture/compare 2 selection
-
[4:7]IC1F (def=0x0) // Input capture 1 filter
-
[2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x4000041CCHCTLR2_Output// capture/compare mode register 2 (output mode)
-
[15]OC4CE (def=0x0) // Output compare 4 clear enable
-
[12:14]OC4M (def=0x0) // Output compare 4 mode
-
[11]OC4PE (def=0x0) // Output compare 4 preload enable
-
[10]OC4FE (def=0x0) // Output compare 4 fast enable
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[7]OC3CE (def=0x0) // Output compare 3 clear enable
-
[4:6]OC3M (def=0x0) // Output compare 3 mode
-
[3]OC3PE (def=0x0) // Output compare 3 preload enable
-
[2]OC3FE (def=0x0) // Output compare 3 fast enable
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x4000041CCHCTLR2_Input// capture/compare mode register 2 (input mode)
-
[12:15]IC4F (def=0x0) // Input capture 4 filter
-
[10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[4:7]IC3F (def=0x0) // Input capture 3 filter
-
[2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x40000420CCER// capture/compare enable register
-
[13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CC4E (def=0x0) // Capture/Compare 4 output enable
-
[9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
-
[8]CC3E (def=0x0) // Capture/Compare 3 output enable
-
[5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
-
[4]CC2E (def=0x0) // Capture/Compare 2 output enable
-
[1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
-
[0]CC1E (def=0x0) // Capture/Compare 1 output enable
0x40000424CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40000428PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4000042CATRLR// auto-reload register
-
[0:15]ARR (def=0xFFFF) // Auto-reload value
0x40000434CH1CVR// capture/compare register 1
-
[0:15]CCR1 (def=0x0) // Capture/Compare 1 value
0x40000438CH2CVR// capture/compare register 2
-
[0:15]CCR2 (def=0x0) // Capture/Compare 2 value
0x4000043CCH3CVR// capture/compare register 3
-
[0:15]CCR3 (def=0x0) // Capture/Compare value
0x40000440CH4CVR// capture/compare register 4
-
[0:15]CCR4 (def=0x0) // Capture/Compare value
0x40000448DMACFGR// DMA control register
-
[8:12]DBL (def=0x0) // DMA burst length
-
[0:4]DBA (def=0x0) // DMA base address
0x4000044CDMAADR// DMA address for full transfer
-
[0:15]DMAADR (def=0x0) // DMA register for burst accesses
- [45] TIM3 // TIM3 global interrupt
0x40000800TIM4//
0x40000800CTLR1// control register 1
-
[8:9]CKD (def=0x0) // Clock division
-
[7]ARPE (def=0x0) // Auto-reload preload enable
-
[5:6]CMS (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]OPM (def=0x0) // One-pulse mode
-
[2]URS (def=0x0) // Update request source
-
[1]UDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000804CTLR2// control register 2
-
[7]TI1S (def=0x0) // TI1 selection
-
[4:6]MMS (def=0x0) // Master mode selection
-
[3]CCDS (def=0x0) // Capture/compare DMA selection
-
[2]CCUS (def=0x0) // Update selection
-
[0]CCPC (def=0x0) // Compare selection
0x40000808SMCFGR// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]ECE (def=0x0) // External clock enable
-
[12:13]ETPS (def=0x0) // External trigger prescaler
-
[8:11]ETF (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
-
[4:6]TS (def=0x0) // Trigger selection
-
[0:2]SMS (def=0x0) // Slave mode selection
0x4000080CDMAINTENR// DMA/Interrupt enable register
-
[14]TDE (def=0x0) // Trigger DMA request enable
-
[13]COMDE (def=0x0) // COM DMA request enable
-
[12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
-
[11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
-
[10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
-
[9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UDE (def=0x0) // Update DMA request enable
-
[6]TIE (def=0x0) // Trigger interrupt enable
-
[4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
-
[3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[0]UIE (def=0x0) // Update interrupt enable
0x40000810INTFR// status register
-
[12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
-
[11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
-
[9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
-
[6]TIF (def=0x0) // Trigger interrupt flag
-
[4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
-
[3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
-
[0]UIF (def=0x0) // Update interrupt flag
0x40000814SWEVGR// event generation register
-
[7]BG (def=0x0) // Brake generation
-
[6]TG (def=0x0) // Trigger generation
-
[5]COMG (def=0x0) // Capture/compare generation
-
[4]CC4G (def=0x0) // Capture/compare 4 generation
-
[3]CC3G (def=0x0) // Capture/compare 3 generation
-
[2]CC2G (def=0x0) // Capture/compare 2 generation
-
[1]CC1G (def=0x0) // Capture/compare 1 generation
-
[0]UG (def=0x0) // Update generation
0x40000818CHCTLR1_Output// capture/compare mode register 1 (output mode)
-
[15]OC2CE (def=0x0) // Output compare 2 clear enable
-
[12:14]OC2M (def=0x0) // Output compare 2 mode
-
[11]OC2PE (def=0x0) // Output compare 2 preload enable
-
[10]OC2FE (def=0x0) // Output compare 2 fast enable
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[7]OC1CE (def=0x0) // Output compare 1 clear enable
-
[4:6]OC1M (def=0x0) // Output compare 1 mode
-
[3]OC1PE (def=0x0) // Output compare 1 preload enable
-
[2]OC1FE (def=0x0) // Output compare 1 fast enable
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40000818CHCTLR1_Input// capture/compare mode register 1 (input mode)
-
[12:15]IC2F (def=0x0) // Input capture 2 filter
-
[10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
-
[8:9]CC2S (def=0x0) // Capture/compare 2 selection
-
[4:7]IC1F (def=0x0) // Input capture 1 filter
-
[2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x4000081CCHCTLR2_Output// capture/compare mode register 2 (output mode)
-
[15]OC4CE (def=0x0) // Output compare 4 clear enable
-
[12:14]OC4M (def=0x0) // Output compare 4 mode
-
[11]OC4PE (def=0x0) // Output compare 4 preload enable
-
[10]OC4FE (def=0x0) // Output compare 4 fast enable
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[7]OC3CE (def=0x0) // Output compare 3 clear enable
-
[4:6]OC3M (def=0x0) // Output compare 3 mode
-
[3]OC3PE (def=0x0) // Output compare 3 preload enable
-
[2]OC3FE (def=0x0) // Output compare 3 fast enable
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x4000081CCHCTLR2_Input// capture/compare mode register 2 (input mode)
-
[12:15]IC4F (def=0x0) // Input capture 4 filter
-
[10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[4:7]IC3F (def=0x0) // Input capture 3 filter
-
[2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x40000820CCER// capture/compare enable register
-
[13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CC4E (def=0x0) // Capture/Compare 4 output enable
-
[9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
-
[8]CC3E (def=0x0) // Capture/Compare 3 output enable
-
[5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
-
[4]CC2E (def=0x0) // Capture/Compare 2 output enable
-
[1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
-
[0]CC1E (def=0x0) // Capture/Compare 1 output enable
0x40000824CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40000828PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x4000082CATRLR// auto-reload register
-
[0:15]ARR (def=0xFFFF) // Auto-reload value
0x40000834CH1CVR// capture/compare register 1
-
[0:15]CCR1 (def=0x0) // Capture/Compare 1 value
0x40000838CH2CVR// capture/compare register 2
-
[0:15]CCR2 (def=0x0) // Capture/Compare 2 value
0x4000083CCH3CVR// capture/compare register 3
-
[0:15]CCR3 (def=0x0) // Capture/Compare value
0x40000840CH4CVR// capture/compare register 4
-
[0:15]CCR4 (def=0x0) // Capture/Compare value
0x40000848DMACFGR// DMA control register
-
[8:12]DBL (def=0x0) // DMA burst length
-
[0:4]DBA (def=0x0) // DMA base address
0x4000084CDMAADR// DMA address for full transfer
-
[0:15]DMAADR (def=0x0) // DMA register for burst accesses
- [46] TIM4 // TIM4 global interrupt
0x40000C00TIM5//
0x40000C00CTLR1// control register 1
-
[8:9]CKD (def=0x0) // Clock division
-
[7]ARPE (def=0x0) // Auto-reload preload enable
-
[5:6]CMS (def=0x0) // Center-aligned mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]OPM (def=0x0) // One-pulse mode
-
[2]URS (def=0x0) // Update request source
-
[1]UDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000C04CTLR2// control register 2
-
[7]TI1S (def=0x0) // TI1 selection
-
[4:6]MMS (def=0x0) // Master mode selection
-
[3]CCDS (def=0x0) // Capture/compare DMA selection
-
[2]CCUS (def=0x0) // Update selection
-
[0]CCPC (def=0x0) // Compare selection
0x40000C08SMCFGR// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]ECE (def=0x0) // External clock enable
-
[12:13]ETPS (def=0x0) // External trigger prescaler
-
[8:11]ETF (def=0x0) // External trigger filter
-
[7]MSM (def=0x0) // Master/Slave mode
-
[4:6]TS (def=0x0) // Trigger selection
-
[0:2]SMS (def=0x0) // Slave mode selection
0x40000C0CDMAINTENR// DMA/Interrupt enable register
-
[14]TDE (def=0x0) // Trigger DMA request enable
-
[13]COMDE (def=0x0) // COM DMA request enable
-
[12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
-
[11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
-
[10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
-
[9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
-
[8]UDE (def=0x0) // Update DMA request enable
-
[6]TIE (def=0x0) // Trigger interrupt enable
-
[4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
-
[3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
-
[2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
-
[1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
-
[0]UIE (def=0x0) // Update interrupt enable
0x40000C10INTFR// status register
-
[12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
-
[11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
-
[10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
-
[9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
-
[6]TIF (def=0x0) // Trigger interrupt flag
-
[4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
-
[3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
-
[2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
-
[1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
-
[0]UIF (def=0x0) // Update interrupt flag
0x40000C14SWEVGR// event generation register
-
[7]BG (def=0x0) // Brake generation
-
[6]TG (def=0x0) // Trigger generation
-
[5]COMG (def=0x0) // Capture/compare generation
-
[4]CC4G (def=0x0) // Capture/compare 4 generation
-
[3]CC3G (def=0x0) // Capture/compare 3 generation
-
[2]CC2G (def=0x0) // Capture/compare 2 generation
-
[1]CC1G (def=0x0) // Capture/compare 1 generation
-
[0]UG (def=0x0) // Update generation
0x40000C18CHCTLR1_Output// capture/compare mode register 1 (output mode)
-
[15]OC2CE (def=0x0) // Output compare 2 clear enable
-
[12:14]OC2M (def=0x0) // Output compare 2 mode
-
[11]OC2PE (def=0x0) // Output compare 2 preload enable
-
[10]OC2FE (def=0x0) // Output compare 2 fast enable
-
[8:9]CC2S (def=0x0) // Capture/Compare 2 selection
-
[7]OC1CE (def=0x0) // Output compare 1 clear enable
-
[4:6]OC1M (def=0x0) // Output compare 1 mode
-
[3]OC1PE (def=0x0) // Output compare 1 preload enable
-
[2]OC1FE (def=0x0) // Output compare 1 fast enable
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40000C18CHCTLR1_Input// capture/compare mode register 1 (input mode)
-
[12:15]IC2F (def=0x0) // Input capture 2 filter
-
[10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
-
[8:9]CC2S (def=0x0) // Capture/compare 2 selection
-
[4:7]IC1F (def=0x0) // Input capture 1 filter
-
[2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
-
[0:1]CC1S (def=0x0) // Capture/Compare 1 selection
0x40000C1CCHCTLR2_Output// capture/compare mode register 2 (output mode)
-
[15]OC4CE (def=0x0) // Output compare 4 clear enable
-
[12:14]OC4M (def=0x0) // Output compare 4 mode
-
[11]OC4PE (def=0x0) // Output compare 4 preload enable
-
[10]OC4FE (def=0x0) // Output compare 4 fast enable
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[7]OC3CE (def=0x0) // Output compare 3 clear enable
-
[4:6]OC3M (def=0x0) // Output compare 3 mode
-
[3]OC3PE (def=0x0) // Output compare 3 preload enable
-
[2]OC3FE (def=0x0) // Output compare 3 fast enable
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x40000C1CCHCTLR2_Input// capture/compare mode register 2 (input mode)
-
[12:15]IC4F (def=0x0) // Input capture 4 filter
-
[10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
-
[8:9]CC4S (def=0x0) // Capture/Compare 4 selection
-
[4:7]IC3F (def=0x0) // Input capture 3 filter
-
[2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
-
[0:1]CC3S (def=0x0) // Capture/Compare 3 selection
0x40000C20CCER// capture/compare enable register
-
[13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
-
[12]CC4E (def=0x0) // Capture/Compare 4 output enable
-
[9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
-
[8]CC3E (def=0x0) // Capture/Compare 3 output enable
-
[5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
-
[4]CC2E (def=0x0) // Capture/Compare 2 output enable
-
[1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
-
[0]CC1E (def=0x0) // Capture/Compare 1 output enable
0x40000C24CNT// counter
-
[0:15]CNT (def=0x0) // counter value
0x40000C28PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value
0x40000C2CATRLR// auto-reload register
-
[0:15]ARR (def=0xFFFF) // Auto-reload value
0x40000C34CH1CVR// capture/compare register 1
-
[0:15]CCR1 (def=0x0) // Capture/Compare 1 value
0x40000C38CH2CVR// capture/compare register 2
-
[0:15]CCR2 (def=0x0) // Capture/Compare 2 value
0x40000C3CCH3CVR// capture/compare register 3
-
[0:15]CCR3 (def=0x0) // Capture/Compare value
0x40000C40CH4CVR// capture/compare register 4
-
[0:15]CCR4 (def=0x0) // Capture/Compare value
0x40000C48DMACFGR// DMA control register
-
[8:12]DBL (def=0x0) // DMA burst length
-
[0:4]DBA (def=0x0) // DMA base address
0x40000C4CDMAADR// DMA address for full transfer
-
[0:15]DMAADR (def=0x0) // DMA register for burst accesses
- [66] TIM5 // TIM5 global interrupt
0x40005400I2C1// Inter integrated circuit
0x40005400CTLR1// Control register 1
-
[15]SWRST (def=0x0) // Software reset
-
[13]ALERT (def=0x0) // SMBus alert
-
[12]PEC (def=0x0) // Packet error checking
-
[11]POS (def=0x0) // Acknowledge/PEC Position (for data reception)
-
[10]ACK (def=0x0) // Acknowledge enable
-
[9]STOP (def=0x0) // Stop generation
-
[8]START (def=0x0) // Start generation
-
[7]NOSTRETCH (def=0x0) // Clock stretching disable (Slave mode)
-
[6]ENGC (def=0x0) // General call enable
-
[5]ENPEC (def=0x0) // PEC enable
-
[4]ENARP (def=0x0) // ARP enable
-
[3]SMBTYPE (def=0x0) // SMBus type
-
[1]SMBUS (def=0x0) // SMBus mode
-
[0]PE (def=0x0) // Peripheral enable
0x40005404CTLR2// Control register 2
-
[12]LAST (def=0x0) // DMA last transfer
-
[11]DMAEN (def=0x0) // DMA requests enable
-
[10]ITBUFEN (def=0x0) // Buffer interrupt enable
-
[9]ITEVTEN (def=0x0) // Event interrupt enable
-
[8]ITERREN (def=0x0) // Error interrupt enable
-
[0:5]FREQ (def=0x0) // Peripheral clock frequency
0x40005408OADDR1// Own address register 1
-
[15]ADDMODE (def=0x0) // Addressing mode (slave mode)
-
[14]MUST1 (def=0x0) // Must be 1
-
[8:9]ADD9_8 (def=0x0) // Interface address
-
[1:7]ADD7_1 (def=0x0) // Interface address
-
[0]ADD0 (def=0x0) // Interface address
0x4000540COADDR2// Own address register 2
-
[1:7]ADD2 (def=0x0) // Interface address
-
[0]ENDUAL (def=0x0) // Dual addressing mode enable
0x40005410DATAR// Data register
-
[0:7]DATAR (def=0x0) // 8-bit data register
0x40005414STAR1// Status register 1
-
[15]SMBALERT (def=0x0) // SMBus alert
-
[14]TIMEOUT (def=0x0) // Timeout or Tlow error
-
[12]PECERR (def=0x0) // PEC Error in reception
-
[11]OVR (def=0x0) // Overrun/Underrun
-
[10]AF (def=0x0) // Acknowledge failure
-
[9]ARLO (def=0x0) // Arbitration lost (master mode)
-
[8]BERR (def=0x0) // Bus error
-
[7]TxE (def=0x0) // Data register empty (transmitters)
-
[6]RxNE (def=0x0) // Data register not empty (receivers)
-
[4]STOPF (def=0x0) // Stop detection (slave mode)
-
[3]ADD10 (def=0x0) // 10-bit header sent (Master mode)
-
[2]BTF (def=0x0) // Byte transfer finished
-
[1]ADDR (def=0x0) // Address sent (master mode)/matched (slave mode)
-
[0]SB (def=0x0) // Start bit (Master mode)
0x40005418STAR2// Status register 2
-
[8:15]PEC (def=0x0) // acket error checking register
-
[7]DUALF (def=0x0) // Dual flag (Slave mode)
-
[6]SMBHOST (def=0x0) // SMBus host header (Slave mode)
-
[5]SMBDEFAULT (def=0x0) // SMBus device default address (Slave mode)
-
[4]GENCALL (def=0x0) // General call address (Slave mode)
-
[2]TRA (def=0x0) // Transmitter/receiver
-
[1]BUSY (def=0x0) // Bus busy
-
[0]MSL (def=0x0) // Master/slave
0x4000541CCKCFGR// Clock control register
-
[15]F_S (def=0x0) // I2C master mode selection
-
[14]DUTY (def=0x0) // Fast mode duty cycle
-
[0:11]CCR (def=0x0) // Clock control register in Fast/Standard mode (Master mode)
0x40005420RTR// Raise time register
-
[0:5]TRISE (def=0x2) // Maximum rise time in Fast/Standard mode (Master mode)
- [47] I2C1_EV // I2C1 event interrupt
- [48] I2C1_ER // I2C1 error interrupt
0x40005800I2C2//
0x40005800CTLR1// Control register 1
-
[15]SWRST (def=0x0) // Software reset
-
[13]ALERT (def=0x0) // SMBus alert
-
[12]PEC (def=0x0) // Packet error checking
-
[11]POS (def=0x0) // Acknowledge/PEC Position (for data reception)
-
[10]ACK (def=0x0) // Acknowledge enable
-
[9]STOP (def=0x0) // Stop generation
-
[8]START (def=0x0) // Start generation
-
[7]NOSTRETCH (def=0x0) // Clock stretching disable (Slave mode)
-
[6]ENGC (def=0x0) // General call enable
-
[5]ENPEC (def=0x0) // PEC enable
-
[4]ENARP (def=0x0) // ARP enable
-
[3]SMBTYPE (def=0x0) // SMBus type
-
[1]SMBUS (def=0x0) // SMBus mode
-
[0]PE (def=0x0) // Peripheral enable
0x40005804CTLR2// Control register 2
-
[12]LAST (def=0x0) // DMA last transfer
-
[11]DMAEN (def=0x0) // DMA requests enable
-
[10]ITBUFEN (def=0x0) // Buffer interrupt enable
-
[9]ITEVTEN (def=0x0) // Event interrupt enable
-
[8]ITERREN (def=0x0) // Error interrupt enable
-
[0:5]FREQ (def=0x0) // Peripheral clock frequency
0x40005808OADDR1// Own address register 1
-
[15]ADDMODE (def=0x0) // Addressing mode (slave mode)
-
[14]MUST1 (def=0x0) // Must be 1
-
[8:9]ADD9_8 (def=0x0) // Interface address
-
[1:7]ADD7_1 (def=0x0) // Interface address
-
[0]ADD0 (def=0x0) // Interface address
0x4000580COADDR2// Own address register 2
-
[1:7]ADD2 (def=0x0) // Interface address
-
[0]ENDUAL (def=0x0) // Dual addressing mode enable
0x40005810DATAR// Data register
-
[0:7]DATAR (def=0x0) // 8-bit data register
0x40005814STAR1// Status register 1
-
[15]SMBALERT (def=0x0) // SMBus alert
-
[14]TIMEOUT (def=0x0) // Timeout or Tlow error
-
[12]PECERR (def=0x0) // PEC Error in reception
-
[11]OVR (def=0x0) // Overrun/Underrun
-
[10]AF (def=0x0) // Acknowledge failure
-
[9]ARLO (def=0x0) // Arbitration lost (master mode)
-
[8]BERR (def=0x0) // Bus error
-
[7]TxE (def=0x0) // Data register empty (transmitters)
-
[6]RxNE (def=0x0) // Data register not empty (receivers)
-
[4]STOPF (def=0x0) // Stop detection (slave mode)
-
[3]ADD10 (def=0x0) // 10-bit header sent (Master mode)
-
[2]BTF (def=0x0) // Byte transfer finished
-
[1]ADDR (def=0x0) // Address sent (master mode)/matched (slave mode)
-
[0]SB (def=0x0) // Start bit (Master mode)
0x40005818STAR2// Status register 2
-
[8:15]PEC (def=0x0) // acket error checking register
-
[7]DUALF (def=0x0) // Dual flag (Slave mode)
-
[6]SMBHOST (def=0x0) // SMBus host header (Slave mode)
-
[5]SMBDEFAULT (def=0x0) // SMBus device default address (Slave mode)
-
[4]GENCALL (def=0x0) // General call address (Slave mode)
-
[2]TRA (def=0x0) // Transmitter/receiver
-
[1]BUSY (def=0x0) // Bus busy
-
[0]MSL (def=0x0) // Master/slave
0x4000581CCKCFGR// Clock control register
-
[15]F_S (def=0x0) // I2C master mode selection
-
[14]DUTY (def=0x0) // Fast mode duty cycle
-
[0:11]CCR (def=0x0) // Clock control register in Fast/Standard mode (Master mode)
0x40005820RTR// Raise time register
-
[0:5]TRISE (def=0x2) // Maximum rise time in Fast/Standard mode (Master mode)
- [49] I2C2_EV // I2C2 event interrupt
- [50] I2C2_ER // I2C2 error interrupt
0x40013000SPI1// Serial peripheral interface
0x40013000CTLR1// control register 1
-
[15]BIDIMODE (def=0x0) // Bidirectional data mode enable
-
[14]BIDIOE (def=0x0) // Output enable in bidirectional mode
-
[13]CRCEN (def=0x0) // Hardware CRC calculation enable
-
[12]CRCNEXT (def=0x0) // CRC transfer next
-
[11]DFF (def=0x0) // Data frame format
-
[10]RXONLY (def=0x0) // Receive only
-
[9]SSM (def=0x0) // Software slave management
-
[8]SSI (def=0x0) // Internal slave select
-
[7]LSBFIRST (def=0x0) // Frame format
-
[6]SPE (def=0x0) // SPI enable
-
[3:5]BR (def=0x0) // Baud rate control
-
[2]MSTR (def=0x0) // Master selection
-
[1]CPOL (def=0x0) // Clock polarity
-
[0]CPHA (def=0x0) // Clock phase
0x40013004CTLR2// control register 2
-
[7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
-
[6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
-
[5]ERRIE (def=0x0) // Error interrupt enable
-
[2]SSOE (def=0x0) // SS output enable
-
[1]TXDMAEN (def=0x0) // Tx buffer DMA enable
-
[0]RXDMAEN (def=0x0) // Rx buffer DMA enable
0x40013008STATR// status register
-
[7]BSY (def=0x0) // Busy flag
-
[6]OVR (def=0x0) // Overrun flag
-
[5]MODF (def=0x0) // Mode fault
-
[4]CRCERR (def=0x0) // CRC error flag
-
[2]CHSID (def=0x0) // Channel side
-
[3]UDR (def=0x0) // Underrun flag
-
[1]TXE (def=0x1) // Transmit buffer empty
-
[0]RXNE (def=0x0) // Receive buffer not empty
0x4001300CDATAR// data register
-
[0:15]DR (def=0x0) // Data register
0x40013010CRCR// CRCR polynomial register
-
[0:15]CRCPOLY (def=0x7) // CRC polynomial register
0x40013014RCRCR// RX CRC register
-
[0:15]RXCRC (def=0x0) // Rx CRC register
0x40013018TCRCR// TX CRC register
-
[0:15]TXCRC (def=0x0) // Tx CRC register
0x4001301CSPI_I2S_CFGR// SPI_I2S configure register
-
[0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
-
[1:2]DATLEN (def=0x0) // DATLEN[1:0] bits (Data length to be transferred)
-
[3]CKPOL (def=0x0) // steady state clock polarity
-
[4:5]I2SSTD (def=0x0) // I2SSTD[1:0] bits (I2S standard selection)
-
[7]PCMSYNC (def=0x0) // PCM frame synchronization
-
[8:9]I2SCFG (def=0x0) // I2SCFG[1:0] bits (I2S configuration mode)
-
[10]I2SE (def=0x0) // I2S Enable
-
[11]I2SMOD (def=0x0) // I2S mode selection
0x40013024HSCR// high speed control register
-
[0]HSRXEN (def=0x0) // High speed mode read enable
- [51] SPI1 // SPI1 global interrupt
0x40003800SPI2// Serial peripheral interface
0x40003800CTLR1// control register 1
-
[15]BIDIMODE (def=0x0) // Bidirectional data mode enable
-
[14]BIDIOE (def=0x0) // Output enable in bidirectional mode
-
[13]CRCEN (def=0x0) // Hardware CRC calculation enable
-
[12]CRCNEXT (def=0x0) // CRC transfer next
-
[11]DFF (def=0x0) // Data frame format
-
[10]RXONLY (def=0x0) // Receive only
-
[9]SSM (def=0x0) // Software slave management
-
[8]SSI (def=0x0) // Internal slave select
-
[7]LSBFIRST (def=0x0) // Frame format
-
[6]SPE (def=0x0) // SPI enable
-
[3:5]BR (def=0x0) // Baud rate control
-
[2]MSTR (def=0x0) // Master selection
-
[1]CPOL (def=0x0) // Clock polarity
-
[0]CPHA (def=0x0) // Clock phase
0x40003804CTLR2// control register 2
-
[7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
-
[6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
-
[5]ERRIE (def=0x0) // Error interrupt enable
-
[2]SSOE (def=0x0) // SS output enable
-
[1]TXDMAEN (def=0x0) // Tx buffer DMA enable
-
[0]RXDMAEN (def=0x0) // Rx buffer DMA enable
0x40003808STATR// status register
-
[7]BSY (def=0x0) // Busy flag
-
[6]OVR (def=0x0) // Overrun flag
-
[5]MODF (def=0x0) // Mode fault
-
[4]CRCERR (def=0x0) // CRC error flag
-
[1]TXE (def=0x1) // Transmit buffer empty
-
[0]RXNE (def=0x0) // Receive buffer not empty
0x4000380CDATAR// data register
-
[0:15]DR (def=0x0) // Data register
0x40003810CRCR// CRCR polynomial register
-
[0:15]CRCPOLY (def=0x7) // CRC polynomial register
0x40003814RCRCR// RX CRC register
-
[0:15]RXCRC (def=0x0) // Rx CRC register
0x40003818TCRCR// TX CRC register
-
[0:15]TXCRC (def=0x0) // Tx CRC register
0x4000381CI2SCFGR// I2S configuration register
-
[11]I2SMOD (def=0x0) // I2S mode selection
-
[10]I2SE (def=0x0) // I2S Enable
-
[8:9]I2SCFG (def=0x0) // I2S configuration mode
-
[7]PCMSYNC (def=0x0) // PCM frame synchronization
-
[4:5]I2SSTD (def=0x0) // I2S standard selection
-
[3]CKPOL (def=0x0) // Steady state clock polarity
-
[1:2]DATLEN (def=0x0) // Data length to be transferred
-
[0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
0x40003820I2SPR// I2S prescaler register
-
[9]MCKOE (def=0x0) // Master clock output enable
-
[8]ODD (def=0x0) // Odd factor for the prescaler
-
[0:7]I2SDIV (def=0x8) // I2S Linear prescaler
0x40003824HSCR// high speed control register
-
[0]HSRXEN (def=0x0) // High speed mode read enable
- [52] SPI2 // SPI2 global interrupt
0x40003C00SPI3//
0x40003C00CTLR1// control register 1
-
[15]BIDIMODE (def=0x0) // Bidirectional data mode enable
-
[14]BIDIOE (def=0x0) // Output enable in bidirectional mode
-
[13]CRCEN (def=0x0) // Hardware CRC calculation enable
-
[12]CRCNEXT (def=0x0) // CRC transfer next
-
[11]DFF (def=0x0) // Data frame format
-
[10]RXONLY (def=0x0) // Receive only
-
[9]SSM (def=0x0) // Software slave management
-
[8]SSI (def=0x0) // Internal slave select
-
[7]LSBFIRST (def=0x0) // Frame format
-
[6]SPE (def=0x0) // SPI enable
-
[3:5]BR (def=0x0) // Baud rate control
-
[2]MSTR (def=0x0) // Master selection
-
[1]CPOL (def=0x0) // Clock polarity
-
[0]CPHA (def=0x0) // Clock phase
0x40003C04CTLR2// control register 2
-
[7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
-
[6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
-
[5]ERRIE (def=0x0) // Error interrupt enable
-
[2]SSOE (def=0x0) // SS output enable
-
[1]TXDMAEN (def=0x0) // Tx buffer DMA enable
-
[0]RXDMAEN (def=0x0) // Rx buffer DMA enable
0x40003C08STATR// status register
-
[7]BSY (def=0x0) // Busy flag
-
[6]OVR (def=0x0) // Overrun flag
-
[5]MODF (def=0x0) // Mode fault
-
[4]CRCERR (def=0x0) // CRC error flag
-
[1]TXE (def=0x1) // Transmit buffer empty
-
[0]RXNE (def=0x0) // Receive buffer not empty
0x40003C0CDATAR// data register
-
[0:15]DR (def=0x0) // Data register
0x40003C10CRCR// CRCR polynomial register
-
[0:15]CRCPOLY (def=0x7) // CRC polynomial register
0x40003C14RCRCR// RX CRC register
-
[0:15]RXCRC (def=0x0) // Rx CRC register
0x40003C18TCRCR// TX CRC register
-
[0:15]TXCRC (def=0x0) // Tx CRC register
0x40003C1CI2SCFGR// I2S configuration register
-
[11]I2SMOD (def=0x0) // I2S mode selection
-
[10]I2SE (def=0x0) // I2S Enable
-
[8:9]I2SCFG (def=0x0) // I2S configuration mode
-
[7]PCMSYNC (def=0x0) // PCM frame synchronization
-
[4:5]I2SSTD (def=0x0) // I2S standard selection
-
[3]CKPOL (def=0x0) // Steady state clock polarity
-
[1:2]DATLEN (def=0x0) // Data length to be transferred
-
[0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
0x40003C20I2SPR// I2S prescaler register
-
[9]MCKOE (def=0x0) // Master clock output enable
-
[8]ODD (def=0x0) // Odd factor for the prescaler
-
[0:7]I2SDIV (def=0x8) // I2S Linear prescaler
0x40003C24HSCR// high speed control register
-
[0]HSRXEN (def=0x0) // High speed mode read enable
- [67] SPI3 // SPI3 global interrupt
0x40013800USART1// Universal synchronous asynchronous receiver transmitter
0x40013800STATR// Status register
-
[9]CTS (def=0x0) // CTS flag
-
[8]LBD (def=0x0) // LIN break detection flag
-
[7]TXE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RXNE (def=0x0) // Read data register not empty
-
[4]IDLE (def=0x0) // IDLE line detected
-
[3]ORE (def=0x0) // Overrun error
-
[2]NE (def=0x0) // Noise error flag
-
[1]FE (def=0x0) // Framing error
-
[0]PE (def=0x0) // Parity error
0x40013804DATAR// Data register
-
[0:8]DR (def=0x0) // Data value
0x40013808BRR// Baud rate register
-
[4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
-
[0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
0x4001380CCTLR1// Control register 1
-
[13]UE (def=0x0) // USART enable
-
[12]M (def=0x0) // Word length
-
[11]WAKE (def=0x0) // Wakeup method
-
[10]PCE (def=0x0) // Parity control enable
-
[9]PS (def=0x0) // Parity selection
-
[8]PEIE (def=0x0) // PE interrupt enable
-
[7]TXEIE (def=0x0) // TXE interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RXNEIE (def=0x0) // RXNE interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE interrupt enable
-
[3]TE (def=0x0) // Transmitter enable
-
[2]RE (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup
-
[0]SBK (def=0x0) // Send break
0x40013810CTLR2// Control register 2
-
[14]LINEN (def=0x0) // LIN mode enable
-
[12:13]STOP (def=0x0) // STOP bits
-
[11]CLKEN (def=0x0) // Clock enable
-
[10]CPOL (def=0x0) // Clock polarity
-
[9]CPHA (def=0x0) // Clock phase
-
[8]LBCL (def=0x0) // Last bit clock pulse
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBDL (def=0x0) // lin break detection length
-
[0:3]ADD (def=0x0) // Address of the USART node
0x40013814CTLR3// Control register 3
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSE (def=0x0) // CTS enable
-
[8]RTSE (def=0x0) // RTS enable
-
[7]DMAT (def=0x0) // DMA enable transmitter
-
[6]DMAR (def=0x0) // DMA enable receiver
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NACK (def=0x0) // Smartcard NACK enable
-
[3]HDSEL (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]EIE (def=0x0) // Error interrupt enable
0x40013818GPR// Guard time and prescaler register
-
[8:15]GT (def=0x0) // Guard time value
-
[0:7]PSC (def=0x0) // Prescaler value
- [53] USART1 // USART1 global interrupt
0x40004400USART2//
0x40004400STATR// Status register
-
[9]CTS (def=0x0) // CTS flag
-
[8]LBD (def=0x0) // LIN break detection flag
-
[7]TXE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RXNE (def=0x0) // Read data register not empty
-
[4]IDLE (def=0x0) // IDLE line detected
-
[3]ORE (def=0x0) // Overrun error
-
[2]NE (def=0x0) // Noise error flag
-
[1]FE (def=0x0) // Framing error
-
[0]PE (def=0x0) // Parity error
0x40004404DATAR// Data register
-
[0:8]DR (def=0x0) // Data value
0x40004408BRR// Baud rate register
-
[4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
-
[0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
0x4000440CCTLR1// Control register 1
-
[13]UE (def=0x0) // USART enable
-
[12]M (def=0x0) // Word length
-
[11]WAKE (def=0x0) // Wakeup method
-
[10]PCE (def=0x0) // Parity control enable
-
[9]PS (def=0x0) // Parity selection
-
[8]PEIE (def=0x0) // PE interrupt enable
-
[7]TXEIE (def=0x0) // TXE interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RXNEIE (def=0x0) // RXNE interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE interrupt enable
-
[3]TE (def=0x0) // Transmitter enable
-
[2]RE (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup
-
[0]SBK (def=0x0) // Send break
0x40004410CTLR2// Control register 2
-
[14]LINEN (def=0x0) // LIN mode enable
-
[12:13]STOP (def=0x0) // STOP bits
-
[11]CLKEN (def=0x0) // Clock enable
-
[10]CPOL (def=0x0) // Clock polarity
-
[9]CPHA (def=0x0) // Clock phase
-
[8]LBCL (def=0x0) // Last bit clock pulse
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBDL (def=0x0) // lin break detection length
-
[0:3]ADD (def=0x0) // Address of the USART node
0x40004414CTLR3// Control register 3
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSE (def=0x0) // CTS enable
-
[8]RTSE (def=0x0) // RTS enable
-
[7]DMAT (def=0x0) // DMA enable transmitter
-
[6]DMAR (def=0x0) // DMA enable receiver
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NACK (def=0x0) // Smartcard NACK enable
-
[3]HDSEL (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]EIE (def=0x0) // Error interrupt enable
0x40004418GPR// Guard time and prescaler register
-
[8:15]GT (def=0x0) // Guard time value
-
[0:7]PSC (def=0x0) // Prescaler value
- [54] USART2 // USART2 global interrupt
0x40004800USART3//
0x40004800STATR// Status register
-
[9]CTS (def=0x0) // CTS flag
-
[8]LBD (def=0x0) // LIN break detection flag
-
[7]TXE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RXNE (def=0x0) // Read data register not empty
-
[4]IDLE (def=0x0) // IDLE line detected
-
[3]ORE (def=0x0) // Overrun error
-
[2]NE (def=0x0) // Noise error flag
-
[1]FE (def=0x0) // Framing error
-
[0]PE (def=0x0) // Parity error
0x40004804DATAR// Data register
-
[0:8]DR (def=0x0) // Data value
0x40004808BRR// Baud rate register
-
[4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
-
[0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
0x4000480CCTLR1// Control register 1
-
[13]UE (def=0x0) // USART enable
-
[12]M (def=0x0) // Word length
-
[11]WAKE (def=0x0) // Wakeup method
-
[10]PCE (def=0x0) // Parity control enable
-
[9]PS (def=0x0) // Parity selection
-
[8]PEIE (def=0x0) // PE interrupt enable
-
[7]TXEIE (def=0x0) // TXE interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RXNEIE (def=0x0) // RXNE interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE interrupt enable
-
[3]TE (def=0x0) // Transmitter enable
-
[2]RE (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup
-
[0]SBK (def=0x0) // Send break
0x40004810CTLR2// Control register 2
-
[14]LINEN (def=0x0) // LIN mode enable
-
[12:13]STOP (def=0x0) // STOP bits
-
[11]CLKEN (def=0x0) // Clock enable
-
[10]CPOL (def=0x0) // Clock polarity
-
[9]CPHA (def=0x0) // Clock phase
-
[8]LBCL (def=0x0) // Last bit clock pulse
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBDL (def=0x0) // lin break detection length
-
[0:3]ADD (def=0x0) // Address of the USART node
0x40004814CTLR3// Control register 3
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSE (def=0x0) // CTS enable
-
[8]RTSE (def=0x0) // RTS enable
-
[7]DMAT (def=0x0) // DMA enable transmitter
-
[6]DMAR (def=0x0) // DMA enable receiver
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NACK (def=0x0) // Smartcard NACK enable
-
[3]HDSEL (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]EIE (def=0x0) // Error interrupt enable
0x40004818GPR// Guard time and prescaler register
-
[8:15]GT (def=0x0) // Guard time value
-
[0:7]PSC (def=0x0) // Prescaler value
- [55] USART3 // USART3 global interrupt
0x40004C00UART4//
0x40004C00STATR// Status register
-
[9]CTS (def=0x0) // CTS flag
-
[8]LBD (def=0x0) // LIN break detection flag
-
[7]TXE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RXNE (def=0x0) // Read data register not empty
-
[4]IDLE (def=0x0) // IDLE line detected
-
[3]ORE (def=0x0) // Overrun error
-
[2]NE (def=0x0) // Noise error flag
-
[1]FE (def=0x0) // Framing error
-
[0]PE (def=0x0) // Parity error
0x40004C04DATAR// Data register
-
[0:8]DR (def=0x0) // Data value
0x40004C08BRR// Baud rate register
-
[4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
-
[0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
0x40004C0CCTLR1// Control register 1
-
[13]UE (def=0x0) // USART enable
-
[12]M (def=0x0) // Word length
-
[11]WAKE (def=0x0) // Wakeup method
-
[10]PCE (def=0x0) // Parity control enable
-
[9]PS (def=0x0) // Parity selection
-
[8]PEIE (def=0x0) // PE interrupt enable
-
[7]TXEIE (def=0x0) // TXE interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RXNEIE (def=0x0) // RXNE interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE interrupt enable
-
[3]TE (def=0x0) // Transmitter enable
-
[2]RE (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup
-
[0]SBK (def=0x0) // Send break
0x40004C10CTLR2// Control register 2
-
[14]LINEN (def=0x0) // LIN mode enable
-
[12:13]STOP (def=0x0) // STOP bits
-
[11]CLKEN (def=0x0) // Clock enable
-
[10]CPOL (def=0x0) // Clock polarity
-
[9]CPHA (def=0x0) // Clock phase
-
[8]LBCL (def=0x0) // Last bit clock pulse
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBDL (def=0x0) // lin break detection length
-
[0:3]ADD (def=0x0) // Address of the USART node
0x40004C14CTLR3// Control register 3
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSE (def=0x0) // CTS enable
-
[8]RTSE (def=0x0) // RTS enable
-
[7]DMAT (def=0x0) // DMA enable transmitter
-
[6]DMAR (def=0x0) // DMA enable receiver
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NACK (def=0x0) // Smartcard NACK enable
-
[3]HDSEL (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]EIE (def=0x0) // Error interrupt enable
0x40004C18GPR// Guard time and prescaler register
-
[8:15]GT (def=0x0) // Guard time value
-
[0:7]PSC (def=0x0) // Prescaler value
- [68] UART4 // UART4 global interrupt
0x40005000UART5//
0x40005000STATR// Status register
-
[9]CTS (def=0x0) // CTS flag
-
[8]LBD (def=0x0) // LIN break detection flag
-
[7]TXE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RXNE (def=0x0) // Read data register not empty
-
[4]IDLE (def=0x0) // IDLE line detected
-
[3]ORE (def=0x0) // Overrun error
-
[2]NE (def=0x0) // Noise error flag
-
[1]FE (def=0x0) // Framing error
-
[0]PE (def=0x0) // Parity error
0x40005004DATAR// Data register
-
[0:8]DR (def=0x0) // Data value
0x40005008BRR// Baud rate register
-
[4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
-
[0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
0x4000500CCTLR1// Control register 1
-
[13]UE (def=0x0) // USART enable
-
[12]M (def=0x0) // Word length
-
[11]WAKE (def=0x0) // Wakeup method
-
[10]PCE (def=0x0) // Parity control enable
-
[9]PS (def=0x0) // Parity selection
-
[8]PEIE (def=0x0) // PE interrupt enable
-
[7]TXEIE (def=0x0) // TXE interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RXNEIE (def=0x0) // RXNE interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE interrupt enable
-
[3]TE (def=0x0) // Transmitter enable
-
[2]RE (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup
-
[0]SBK (def=0x0) // Send break
0x40005010CTLR2// Control register 2
-
[14]LINEN (def=0x0) // LIN mode enable
-
[12:13]STOP (def=0x0) // STOP bits
-
[11]CLKEN (def=0x0) // Clock enable
-
[10]CPOL (def=0x0) // Clock polarity
-
[9]CPHA (def=0x0) // Clock phase
-
[8]LBCL (def=0x0) // Last bit clock pulse
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBDL (def=0x0) // lin break detection length
-
[0:3]ADD (def=0x0) // Address of the USART node
0x40005014CTLR3// Control register 3
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSE (def=0x0) // CTS enable
-
[8]RTSE (def=0x0) // RTS enable
-
[7]DMAT (def=0x0) // DMA enable transmitter
-
[6]DMAR (def=0x0) // DMA enable receiver
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NACK (def=0x0) // Smartcard NACK enable
-
[3]HDSEL (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]EIE (def=0x0) // Error interrupt enable
0x40005018GPR// Guard time and prescaler register
-
[8:15]GT (def=0x0) // Guard time value
-
[0:7]PSC (def=0x0) // Prescaler value
- [69] UART5 // UART5 global interrupt
0x40001800UART6//
0x40001800STATR// Status register
-
[9]CTS (def=0x0) // CTS flag
-
[8]LBD (def=0x0) // LIN break detection flag
-
[7]TXE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RXNE (def=0x0) // Read data register not empty
-
[4]IDLE (def=0x0) // IDLE line detected
-
[3]ORE (def=0x0) // Overrun error
-
[2]NE (def=0x0) // Noise error flag
-
[1]FE (def=0x0) // Framing error
-
[0]PE (def=0x0) // Parity error
0x40001804DATAR// Data register
-
[0:8]DR (def=0x0) // Data value
0x40001808BRR// Baud rate register
-
[4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
-
[0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
0x4000180CCTLR1// Control register 1
-
[13]UE (def=0x0) // USART enable
-
[12]M (def=0x0) // Word length
-
[11]WAKE (def=0x0) // Wakeup method
-
[10]PCE (def=0x0) // Parity control enable
-
[9]PS (def=0x0) // Parity selection
-
[8]PEIE (def=0x0) // PE interrupt enable
-
[7]TXEIE (def=0x0) // TXE interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RXNEIE (def=0x0) // RXNE interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE interrupt enable
-
[3]TE (def=0x0) // Transmitter enable
-
[2]RE (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup
-
[0]SBK (def=0x0) // Send break
0x40001810CTLR2// Control register 2
-
[14]LINEN (def=0x0) // LIN mode enable
-
[12:13]STOP (def=0x0) // STOP bits
-
[11]CLKEN (def=0x0) // Clock enable
-
[10]CPOL (def=0x0) // Clock polarity
-
[9]CPHA (def=0x0) // Clock phase
-
[8]LBCL (def=0x0) // Last bit clock pulse
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBDL (def=0x0) // lin break detection length
-
[0:3]ADD (def=0x0) // Address of the USART node
0x40001814CTLR3// Control register 3
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSE (def=0x0) // CTS enable
-
[8]RTSE (def=0x0) // RTS enable
-
[7]DMAT (def=0x0) // DMA enable transmitter
-
[6]DMAR (def=0x0) // DMA enable receiver
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NACK (def=0x0) // Smartcard NACK enable
-
[3]HDSEL (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]EIE (def=0x0) // Error interrupt enable
0x40001818GPR// Guard time and prescaler register
-
[8:15]GT (def=0x0) // Guard time value
-
[0:7]PSC (def=0x0) // Prescaler value
- [87] UART6 // UART6 global interrupt
0x40001C00UART7//
0x40001C00STATR// Status register
-
[9]CTS (def=0x0) // CTS flag
-
[8]LBD (def=0x0) // LIN break detection flag
-
[7]TXE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RXNE (def=0x0) // Read data register not empty
-
[4]IDLE (def=0x0) // IDLE line detected
-
[3]ORE (def=0x0) // Overrun error
-
[2]NE (def=0x0) // Noise error flag
-
[1]FE (def=0x0) // Framing error
-
[0]PE (def=0x0) // Parity error
0x40001C04DATAR// Data register
-
[0:8]DR (def=0x0) // Data value
0x40001C08BRR// Baud rate register
-
[4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
-
[0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
0x40001C0CCTLR1// Control register 1
-
[13]UE (def=0x0) // USART enable
-
[12]M (def=0x0) // Word length
-
[11]WAKE (def=0x0) // Wakeup method
-
[10]PCE (def=0x0) // Parity control enable
-
[9]PS (def=0x0) // Parity selection
-
[8]PEIE (def=0x0) // PE interrupt enable
-
[7]TXEIE (def=0x0) // TXE interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RXNEIE (def=0x0) // RXNE interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE interrupt enable
-
[3]TE (def=0x0) // Transmitter enable
-
[2]RE (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup
-
[0]SBK (def=0x0) // Send break
0x40001C10CTLR2// Control register 2
-
[14]LINEN (def=0x0) // LIN mode enable
-
[12:13]STOP (def=0x0) // STOP bits
-
[11]CLKEN (def=0x0) // Clock enable
-
[10]CPOL (def=0x0) // Clock polarity
-
[9]CPHA (def=0x0) // Clock phase
-
[8]LBCL (def=0x0) // Last bit clock pulse
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBDL (def=0x0) // lin break detection length
-
[0:3]ADD (def=0x0) // Address of the USART node
0x40001C14CTLR3// Control register 3
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSE (def=0x0) // CTS enable
-
[8]RTSE (def=0x0) // RTS enable
-
[7]DMAT (def=0x0) // DMA enable transmitter
-
[6]DMAR (def=0x0) // DMA enable receiver
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NACK (def=0x0) // Smartcard NACK enable
-
[3]HDSEL (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]EIE (def=0x0) // Error interrupt enable
0x40001C18GPR// Guard time and prescaler register
-
[8:15]GT (def=0x0) // Guard time value
-
[0:7]PSC (def=0x0) // Prescaler value
- [88] UART7 // UART7 global interrupt
0x40002000UART8//
0x40002000STATR// Status register
-
[9]CTS (def=0x0) // CTS flag
-
[8]LBD (def=0x0) // LIN break detection flag
-
[7]TXE (def=0x1) // Transmit data register empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RXNE (def=0x0) // Read data register not empty
-
[4]IDLE (def=0x0) // IDLE line detected
-
[3]ORE (def=0x0) // Overrun error
-
[2]NE (def=0x0) // Noise error flag
-
[1]FE (def=0x0) // Framing error
-
[0]PE (def=0x0) // Parity error
0x40002004DATAR// Data register
-
[0:8]DR (def=0x0) // Data value
0x40002008BRR// Baud rate register
-
[4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
-
[0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
0x4000200CCTLR1// Control register 1
-
[13]UE (def=0x0) // USART enable
-
[12]M (def=0x0) // Word length
-
[11]WAKE (def=0x0) // Wakeup method
-
[10]PCE (def=0x0) // Parity control enable
-
[9]PS (def=0x0) // Parity selection
-
[8]PEIE (def=0x0) // PE interrupt enable
-
[7]TXEIE (def=0x0) // TXE interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RXNEIE (def=0x0) // RXNE interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE interrupt enable
-
[3]TE (def=0x0) // Transmitter enable
-
[2]RE (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup
-
[0]SBK (def=0x0) // Send break
0x40002010CTLR2// Control register 2
-
[14]LINEN (def=0x0) // LIN mode enable
-
[12:13]STOP (def=0x0) // STOP bits
-
[11]CLKEN (def=0x0) // Clock enable
-
[10]CPOL (def=0x0) // Clock polarity
-
[9]CPHA (def=0x0) // Clock phase
-
[8]LBCL (def=0x0) // Last bit clock pulse
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBDL (def=0x0) // lin break detection length
-
[0:3]ADD (def=0x0) // Address of the USART node
0x40002014CTLR3// Control register 3
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSE (def=0x0) // CTS enable
-
[8]RTSE (def=0x0) // RTS enable
-
[7]DMAT (def=0x0) // DMA enable transmitter
-
[6]DMAR (def=0x0) // DMA enable receiver
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NACK (def=0x0) // Smartcard NACK enable
-
[3]HDSEL (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]EIE (def=0x0) // Error interrupt enable
0x40002018GPR// Guard time and prescaler register
-
[8:15]GT (def=0x0) // Guard time value
-
[0:7]PSC (def=0x0) // Prescaler value
- [89] UART8 // UART8 global interrupt
0x40012400ADC1// Analog to digital converter
0x40012400STATR// status register
-
[4]STRT (def=0x0) // Regular channel start flag
-
[3]JSTRT (def=0x0) // Injected channel start flag
-
[2]JEOC (def=0x0) // Injected channel end of conversion
-
[1]EOC (def=0x0) // Regular channel end of conversion
-
[0]AWD (def=0x0) // Analog watchdog flag
0x40012404CTLR1// control register 1/TKEY_V_CTLR
-
[27:28]PGA (def=0x0) // ADC_PGA
-
[26]BUFEN (def=0x0) // TKEY_BUF_Enable
-
[25]TKITUNE (def=0x0) // TKEY_I enable
-
[24]TKEYEN (def=0x0) // TKEY enable, including TKEY_F and TKEY_V
-
[23]AWDEN (def=0x0) // Analog watchdog enable on regular channels
-
[22]JAWDEN (def=0x0) // Analog watchdog enable on injected channels
-
[16:19]DUALMOD (def=0x0) // Dual mode selection
-
[13:15]DISCNUM (def=0x0) // Discontinuous mode channel count
-
[12]JDISCEN (def=0x0) // Discontinuous mode on injected channels
-
[11]DISCEN (def=0x0) // Discontinuous mode on regular channels
-
[10]JAUTO (def=0x0) // Automatic injected group conversion
-
[9]AWDSGL (def=0x0) // Enable the watchdog on a single channel in scan mode
-
[8]SCAN (def=0x0) // Scan mode enable
-
[7]JEOCIE (def=0x0) // Interrupt enable for injected channels
-
[6]AWDIE (def=0x0) // Analog watchdog interrupt enable
-
[5]EOCIE (def=0x0) // Interrupt enable for EOC
-
[0:4]AWDCH (def=0x0) // Analog watchdog channel select bits
0x40012408CTLR2// control register 2
-
[23]TSVREFE (def=0x0) // Temperature sensor and VREFINT enable
-
[22]SWSTART (def=0x0) // Start conversion of regular channels
-
[21]JSWSTART (def=0x0) // Start conversion of injected channels
-
[20]EXTTRIG (def=0x0) // External trigger conversion mode for regular channels
-
[17:19]EXTSEL (def=0x0) // External event select for regular group
-
[15]JEXTTRIG (def=0x0) // External trigger conversion mode for injected channels
-
[12:14]JEXTSEL (def=0x0) // External event select for injected group
-
[11]ALIGN (def=0x0) // Data alignment
-
[8]DMA (def=0x0) // Direct memory access mode
-
[3]RSTCAL (def=0x0) // Reset calibration
-
[2]CAL (def=0x0) // A/D calibration
-
[1]CONT (def=0x0) // Continuous conversion
-
[0]ADON (def=0x0) // A/D converter ON / OFF
0x4001240CSAMPTR1_CHARGE1// sample time register 1
-
[0:2]SMP10_TKCG10 (def=0x0) // Channel 10 sample time selection
-
[3:5]SMP11_TKCG11 (def=0x0) // Channel 11 sample time selection
-
[6:8]SMP12_TKCG12 (def=0x0) // Channel 12 sample time selection
-
[9:11]SMP13_TKCG13 (def=0x0) // Channel 13 sample time selection
-
[12:14]SMP14_TKCG14 (def=0x0) // Channel 14 sample time selection
-
[15:17]SMP15_TKCG15 (def=0x0) // Channel 15 sample time selection
-
[18:20]SMP16_TKCG16 (def=0x0) // Channel 16 sample time selection
-
[21:23]SMP17_TKCG17 (def=0x0) // Channel 17 sample time selection
0x40012410SAMPTR2_CHARGE2// sample time register 2
-
[0:2]SMP0_TKCG0 (def=0x0) // Channel 0 sample time selection
-
[3:5]SMP1_TKCG1 (def=0x0) // Channel 1 sample time selection
-
[6:8]SMP2_TKCG2 (def=0x0) // Channel 2 sample time selection
-
[9:11]SMP3_TKCG3 (def=0x0) // Channel 3 sample time selection
-
[12:14]SMP4_TKCG4 (def=0x0) // Channel 4 sample time selection
-
[15:17]SMP5_TKCG5 (def=0x0) // Channel 5 sample time selection
-
[18:20]SMP6_TKCG6 (def=0x0) // Channel 6 sample time selection
-
[21:23]SMP7_TKCG7 (def=0x0) // Channel 7 sample time selection
-
[24:26]SMP8_TKCG8 (def=0x0) // Channel 8 sample time selection
-
[27:29]SMP9_TKCG9 (def=0x0) // Channel 9 sample time selection
0x40012414IOFR1// injected channel data offset register x
-
[0:11]JOFFSET1 (def=0x0) // Data offset for injected channel x
0x40012418IOFR2// injected channel data offset register x
-
[0:11]JOFFSET2 (def=0x0) // Data offset for injected channel x
0x4001241CIOFR3// injected channel data offset register x
-
[0:11]JOFFSET3 (def=0x0) // Data offset for injected channel x
0x40012420IOFR4// injected channel data offset register x
-
[0:11]JOFFSET4 (def=0x0) // Data offset for injected channel x
0x40012424WDHTR// watchdog higher threshold register
-
[0:11]HT (def=0xFFF) // Analog watchdog higher threshold
0x40012428WDLTR// watchdog lower threshold register
-
[0:11]LT (def=0x0) // Analog watchdog lower threshold
0x4001242CRSQR1// regular sequence register 1
-
[20:23]L (def=0x0) // Regular channel sequence length
-
[15:19]SQ16 (def=0x0) // 16th conversion in regular sequence
-
[10:14]SQ15 (def=0x0) // 15th conversion in regular sequence
-
[5:9]SQ14 (def=0x0) // 14th conversion in regular sequence
-
[0:4]SQ13 (def=0x0) // 13th conversion in regular sequence
0x40012430RSQR2// regular sequence register 2
-
[25:29]SQ12 (def=0x0) // 12th conversion in regular sequence
-
[20:24]SQ11 (def=0x0) // 11th conversion in regular sequence
-
[15:19]SQ10 (def=0x0) // 10th conversion in regular sequence
-
[10:14]SQ9 (def=0x0) // 9th conversion in regular sequence
-
[5:9]SQ8 (def=0x0) // 8th conversion in regular sequence
-
[0:4]SQ7 (def=0x0) // 7th conversion in regular sequence
0x40012434RSQR3__CHANNEL// regular sequence register 3;TKEY_V_CHANNEL
-
[25:29]SQ6 (def=0x0) // 6th conversion in regular sequence
-
[20:24]SQ5 (def=0x0) // 5th conversion in regular sequence
-
[15:19]SQ4 (def=0x0) // 4th conversion in regular sequence
-
[10:14]SQ3 (def=0x0) // 3rd conversion in regular sequence
-
[5:9]SQ2 (def=0x0) // 2nd conversion in regular sequence
-
[0:4]SQ1__CHSEL (def=0x0) // 1st conversion in regular sequence;TKDY_V channel select
0x40012438ISQR// injected sequence register
-
[20:21]JL (def=0x0) // Injected sequence length
-
[15:19]JSQ4 (def=0x0) // 4th conversion in injected sequence
-
[10:14]JSQ3 (def=0x0) // 3rd conversion in injected sequence
-
[5:9]JSQ2 (def=0x0) // 2nd conversion in injected sequence
-
[0:4]JSQ1 (def=0x0) // 1st conversion in injected sequence
0x4001243CIDATAR1_CHGOFFSET// injected data register x_Charge data offset for injected channel x
-
[0:7]IDATA0_7_TKCGOFFSET (def=0x0) // Injected data_Touch key charge data offset for injected channel x
-
[8:15]IDATA8_15 (def=0x0) // Injected data
0x40012440IDATAR2// injected data register x
-
[0:15]JDATA (def=0x0) // Injected data
0x40012444IDATAR3// injected data register x
-
[0:15]JDATA (def=0x0) // Injected data
0x40012448IDATAR4// injected data register x
-
[0:15]JDATA (def=0x0) // Injected data
0x4001244CRDATAR_DR// regular data register
-
[0:7]DATA0_7 (def=0x0) // Regular data
-
[8:15]DATA8_15 (def=0x0) // Regular data
-
[16:31]ADC2DATA (def=0x0) // converter data
0x4001244CACT_DCG// start and discharge time register
-
[0:7]TKACT_DCG (def=0x0) // Touch key start and discharge time register
- [34] ADC // ADC global interrupt
0x40012800ADC2// Analog to digital converter
0x40012800STATR// status register
-
[4]STRT (def=0x0) // Regular channel start flag
-
[3]JSTRT (def=0x0) // Injected channel start flag
-
[2]JEOC (def=0x0) // Injected channel end of conversion
-
[1]EOC (def=0x0) // Regular channel end of conversion
-
[0]AWD (def=0x0) // Analog watchdog flag
0x40012804CTLR1// control register 1/TKEY_V_CTLR
-
[27:28]PGA (def=0x0) // ADC_PGA
-
[26]BUFEN (def=0x0) // TKEY_BUF_Enable
-
[25]TKITUNE (def=0x0) // TKEY_I enable
-
[24]TKEYEN (def=0x0) // TKEY enable, including TKEY_F and TKEY_V
-
[23]AWDEN (def=0x0) // Analog watchdog enable on regular channels
-
[22]JAWDEN (def=0x0) // Analog watchdog enable on injected channels
-
[16:19]DUALMOD (def=0x0) // Dual mode selection
-
[13:15]DISCNUM (def=0x0) // Discontinuous mode channel count
-
[12]JDISCEN (def=0x0) // Discontinuous mode on injected channels
-
[11]DISCEN (def=0x0) // Discontinuous mode on regular channels
-
[10]JAUTO (def=0x0) // Automatic injected group conversion
-
[9]AWDSGL (def=0x0) // Enable the watchdog on a single channel in scan mode
-
[8]SCAN (def=0x0) // Scan mode enable
-
[7]JEOCIE (def=0x0) // Interrupt enable for injected channels
-
[6]AWDIE (def=0x0) // Analog watchdog interrupt enable
-
[5]EOCIE (def=0x0) // Interrupt enable for EOC
-
[0:4]AWDCH (def=0x0) // Analog watchdog channel select bits
0x40012808CTLR2// control register 2
-
[23]TSVREFE (def=0x0) // Temperature sensor and VREFINT enable
-
[22]SWSTART (def=0x0) // Start conversion of regular channels
-
[21]JSWSTART (def=0x0) // Start conversion of injected channels
-
[20]EXTTRIG (def=0x0) // External trigger conversion mode for regular channels
-
[17:19]EXTSEL (def=0x0) // External event select for regular group
-
[15]JEXTTRIG (def=0x0) // External trigger conversion mode for injected channels
-
[12:14]JEXTSEL (def=0x0) // External event select for injected group
-
[11]ALIGN (def=0x0) // Data alignment
-
[8]DMA (def=0x0) // Direct memory access mode
-
[3]RSTCAL (def=0x0) // Reset calibration
-
[2]CAL (def=0x0) // A/D calibration
-
[1]CONT (def=0x0) // Continuous conversion
-
[0]ADON (def=0x0) // A/D converter ON / OFF
0x4001280CSAMPTR1_CHARGE1// sample time register 1
-
[0:2]SMP10_TKCG10 (def=0x0) // Channel 10 sample time selection
-
[3:5]SMP11_TKCG11 (def=0x0) // Channel 11 sample time selection
-
[6:8]SMP12_TKCG12 (def=0x0) // Channel 12 sample time selection
-
[9:11]SMP13_TKCG13 (def=0x0) // Channel 13 sample time selection
-
[12:14]SMP14_TKCG14 (def=0x0) // Channel 14 sample time selection
-
[15:17]SMP15_TKCG15 (def=0x0) // Channel 15 sample time selection
-
[18:20]SMP16_TKCG16 (def=0x0) // Channel 16 sample time selection
-
[21:23]SMP17_TKCG17 (def=0x0) // Channel 17 sample time selection
0x40012810SAMPTR2_CHARGE2// sample time register 2
-
[0:2]SMP0_TKCG0 (def=0x0) // Channel 0 sample time selection
-
[3:5]SMP1_TKCG1 (def=0x0) // Channel 1 sample time selection
-
[6:8]SMP2_TKCG2 (def=0x0) // Channel 2 sample time selection
-
[9:11]SMP3_TKCG3 (def=0x0) // Channel 3 sample time selection
-
[12:14]SMP4_TKCG4 (def=0x0) // Channel 4 sample time selection
-
[15:17]SMP5_TKCG5 (def=0x0) // Channel 5 sample time selection
-
[18:20]SMP6_TKCG6 (def=0x0) // Channel 6 sample time selection
-
[21:23]SMP7_TKCG7 (def=0x0) // Channel 7 sample time selection
-
[24:26]SMP8_TKCG8 (def=0x0) // Channel 8 sample time selection
-
[27:29]SMP9_TKCG9 (def=0x0) // Channel 9 sample time selection
0x40012814IOFR1// injected channel data offset register x
-
[0:11]JOFFSET1 (def=0x0) // Data offset for injected channel x
0x40012818IOFR2// injected channel data offset register x
-
[0:11]JOFFSET2 (def=0x0) // Data offset for injected channel x
0x4001281CIOFR3// injected channel data offset register x
-
[0:11]JOFFSET3 (def=0x0) // Data offset for injected channel x
0x40012820IOFR4// injected channel data offset register x
-
[0:11]JOFFSET4 (def=0x0) // Data offset for injected channel x
0x40012824WDHTR// watchdog higher threshold register
-
[0:11]HT (def=0xFFF) // Analog watchdog higher threshold
0x40012828WDLTR// watchdog lower threshold register
-
[0:11]LT (def=0x0) // Analog watchdog lower threshold
0x4001282CRSQR1// regular sequence register 1
-
[20:23]L (def=0x0) // Regular channel sequence length
-
[15:19]SQ16 (def=0x0) // 16th conversion in regular sequence
-
[10:14]SQ15 (def=0x0) // 15th conversion in regular sequence
-
[5:9]SQ14 (def=0x0) // 14th conversion in regular sequence
-
[0:4]SQ13 (def=0x0) // 13th conversion in regular sequence
0x40012830RSQR2// regular sequence register 2
-
[25:29]SQ12 (def=0x0) // 12th conversion in regular sequence
-
[20:24]SQ11 (def=0x0) // 11th conversion in regular sequence
-
[15:19]SQ10 (def=0x0) // 10th conversion in regular sequence
-
[10:14]SQ9 (def=0x0) // 9th conversion in regular sequence
-
[5:9]SQ8 (def=0x0) // 8th conversion in regular sequence
-
[0:4]SQ7 (def=0x0) // 7th conversion in regular sequence
0x40012834RSQR3__CHANNEL// regular sequence register 3;TKEY_V_CHANNEL
-
[25:29]SQ6 (def=0x0) // 6th conversion in regular sequence
-
[20:24]SQ5 (def=0x0) // 5th conversion in regular sequence
-
[15:19]SQ4 (def=0x0) // 4th conversion in regular sequence
-
[10:14]SQ3 (def=0x0) // 3rd conversion in regular sequence
-
[5:9]SQ2 (def=0x0) // 2nd conversion in regular sequence
-
[0:4]SQ1__CHSEL (def=0x0) // 1st conversion in regular sequence;TKDY_V channel select
0x40012838ISQR// injected sequence register
-
[20:21]JL (def=0x0) // Injected sequence length
-
[15:19]JSQ4 (def=0x0) // 4th conversion in injected sequence
-
[10:14]JSQ3 (def=0x0) // 3rd conversion in injected sequence
-
[5:9]JSQ2 (def=0x0) // 2nd conversion in injected sequence
-
[0:4]JSQ1 (def=0x0) // 1st conversion in injected sequence
0x4001283CIDATAR1_CHGOFFSET// injected data register x_Charge data offset for injected channel x
-
[0:7]IDATA0_7_TKCGOFFSET (def=0x0) // Injected data_Touch key charge data offset for injected channel x
-
[8:15]IDATA8_15 (def=0x0) // Injected data
0x40012840IDATAR2// injected data register x
-
[0:15]JDATA (def=0x0) // Injected data
0x40012844IDATAR3// injected data register x
-
[0:15]JDATA (def=0x0) // Injected data
0x40012848IDATAR4// injected data register x
-
[0:15]JDATA (def=0x0) // Injected data
0x4001284CRDATAR_DR// regular data register
-
[0:7]DATA0_7 (def=0x0) // Regular data
-
[8:15]DATA8_15 (def=0x0) // Regular data
0x4001284CACT_DCG// start and discharge time register
-
[0:7]TKACT_DCG (def=0x0) // Touch key start and discharge time register
0xE000D000DBG// Debug support
0xE000D000CFGR1// DBGMCU_CFGR1
-
[0]DEG_IWDG (def=0x0) // DEG_IWDG
-
[1]DEG_WWDG (def=0x0) // DEG_WWDG
-
[2]DEG_I2C1 (def=0x0) // DEG_I2C1
-
[3]DEG_I2C2 (def=0x0) // DEG_I2C2
-
[4]DEG_TIM1 (def=0x0) // DEG_TIM1
-
[5]DEG_TIM2 (def=0x0) // DEG_TIM2
-
[6]DEG_TIM3 (def=0x0) // DEG_TIM3
-
[7]DEG_TIM4 (def=0x0) // DEG_TIM4
0xE000D004CFGR2// DBGMCU_CFGR2
-
[0]DBG_SLEEP (def=0x0) // DBG_SLEEP
-
[1]DBG_STOP (def=0x0) // DBG_STOP
-
[2]DBG_STANDBY (def=0x0) // DBG_STANDBY
0x40023400USBHS// USB register
0x40023400USB_CTRL// USB base control
-
[0]RB_UC_DMA_EN (def=0x0) // DMA enable and DMA interrupt enable for USB
-
[1]RB_UC_CLR_ALL (def=0x1) // force clear FIFO and count of USB
-
[2]RB_UC_RST_SIE (def=0x1) // force reset USB SIE, need software clear
-
[3]RB_UC_INT_BUSY (def=0x0) // enable automatic responding busy for device mode or automatic pause for host mode during interrupt
-
[4]RB_UC_DEV_PU_EN (def=0x0) // USB device enable and internal pullup resistance enable
-
[5:6]RB_UC_SPEED_TYPE (def=0x0) // enable USB low speed: 00=full speed, 01=high speed, 10 =low speed
-
[7]RB_UC_HOST_MODE (def=0x0) // enable USB host mode: 0=device mode, 1=host mode
0x40023401UHOST_CTRL// USB HOST control
-
[0]RB_UH_TX_BUS_RST (def=0x0) // USB host bus reset status
-
[1]bUH_TX_BUS_SUSPENDRB_UH_TX_BUS_SUSPEND (def=0x0) // the host sends hang sigal
-
[2]RB_UH_TX_BUS_RESUME (def=0x0) // host wake up device
-
[3]RB_UH_REMOTE_WKUP (def=0x0) // the remoke wake-up
-
[4]RB_UH_PHY_SUSPENDM (def=0x0) // USB-PHY thesuspended state the internal USB-PLL is turned off
-
[6]RB_UH_SOF_FREE (def=0x0) // the bus is idle
-
[7]RB_UH_SOF_EN (def=0x0) // automatically generate the SOF packet enabling control bit
0x40023402USB_INT_EN// USB interrupt enable
-
[0]RB_UIE_BUS_RST__RB_UIE_DETECT (def=0x0) // enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detect
-
[1]RB_UIE_TRANSFER (def=0x0) // enable interrupt for USB transfer completion
-
[2]RB_UIE_SUSPEND (def=0x0) // enable interrupt for USB suspend or resume event
-
[3]RB_UIE_HST_SOF (def=0x0) // indicate host SOF timer action status for USB host
-
[4]RB_UIE_FIFO_OV (def=0x0) // enable interrupt for FIFO overflow
-
[5]RB_UIE_SETUP_ACT (def=0x0) // indicate host SETUP timer action status for USB host
-
[6]RB_UIE_ISO_ACT (def=0x0) // enable interrupt for NAK responded for USB device mode
-
[7]RB_UIE_DEV_NAK (def=0x0) // enable interrupt for NAK responded for USB device mode
0x40023403USB_DEV_AD// USB device address
-
[0:6]MASK_USB_ADDR (def=0x0) // bit mask for USB device address
-
[7]RB_UDA_GP_BIT (def=0x0) // general purpose bit
0x40023404USB_FRAME_NO// USB_FRAME_NO
-
[0:15]USB_FRAME_NO (def=0x0) // USB_FRAME_NO
0x40023406USB_USB_SUSPEND// indicate USB suspend status
-
[0:1]USB_SYS_MOD (def=0x0) // USB_SYS_MOD
-
[2]USB_WAKEUP (def=0x0) // remote resume
-
[4:5]USB_LINESTATE (def=0x0) // USB_LINESTATE
0x40023408USB_SPEED_TYPE// USB_SPEED_TYPE
-
[0:1]USB_SPEED_TYPE (def=0x0) // USB_SPEED_TYPE
0x40023409USB_MIS_ST// USB miscellaneous status
-
[0]RB_UMS_SPLIT_CAN (def=0x0) // RO, indicate device attached status on USB host
-
[1]RB_UMS_ATTACH (def=0x0) // RO, indicate UDM level saved at device attached to USB host
-
[2]RB_UMS_SUSPEND (def=0x0) // RO, indicate USB suspend status
-
[3]RB_UMS_BUS_RESET (def=0x0) // RO, indicate USB bus reset status
-
[4]RB_UMS_R_FIFO_RDY (def=0x0) // RO, indicate USB receiving FIFO ready status (not empty)
-
[5]RB_UMS_SIE_FREE (def=0x0) // RO, indicate USB SIE free status
-
[6]RB_UMS_SOF_ACT (def=0x0) // RO, indicate host SOF timer action status for USB host
-
[7]RB_UMS_SOF_PRES (def=0x0) // RO, indicate host SOF timer presage status
0x4002340AUSB_INT_FG// USB interrupt flag
-
[0]RB_UIF_BUS_RST (def=0x0) // RB_UIF_BUS_RST
-
[1]RB_UIF_TRANSFER (def=0x0) // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-
[2]RB_UIF_SUSPEND (def=0x0) // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-
[3]RB_UIF_HST_SOF (def=0x0) // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-
[4]RB_UIF_FIFO_OV (def=0x0) // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-
[5]RB_U_SETUP_ACT (def=0x1) // USB_SETUP_ACT
-
[6]UIF_ISO_ACT (def=0x0) // UIF_ISO_ACT
-
[7]RB_U_IS_NAK (def=0x0) // RO, indicate current USB transfer is NAK received
0x4002340BUSB_INT_ST// USB interrupt status
-
[0:3]MASK_UIS_H_RES__MASK_UIS_ENDP (def=0x0) // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out f
-
[4:5]MASK_UIS_TOKEN (def=0x0) // RO, bit mask of current token PID code received for USB device mode
-
[6]RB_UIS_TOG_OK (def=0x0) // RO, indicate current USB transfer toggle is OK
-
[7]RB_UIS_IS_NAK (def=0x0) // RO, indicate current USB transfer is NAK received for USB device mode
0x4002340CUSB_RX_LEN// USB receiving length
-
[0:15]R16_USB_RX_LEN (def=0x0) // length of received bytes
0x40023410UEP_CONFIG__UHOST_CTRL// USB endpoint configuration
-
[17:31]RB_UEP_T_EN__UH_EP_MOD (def=0x0) // endpoint RX enable/bUH_TX_EN
-
[1:15]RB_UEP_T_EN_bUH_TX_EN (def=0x0) // endpoint TX enable/bUH_TX_EN
0x40023414UEP_TYPE// USB endpoint type
-
[17:31]RB_UEP_R_TYPE (def=0x0) // endpoint RX type
-
[1:15]RB_UEP_T_TYPE (def=0x0) // endpoint TX type
0x40023418UEP_BUF_MOD// USB endpoint buffer mode
-
[16:31]RB_UEP_ISO_BUF_MOD (def=0x0) // buffer mode of USB endpoint
-
[0:15]RB_UEP_BUF_MOD (def=0x0) // buffer mode of USB endpoint
0x4002341CUEP0_DMA// B endpoint 0 DMA buffer address
-
[0:31]UEP0_DMA (def=0x0) // endpoint 0 DMA buffer address
0x40023420UEP1_RX_DMA// endpoint 1 DMA RX buffer address
-
[0:31]UEP1_RX_DMA (def=0x0) // endpoint 1 DMA buffer address
0x40023424UEP2_RX_DMA__UH_RX_DMA// endpoint 2 DMA RX buffer address/UH_RX_DMA
-
[0:31]UEP2_RX_DMA__UH_RX_DMA (def=0x0) // endpoint 2 DMA buffer address
0x40023428UEP3_RX_DMA// endpoint 3 DMA RX buffer address
-
[0:31]UEP3_RX_DMA (def=0x0) // endpoint 3 DMA buffer address
0x4002342CUEP4_RX_DMA// endpoint 4 DMA RX buffer address
-
[0:31]UEP4_RX_DMA (def=0x0) // endpoint 4 DMA buffer address
0x40023430UEP5_RX_DMA// endpoint 5 DMA RX buffer address
-
[0:31]UEP5_DMA (def=0x0) // endpoint 5 DMA buffer address
0x40023434UEP6_RX_DMA// endpoint 6 DMA RX buffer address
-
[0:31]UEP6_RX_DMA (def=0x0) // endpoint 6 DMA buffer address
0x40023438UEP7_RX_DMA// endpoint 7 DMA RX buffer address
-
[0:31]UEP7_RX_DMA (def=0x0) // endpoint 7 DMA buffer address
0x4002343CUEP8_RX_DMA// endpoint 8 DMA RX buffer address
-
[0:31]UEP8_RX_DMA (def=0x0) // endpoint 8 DMA buffer address
0x40023440UEP9_RX_DMA// endpoint 9 DMA RX buffer address
-
[0:31]UEP9_RX_DMA (def=0x0) // endpoint 9 DMA buffer address
0x40023444UEP10_RX_DMA// endpoint 10 DMA RX buffer address
-
[0:31]UEP10_RX_DMA (def=0x0) // endpoint 10 DMA buffer address
0x40023448UEP11_RX_DMA// endpoint 11 DMA RX buffer address
-
[0:31]UEP11_RX_DMA (def=0x0) // endpoint 11 DMA buffer address
0x4002344CUEP12_RX_DMA// endpoint 12 DMA RX buffer address
-
[0:31]UEP12_RX_DMA (def=0x0) // endpoint 12 DMA buffer address
0x40023450UEP13_RX_DMA// endpoint 13 DMA RX buffer address
-
[0:31]UEP13_RX_DMA (def=0x0) // endpoint 13 DMA buffer address
0x40023454UEP14_RX_DMA// endpoint 14 DMA RX buffer address
-
[0:31]UEP14_RX_DMA (def=0x0) // endpoint 14 DMA buffer address
0x40023458UEP15_RX_DMA// endpoint 15 DMA RX buffer address
-
[0:31]UEP15_RX_DMA (def=0x0) // endpoint 15 DMA buffer address
0x4002345CUEP1_TX_DMA// endpoint 1 DMA TX buffer address
-
[0:31]UEP1_TX_DMA (def=0x0) // endpoint 1 DMA buffer address
0x40023460UEP2_TX_DMA// endpoint 2 DMA TX buffer address
-
[0:31]UEP2_TX_DMA (def=0x0) // endpoint 2 DMA buffer address
0x40023464UEP3_TX_DMA__UH_TX_DMA// endpoint 3 DMA TX buffer address
-
[0:31]UEP3_TX_DMA__UH_TX_DMA (def=0x0) // endpoint 3 DMA buffer address
0x40023468UEP4_TX_DMA// endpoint 4 DMA TX buffer address
-
[0:31]UEP4_TX_DMA (def=0x0) // endpoint 4 DMA buffer address
0x4002346CUEP5_TX_DMA// endpoint 5 DMA TX buffer address
-
[0:31]UEP5_TX_DMA (def=0x0) // endpoint 5 DMA buffer address
0x40023470UEP6_TX_DMA// endpoint 6 DMA TX buffer address
-
[0:31]UEP6_TX_DMA (def=0x0) // endpoint 6 DMA buffer address
0x40023474UEP7_TX_DMA// endpoint 7 DMA TX buffer address
-
[0:31]UEP7_TX_DMA (def=0x0) // endpoint 7 DMA buffer address
0x40023478UEP8_TX_DMA// endpoint 8 DMA TX buffer address
-
[0:31]UEP8_TX_DMA (def=0x0) // endpoint 8 DMA buffer address
0x4002347CUEP9_TX_DMA// endpoint 9 DMA TX buffer address
-
[0:31]UEP9_TX_DMA (def=0x0) // endpoint 9 DMA buffer address
0x40023480UEP10_TX_DMA// endpoint 10 DMA TX buffer address
-
[0:31]UEP10_TX_DMA (def=0x0) // endpoint 10 DMA buffer address
0x40023484UEP11_TX_DMA// endpoint 11 DMA TX buffer address
-
[0:31]UEP11_TX_DMA (def=0x0) // endpoint 11 DMA buffer address
0x40023488UEP12_TX_DMA____UH_SPLIT_DATA// endpoint 12 DMA TX buffer address
-
[0:31]UEP12_TX_DMA___UH_SPLIT_DATA (def=0x0) // endpoint 12 DMA buffer address
0x4002348CUEP13_TX_DMA// endpoint 13 DMA TX buffer address
-
[0:31]UEP13_TX_DMA (def=0x0) // endpoint 13 DMA buffer address
0x40023490UEP14_TX_DMA// endpoint 14 DMA TX buffer address
-
[0:31]UEP14_TX_DMA (def=0x0) // endpoint 14 DMA buffer address
0x40023494UEP15_TX_DMA// endpoint 15 DMA TX buffer address
-
[0:31]UEP15_TX_DMA (def=0x0) // endpoint 15 DMA buffer address
0x40023498UEP0_MAX_LEN// endpoint 0 max acceptable length
-
[0:10]UEP0_MAX_LEN (def=0x0) // endpoint 0 max acceptable length
0x4002349CUEP1_MAX_LEN// endpoint 1 max acceptable length
-
[0:10]UEP1_MAX_LEN (def=0x0) // endpoint 1 max acceptable length
0x400234A0UEP2_MAX_LEN__UH_RX_MAX_LEN// endpoint 2 max acceptable length
-
[0:10]UEP2_MAX_LEN__UH_RX_MAX_LEN (def=0x0) // endpoint 2 max acceptable length
0x400234A4UEP3_MAX_LEN// endpoint 3 MAX_LEN TX
-
[0:10]UEP3_MAX_LEN (def=0x0) // endpoint 3 max acceptable length
0x400234A8UEP4_MAX_LEN// endpoint 4 max acceptable length
-
[0:10]UEP4_MAX_LEN (def=0x0) // endpoint 4 max acceptable length
0x400234ACUEP5_MAX_LEN// endpoint 5 max acceptable length
-
[0:10]UEP5_MAX_LEN (def=0x0) // endpoint 5 max acceptable length
0x400234B0UEP6_MAX_LEN// endpoint 6 max acceptable length
-
[0:10]UEP6_MAX_LEN (def=0x0) // endpoint 6 max acceptable length
0x400234B4UEP7_MAX_LEN// endpoint 7 max acceptable length
-
[0:10]UEP7_MAX_LEN (def=0x0) // endpoint 7 max acceptable length
0x400234B8UEP8_MAX_LEN// endpoint 8 max acceptable length
-
[0:10]UEP8_MAX_LEN (def=0x0) // endpoint 8 max acceptable length
0x400234BCUEP9_MAX_LEN// endpoint 9 max acceptable length
-
[0:10]UEP9_MAX_LEN (def=0x0) // endpoint 9 max acceptable length
0x400234C0UEP10_MAX_LEN// endpoint 10 max acceptable length
-
[0:10]UEP10_MAX_LEN (def=0x0) // endpoint 10 max acceptable length
0x400234C4UEP11_MAX_LEN// endpoint 11 max acceptable length
-
[0:10]UEP11_MAX_LEN (def=0x0) // endpoint 11 max acceptable length
0x400234C8UEP12_MAX_LEN// endpoint 12 max acceptable length
-
[0:10]UEP12_MAX_LEN (def=0x0) // endpoint 12 max acceptable length
0x400234CCUEP13_MAX_LEN// endpoint 13 max acceptable length
-
[0:10]UEP13_MAX_LEN (def=0x0) // endpoint 13 max acceptable length
0x400234D0UEP14_MAX_LEN// endpoint 14 max acceptable length
-
[0:10]UEP14_MAX_LEN (def=0x0) // endpoint 14 max acceptable length
0x400234D4UEP15_MAX_LEN// endpoint 15 max acceptable length
-
[0:10]UEP15_MAX_LEN (def=0x0) // endpoint 15 max acceptable length
0x400234D8UEP0_T_LEN// endpoint 0 send the length
-
[0:6]UEP0_T_LEN (def=0x0) // endpoint 0 send the length
0x400234DAUEP0_TX_CTRL// endpoint 0 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 0 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 0 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 0 synchronous trigger bit automatic filp enables the control bit
0x400234DBUEP0_RX_CTRL// endpoint 0 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 0 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 0 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 0 synchronous trigger bit automatic filp enables the control bit
0x400234DCUEP1_T_LEN// endpoint 1 send the length
-
[0:10]UEP1_T_LEN (def=0x0) // endpoint 1 send the length
0x400234DEUEP1_TX_CTRL// endpoint 1 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 1 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 1 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 1 synchronous trigger bit automatic filp enables the control bit
0x400234DFUEP1_RX_CTRL// endpoint 1 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 1 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 1 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 1 synchronous trigger bit automatic filp enables the control bit
0x400234E0UEP2_T_LEN__UH_EP_PID// endpoint 2 send the length
-
[0:10]UEP2_T_LEN__MASK_UH_ENDP__MASK_UH_TOKEN (def=0x0) // endpoint 2 send the length
0x400234E2UEP2_TX_CTRL// endpoint 2 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 2 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 2 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 2 synchronous trigger bit automatic filp enables the control bit
0x400234E3UEP2_RX_CTRL__UH_RX_CTRL// endpoint 2 send control
-
[0:1]MASK_UEP_R_RES__MASK_UH_R_RES (def=0x0) // endpoint 2 control of the accept response to OUT transactions
-
[2]bUH_R_RES_NO (def=0x0) // bUH_R_RES_NO
-
[3:4]MASK_UEP_R_TOG__MASK_UH_R_TOG (def=0x0) // endpoint 2 synchronous trigger bit for the accept to prepare
-
[5]bUEP_R_TOG_AUTO__bUH_R_AUTO_TOG (def=0x0) // endpoint 2 synchronous trigger bit automatic filp enables the control bit
-
[6]RB_UH_R_DATA_NO (def=0x0) // bUH_R_DATA_NO
0x400234E4UEP3_T_LEN___UH_TX_LEN_H// endpoint 3 send the length
-
[0:10]UEP3_T_LEN___UH_TX_LEN_H (def=0x0) // endpoint 3 send the length
0x400234E6UEP3_TX_CTRL___UH_TX_CTRL// endpoint 3 send control
-
[0:1]MASK_UEP_T_RES_____MASK_UH_T_RES (def=0x0) // endpoint 3 control of the send response to IN transactions
-
[2]bUH_T_RES_NO (def=0x0) // bUH_T_RES_NO
-
[3:4]MASK_UEP_T_TOG____MASK_UH_T_TOG (def=0x0) // endpoint 3 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO____bUH_T_AUTO_TOG (def=0x0) // endpoint 3 synchronous trigger bit automatic filp enables the control bit
-
[6]bUH_T_DATA_NO (def=0x0) // bUH_T_DATA_NO
0x400234E7UEP3_RX_CTRL// endpoint 3 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 3 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 3 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 3 synchronous trigger bit automatic filp enables the control bit
0x400234E8UEP4_T_LEN// endpoint 4 send the length
-
[0:10]UEP4_T_LEN (def=0x0) // endpoint 0 send the length
0x400234EAUEP4_TX_CTRL// endpoint 4 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 4 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 4 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 4 synchronous trigger bit automatic filp enables the control bit
0x400234EBUEP4_RX_CTRL// endpoint 4 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 4 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 4 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 4 synchronous trigger bit automatic filp enables the control bit
0x400234ECUEP5_T_LEN// endpoint 5 send the length
-
[0:10]UEP5_T_LEN (def=0x0) // endpoint 5 send the length
0x400234EEUEP5_TX_CTRL// endpoint 5 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 5 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 5 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 5 synchronous trigger bit automatic filp enables the control bit
0x400234EFUEP5_RX_CTRL// endpoint 5 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 5 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 5 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 5 synchronous trigger bit automatic filp enables the control bit
0x400234F0UEP6_T_LEN// endpoint 6 send the length
-
[0:10]UEP6_T_LEN (def=0x0) // endpoint 6 send the length
0x400234F2UEP6_TX_CTRL// endpoint 6 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 6 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 6 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 6 synchronous trigger bit automatic filp enables the control bit
0x400234F3UEP6_RX_CTRL// endpoint 6 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 6 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 6 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 6 synchronous trigger bit automatic filp enables the control bit
0x400234F4UEP7_T_LEN// endpoint 7 send the length
-
[0:10]UEP7_T_LEN (def=0x0) // endpoint 7 send the length
0x400234F6UEP7_TX_CTRL// endpoint 7 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 7 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 7 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 7 synchronous trigger bit automatic filp enables the control bit
0x400234F7UEP7_RX_CTRL// endpoint 7 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 7 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 7 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 7 synchronous trigger bit automatic filp enables the control bit
0x400234F8UEP8_T_LEN// endpoint 8 send the length
-
[0:10]UEP8_T_LEN (def=0x0) // endpoint 8 send the length
0x400234FAUEP8_TX_CTRL// endpoint 8 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 8 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 8 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 8 synchronous trigger bit automatic filp enables the control bit
0x400234FBUEP8_RX_CTRL// endpoint 8 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 8 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 8 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 8 synchronous trigger bit automatic filp enables the control bit
0x400234FCUEP9_T_LEN// endpoint9 send the length
-
[0:10]UEP9_T_LEN (def=0x0) // endpoint 9 send the length
0x400234FEUEP9_TX_CTRL// endpoint 9 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 9 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 9 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 9 synchronous trigger bit automatic filp enables the control bit
0x400234FFUEP9_RX_CTRL// endpoint 9 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 9 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 9 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 9 synchronous trigger bit automatic filp enables the control bit
0x40023500UEP10_T_LEN// endpoint 10 send the length
-
[0:10]UEP10_T_LEN (def=0x0) // endpoint 10 send the length
0x40023502UEP10_TX_CTRL// endpoint 10 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 10 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 10 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 10 synchronous trigger bit automatic filp enables the control bit
0x40023503UEP10_RX_CTRL// endpoint 10 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 10 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 10 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 10 synchronous trigger bit automatic filp enables the control bit
0x40023504UEP11_T_LEN// endpoint 11 send the length
-
[0:10]UEP0_T_LEN (def=0x0) // endpoint 11 send the length
0x40023506UEP11_TX_CTRL// endpoint 11 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 11 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 11 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 11 synchronous trigger bit automatic filp enables the control bit
0x40023507UEP11_RX_CTRL// endpoint 11 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 11 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 11 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 11 synchronous trigger bit automatic filp enables the control bit
0x40023508UEP12_T_LEN// endpoint 12 send the length
-
[0:10]UEP0_T_LEN (def=0x0) // endpoint 12 send the length
0x4002350AUEP12_TX_CTRL// endpoint 12 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 12 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 12 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 12 synchronous trigger bit automatic filp enables the control bit
0x4002350BUEP12_RX_CTRL// endpoint 12 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 12 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 12 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 12 synchronous trigger bit automatic filp enables the control bit
0x4002350CUEP13_T_LEN// endpoint 13 send the length
-
[0:10]UEP13_T_LEN (def=0x0) // endpoint 13 send the length
0x4002350EUEP13_TX_CTRL// endpoint 13 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 13 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 13 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 13 synchronous trigger bit automatic filp enables the control bit
0x4002350FUEP13_RX_CTRL// endpoint 13 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 13 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 13 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 13 synchronous trigger bit automatic filp enables the control bit
0x40023510UEP14_T_LEN// endpoint 14 send the length
-
[0:10]UEP14_T_LEN (def=0x0) // endpoint 14 send the length
0x40023512UEP14_TX_CTRL// endpoint 14 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 14 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 14 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 14 synchronous trigger bit automatic filp enables the control bit
0x40023513UEP14_RX_CTRL// endpoint 14 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 14 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 14 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 14 synchronous trigger bit automatic filp enables the control bit
0x40023514UEP15_T_LEN// endpoint 15 send the length
-
[0:10]UEP0_T_LEN (def=0x0) // endpoint 15 send the length
0x40023516UEP15_TX_CTRL// endpoint 15 send control
-
[0:1]MASK_UEP_T_RES (def=0x0) // endpoint 15 control of the send response to IN transactions
-
[3:4]MASK_UEP_T_TOG (def=0x0) // endpoint 15 synchronous trigger bit for the sender to prepare
-
[5]RB_UEP_T_TOG_AUTO (def=0x0) // endpoint 15 synchronous trigger bit automatic filp enables the control bit
0x40023517UEP15_RX_CTRL// endpoint 15 send control
-
[0:1]MASK_UEP_R_RES (def=0x0) // endpoint 15 control of the accept response to OUT transactions
-
[3:4]MASK_UEP_R_TOG (def=0x0) // endpoint 15 synchronous trigger bit for the accept to prepare
-
[5]RB_UEP_R_TOG_AUTO (def=0x0) // endpoint 15 synchronous trigger bit automatic filp enables the control bit
- [84] USBHSWakeup // USBHSWakeup
- [85] USBHS // USBHS
0x40023000CRC// CRC calculation unit
0x40023000DATAR// Data register
-
[0:31]DR (def=0xFFFFFFFF) // Data Register
0x40023004IDATAR// Independent Data register
-
[0:7]IDR (def=0x0) // Independent Data register
0x40023008CTLR// Control register
-
[0]RST (def=0x0) // Reset bit
0x40022000FLASH// FLASH
0x40022004KEYR// Flash key register
-
[0:31]KEYR (def=0x0) // FPEC key
0x40022008OBKEYR// Flash option key register
-
[0:31]OPTKEY (def=0x0) // Option byte key
0x4002200CSTATR// Status register
-
[7]EHMODS (def=0x0) // Enhance mode start
-
[5]EOP (def=0x0) // End of operation
-
[4]WRPRTERR (def=0x0) // Write protection error
-
[1]WRBSY (def=0x0) // Quick page programming
-
[0]BSY (def=0x0) // Busy
0x40022010CTLR// Control register
-
[0]PG (def=0x0) // Programming
-
[1]PER (def=0x0) // Page Erase
-
[2]MER (def=0x0) // Mass Erase
-
[4]OBPG (def=0x0) // Option byte programming
-
[5]OBER (def=0x0) // Option byte erase
-
[6]STRT (def=0x0) // Start
-
[7]LOCK (def=0x1) // Lock
-
[9]OBWRE (def=0x0) // Option bytes write enable
-
[10]ERRIE (def=0x0) // Error interrupt enable
-
[12]EOPIE (def=0x0) // End of operation interrupt enable
-
[15]FLOCK (def=0x0) // Fast programmable lock
-
[16]FTPG (def=0x0) // Fast programming
-
[17]FTER (def=0x0) // Fast erase
-
[18]BER32 (def=0x0) // Block Erase 32K
-
[21]PGSTRT (def=0x0) // Page Programming Start
-
[22]RSENACT (def=0x0) // Reset Flash Enhance read mode
-
[24]EHMOD (def=0x0) // Flash Enhance read mode
-
[25]SCKMODE (def=0x0) // Flash SCK mode
0x40022014ADDR// Flash address register
-
[0:31]FAR (def=0x0) // Flash Address
0x4002201COBR// Option byte register
-
[0]OBERR (def=0x0) // Option byte error
-
[1]RDPRT (def=0x0) // Read protection
-
[2]IWDGSW (def=0x1) // IWDG_SW
-
[3]STOPRST (def=0x1) // STOP_RST
-
[4]STANDYRST (def=0x1) // STANDY_RST
-
[8:9]SRAM_CODE_MODE (def=0x3) // SRAM_CODE_MODE
0x40022020WPR// Write protection register
-
[0:31]WRP (def=0xFFFFFFFF) // Write protect
0x40022024MODEKEYR// Mode select register
-
[0:31]MODEKEYR (def=0x0) // Mode select
0x4002202CHSE_CAL_CTRL// External crystal oscillator calibration control register
-
[24:25]HSEITRIM (def=0x1) // HSE initiation current adjustment bit
-
[27]HSEFAULT (def=0x1) // HSE Failure Detection Disable Control Bit
-
[28:30]HSEC (def=0x0) // HSE Built-in Matching Capacitor Adjustment Bit
0x40022036LSI32K_TUNE// Internal Low Speed Crystal Calibration Adjustment Register
-
[0:4]LTUNE (def=0x11) // LSI32K coarse configuration bits
-
[5:12]HTUNE (def=0x80) // LSI32K fine-tunes the configuration bits
0x40022049LSI32K_CAL_CFG// Internal low-speed crystal calibration configuration register
-
[0:3]CNTVLU (def=0x1) // LSI32K calibrated sampling duration configuration bit
-
[4]HALTMD (def=0x0) // LSI32K Calibration Count Pause Duration Configuration Bit
-
[5]WKUPEN (def=0x0) // LSI32K Wake-Up Interrupt Enable
-
[6]LPEN (def=0x0) // Calibrate enable bit in low-power mode
0x4002204CLSI32K_CAL_STATR// Internal low-speed crystal calibration status register
-
[0:13]CNT (def=0x0) // For several CK32K cycles, the count value is based on the system frequency
-
[14]CNTOV (def=0x0) // LSI32K Sample Counter Overflow Flag
-
[15]IFEND (def=0x0) // LSI32K Calibration Count End Interrupt Flag
0x4002204ELSI32K_CAL_OV_CNT// Internal low-speed crystal calibration times counter
-
[0:7]OVCNT (def=0x0) // The number of LSI32K sample counter overflows
0x4002204FLSI32K_CAL_CTRL// Internal low-speed crystal calibration control register
-
[0]CALINTEN (def=0x0) // LSI32K Calibration Interrupt Enable
-
[1]CALEN (def=0x0) // LSI32K Calibration Enable
-
[7]HALT (def=0x1) // LSI32K Calibrated Count Status Bit
- [20] FLASH // Flash global interrupt
0x50000000USB_OTG_FS// USB FS OTG register
0x50000000R8_USB_CTRL// USB base control
-
[0]RB_UC_DMA_EN (def=0x0) // DMA enable and DMA interrupt enable for USB
-
[1]RB_UC_CLR_ALL (def=0x0) // force clear FIFO and count of USB
-
[2]RB_UC_RST_SIE (def=0x0) // force reset USB SIE, need software clear
-
[3]RB_UC_INT_BUSY (def=0x0) // enable automatic responding busy for device mode or automatic pause for host mode during interrupt
-
[4:5]MASK_UC_SYS_CTRL_RB_UC_DEV_PU_EN (def=0x0) // USB device enable and internal pullup resistance enable
-
[6]RB_UC_LOW_SPEED (def=0x0) // enable USB low speed: 0=12Mbps, 1=1.5Mbps
-
[7]RB_UC_HOST_MODE (def=0x0) // enable USB host mode: 0=device mode, 1=host mode
0x50000001UDEV_CTRL__UHOST_CTRL// USB device/host physical prot control
-
[0]RB_UH_PORT_EN__RB_UD_PORT_EN (def=0x0) // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
-
[1]RB_UH_BUS_RESET__RB_UD_GP_BIT (def=0x0) // force clear FIFO and count of USB
-
[2]RB_UH_LOW_SPEED__RB_UD_LOW_SPEED (def=0x0) // enable USB port low speed: 0=full speed, 1=low speed
-
[4]RB_UH_DM_PIN__RB_UD_DM_PIN (def=0x0) // ReadOnly: indicate current UDM pin level
-
[5]RB_UH_DP_PIN__RB_UD_DP_PIN (def=0x0) // USB device enable and internal pullup resistance enable
-
[7]RB_UH_PD_DIS__RB_UD_PD_DIS (def=0x0) // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
0x50000002R8_USB_INT_EN// USB interrupt enable
-
[0]RB_UIE_BUS_RST__RB_UIE_DETECT (def=0x0) // enable interrupt for USB bus reset event for USB device mode
-
[1]RB_UIE_TRANSFER (def=0x0) // enable interrupt for USB transfer completion
-
[2]RB_UIE_SUSPEND (def=0x0) // enable interrupt for USB suspend or resume event
-
[3]RB_UIE_HST_SOF (def=0x0) // enable interrupt for host SOF timer action for USB host mode
-
[4]RB_UIE_FIFO_OV (def=0x0) // enable interrupt for FIFO overflow
-
[6]RB_UIE_DEV_NAK (def=0x0) // enable interrupt for NAK responded for USB device mode
-
[7]RB_UIE_DEV_SOF (def=0x0) // enable interrupt for SOF received for USB device mode
0x50000003R8_USB_DEV_AD// USB device address
-
[0:6]MASK_USB_ADDR (def=0x0) // bit mask for USB device address
-
[7]RB_UDA_GP_BIT (def=0x0) // general purpose bit
0x50000005R8_USB_MIS_ST// USB miscellaneous status
-
[0]RB_UMS_DEV_ATTACH (def=0x0) // RO, indicate device attached status on USB host
-
[1]RB_UMS_DM_LEVEL (def=0x0) // RO, indicate UDM level saved at device attached to USB host
-
[2]RB_UMS_SUSPEND (def=0x0) // RO, indicate USB suspend status
-
[3]RB_UMS_BUS_RESET (def=0x0) // RO, indicate USB bus reset status
-
[4]RB_UMS_R_FIFO_RDY (def=0x0) // RO, indicate USB receiving FIFO ready status (not empty)
-
[5]RB_UMS_SIE_FREE (def=0x0) // RO, indicate USB SIE free status
-
[6]RB_UMS_SOF_ACT (def=0x0) // RO, indicate host SOF timer action status for USB host
-
[7]RB_UMS_SOF_PRES (def=0x0) // RO, indicate host SOF timer presage status
0x50000006R8_USB_INT_FG// USB interrupt flag
-
[0]RB_UIF_BUS_RST__RB_UIF_DETECT (def=0x0) // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;de
-
[1]RB_UIF_TRANSFER (def=0x0) // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
-
[2]RB_UIF_SUSPEND (def=0x0) // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
-
[3]RB_UIF_HST_SOF (def=0x0) // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
-
[4]RB_UIF_FIFO_OV (def=0x0) // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
-
[5]RB_U_SIE_FREE (def=0x0) // RO, indicate USB SIE free status
-
[6]RB_U_TOG_OK (def=0x0) // RO, indicate current USB transfer toggle is OK
-
[7]RB_U_IS_NAK (def=0x0) // RO, indicate current USB transfer is NAK received
0x50000007R8_USB_INT_ST// USB interrupt status
-
[0:3]MASK_UIS_H_RES__MASK_UIS_ENDP (def=0x0) // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out f
-
[4:5]MASK_UIS_TOKEN (def=0x0) // RO, bit mask of current token PID code received for USB device mode
-
[6]RB_UIS_TOG_OK (def=0x0) // RO, indicate current USB transfer toggle is OK
-
[7]RB_UIS_IS_NAK (def=0x0) // RO, indicate current USB transfer is NAK received for USB device mode
0x50000008R16_USB_RX_LEN// USB receiving length
0x5000000CR8_UEP4_1_MOD// endpoint 4/1 mode
-
[2]RB_UEP4_TX_EN (def=0x0) // enable USB endpoint 4 transmittal (IN)
-
[3]RB_UEP4_RX_EN (def=0x0) // enable USB endpoint 4 receiving (OUT)
-
[4]RB_UEP1_BUF_MOD (def=0x0) // buffer mode of USB endpoint 1
-
[6]RB_UEP1_TX_EN (def=0x0) // enable USB endpoint 1 transmittal (IN)
-
[7]RB_UEP1_RX_EN (def=0x0) // enable USB endpoint 1 receiving (OUT)
0x5000000DR8_UEP2_3_MOD__R8_UH_EP_MOD// endpoint 2/3 mode;host endpoint mode
-
[0]RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD (def=0x0) // buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint
-
[2]RB_UEP2_TX_EN (def=0x0) // enable USB endpoint 2 transmittal (IN)
-
[3]RB_UEP2_RX_EN__RB_UH_EP_RX_EN (def=0x0) // enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving
-
[4]RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD (def=0x0) // buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint
-
[6]RB_UEP3_TX_EN__RB_UH_EP_TX_EN (def=0x0) // enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal
-
[7]RB_UEP3_RX_EN (def=0x0) // enable USB endpoint 3 receiving (OUT)
0x5000000ER8_UEP5_6_MOD// endpoint 5/6 mode
-
[0]RB_UEP5_BUF_MOD (def=0x0) // buffer mode of USB endpoint 5
-
[2]RB_UEP5_TX_EN (def=0x0) // enable USB endpoint 5 transmittal (IN)
-
[3]RB_UEP5_RX_EN (def=0x0) // enable USB endpoint 5 receiving (OUT)
-
[4]RB_UEP6_BUF_MOD (def=0x0) // buffer mode of USB endpoint 6
-
[6]RB_UEP6_TX_EN (def=0x0) // enable USB endpoint 6 transmittal (IN)
-
[7]RB_UEP3_RX_EN (def=0x0) // enable USB endpoint 6 receiving (OUT)
0x5000000FR8_UEP7_MOD// endpoint 7 mode
-
[0]RB_UEP7_BUF_MOD (def=0x0) // buffer mode of USB endpoint 7
-
[2]RB_UEP7_TX_EN (def=0x0) // enable USB endpoint 7 transmittal (IN)
-
[3]RB_UEP7_RX_EN (def=0x0) // enable USB endpoint 7 receiving (OUT)
0x50000010R32_UEP0_DMA// endpoint 0 DMA buffer address
0x50000014R32_UEP1_DMA// endpoint 1 DMA buffer address
0x50000018R32_UEP2_DMA__R32_UH_RX_DMA// endpoint 2 DMA buffer address;host rx endpoint buffer high address
0x5000001CR32_UEP3_DMA__R32_UH_TX_DMA// endpoint 3 DMA buffer address;host tx endpoint buffer high address
0x50000020R32_UEP4_DMA// endpoint 4 DMA buffer address
0x50000024R32_UEP5_DMA// endpoint 5 DMA buffer address
0x50000028R32_UEP6_DMA// endpoint 6 DMA buffer address
0x5000002CR32_UEP7_DMA// endpoint 7 DMA buffer address
0x50000030R8_UEP0_T_LEN// endpoint 0 transmittal length
0x50000032R8_UEP0_T_CTRL// endpoint 0 control
-
[0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
-
[2]RB_UEP_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x50000033R8_UEP0_R_CTRL// endpoint 0 control
-
[0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
-
[2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x50000034R8_UEP1_T_LEN// endpoint 1 transmittal length
0x50000036R8_UEP1_T_CTRL___USBHD_UH_SETUP// endpoint 1 control
-
[0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
-
[2]RB_UEP_T_TOG_ (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
-
[6]RB_UH_SOF_EN (def=0x0) // USB host automatic SOF enable
-
[7]RB_UH_PRE_PID_EN (def=0x0) // USB host PRE PID enable for low speed device via hub
0x50000037R8_UEP1_R_CTRL// endpoint 1 control
-
[0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
-
[2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x50000038R8_UEP2_T_LEN__USBHD_UH_EP_PID// endpoint 2 transmittal length
-
[0:3]RB_UH_ENDP_MASK (def=0x0) // bit mask of endpoint number for USB host transfer
-
[4:7]RB_UH_TOKEN_MASK (def=0x0) // bit mask of token PID for USB host transfer
0x5000003AR8_UEP2_T_CTRL// endpoint 2 control
-
[0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
-
[2]RB_UEP_T_TOG_ (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x5000003BR8_UEP2_R_CTRL__USBHD_UH_RX_CTRL// endpoint 2 control
-
[0:1]MASK_UEP_R_RES___RB_UH_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
-
[2]RB_UEP_R_TOG___RB_UH_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG___RB_UH_R_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x5000003CR8_UEP3_T_LEN__USBHD_UH_TX_LEN// endpoint 3 transmittal length
0x5000003ER8_UEP3_T_CTRL__USBHD_UH_TX_CTRL// endpoint 3 control
-
[0:1]MASK_UEP_T_RES___RB_UH_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
-
[2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x5000003FR8_UEP3_R_CTRL_// endpoint 3 control
-
[0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
-
[2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x50000040R8_UEP4_T_LEN// endpoint 4 transmittal length
0x50000042R8_UEP4_T_CTRL// endpoint 4 control
-
[0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
-
[2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x50000043R8_UEP4_R_CTRL_// endpoint 4 control
-
[0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
-
[2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x50000044R8_UEP5_T_LEN// endpoint 5 transmittal length
0x50000046R8_UEP5_T_CTRL// endpoint 5 control
-
[0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
-
[2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x50000047R8_UEP5_R_CTRL_// endpoint 5 control
-
[0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
-
[2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x50000048R8_UEP6_T_LEN// endpoint 6 transmittal length
0x5000004AR8_UEP6_T_CTRL// endpoint 6 control
-
[0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
-
[2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x5000004BR8_UEP6_R_CTRL_// endpoint 6 control
-
[0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
-
[2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x5000004CR8_UEP7_T_LEN// endpoint 7 transmittal length
0x5000004ER8_UEP7_T_CTRL// endpoint 7 control
-
[0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
-
[2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x5000004FR8_UEP7_R_CTRL_// endpoint 7 control
-
[0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
-
[2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
-
[3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
0x50000054USB_OTG_CR// usb otg control
-
[0]USB_OTG_CR_DISCHARGEVBUS (def=0x0) // usb otg control
-
[1]USB_OTG_CR_CHARGEVBUS (def=0x0) // usb otg control
-
[2]USB_OTG_CR_IDPU (def=0x0) // usb otg control
-
[3]USB_OTG_CR_OTG_EN (def=0x0) // usb otg control
-
[4]USB_OTG_CR_VBUS (def=0x0) // usb otg control
-
[5]USB_OTG_CR_SESS (def=0x0) // usb otg control
0x50000058USB_OTG_SR// usb otg status
-
[0]USB_OTG_SR_VBUS_VLD (def=0x0) // usb otg status
-
[1]USB_OTG_SR_SESS_VLD (def=0x0) // usb otg status
-
[2]USB_OTG_SR_SESS_END (def=0x0) // usb otg status
-
[3]USB_OTG_SR_ID_DIG (def=0x0) // usb otg status
- [84] USBHSWakeup // USBHSWakeup
- [85] USBHS // USBHS
- [83] OTG_FS // OTG_FS
0xE000E000PFIC// Programmable Fast Interrupt Controller
0xE000E000ISR1// Interrupt Status Register
-
[2:3]INTENSTA2_3 (def=0x3) // Interrupt ID Status
-
[12:31]INTENSTA12_31 (def=0x0) // Interrupt ID Status
0xE000E004ISR2// Interrupt Status Register
-
[0:31]INTENSTA (def=0x0) // Interrupt ID Status
0xE000E008ISR3// Interrupt Status Register
-
[0:31]INTENSTA (def=0x0) // Interrupt ID Status
0xE000E00CISR4// Interrupt Status Register
-
[0:7]INTENSTA (def=0x0) // Interrupt ID Status
0xE000E020IPR1// Interrupt Pending Register
-
[2:3]PENDSTA2_3 (def=0x0) // PENDSTA
-
[12:31]PENDSTA12_31 (def=0x0) // PENDSTA
0xE000E024IPR2// Interrupt Pending Register
-
[0:31]PENDSTA (def=0x0) // PENDSTA
0xE000E028IPR3// Interrupt Pending Register
-
[0:31]PENDSTA (def=0x0) // PENDSTA
0xE000E02CIPR4// Interrupt Pending Register
-
[0:7]PENDSTA (def=0x0) // PENDSTA
0xE000E040ITHRESDR// Interrupt Priority Register
-
[0:7]THRESHOLD (def=0x0) // THRESHOLD
0xE000E048CFGR// Interrupt Config Register
-
[7]RESETSYS (def=0x0) // RESETSYS
-
[16:31]KEYCODE (def=0x0) // KEYCODE
0xE000E04CGISR// Interrupt Global Register
-
[0:7]NESTSTA (def=0x0) // NESTSTA
-
[8]GACTSTA (def=0x0) // GACTSTA
-
[9]GPENDSTA (def=0x0) // GPENDSTA
0xE000E050VTFIDR// ID Config Register
-
[0:7]VTFID0 (def=0x0) // VTFID0
-
[8:15]VTFID1 (def=0x0) // VTFID1
-
[16:23]VTFID2 (def=0x0) // VTFID2
-
[24:31]VTFID3 (def=0x0) // VTFID3
0xE000E060VTFADDRR0// Interrupt 0 address Register
-
[0]VTF0EN (def=0x0) // VTF0EN
-
[1:31] ADDR0 (def=0x0) // ADDR0
0xE000E064VTFADDRR1// Interrupt 1 address Register
-
[0]VTF1EN (def=0x0) // VTF1EN
-
[1:31] ADDR1 (def=0x0) // ADDR1
0xE000E068VTFADDRR2// Interrupt 2 address Register
-
[0]VTF2EN (def=0x0) // VTF2EN
-
[1:31] ADDR2 (def=0x0) // ADDR2
0xE000E06CVTFADDRR3// Interrupt 3 address Register
-
[0]VTF3EN (def=0x0) // VTF3EN
-
[1:31] ADDR3 (def=0x0) // ADDR3
0xE000E100IENR1// Interrupt Setting Register
-
[12:31]INTEN (def=0x0) // INTEN
0xE000E104IENR2// Interrupt Setting Register
-
[0:31]INTEN (def=0x0) // INTEN
0xE000E108IENR3// Interrupt Setting Register
-
[0:31]INTEN (def=0x0) // INTEN
0xE000E10CIENR4// Interrupt Setting Register
-
[0:7]INTEN (def=0x0) // INTEN
0xE000E180IRER1// Interrupt Clear Register
-
[12:31]INTRSET (def=0x0) // INTRSET
0xE000E184IRER2// Interrupt Clear Register
-
[0:31]INTRSET (def=0x0) // INTRSET
0xE000E188IRER3// Interrupt Clear Register
-
[0:31]INTRSET (def=0x0) // INTRSET
0xE000E18CIRER4// Interrupt Clear Register
-
[0:7]INTRSET (def=0x0) // INTRSET
0xE000E200IPSR1// Interrupt Pending Register
-
[2:3]PENDSET2_3 (def=0x0) // PENDSET
-
[12:31]PENDSET12_31 (def=0x0) // PENDSET
0xE000E204IPSR2// Interrupt Pending Register
-
[0:31]PENDSET (def=0x0) // PENDSET
0xE000E208IPSR3// Interrupt Pending Register
-
[0:31]PENDSET (def=0x0) // PENDSET
0xE000E20CIPSR4// Interrupt Pending Register
-
[0:7]PENDSET (def=0x0) // PENDSET
0xE000E280IPRR1// Interrupt Pending Clear Register
-
[2:3]PENDRESET2_3 (def=0x0) // PENDRESET
-
[12:31]PENDRESET12_31 (def=0x0) // PENDRESET
0xE000E284IPRR2// Interrupt Pending Clear Register
-
[0:31]PENDRESET (def=0x0) // PENDRESET
0xE000E288IPRR3// Interrupt Pending Clear Register
-
[0:31]PENDRESET (def=0x0) // PENDRESET
0xE000E28CIPRR4// Interrupt Pending Clear Register
-
[0:7]PENDRESET (def=0x0) // PENDRESET
0xE000E300IACTR1// Interrupt ACTIVE Register
-
[2:3]IACTS2_3 (def=0x0) // IACTS
-
[12:31]IACTS12_31 (def=0x0) // IACTS
0xE000E304IACTR2// Interrupt ACTIVE Register
-
[0:31]IACTS (def=0x0) // IACTS
0xE000E308IACTR3// Interrupt ACTIVE Register
-
[0:31]IACTS (def=0x0) // IACTS
0xE000E30CIACTR4// Interrupt ACTIVE Register
-
[0:7]IACTS (def=0x0) // IACTS
0xE000E400IPRIOR0// Interrupt Priority Register
0xE000E401IPRIOR1// Interrupt Priority Register
0xE000E402IPRIOR2// Interrupt Priority Register
0xE000E403IPRIOR3// Interrupt Priority Register
0xE000E404IPRIOR4// Interrupt Priority Register
0xE000E405IPRIOR5// Interrupt Priority Register
0xE000E406IPRIOR6// Interrupt Priority Register
0xE000E407IPRIOR7// Interrupt Priority Register
0xE000E408IPRIOR8// Interrupt Priority Register
0xE000E409IPRIOR9// Interrupt Priority Register
0xE000E40AIPRIOR10// Interrupt Priority Register
0xE000E40BIPRIOR11// Interrupt Priority Register
0xE000E40CIPRIOR12// Interrupt Priority Register
0xE000E40DIPRIOR13// Interrupt Priority Register
0xE000E40EIPRIOR14// Interrupt Priority Register
0xE000E40FIPRIOR15// Interrupt Priority Register
0xE000E410IPRIOR16// Interrupt Priority Register
0xE000E411IPRIOR17// Interrupt Priority Register
0xE000E412IPRIOR18// Interrupt Priority Register
0xE000E413IPRIOR19// Interrupt Priority Register
0xE000E414IPRIOR20// Interrupt Priority Register
0xE000E415IPRIOR21// Interrupt Priority Register
0xE000E416IPRIOR22// Interrupt Priority Register
0xE000E417IPRIOR23// Interrupt Priority Register
0xE000E418IPRIOR24// Interrupt Priority Register
0xE000E419IPRIOR25// Interrupt Priority Register
0xE000E41AIPRIOR26// Interrupt Priority Register
0xE000E41BIPRIOR27// Interrupt Priority Register
0xE000E41CIPRIOR28// Interrupt Priority Register
0xE000E41DIPRIOR29// Interrupt Priority Register
0xE000E41EIPRIOR30// Interrupt Priority Register
0xE000E41FIPRIOR31// Interrupt Priority Register
0xE000E420IPRIOR32// Interrupt Priority Register
0xE000E421IPRIOR33// Interrupt Priority Register
0xE000E422IPRIOR34// Interrupt Priority Register
0xE000E423IPRIOR35// Interrupt Priority Register
0xE000E424IPRIOR36// Interrupt Priority Register
0xE000E425IPRIOR37// Interrupt Priority Register
0xE000E426IPRIOR38// Interrupt Priority Register
0xE000E427IPRIOR39// Interrupt Priority Register
0xE000E428IPRIOR40// Interrupt Priority Register
0xE000E429IPRIOR41// Interrupt Priority Register
0xE000E42AIPRIOR42// Interrupt Priority Register
0xE000E42BIPRIOR43// Interrupt Priority Register
0xE000E42CIPRIOR44// Interrupt Priority Register
0xE000E42DIPRIOR45// Interrupt Priority Register
0xE000E42EIPRIOR46// Interrupt Priority Register
0xE000E42FIPRIOR47// Interrupt Priority Register
0xE000E430IPRIOR48// Interrupt Priority Register
0xE000E431IPRIOR49// Interrupt Priority Register
0xE000E432IPRIOR50// Interrupt Priority Register
0xE000E433IPRIOR51// Interrupt Priority Register
0xE000E434IPRIOR52// Interrupt Priority Register
0xE000E435IPRIOR53// Interrupt Priority Register
0xE000E436IPRIOR54// Interrupt Priority Register
0xE000E437IPRIOR55// Interrupt Priority Register
0xE000E438IPRIOR56// Interrupt Priority Register
0xE000E439IPRIOR57// Interrupt Priority Register
0xE000E43AIPRIOR58// Interrupt Priority Register
0xE000E43BIPRIOR59// Interrupt Priority Register
0xE000E43CIPRIOR60// Interrupt Priority Register
0xE000E43DIPRIOR61// Interrupt Priority Register
0xE000E43EIPRIOR62// Interrupt Priority Register
0xE000E43FIPRIOR63// Interrupt Priority Register
0xE000E440IPRIOR64// Interrupt Priority Register
0xE000E441IPRIOR65// Interrupt Priority Register
0xE000E442IPRIOR66// Interrupt Priority Register
0xE000E443IPRIOR67// Interrupt Priority Register
0xE000E444IPRIOR68// Interrupt Priority Register
0xE000E445IPRIOR69// Interrupt Priority Register
0xE000E446IPRIOR70// Interrupt Priority Register
0xE000E447IPRIOR71// Interrupt Priority Register
0xE000E448IPRIOR72// Interrupt Priority Register
0xE000E449IPRIOR73// Interrupt Priority Register
0xE000E44AIPRIOR74// Interrupt Priority Register
0xE000E44BIPRIOR75// Interrupt Priority Register
0xE000E44CIPRIOR76// Interrupt Priority Register
0xE000E44DIPRIOR77// Interrupt Priority Register
0xE000E44EIPRIOR78// Interrupt Priority Register
0xE000E44FIPRIOR79// Interrupt Priority Register
0xE000E450IPRIOR80// Interrupt Priority Register
0xE000E451IPRIOR81// Interrupt Priority Register
0xE000E452IPRIOR82// Interrupt Priority Register
0xE000E453IPRIOR83// Interrupt Priority Register
0xE000E454IPRIOR84// Interrupt Priority Register
0xE000E455IPRIOR85// Interrupt Priority Register
0xE000E456IPRIOR86// Interrupt Priority Register
0xE000E457IPRIOR87// Interrupt Priority Register
0xE000E458IPRIOR88// Interrupt Priority Register
0xE000E459IPRIOR89// Interrupt Priority Register
0xE000E45AIPRIOR90// Interrupt Priority Register
0xE000E45BIPRIOR91// Interrupt Priority Register
0xE000E45CIPRIOR92// Interrupt Priority Register
0xE000E45DIPRIOR93// Interrupt Priority Register
0xE000E45EIPRIOR94// Interrupt Priority Register
0xE000E45FIPRIOR95// Interrupt Priority Register
0xE000E460IPRIOR96// Interrupt Priority Register
0xE000E461IPRIOR97// Interrupt Priority Register
0xE000E462IPRIOR98// Interrupt Priority Register
0xE000E463IPRIOR99// Interrupt Priority Register
0xE000E464IPRIOR100// Interrupt Priority Register
0xE000E465IPRIOR101// Interrupt Priority Register
0xE000E466IPRIOR102// Interrupt Priority Register
0xE000E467IPRIOR103// Interrupt Priority Register
0xE000E468IPRIOR104// Interrupt Priority Register
0xE000E469IPRIOR105// Interrupt Priority Register
0xE000E46AIPRIOR106// Interrupt Priority Register
0xE000E46BIPRIOR107// Interrupt Priority Register
0xE000E46CIPRIOR108// Interrupt Priority Register
0xE000E46DIPRIOR109// Interrupt Priority Register
0xE000E46EIPRIOR110// Interrupt Priority Register
0xE000E46FIPRIOR111// Interrupt Priority Register
0xE000E470IPRIOR112// Interrupt Priority Register
0xE000E471IPRIOR113// Interrupt Priority Register
0xE000E472IPRIOR114// Interrupt Priority Register
0xE000E473IPRIOR115// Interrupt Priority Register
0xE000E474IPRIOR116// Interrupt Priority Register
0xE000E475IPRIOR117// Interrupt Priority Register
0xE000E476IPRIOR118// Interrupt Priority Register
0xE000E477IPRIOR119// Interrupt Priority Register
0xE000E478IPRIOR120// Interrupt Priority Register
0xE000E479IPRIOR121// Interrupt Priority Register
0xE000E47AIPRIOR122// Interrupt Priority Register
0xE000E47BIPRIOR123// Interrupt Priority Register
0xE000E47CIPRIOR124// Interrupt Priority Register
0xE000E47DIPRIOR125// Interrupt Priority Register
0xE000E47EIPRIOR126// Interrupt Priority Register
0xE000E47FIPRIOR127// Interrupt Priority Register
0xE000E480IPRIOR128// Interrupt Priority Register
0xE000E481IPRIOR129// Interrupt Priority Register
0xE000E482IPRIOR130// Interrupt Priority Register
0xE000E483IPRIOR131// Interrupt Priority Register
0xE000E484IPRIOR132// Interrupt Priority Register
0xE000E485IPRIOR133// Interrupt Priority Register
0xE000E486IPRIOR134// Interrupt Priority Register
0xE000E487IPRIOR135// Interrupt Priority Register
0xE000E488IPRIOR136// Interrupt Priority Register
0xE000E489IPRIOR137// Interrupt Priority Register
0xE000E48AIPRIOR138// Interrupt Priority Register
0xE000E48BIPRIOR139// Interrupt Priority Register
0xE000E48CIPRIOR140// Interrupt Priority Register
0xE000E48DIPRIOR141// Interrupt Priority Register
0xE000E48EIPRIOR142// Interrupt Priority Register
0xE000E48FIPRIOR143// Interrupt Priority Register
0xE000E490IPRIOR144// Interrupt Priority Register
0xE000E491IPRIOR145// Interrupt Priority Register
0xE000E492IPRIOR146// Interrupt Priority Register
0xE000E493IPRIOR147// Interrupt Priority Register
0xE000E494IPRIOR148// Interrupt Priority Register
0xE000E495IPRIOR149// Interrupt Priority Register
0xE000E496IPRIOR150// Interrupt Priority Register
0xE000E497IPRIOR151// Interrupt Priority Register
0xE000E498IPRIOR152// Interrupt Priority Register
0xE000E499IPRIOR153// Interrupt Priority Register
0xE000E49AIPRIOR154// Interrupt Priority Register
0xE000E49BIPRIOR155// Interrupt Priority Register
0xE000E49CIPRIOR156// Interrupt Priority Register
0xE000E49DIPRIOR157// Interrupt Priority Register
0xE000E49EIPRIOR158// Interrupt Priority Register
0xE000E49FIPRIOR159// Interrupt Priority Register
0xE000E4A0IPRIOR160// Interrupt Priority Register
0xE000E4A1IPRIOR161// Interrupt Priority Register
0xE000E4A2IPRIOR162// Interrupt Priority Register
0xE000E4A3IPRIOR163// Interrupt Priority Register
0xE000E4A4IPRIOR164// Interrupt Priority Register
0xE000E4A5IPRIOR165// Interrupt Priority Register
0xE000E4A6IPRIOR166// Interrupt Priority Register
0xE000E4A7IPRIOR167// Interrupt Priority Register
0xE000E4A8IPRIOR168// Interrupt Priority Register
0xE000E4A9IPRIOR169// Interrupt Priority Register
0xE000E4AAIPRIOR170// Interrupt Priority Register
0xE000E4ABIPRIOR171// Interrupt Priority Register
0xE000E4ACIPRIOR172// Interrupt Priority Register
0xE000E4ADIPRIOR173// Interrupt Priority Register
0xE000E4AEIPRIOR174// Interrupt Priority Register
0xE000E4AFIPRIOR175// Interrupt Priority Register
0xE000E4B0IPRIOR176// Interrupt Priority Register
0xE000E4B1IPRIOR177// Interrupt Priority Register
0xE000E4B2IPRIOR178// Interrupt Priority Register
0xE000E4B3IPRIOR179// Interrupt Priority Register
0xE000E4B4IPRIOR180// Interrupt Priority Register
0xE000E4B5IPRIOR181// Interrupt Priority Register
0xE000E4B6IPRIOR182// Interrupt Priority Register
0xE000E4B7IPRIOR183// Interrupt Priority Register
0xE000E4B8IPRIOR184// Interrupt Priority Register
0xE000E4B9IPRIOR185// Interrupt Priority Register
0xE000E4BAIPRIOR186// Interrupt Priority Register
0xE000E4BBIPRIOR187// Interrupt Priority Register
0xE000E4BCIPRIOR188// Interrupt Priority Register
0xE000E4BDIPRIOR189// Interrupt Priority Register
0xE000E4BEIPRIOR190// Interrupt Priority Register
0xE000E4BFIPRIOR191// Interrupt Priority Register
0xE000E4C0IPRIOR192// Interrupt Priority Register
0xE000E4C1IPRIOR193// Interrupt Priority Register
0xE000E4C2IPRIOR194// Interrupt Priority Register
0xE000E4C3IPRIOR195// Interrupt Priority Register
0xE000E4C4IPRIOR196// Interrupt Priority Register
0xE000E4C5IPRIOR197// Interrupt Priority Register
0xE000E4C6IPRIOR198// Interrupt Priority Register
0xE000E4C7IPRIOR199// Interrupt Priority Register
0xE000E4C8IPRIOR200// Interrupt Priority Register
0xE000E4C9IPRIOR201// Interrupt Priority Register
0xE000E4CAIPRIOR202// Interrupt Priority Register
0xE000E4CBIPRIOR203// Interrupt Priority Register
0xE000E4CCIPRIOR204// Interrupt Priority Register
0xE000E4CDIPRIOR205// Interrupt Priority Register
0xE000E4CEIPRIOR206// Interrupt Priority Register
0xE000E4CFIPRIOR207// Interrupt Priority Register
0xE000E4D0IPRIOR208// Interrupt Priority Register
0xE000E4D1IPRIOR209// Interrupt Priority Register
0xE000E4D2IPRIOR210// Interrupt Priority Register
0xE000E4D3IPRIOR211// Interrupt Priority Register
0xE000E4D4IPRIOR212// Interrupt Priority Register
0xE000E4D5IPRIOR213// Interrupt Priority Register
0xE000E4D6IPRIOR214// Interrupt Priority Register
0xE000E4D7IPRIOR215// Interrupt Priority Register
0xE000E4D8IPRIOR216// Interrupt Priority Register
0xE000E4D9IPRIOR217// Interrupt Priority Register
0xE000E4DAIPRIOR218// Interrupt Priority Register
0xE000E4DBIPRIOR219// Interrupt Priority Register
0xE000E4DCIPRIOR220// Interrupt Priority Register
0xE000E4DDIPRIOR221// Interrupt Priority Register
0xE000E4DEIPRIOR222// Interrupt Priority Register
0xE000E4DFIPRIOR223// Interrupt Priority Register
0xE000E4E0IPRIOR224// Interrupt Priority Register
0xE000E4E1IPRIOR225// Interrupt Priority Register
0xE000E4E2IPRIOR226// Interrupt Priority Register
0xE000E4E3IPRIOR227// Interrupt Priority Register
0xE000E4E4IPRIOR228// Interrupt Priority Register
0xE000E4E5IPRIOR229// Interrupt Priority Register
0xE000E4E6IPRIOR230// Interrupt Priority Register
0xE000E4E7IPRIOR231// Interrupt Priority Register
0xE000E4E8IPRIOR232// Interrupt Priority Register
0xE000E4E9IPRIOR233// Interrupt Priority Register
0xE000E4EAIPRIOR234// Interrupt Priority Register
0xE000E4EBIPRIOR235// Interrupt Priority Register
0xE000E4ECIPRIOR236// Interrupt Priority Register
0xE000E4EDIPRIOR237// Interrupt Priority Register
0xE000E4EEIPRIOR238// Interrupt Priority Register
0xE000E4EFIPRIOR239// Interrupt Priority Register
0xE000E4F0IPRIOR240// Interrupt Priority Register
0xE000E4F1IPRIOR241// Interrupt Priority Register
0xE000E4F2IPRIOR242// Interrupt Priority Register
0xE000E4F3IPRIOR243// Interrupt Priority Register
0xE000E4F4IPRIOR244// Interrupt Priority Register
0xE000E4F5IPRIOR245// Interrupt Priority Register
0xE000E4F6IPRIOR246// Interrupt Priority Register
0xE000E4F7IPRIOR247// Interrupt Priority Register
0xE000E4F8IPRIOR248// Interrupt Priority Register
0xE000E4F9IPRIOR249// Interrupt Priority Register
0xE000E4FAIPRIOR250// Interrupt Priority Register
0xE000E4FBIPRIOR251// Interrupt Priority Register
0xE000E4FCIPRIOR252// Interrupt Priority Register
0xE000E4FDIPRIOR253// Interrupt Priority Register
0xE000E4FEIPRIOR254// Interrupt Priority Register
0xE000E4FFIPRIOR255// Interrupt Priority Register
0xE000ED10SCTLR// System Control Register
-
[1]SLEEPONEXIT (def=0x0) // SLEEPONEXIT
-
[2]SLEEPDEEP (def=0x0) // SLEEPDEEP
-
[3]WFITOWFE (def=0x0) // WFITOWFE
-
[4]SEVONPEND (def=0x0) // SEVONPEND
-
[5]SETEVENT (def=0x0) // SETEVENT
-
[31]SYSRESET (def=0x0) // SYSRESET
0xE000F000STK_CTLR// System counter control register
-
[0]STE (def=0x0) // System counter enable
-
[1]STIE (def=0x0) // System counter interrupt enable
-
[2]STCLK (def=0x0) // System selects the clock source
-
[3]STRE (def=0x0) // System reload register
-
[4]MODE (def=0x0) // System Mode
-
[5]INIT (def=0x0) // System Initialization update
-
[31]SWIE (def=0x0) // System software triggered interrupts enable
0xE000F004STK_SR// System START
-
[0]CNTIF (def=0x0) // CNTIF
0xE000F008STK_CNTL// System counter low register
-
[0:31]CNTL (def=0x0) // CNTL
0xE000F00CSTK_CNTH// System counter high register
-
[0:31]CNTH (def=0x0) // CNTH
0xE000F010STK_CMPLR// System compare low register
-
[0:31]CMPL (def=0x0) // CMPL
0xE000F014STK_CMPHR// System compare high register
-
[0:31]CMPH (def=0x0) // CMPH