CH32H417

Search Reset

• 0x40021000RCC// Reset and clock control

  • 0x40021000CTLR// Clock control register

    • [0]HSION (def=0x1) // Internal High Speed clock enable
    • [1]HSIRDY (def=0x1) // Internal High Speed clock ready flag
    • [3:7]HSITRIM (def=0x10) // Internal High Speed clock trimming
    • [16]HSEON (def=0x0) // External High Speed clock enable
    • [17]HSERDY (def=0x0) // External High Speed clock ready flag
    • [18]HSEBYP (def=0x0) // External High Speed clock Bypass
    • [19]CSSON (def=0x0) // Clock Security System enable
    • [20]USBHS_PLLON (def=0x0) // USBHS PLL clock enable
    • [21]USBHS_PLLRDY (def=0x0) // USBHS PLL clock ready flag
    • [22]USBSS_PLLON (def=0x0) // USBSS PLL clock enable
    • [23]USBSS_PLLRDY (def=0x0) // USBSS PLL clock ready flag
    • [24]PLLON (def=0x0) // PLL clock enable
    • [25]PLLRDY (def=0x0) // PLL clock ready flag
    • [26]ETH_PLLON (def=0x0) // ETH PLL clock enable
    • [27]ETH_PLLRDY (def=0x0) // ETH PLL clock ready flag
    • [28]SERDES_PLLON (def=0x0) // SERDES PLL clock enable
    • [29]SERDES_PLLRDY (def=0x0) // SERDES PLL clock ready flag
    • [31]CSS_HSE_DIS (def=0x0) // Upon the occurrence of an HSE failure event with CSSON enabled
  • 0x40021004CFGR0// Clock configuration register (RCC_CFGR0)

    • [0:1]SW (def=0x0) // System clock Switch
    • [2:3]SWS (def=0x0) // System Clock Switch Status
    • [4:7]HPRE (def=0x0) // HB prescaler
    • [8:10]PPRE1 (def=0x0) // Timer prescaler (PB1)
    • [11:13]PPRE2 (def=0x0) // TIMER or ADC clock prescaler (PB2)
    • [14:15]ADCPRE (def=0x0) // ADC prescaler
    • [16]FPRE (def=0x0) // HCLK prescaler
    • [17]PLLXTPRE (def=0x0) // HSE divider for PLL entry
    • [21]RGMIION (def=0x0) // GMII clock gating enable
    • [22]PIPEON (def=0x0) // USBSS_PLL clock gating enable
    • [23]UTMION (def=0x0) // UTMI clock gating enable
    • [24:27]MCO (def=0x0) // Microcontroller clock output
    • [30]ADC_DUTY_SEL (def=0x0) // ADC clock duty cycle selection
    • [31]ADCSRC (def=0x0) // ADC intput clock source selection
  • 0x40021008PLLCFGR// PLL clock configuration register (RCC_PLLCFGR)

    • [0:4]PLLMUL (def=0x4) // PLL clock multiplication factor
    • [5:7]PLLSRC (def=0x0) // PLL intput clock source selection
    • [8:13]PLL_SRC_DIV (def=0x0) // PLL intput clock source prescaler
    • [28:30]SYSPLL_SEL (def=0x0) // Switch the System clock to PLL selection
    • [31]SYSPLL_GATE (def=0x0) // Switch the System clock to PLL gate
  • 0x4002100CINTR// Clock interrupt register (RCC_INTR)

    • [0]LSIRDYF (def=0x0) // LSI Ready Interrupt flag
    • [1]LSERDYF (def=0x0) // LSE Ready Interrupt flag
    • [2]HSIRDYF (def=0x0) // HSI Ready Interrupt flag
    • [3]HSERDYF (def=0x0) // HSE Ready Interrupt flag
    • [4]PLLRDYF (def=0x0) // PLL Ready Interrupt flag
    • [5]ETHPLLRDYF (def=0x0) // ETH Ready Interrupt flag
    • [6]SERDESPLLRDYF (def=0x0) // SERDES_PLL Ready Interrupt flag
    • [7]CSSF (def=0x0) // Clock Security System Interrupt flag
    • [8]LSIRDYIE (def=0x0) // LSI Ready Interrupt Enable
    • [9]LSERDYIE (def=0x0) // LSE Ready Interrupt Enable
    • [10]HSIRDYIE (def=0x0) // HSI Ready Interrupt Enable
    • [11]HSERDYIE (def=0x0) // HSE Ready Interrupt Enable
    • [12]PLLRDYIE (def=0x0) // PLL Ready Interrupt Enable
    • [13]ETHPLLRDYIE (def=0x0) // ETHPLL Ready Interrupt Enable
    • [14]SERDESPLLRDYIE (def=0x0) // SERDESPLL Ready Interrupt Enable
    • [16]LSIRDYC (def=0x0) // LSI Ready Interrupt Clear
    • [17]LSERDYC (def=0x0) // LSE Ready Interrupt Clear
    • [18]HSIRDYC (def=0x0) // HSI Ready Interrupt Clear
    • [19]HSERDYC (def=0x0) // HSE Ready Interrupt Clear
    • [20]PLLRDYC (def=0x0) // PLL Ready Interrupt Clear
    • [21]ETHPLLRDYC (def=0x0) // ETH PLL Ready Interrupt Clear
    • [22]SERDESPLLRDYC (def=0x0) // SERDES Ready Interrupt Clear
    • [23]CSSC (def=0x0) // Clock security system interrupt clear
  • 0x40021010HB2PRSTR// HB2 peripheral reset register (RCC_HB2PRSTR)

    • [0]AFIORST (def=0x0) // Alternate function I/O reset
    • [1]HSADCRST (def=0x0) // HSADC reset
    • [2]IOPARST (def=0x0) // IO port A reset
    • [3]IOPBRST (def=0x0) // IO port B reset
    • [4]IOPCRST (def=0x0) // IO port C reset
    • [5]IOPDRST (def=0x0) // IO port D reset
    • [6]IOPERST (def=0x0) // IO port E reset
    • [7]IOPFRST (def=0x0) // IO port F reset
    • [9]ADC1RST (def=0x0) // ADC 1 interface reset
    • [10]ADC2RST (def=0x0) // ADC 2 interface reset
    • [11]TIM1RST (def=0x0) // TIM1 timer reset
    • [12]SPI1RST (def=0x0) // SPI 1 reset
    • [13]TIM8RST (def=0x0) // TIM8 timer reset
    • [14]USART1RST (def=0x0) // USART1 reset
    • [15]I2C4RST (def=0x0) // I2C4 reset
    • [16]SAIRST (def=0x0) // SAI reset
    • [18]SDIORST (def=0x0) // SDIO reset
    • [19]TIM9RST (def=0x0) // TIM9 timer reset
    • [20]TIM10RST (def=0x0) // TIM10 timer reset
    • [21]TIM11RST (def=0x0) // TIM11 timer reset
    • [22]TIM12RST (def=0x0) // TIM12 timer reset
    • [23]OPCMRST (def=0x0) // OPA and CMP reset
    • [25]DFSDMRST (def=0x0) // DFSDM reset
    • [26]ECDCRST (def=0x0) // ECDC reset
    • [27]GPHARST (def=0x0) // GPHA reset
    • [30]LTDCRST (def=0x0) // LTDC reset
    • [31]I3CRST (def=0x0) // I3C reset
  • 0x40021014HB1PRSTR// HB1 peripheral reset register (RCC_HB1PRSTR)

    • [0]TIM2RST (def=0x0) // Timer 2 reset
    • [1]TIM3RST (def=0x0) // Timer 3 reset
    • [2]TIM4RST (def=0x0) // Timer 4 reset
    • [3]TIM5RST (def=0x0) // Timer 5 reset
    • [4]TIM6RST (def=0x0) // Timer 6 reset
    • [5]TIM7RST (def=0x0) // Timer 7 reset
    • [6]USART6RST (def=0x0) // USART 6 reset
    • [7]USART7RST (def=0x0) // USART 7 reset
    • [8]USART8RST (def=0x0) // USART 8 reset
    • [9]LPTIM1RST (def=0x0) // LPTIM1 reset
    • [10]LPTIM2RST (def=0x0) // LPTIM2 reset
    • [11]WWDGRST (def=0x0) // Window watchdog reset
    • [12]QSPI1RST (def=0x0) // QSPI1 reset
    • [13]QSPI2RST (def=0x0) // QSPI2 reset
    • [14]SPI2RST (def=0x0) // SPI2 reset
    • [15]SPI3RST (def=0x0) // SPI3 reset
    • [16]SPI4RST (def=0x0) // SPI4 reset
    • [17]USART2RST (def=0x0) // USART 2 reset
    • [18]USART3RST (def=0x0) // USART 3 reset
    • [19]USART4RST (def=0x0) // USART 4 reset
    • [20]USART5RST (def=0x0) // USART 5 reset
    • [21]I2C1RST (def=0x0) // I2C1 reset
    • [22]I2C2RST (def=0x0) // I2C2 reset
    • [24]CAN3RST (def=0x0) // CAN3 reset
    • [25]CAN1RST (def=0x0) // CAN1 reset
    • [26]CAN2RST (def=0x0) // CAN2 reset
    • [27]BKPRST (def=0x0) // Backup interface reset
    • [28]PWRRST (def=0x0) // Power interface reset
    • [29]DACRST (def=0x0) // DAC interface reset
    • [30]I2C3RST (def=0x0) // I2C3 reset
    • [31]SWPMIRST (def=0x0) // SWPMI reset
  • 0x40021018HBPCENR// HB Peripheral Clock enable register (RCC_HBPCENR)

    • [0]DMA1EN (def=0x0) // DMA clock enable
    • [1]DMA2EN (def=0x0) // DMA2 clock enable
    • [6]CRCEN (def=0x0) // CRC clock enable
    • [8]FMCEN (def=0x0) // FMC clock enable
    • [9]RNGEN (def=0x0) // RNG clock enable
    • [10]SDMMCEN (def=0x0) // SDMMC clock enable
    • [11]USBHSEN (def=0x0) // USBHS clock enable
    • [12]USBSSEN (def=0x0) // USBSS clock enable
    • [13]DVPEN (def=0x0) // DVP clock enable
    • [14]ETHMACEN (def=0x0) // Ethernet MAC clock enable
    • [17]OTGFSEN (def=0x0) // USBFS_OTG_FS clock enable
    • [18]UHSIFEN (def=0x0) // UHSIF clock enable
    • [19]USBPDEN (def=0x0) // USBPD clock enable
    • [20]SERDESEN (def=0x0) // SERDES clock enable
    • [22]POICEN (def=0x0) // POIC clock enable
  • 0x4002101CHB2PCENR// HB2 peripheral clock enable register (RCC_HB2PCENR)

    • [0]AFIOEN (def=0x0) // Alternate function I/O clock enable
    • [1]HSADCEN (def=0x0) // HSADC clock enable
    • [2]IOPAEN (def=0x0) // I/O port A clock enable
    • [3]IOPBEN (def=0x0) // I/O port B clock enable
    • [4]IOPCEN (def=0x0) // I/O port C clock enable
    • [5]IOPDEN (def=0x0) // I/O port D clock enable
    • [6]IOPEEN (def=0x0) // I/O port E clock enable
    • [7]IOPFEN (def=0x0) // I/O port F clock enable
    • [9]ADC1EN (def=0x0) // ADC1 interface clock enable
    • [10]ADC2EN (def=0x0) // ADC 2 interface clock enable
    • [11]TIM1EN (def=0x0) // TIM1 Timer clock enable
    • [12]SPI1EN (def=0x0) // SPI 1 clock enable
    • [13]TIM8EN (def=0x0) // TIM8 Timer clock enable
    • [14]USART1EN (def=0x0) // USART1 clock enable
    • [15]I2C4EN (def=0x0) // I2C4 clock enable
    • [16]SAIEN (def=0x0) // SAI clock enable
    • [18]SDIOEN (def=0x0) // SDIO clock enable
    • [19]TIM9EN (def=0x0) // TIM9 Timer clock enable
    • [20]TIM10EN (def=0x0) // TIM10 Timer clock enable
    • [21]TIM11EN (def=0x0) // TIM11 Timer clock enable
    • [22]TIM12EN (def=0x0) // TIM12 Timer clock enable
    • [23]OPCMEN (def=0x0) // OPA and CMP clock enable
    • [25]DFSDMEN (def=0x0) // DFSDM clock enable
    • [26]ECDCEN (def=0x0) // ECDC clock enable
    • [27]GPHAEN (def=0x0) // GPHA clock enable
    • [30]LTDCEN (def=0x0) // LTDC clock enable
    • [31]I3CEN (def=0x0) // I3C clock enable
  • 0x40021020HB1PCENR// HB1 peripheral clock enable register (RCC_HB1PCENR)

    • [0]TIM2EN (def=0x0) // Timer 2 clock enable
    • [1]TIM3EN (def=0x0) // Timer 3 clock enable
    • [2]TIM4EN (def=0x0) // Timer 4 clock enable
    • [3]TIM5EN (def=0x0) // Timer 5 clock enable
    • [4]TIM6EN (def=0x0) // Timer 6 clock enable
    • [5]TIM7EN (def=0x0) // Timer 7 clock enable
    • [6]USART6EN (def=0x0) // USART 6 clock enable
    • [7]USART7EN (def=0x0) // USART 7 clock enable
    • [8]USART8EN (def=0x0) // USART 8 clock enable
    • [9]LPTIM1EN (def=0x0) // LPTIM1 clock enable
    • [10]LPTIM2EN (def=0x0) // LPTIM2 clock enable
    • [11]WWDGEN (def=0x0) // Window watchdog clock enable
    • [12]QSPI1EN (def=0x0) // QSPI1 clock enable
    • [13]QSPI2EN (def=0x0) // QSPI2 clock enable
    • [14]SPI2EN (def=0x0) // SPI2 clock enable
    • [15]SPI3EN (def=0x0) // SPI3 clock enable
    • [16]SPI4EN (def=0x0) // SPI4 clock enable
    • [17]USART2EN (def=0x0) // USART2 clock enable
    • [18]USART3EN (def=0x0) // USART3 clock enable
    • [19]USART4EN (def=0x0) // USART4 clock enable
    • [20]USART5EN (def=0x0) // USART5 clock enable
    • [21]I2C1EN (def=0x0) // I2C1 clock enable
    • [22]I2C2EN (def=0x0) // I2C2 clock enable
    • [24]CAN3EN (def=0x0) // CAN3 clock enable
    • [25]CAN1EN (def=0x0) // CAN1 clock enable
    • [26]CAN2EN (def=0x0) // CAN2 clock enable
    • [27]BKPEN (def=0x0) // Backup interface clock enable
    • [28]PWREN (def=0x0) // Power interface clock enable
    • [29]DACEN (def=0x0) // DAC interface clock enable
    • [30]I2C3EN (def=0x0) // I2C3 clock enable
    • [31]SWPMIEN (def=0x0) // SWPMI clock enable
  • 0x40021024BDCTLR// Backup domain control register (RCC_BDCTLR)

    • [0]LSEON (def=0x0) // External Low Speed oscillator enable
    • [1]LSERDY (def=0x0) // External Low Speed oscillator ready
    • [2]LSEBYP (def=0x0) // External Low Speed oscillator bypass
    • [3]CCO (def=0x0) // calibrate the clock output selection
    • [4]ASOE (def=0x0) // TAMPER pin enables pulse output
    • [5]ASOS (def=0x0) // TAMPER pin alarm/second pulse output
    • [6:7]RTCSEL (def=0x0) // RTC clock source selection
    • [8]RTCEN (def=0x0) // RTC clock enable
    • [9:15]RTCCAL (def=0x0) // RTC calibration value
    • [16]BDRST (def=0x0) // Backup domain software reset
  • 0x40021028RSTSCKR// Control/status register (RCC_RSTSCKR)

    • [0]LSION (def=0x0) // Internal low speed oscillator enable
    • [1]LSIRDY (def=0x0) // Internal low speed oscillator ready
    • [24]RMVF (def=0x0) // Remove reset flag
    • [26]PINRSTF (def=0x0) // PIN reset flag
    • [27]PORRSTF (def=0x1) // POR/PDR reset flag
    • [28]SFTRSTF (def=0x0) // Software reset flag
    • [29]IWDGRSTF (def=0x0) // Independent watchdog reset flag
    • [30]WWDGRSTF (def=0x0) // Window watchdog reset flag
    • [31]LKUPRSTF (def=0x0) // LOCKUP reset flag
  • 0x4002102CHBRSTR// HB reset register (RCC_PHBRSTR)

    • [0]DMA1RST (def=0x0) // DMA1 reset
    • [1]DMA2RST (def=0x0) // DMA2 reset
    • [8]FMCRST (def=0x0) // FMC reset
    • [9]RNGRST (def=0x0) // RNG reset
    • [10]SDMMCRST (def=0x0) // SDMMC reset
    • [11]USBHSRST (def=0x0) // USBHS reset
    • [12]USBSSRST (def=0x0) // USBSS reset
    • [13]DVPRST (def=0x0) // DVP reset
    • [14]ETHMACRST (def=0x0) // Ethernet MAC reset
    • [17]OTGFSRST (def=0x0) // USBFS_OTG_FS eset
    • [18]UHSIFRST (def=0x0) // UHSIF reset
    • [19]USBPDRST (def=0x0) // USBPD reset
    • [20]SERDESRST (def=0x0) // SERDES reset
    • [22]POICRST (def=0x0) // POIC reset
  • 0x40021030CFGR2// Clock configuration register2 (RCC_CFGR2)

    • [0:5]UHSIFDIV (def=0x0) // UHSIF division factor
    • [6:7]UHSIFSRC (def=0x0) // UHSIF clock source selection
    • [8:13]LTDCDIV (def=0x0) // LTDC division factor
    • [14:15]LTDCSRC (def=0x0) // LTDC clock source selection
    • [16:19]USBFSDIV (def=0x0) // USBFS 48M division factor
    • [20]USBFSSRC (def=0x0) // USBFS 48M clock source selection
    • [23]RNGSRC (def=0x0) // RNG clock source selection
    • [24]I2S2SRC (def=0x0) // I2S2 clock source selection
    • [25]I2S3SRC (def=0x0) // I2S3 clock source selection
    • [28:29]HSADCSRC (def=0x0) // HSADC clock source selection
    • [30:31]ETH1GSRC (def=0x0) // ETH1G clock source selection
  • 0x40021034PLLCFGR2// PLL Clock configuration register2 (RCC_PLLCFGR2)

    • [0:1]USBHSPLLSRC (def=0x0) // USBHS clock source selection
    • [2:3]USBHSPLL_REFSEL (def=0x0) // USBHS_PLL reference clock frequency selection
    • [4:5]USBSSPLL_REFSEL (def=0x2) // USBSS_PLL reference clock frequency selection
    • [8:12]USBHSPLL_IN_DIV (def=0x0) // USBHS_PLL intput clock source SYS_PLL division setting
    • [16:19]SERDESPLL_MUL (def=0x8) // SERDESPLL clock multiplication factor
  interrupts:
  • [35] RCC // RCC global interrupt
• 0x40007000PWR// Power control

  • 0x40007000CTLR// Power control register (PWR_CTRL)

    • [0]LPDS (def=0x0) // Low Power Deep Sleep
    • [4]PVDE (def=0x0) // Power Voltage Detector Enable
    • [5:7]PLS (def=0x0) // PVD Level Selection
    • [8]DBP (def=0x0) // Disable Backup Domain write protection
    • [9]VIO_SW_CR (def=0x0) // VIO18 power regulation mode selection
    • [10:12]VSEL_VIO18 (def=0x0) // VIO18 power supply adjustment position
  • 0x40007004CSR// Power control register (PWR_CSR)

    • [0]PVDO (def=0x0) // PVD Output
    • [8:9]VIO18_SR (def=0x0) // VIO18 power supply initial status indicator
• 0x40023000CRC// CRC calculation unit

  • 0x40023000DATAR// Data register

    • [0:31]DR (def=0xFFFFFFFF) // Data Register
  • 0x40023004IDATAR// Independent Data register

    • [0:7]IDR (def=0x0) // Independent Data register
  • 0x40023008CTLR// Control register

    • [0]RESET (def=0x0) // Reset bit
• 0x40002800RTC// Real time clock

  • 0x40002800CTLRH// RTC Control Register High

    • [0]SECIE (def=0x0) // Second interrupt Enable
    • [1]ALRIE (def=0x0) // Alarm interrupt Enable
    • [2]OWIE (def=0x0) // Overflow interrupt Enable
  • 0x40002804CTLRL// RTC Control Register Low

    • [0]SECF (def=0x0) // Second Flag
    • [1]ALRF (def=0x0) // Alarm Flag
    • [2]OWF (def=0x0) // Overflow Flag
    • [3]RSF (def=0x0) // Registers Synchronized Flag
    • [4]CNF (def=0x0) // Configuration Flag
    • [5]RTOFF (def=0x1) // RTC operation OFF
  • 0x40002808PSCRH// RTC Prescaler Load Register High

    • [0:3]PRL (def=0x0) // RTC Prescaler Load Register High
  • 0x4000280CPSCRL// RTC Prescaler Load Register Low

    • [0:15]PRL (def=0x0) // RTC Prescaler Divider Register Low
  • 0x40002810DIVH// RTC Prescaler Divider Register High

    • [0:3]DIV (def=0x0) // RTC prescaler divider register high
  • 0x40002814DIVL// RTC Prescaler Divider Register Low

    • [0:15]DIV (def=0x0) // RTC prescaler divider register Low
  • 0x40002818CNTH// RTC Counter Register High

    • [0:15]CNTH (def=0x0) // RTC counter register high
  • 0x4000281CCNTL// RTC Counter Register Low

    • [0:15]CNTL (def=0x0) // RTC counter register Low
  • 0x40002820ALRMH// RTC Alarm Register High

    • [0:15]ALR (def=0x0) // RTC alarm register high
  • 0x40002824ALRML// RTC Alarm Register Low

    • [0:15]ALR (def=0x0) // RTC alarm register low
  interrupts:
  • [143] RTC // RTC global interrupt
  • [66] RTCAlarm // RTC Alarm-clock interrupt
• 0x40003000IWDG// Independent watchdog

  • 0x40003000CTLR// Key register (IWDG_CTLR)

    • [0:15]KEY (def=0x0) // Key value
  • 0x40003004PSCR// Prescaler register (IWDG_PSCR)

    • [0:2]PR (def=0x0) // Prescaler divider
  • 0x40003008RLDR// Reload register (IWDG_RLDR)

    • [0:11]RL (def=0xFFF) // Watchdog counter reload value
  • 0x4000300CSTATR// Status register (IWDG_SR)

    • [0]PVU (def=0x0) // Watchdog prescaler value update
    • [1]RVU (def=0x0) // Watchdog counter reload value update
• 0x40002C00WWDG// Window watchdog

  • 0x40002C00CTLR// Control register (WWDG_CR)

    • [0:6]T (def=0x7F) // 7-bit counter (MSB to LSB)
    • [7]WDGA (def=0x0) // Activation bit
  • 0x40002C04CFGR// Configuration register (WWDG_CFGR)

    • [0:6]W (def=0x7F) // 7-bit window value
    • [7:8]WDGTB (def=0x0) // Timer Base
    • [9]EWI (def=0x0) // Early Wakeup Interrupt
  • 0x40002C08STATR// Status register (WWDG_SR)

    • [0]EWIF (def=0x0) // Early Wakeup Interrupt Flag
  interrupts:
  • [32] WWDG // Window Watchdog interrupt
• 0x40010800GPIOA// General purpose I/O

  • 0x40010800CFGLR// Port configuration register low (GPIOn_CFGLR)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40010804CFGHR// Port configuration register high (GPIOn_CFGHR)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40010808INDR// Port input data register (GPIOn_INDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x4001080COUTDR// Port output data register (GPIOn_OUTDR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40010810BSHR// Port bit set/reset register (GPIOn_BSHR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40010814BCR// Port bit reset register (GPIOn_BCR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40010818LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40010C00GPIOB//

  • 0x40010C00CFGLR// Port configuration register low (GPIOn_CFGLR)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40010C04CFGHR// Port configuration register high (GPIOn_CFGHR)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40010C08INDR// Port input data register (GPIOn_INDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x40010C0COUTDR// Port output data register (GPIOn_OUTDR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40010C10BSHR// Port bit set/reset register (GPIOn_BSHR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40010C14BCR// Port bit reset register (GPIOn_BCR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40010C18LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40011000GPIOC//

  • 0x40011000CFGLR// Port configuration register low (GPIOn_CFGLR)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40011004CFGHR// Port configuration register high (GPIOn_CFGHR)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40011008INDR// Port input data register (GPIOn_INDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x4001100COUTDR// Port output data register (GPIOn_OUTDR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40011010BSHR// Port bit set/reset register (GPIOn_BSHR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40011014BCR// Port bit reset register (GPIOn_BCR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40011018LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40011400GPIOD//

  • 0x40011400CFGLR// Port configuration register low (GPIOn_CFGLR)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40011404CFGHR// Port configuration register high (GPIOn_CFGHR)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40011408INDR// Port input data register (GPIOn_INDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x4001140COUTDR// Port output data register (GPIOn_OUTDR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40011410BSHR// Port bit set/reset register (GPIOn_BSHR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40011414BCR// Port bit reset register (GPIOn_BCR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40011418LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40011800GPIOE//

  • 0x40011800CFGLR// Port configuration register low (GPIOn_CFGLR)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40011804CFGHR// Port configuration register high (GPIOn_CFGHR)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40011808INDR// Port input data register (GPIOn_INDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x4001180COUTDR// Port output data register (GPIOn_OUTDR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40011810BSHR// Port bit set/reset register (GPIOn_BSHR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40011814BCR// Port bit reset register (GPIOn_BCR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40011818LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40011C00GPIOF//

  • 0x40011C00CFGLR// Port configuration register low (GPIOn_CFGLR)

    • [0:1]MODE0 (def=0x0) // Port n.0 mode bits
    • [2:3]CNF0 (def=0x1) // Port n.0 configuration bits
    • [4:5]MODE1 (def=0x0) // Port n.1 mode bits
    • [6:7]CNF1 (def=0x1) // Port n.1 configuration bits
    • [8:9]MODE2 (def=0x0) // Port n.2 mode bits
    • [10:11]CNF2 (def=0x1) // Port n.2 configuration bits
    • [12:13]MODE3 (def=0x0) // Port n.3 mode bits
    • [14:15]CNF3 (def=0x1) // Port n.3 configuration bits
    • [16:17]MODE4 (def=0x0) // Port n.4 mode bits
    • [18:19]CNF4 (def=0x1) // Port n.4 configuration bits
    • [20:21]MODE5 (def=0x0) // Port n.5 mode bits
    • [22:23]CNF5 (def=0x1) // Port n.5 configuration bits
    • [24:25]MODE6 (def=0x0) // Port n.6 mode bits
    • [26:27]CNF6 (def=0x1) // Port n.6 configuration bits
    • [28:29]MODE7 (def=0x0) // Port n.7 mode bits
    • [30:31]CNF7 (def=0x1) // Port n.7 configuration bits
  • 0x40011C04CFGHR// Port configuration register high (GPIOn_CFGHR)

    • [0:1]MODE8 (def=0x0) // Port n.8 mode bits
    • [2:3]CNF8 (def=0x1) // Port n.8 configuration bits
    • [4:5]MODE9 (def=0x0) // Port n.9 mode bits
    • [6:7]CNF9 (def=0x1) // Port n.9 configuration bits
    • [8:9]MODE10 (def=0x0) // Port n.10 mode bits
    • [10:11]CNF10 (def=0x1) // Port n.10 configuration bits
    • [12:13]MODE11 (def=0x0) // Port n.11 mode bits
    • [14:15]CNF11 (def=0x1) // Port n.11 configuration bits
    • [16:17]MODE12 (def=0x0) // Port n.12 mode bits
    • [18:19]CNF12 (def=0x1) // Port n.12 configuration bits
    • [20:21]MODE13 (def=0x0) // Port n.13 mode bits
    • [22:23]CNF13 (def=0x1) // Port n.13 configuration bits
    • [24:25]MODE14 (def=0x0) // Port n.14 mode bits
    • [26:27]CNF14 (def=0x1) // Port n.14 configuration bits
    • [28:29]MODE15 (def=0x0) // Port n.15 mode bits
    • [30:31]CNF15 (def=0x1) // Port n.15 configuration bits
  • 0x40011C08INDR// Port input data register (GPIOn_INDR)

    • [0]IDR0 (def=0x0) // Port input data
    • [1]IDR1 (def=0x0) // Port input data
    • [2]IDR2 (def=0x0) // Port input data
    • [3]IDR3 (def=0x0) // Port input data
    • [4]IDR4 (def=0x0) // Port input data
    • [5]IDR5 (def=0x0) // Port input data
    • [6]IDR6 (def=0x0) // Port input data
    • [7]IDR7 (def=0x0) // Port input data
    • [8]IDR8 (def=0x0) // Port input data
    • [9]IDR9 (def=0x0) // Port input data
    • [10]IDR10 (def=0x0) // Port input data
    • [11]IDR11 (def=0x0) // Port input data
    • [12]IDR12 (def=0x0) // Port input data
    • [13]IDR13 (def=0x0) // Port input data
    • [14]IDR14 (def=0x0) // Port input data
    • [15]IDR15 (def=0x0) // Port input data
  • 0x40011C0COUTDR// Port output data register (GPIOn_OUTDR)

    • [0]ODR0 (def=0x0) // Port output data
    • [1]ODR1 (def=0x0) // Port output data
    • [2]ODR2 (def=0x0) // Port output data
    • [3]ODR3 (def=0x0) // Port output data
    • [4]ODR4 (def=0x0) // Port output data
    • [5]ODR5 (def=0x0) // Port output data
    • [6]ODR6 (def=0x0) // Port output data
    • [7]ODR7 (def=0x0) // Port output data
    • [8]ODR8 (def=0x0) // Port output data
    • [9]ODR9 (def=0x0) // Port output data
    • [10]ODR10 (def=0x0) // Port output data
    • [11]ODR11 (def=0x0) // Port output data
    • [12]ODR12 (def=0x0) // Port output data
    • [13]ODR13 (def=0x0) // Port output data
    • [14]ODR14 (def=0x0) // Port output data
    • [15]ODR15 (def=0x0) // Port output data
  • 0x40011C10BSHR// Port bit set/reset register (GPIOn_BSHR)

    • [0]BS0 (def=0x0) // Set bit 0
    • [1]BS1 (def=0x0) // Set bit 1
    • [2]BS2 (def=0x0) // Set bit 1
    • [3]BS3 (def=0x0) // Set bit 3
    • [4]BS4 (def=0x0) // Set bit 4
    • [5]BS5 (def=0x0) // Set bit 5
    • [6]BS6 (def=0x0) // Set bit 6
    • [7]BS7 (def=0x0) // Set bit 7
    • [8]BS8 (def=0x0) // Set bit 8
    • [9]BS9 (def=0x0) // Set bit 9
    • [10]BS10 (def=0x0) // Set bit 10
    • [11]BS11 (def=0x0) // Set bit 11
    • [12]BS12 (def=0x0) // Set bit 12
    • [13]BS13 (def=0x0) // Set bit 13
    • [14]BS14 (def=0x0) // Set bit 14
    • [15]BS15 (def=0x0) // Set bit 15
    • [16]BR0 (def=0x0) // Reset bit 0
    • [17]BR1 (def=0x0) // Reset bit 1
    • [18]BR2 (def=0x0) // Reset bit 2
    • [19]BR3 (def=0x0) // Reset bit 3
    • [20]BR4 (def=0x0) // Reset bit 4
    • [21]BR5 (def=0x0) // Reset bit 5
    • [22]BR6 (def=0x0) // Reset bit 6
    • [23]BR7 (def=0x0) // Reset bit 7
    • [24]BR8 (def=0x0) // Reset bit 8
    • [25]BR9 (def=0x0) // Reset bit 9
    • [26]BR10 (def=0x0) // Reset bit 10
    • [27]BR11 (def=0x0) // Reset bit 11
    • [28]BR12 (def=0x0) // Reset bit 12
    • [29]BR13 (def=0x0) // Reset bit 13
    • [30]BR14 (def=0x0) // Reset bit 14
    • [31]BR15 (def=0x0) // Reset bit 15
  • 0x40011C14BCR// Port bit reset register (GPIOn_BCR)

    • [0]BR0 (def=0x0) // Reset bit 0
    • [1]BR1 (def=0x0) // Reset bit 1
    • [2]BR2 (def=0x0) // Reset bit 1
    • [3]BR3 (def=0x0) // Reset bit 3
    • [4]BR4 (def=0x0) // Reset bit 4
    • [5]BR5 (def=0x0) // Reset bit 5
    • [6]BR6 (def=0x0) // Reset bit 6
    • [7]BR7 (def=0x0) // Reset bit 7
    • [8]BR8 (def=0x0) // Reset bit 8
    • [9]BR9 (def=0x0) // Reset bit 9
    • [10]BR10 (def=0x0) // Reset bit 10
    • [11]BR11 (def=0x0) // Reset bit 11
    • [12]BR12 (def=0x0) // Reset bit 12
    • [13]BR13 (def=0x0) // Reset bit 13
    • [14]BR14 (def=0x0) // Reset bit 14
    • [15]BR15 (def=0x0) // Reset bit 15
  • 0x40011C18LCKR// Port configuration lock register

    • [0]LCK0 (def=0x0) // Port A Lock bit 0
    • [1]LCK1 (def=0x0) // Port A Lock bit 1
    • [2]LCK2 (def=0x0) // Port A Lock bit 2
    • [3]LCK3 (def=0x0) // Port A Lock bit 3
    • [4]LCK4 (def=0x0) // Port A Lock bit 4
    • [5]LCK5 (def=0x0) // Port A Lock bit 5
    • [6]LCK6 (def=0x0) // Port A Lock bit 6
    • [7]LCK7 (def=0x0) // Port A Lock bit 7
    • [8]LCK8 (def=0x0) // Port A Lock bit 8
    • [9]LCK9 (def=0x0) // Port A Lock bit 9
    • [10]LCK10 (def=0x0) // Port A Lock bit 10
    • [11]LCK11 (def=0x0) // Port A Lock bit 11
    • [12]LCK12 (def=0x0) // Port A Lock bit 12
    • [13]LCK13 (def=0x0) // Port A Lock bit 13
    • [14]LCK14 (def=0x0) // Port A Lock bit 14
    • [15]LCK15 (def=0x0) // Port A Lock bit 15
    • [16]LCKK (def=0x0) // Lock key
• 0x40010000AFIO// Alternate function I/O

  • 0x40010000PCFR1// AF remap and debug I/O configuration register (AFIO_PCFR1)

    • [0]PD0PD1_RM (def=0x0) // PD0PD1 remapping
    • [1]ADC1_ETRGINJ_RM (def=0x0) // ADC1_ETRGINJ remapping
    • [2]ADC1_ETRGREG_RM (def=0x0) // ADC1_ETRGREG remapping
    • [3]ADC2_ETRGINJ_RM (def=0x0) // ADC2_ETRGINJ remapping
    • [4]ADC2_ETRGREG_RM (def=0x0) // ADC2_ETRGREG remapping
    • [6:7]UHSIF_CLK_RM (def=0x0) // UHSIF_CLK remapping
    • [8:9]UHSIF_PORT_RM (def=0x0) // UHSIF_PORT remapping
    • [10:11]SDMMC_RM (def=0x0) // SDMMC remapping
    • [12]TIM2ITR1_RM (def=0x0) // TIM2ITR1 remapping
    • [16]VIO18_IO_HSLV (def=0x0) // VIO18 IO speed configuration at low voltage
    • [17]VIO33_IO_HSLV (def=0x0) // VIO33 IO speed configuration at low voltage
    • [18]VDD33_IO_HSLV (def=0x0) // VDD33 IO speed configuration at low voltage
    • [20]USBPD_CC_HVT (def=0x0) // CC pin intput channel threshold adjustment
    • [24:26]SW_CFG (def=0x0) // Serial wire JTAG configuration
  • 0x40010004GPIOA_AFLR// PA port multiplexing function register

    • [0:3]AFR0 (def=0x0) // selection of multiplexing function for pin 0 of PA port
    • [4:7]AFR1 (def=0x0) // selection of multiplexing function for pin 1 of PA port
    • [8:11]AFR2 (def=0x0) // selection of multiplexing function for pin 2 of PA port
    • [12:15]AFR3 (def=0x0) // selection of multiplexing function for pin 3 of PA port
    • [16:19]AFR4 (def=0x0) // selection of multiplexing function for pin 4 of PA port
    • [20:23]AFR5 (def=0x0) // selection of multiplexing function for pin 5 of PA port
    • [24:27]AFR6 (def=0x0) // selection of multiplexing function for pin 6 of PA port
    • [28:31]AFR7 (def=0x0) // selection of multiplexing function for pin 7 of PA port
  • 0x40010008GPIOA_AFHR// PA port multiplexing function register

    • [0:3]AFR8 (def=0x0) // selection of multiplexing function for pin 8 of PA port
    • [4:7]AFR9 (def=0x0) // selection of multiplexing function for pin 9 of PA port
    • [8:11]AFR10 (def=0x0) // selection of multiplexing function for pin 10 of PA port
    • [12:15]AFR11 (def=0x0) // selection of multiplexing function for pin 11 of PA port
    • [16:19]AFR12 (def=0x0) // selection of multiplexing function for pin 12 of PA port
    • [20:23]AFR13 (def=0x0) // selection of multiplexing function for pin 13 of PA port
    • [24:27]AFR14 (def=0x0) // selection of multiplexing function for pin 14 of PA port
    • [28:31]AFR15 (def=0x0) // selection of multiplexing function for pin 15 of PA port
  • 0x4001000CGPIOB_AFLR// PB port multiplexing function register

    • [0:3]AFR0 (def=0x0) // selection of multiplexing function for pin 0 of PB port
    • [4:7]AFR1 (def=0x0) // selection of multiplexing function for pin 1 of PB port
    • [8:11]AFR2 (def=0x0) // selection of multiplexing function for pin 2 of PB port
    • [12:15]AFR3 (def=0x0) // selection of multiplexing function for pin 3 of PB port
    • [16:19]AFR4 (def=0x0) // selection of multiplexing function for pin 4 of PB port
    • [20:23]AFR5 (def=0x0) // selection of multiplexing function for pin 5 of PB port
    • [24:27]AFR6 (def=0x0) // selection of multiplexing function for pin 6 of PB port
    • [28:31]AFR7 (def=0x0) // selection of multiplexing function for pin 7 of PB port
  • 0x40010010GPIOB_AFHR// PB port multiplexing function register

    • [0:3]AFR8 (def=0x0) // selection of multiplexing function for pin 8 of PA port
    • [4:7]AFR9 (def=0x0) // selection of multiplexing function for pin 9 of PB port
    • [8:11]AFR10 (def=0x0) // selection of multiplexing function for pin 10 of PB port
    • [12:15]AFR11 (def=0x0) // selection of multiplexing function for pin 11 of PB port
    • [16:19]AFR12 (def=0x0) // selection of multiplexing function for pin 12 of PB port
    • [20:23]AFR13 (def=0x0) // selection of multiplexing function for pin 13 of PB port
    • [24:27]AFR14 (def=0x0) // selection of multiplexing function for pin 14 of PB port
    • [28:31]AFR15 (def=0x0) // selection of multiplexing function for pin 15 of PB port
  • 0x40010014GPIOC_AFLR// PC port multiplexing function register

    • [0:3]AFR0 (def=0x0) // selection of multiplexing function for pin 0 of PC port
    • [4:7]AFR1 (def=0x0) // selection of multiplexing function for pin 1 of PC port
    • [8:11]AFR2 (def=0x0) // selection of multiplexing function for pin 2 of PC port
    • [12:15]AFR3 (def=0x0) // selection of multiplexing function for pin 3 of PC port
    • [16:19]AFR4 (def=0x0) // selection of multiplexing function for pin 4 of PC port
    • [20:23]AFR5 (def=0x0) // selection of multiplexing function for pin 5 of PC port
    • [24:27]AFR6 (def=0x0) // selection of multiplexing function for pin 6 of PC port
    • [28:31]AFR7 (def=0x0) // selection of multiplexing function for pin 7 of PC port
  • 0x40010018GPIOC_AFHR// PC port multiplexing function register

    • [0:3]AFR8 (def=0x0) // selection of multiplexing function for pin 8 of PC port
    • [4:7]AFR9 (def=0x0) // selection of multiplexing function for pin 9 of PC port
    • [8:11]AFR10 (def=0x0) // selection of multiplexing function for pin 10 of PC port
    • [12:15]AFR11 (def=0x0) // selection of multiplexing function for pin 11 of PC port
    • [16:19]AFR12 (def=0x0) // selection of multiplexing function for pin 12 of PC port
    • [20:23]AFR13 (def=0x0) // selection of multiplexing function for pin 13 of PC port
    • [24:27]AFR14 (def=0x0) // selection of multiplexing function for pin 14 of PC port
    • [28:31]AFR15 (def=0x0) // selection of multiplexing function for pin 15 of PC port
  • 0x4001001CGPIOD_AFLR// PD port multiplexing function register

    • [0:3]AFR0 (def=0x0) // selection of multiplexing function for pin 0 of PD port
    • [4:7]AFR1 (def=0x0) // selection of multiplexing function for pin 1 of PD port
    • [8:11]AFR2 (def=0x0) // selection of multiplexing function for pin 2 of PD port
    • [12:15]AFR3 (def=0x0) // selection of multiplexing function for pin 3 of PA port
    • [16:19]AFR4 (def=0x0) // selection of multiplexing function for pin 4 of PD port
    • [20:23]AFR5 (def=0x0) // selection of multiplexing function for pin 5 of PD port
    • [24:27]AFR6 (def=0x0) // selection of multiplexing function for pin 6 of PD port
    • [28:31]AFR7 (def=0x0) // selection of multiplexing function for pin 7 of PD port
  • 0x40010020GPIOD_AFHR// PD port multiplexing function register

    • [0:3]AFR8 (def=0x0) // selection of multiplexing function for pin 8 of PD port
    • [4:7]AFR9 (def=0x0) // selection of multiplexing function for pin 9 of PD port
    • [8:11]AFR10 (def=0x0) // selection of multiplexing function for pin 10 of PD port
    • [12:15]AFR11 (def=0x0) // selection of multiplexing function for pin 11 of PD port
    • [16:19]AFR12 (def=0x0) // selection of multiplexing function for pin 12 of PD port
    • [20:23]AFR13 (def=0x0) // selection of multiplexing function for pin 13 of PD port
    • [24:27]AFR14 (def=0x0) // selection of multiplexing function for pin 14 of PD port
    • [28:31]AFR15 (def=0x0) // selection of multiplexing function for pin 15 of PD port
  • 0x40010024GPIOE_AFLR// PE port multiplexing function register

    • [0:3]AFR0 (def=0x0) // selection of multiplexing function for pin 0 of PE port
    • [4:7]AFR1 (def=0x0) // selection of multiplexing function for pin 1 of PE port
    • [8:11]AFR2 (def=0x0) // selection of multiplexing function for pin 2 of PE port
    • [12:15]AFR3 (def=0x0) // selection of multiplexing function for pin 3 of PE port
    • [16:19]AFR4 (def=0x0) // selection of multiplexing function for pin 4 of PE port
    • [20:23]AFR5 (def=0x0) // selection of multiplexing function for pin 5 of PE port
    • [24:27]AFR6 (def=0x0) // selection of multiplexing function for pin 6 of PE port
    • [28:31]AFR7 (def=0x0) // selection of multiplexing function for pin 7 of PE port
  • 0x40010028GPIOE_AFHR// PA port multiplexing function register

    • [0:3]AFR8 (def=0x0) // selection of multiplexing function for pin 8 of PE port
    • [4:7]AFR9 (def=0x0) // selection of multiplexing function for pin 9 of PE port
    • [8:11]AFR10 (def=0x0) // selection of multiplexing function for pin 10 of PE port
    • [12:15]AFR11 (def=0x0) // selection of multiplexing function for pin 11 of PE port
    • [16:19]AFR12 (def=0x0) // selection of multiplexing function for pin 12 of PE port
    • [20:23]AFR13 (def=0x0) // selection of multiplexing function for pin 13 of PE port
    • [24:27]AFR14 (def=0x0) // selection of multiplexing function for pin 14 of PE port
    • [28:31]AFR15 (def=0x0) // selection of multiplexing function for pin 15 of PE port
  • 0x4001002CGPIOF_AFLR// PF port multiplexing function register

    • [0:3]AFR0 (def=0x0) // selection of multiplexing function for pin 0 of PF port
    • [4:7]AFR1 (def=0x0) // selection of multiplexing function for pin 1 of PF port
    • [8:11]AFR2 (def=0x0) // selection of multiplexing function for pin 2 of PF port
    • [12:15]AFR3 (def=0x0) // selection of multiplexing function for pin 3 of PF port
    • [16:19]AFR4 (def=0x0) // selection of multiplexing function for pin 4 of PF port
    • [20:23]AFR5 (def=0x0) // selection of multiplexing function for pin 5 of PF port
    • [24:27]AFR6 (def=0x0) // selection of multiplexing function for pin 6 of PF port
    • [28:31]AFR7 (def=0x0) // selection of multiplexing function for pin 7 of PF port
  • 0x40010030GPIOF_AFHR// PF port multiplexing function register

    • [0:3]AFR8 (def=0x0) // selection of multiplexing function for pin 8 of PF port
    • [4:7]AFR9 (def=0x0) // selection of multiplexing function for pin 9 of PF port
    • [8:11]AFR10 (def=0x0) // selection of multiplexing function for pin 10 of PF port
    • [12:15]AFR11 (def=0x0) // selection of multiplexing function for pin 11 of PF port
    • [16:19]AFR12 (def=0x0) // selection of multiplexing function for pin 12 of PF port
    • [20:23]AFR13 (def=0x0) // selection of multiplexing function for pin 13 of PF port
    • [24:27]AFR14 (def=0x0) // selection of multiplexing function for pin 14 of PF port
    • [28:31]AFR15 (def=0x0) // selection of multiplexing function for pin 15 of PE port
  • 0x4001003CEXTICR1// External interrupt configuration register 1

    • [0:3]EXTI0 (def=0x0) // External interrupt 0 input pin configuration
    • [4:7]EXTI1 (def=0x0) // External interrupt 1 input pin configuration
    • [8:11]EXTI2 (def=0x0) // External interrupt 2 input pin configuration
    • [12:15]EXTI3 (def=0x0) // External interrupt 3 input pin configuration
    • [16:19]EXTI4 (def=0x0) // External interrupt 4 input pin configuration
    • [20:23]EXTI5 (def=0x0) // External interrupt 5 input pin configuration
    • [24:27]EXTI6 (def=0x0) // External interrupt 6 input pin configuration
    • [28:31]EXTI7 (def=0x0) // External interrupt 7 input pin configuration
  • 0x40010040EXTICR2// External interrupt configuration register 2

    • [0:3]EXTI8 (def=0x0) // External interrupt 8 input pin configuration
    • [4:7]EXTI9 (def=0x0) // External interrupt 9 input pin configuration
    • [8:11]EXTI10 (def=0x0) // External interrupt 10 input pin configuration
    • [12:15]EXTI11 (def=0x0) // External interrupt 11 input pin configuration
    • [16:19]EXTI12 (def=0x0) // External interrupt 12 input pin configuration
    • [20:23]EXTI13 (def=0x0) // External interrupt 13 input pin configuration
    • [24:27]EXTI14 (def=0x0) // External interrupt 14 input pin configuration
    • [28:31]EXTI15 (def=0x0) // External interrupt 15 input pin configuration
• 0x40020000DMA1// DMA1 controller

  • 0x40020000INTFR// DMA interrupt status register (DMA_INTFR)

    • [0]GIF1 (def=0x0) // Channel 1 Global interrupt flag
    • [1]TCIF1 (def=0x0) // Channel 1 Transfer Complete flag
    • [2]HTIF1 (def=0x0) // Channel 1 Half Transfer Complete flag
    • [3]TEIF1 (def=0x0) // Channel 1 Transfer Error flag
    • [4]GIF2 (def=0x0) // Channel 2 Global interrupt flag
    • [5]TCIF2 (def=0x0) // Channel 2 Transfer Complete flag
    • [6]HTIF2 (def=0x0) // Channel 2 Half Transfer Complete flag
    • [7]TEIF2 (def=0x0) // Channel 2 Transfer Error flag
    • [8]GIF3 (def=0x0) // Channel 3 Global interrupt flag
    • [9]TCIF3 (def=0x0) // Channel 3 Transfer Complete flag
    • [10]HTIF3 (def=0x0) // Channel 3 Half Transfer Complete flag
    • [11]TEIF3 (def=0x0) // Channel 3 Transfer Error flag
    • [12]GIF4 (def=0x0) // Channel 4 Global interrupt flag
    • [13]TCIF4 (def=0x0) // Channel 4 Transfer Complete flag
    • [14]HTIF4 (def=0x0) // Channel 4 Half Transfer Complete flag
    • [15]TEIF4 (def=0x0) // Channel 4 Transfer Error flag
    • [16]GIF5 (def=0x0) // Channel 5 Global interrupt flag
    • [17]TCIF5 (def=0x0) // Channel 5 Transfer Complete flag
    • [18]HTIF5 (def=0x0) // Channel 5 Half Transfer Complete flag
    • [19]TEIF5 (def=0x0) // Channel 5 Transfer Error flag
    • [20]GIF6 (def=0x0) // Channel 6 Global interrupt flag
    • [21]TCIF6 (def=0x0) // Channel 6 Transfer Complete flag
    • [22]HTIF6 (def=0x0) // Channel 6 Half Transfer Complete flag
    • [23]TEIF6 (def=0x0) // Channel 6 Transfer Error flag
    • [24]GIF7 (def=0x0) // Channel 7 Global interrupt flag
    • [25]TCIF7 (def=0x0) // Channel 7 Transfer Complete flag
    • [26]HTIF7 (def=0x0) // Channel 7 Half Transfer Complete flag
    • [27]TEIF7 (def=0x0) // Channel 7 Transfer Error flag
    • [28]GIF8 (def=0x0) // Channel 8 Global interrupt flag
    • [29]TCIF8 (def=0x0) // Channel 8 Transfer Complete flag
    • [30]HTIF8 (def=0x0) // Channel 8 Half Transfer Complete flag
    • [31]TEIF8 (def=0x0) // Channel 8 Transfer Error flag
  • 0x40020004INTFCR// DMA interrupt flag clear register (DMA_INTFCR)

    • [0]CGIF1 (def=0x0) // Channel 1 Global interrupt clear
    • [4]CGIF2 (def=0x0) // Channel 2 Global interrupt clear
    • [8]CGIF3 (def=0x0) // Channel 3 Global interrupt clear
    • [12]CGIF4 (def=0x0) // Channel 4 Global interrupt clear
    • [16]CGIF5 (def=0x0) // Channel 5 Global interrupt clear
    • [20]CGIF6 (def=0x0) // Channel 6 Global interrupt clear
    • [24]CGIF7 (def=0x0) // Channel 7 Global interrupt clear
    • [28]CGIF8 (def=0x0) // Channel 8 Global interrupt clear
    • [1]CTCIF1 (def=0x0) // Channel 1 Transfer Complete clear
    • [5]CTCIF2 (def=0x0) // Channel 2 Transfer Complete clear
    • [9]CTCIF3 (def=0x0) // Channel 3 Transfer Complete clear
    • [13]CTCIF4 (def=0x0) // Channel 4 Transfer Complete clear
    • [17]CTCIF5 (def=0x0) // Channel 5 Transfer Complete clear
    • [21]CTCIF6 (def=0x0) // Channel 6 Transfer Complete clear
    • [25]CTCIF7 (def=0x0) // Channel 7 Transfer Complete clear
    • [29]CTCIF8 (def=0x0) // Channel 8 Transfer Complete clear
    • [2]CHTIF1 (def=0x0) // Channel 1 Half Transfer clear
    • [6]CHTIF2 (def=0x0) // Channel 2 Half Transfer clear
    • [10]CHTIF3 (def=0x0) // Channel 3 Half Transfer clear
    • [14]CHTIF4 (def=0x0) // Channel 4 Half Transfer clear
    • [18]CHTIF5 (def=0x0) // Channel 5 Half Transfer clear
    • [22]CHTIF6 (def=0x0) // Channel 6 Half Transfer clear
    • [26]CHTIF7 (def=0x0) // Channel 7 Half Transfer clear
    • [30]CHTIF8 (def=0x0) // Channel 8 Half Transfer clear
    • [3]CTEIF1 (def=0x0) // Channel 1 Transfer Error clear
    • [7]CTEIF2 (def=0x0) // Channel 2 Transfer Error clear
    • [11]CTEIF3 (def=0x0) // Channel 3 Transfer Error clear
    • [15]CTEIF4 (def=0x0) // Channel 4 Transfer Error clear
    • [19]CTEIF5 (def=0x0) // Channel 5 Transfer Error clear
    • [23]CTEIF6 (def=0x0) // Channel 6 Transfer Error clear
    • [27]CTEIF7 (def=0x0) // Channel 7 Transfer Error clear
    • [31]CTEIF8 (def=0x0) // Channel 8 Transfer Error clear
  • 0x40020008CFGR1// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
    • [15]DOUBLE_MODE (def=0x0) // Double buffer mode enable bit
    • [16]FLAG_CUR_MEM (def=0x0) // Memory address selection setting
  • 0x4002000CCNTR1// DMA channel 1 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020010PADDR1// DMA channel 1 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020014MADDR1// DMA channel 1 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020018M1ADDR1// DMA channel 1 memory address1 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x4002001CCFGR2// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020020CNTR2// DMA channel 2 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020024PADDR2// DMA channel 2 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020028MADDR2// DMA channel 2 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002002CM1ADDR2// DMA channel 2 memory address 1 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020030CFGR3// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020034CNTR3// DMA channel 3 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020038PADDR3// DMA channel 3 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x4002003CMADDR3// DMA channel 3 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020040M1ADDR3// DMA channel 3 memory address 1 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020044CFGR4// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020048CNTR4// DMA channel 4 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x4002004CPADDR4// DMA channel 4 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020050MADDR4// DMA channel 4 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020054M1ADDR4// DMA channel 4 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020058CFGR5// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x4002005CCNTR5// DMA channel 5 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020060PADDR5// DMA channel 5 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020064MADDR5// DMA channel 5 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020068M1ADDR5// DMA channel 5 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x4002006CCFGR6// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020070CNTR6// DMA channel 6 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020074PADDR6// DMA channel 6 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020078MADDR6// DMA channel 6 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002007CM1ADDR6// DMA channel 6 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020080CFGR7// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020084CNTR7// DMA channel 7 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020088PADDR7// DMA channel 7 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x4002008CMADDR7// DMA channel 7 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020090M1ADDR7// DMA channel 7 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020094CFGR8// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020098CNTR8// DMA channel 8 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x4002009CPADDR8// DMA channel 8 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x400200A0MADDR8// DMA channel 8 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x400200A4M1ADDR8// DMA channel 8 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  interrupts:
  • [57] DMA1_CH1 // DMA1 Channel1 global interrupt
  • [38] DMA1_CH2 // DMA1 Channel2 global interrupt
  • [39] DMA1_CH3 // DMA1 Channel3 global interrupt
  • [40] DMA1_CH4 // DMA1 Channel4 global interrupt
  • [41] DMA1_CH5 // DMA1 Channel5 global interrupt
  • [42] DMA1_CH6 // DMA1 Channel6 global interrupt
  • [43] DMA1_CH7 // DMA1 Channel7 global interrupt
  • [44] DMA1_CH8 // DMA1 Channel8 global interrupt
• 0x40020400DMA2//

  • 0x40020400INTFR// DMA interrupt status register (DMA_INTFR)

    • [0]GIF1 (def=0x0) // Channel 1 Global interrupt flag
    • [1]TCIF1 (def=0x0) // Channel 1 Transfer Complete flag
    • [2]HTIF1 (def=0x0) // Channel 1 Half Transfer Complete flag
    • [3]TEIF1 (def=0x0) // Channel 1 Transfer Error flag
    • [4]GIF2 (def=0x0) // Channel 2 Global interrupt flag
    • [5]TCIF2 (def=0x0) // Channel 2 Transfer Complete flag
    • [6]HTIF2 (def=0x0) // Channel 2 Half Transfer Complete flag
    • [7]TEIF2 (def=0x0) // Channel 2 Transfer Error flag
    • [8]GIF3 (def=0x0) // Channel 3 Global interrupt flag
    • [9]TCIF3 (def=0x0) // Channel 3 Transfer Complete flag
    • [10]HTIF3 (def=0x0) // Channel 3 Half Transfer Complete flag
    • [11]TEIF3 (def=0x0) // Channel 3 Transfer Error flag
    • [12]GIF4 (def=0x0) // Channel 4 Global interrupt flag
    • [13]TCIF4 (def=0x0) // Channel 4 Transfer Complete flag
    • [14]HTIF4 (def=0x0) // Channel 4 Half Transfer Complete flag
    • [15]TEIF4 (def=0x0) // Channel 4 Transfer Error flag
    • [16]GIF5 (def=0x0) // Channel 5 Global interrupt flag
    • [17]TCIF5 (def=0x0) // Channel 5 Transfer Complete flag
    • [18]HTIF5 (def=0x0) // Channel 5 Half Transfer Complete flag
    • [19]TEIF5 (def=0x0) // Channel 5 Transfer Error flag
    • [20]GIF6 (def=0x0) // Channel 6 Global interrupt flag
    • [21]TCIF6 (def=0x0) // Channel 6 Transfer Complete flag
    • [22]HTIF6 (def=0x0) // Channel 6 Half Transfer Complete flag
    • [23]TEIF6 (def=0x0) // Channel 6 Transfer Error flag
    • [24]GIF7 (def=0x0) // Channel 7 Global interrupt flag
    • [25]TCIF7 (def=0x0) // Channel 7 Transfer Complete flag
    • [26]HTIF7 (def=0x0) // Channel 7 Half Transfer Complete flag
    • [27]TEIF7 (def=0x0) // Channel 7 Transfer Error flag
    • [28]GIF8 (def=0x0) // Channel 8 Global interrupt flag
    • [29]TCIF8 (def=0x0) // Channel 8 Transfer Complete flag
    • [30]HTIF8 (def=0x0) // Channel 8 Half Transfer Complete flag
    • [31]TEIF8 (def=0x0) // Channel 8 Transfer Error flag
  • 0x40020404INTFCR// DMA interrupt flag clear register (DMA_INTFCR)

    • [0]CGIF1 (def=0x0) // Channel 1 Global interrupt clear
    • [4]CGIF2 (def=0x0) // Channel 2 Global interrupt clear
    • [8]CGIF3 (def=0x0) // Channel 3 Global interrupt clear
    • [12]CGIF4 (def=0x0) // Channel 4 Global interrupt clear
    • [16]CGIF5 (def=0x0) // Channel 5 Global interrupt clear
    • [20]CGIF6 (def=0x0) // Channel 6 Global interrupt clear
    • [24]CGIF7 (def=0x0) // Channel 7 Global interrupt clear
    • [28]CGIF8 (def=0x0) // Channel 8 Global interrupt clear
    • [1]CTCIF1 (def=0x0) // Channel 1 Transfer Complete clear
    • [5]CTCIF2 (def=0x0) // Channel 2 Transfer Complete clear
    • [9]CTCIF3 (def=0x0) // Channel 3 Transfer Complete clear
    • [13]CTCIF4 (def=0x0) // Channel 4 Transfer Complete clear
    • [17]CTCIF5 (def=0x0) // Channel 5 Transfer Complete clear
    • [21]CTCIF6 (def=0x0) // Channel 6 Transfer Complete clear
    • [25]CTCIF7 (def=0x0) // Channel 7 Transfer Complete clear
    • [29]CTCIF8 (def=0x0) // Channel 8 Transfer Complete clear
    • [2]CHTIF1 (def=0x0) // Channel 1 Half Transfer clear
    • [6]CHTIF2 (def=0x0) // Channel 2 Half Transfer clear
    • [10]CHTIF3 (def=0x0) // Channel 3 Half Transfer clear
    • [14]CHTIF4 (def=0x0) // Channel 4 Half Transfer clear
    • [18]CHTIF5 (def=0x0) // Channel 5 Half Transfer clear
    • [22]CHTIF6 (def=0x0) // Channel 6 Half Transfer clear
    • [26]CHTIF7 (def=0x0) // Channel 7 Half Transfer clear
    • [30]CHTIF8 (def=0x0) // Channel 8 Half Transfer clear
    • [3]CTEIF1 (def=0x0) // Channel 1 Transfer Error clear
    • [7]CTEIF2 (def=0x0) // Channel 2 Transfer Error clear
    • [11]CTEIF3 (def=0x0) // Channel 3 Transfer Error clear
    • [15]CTEIF4 (def=0x0) // Channel 4 Transfer Error clear
    • [19]CTEIF5 (def=0x0) // Channel 5 Transfer Error clear
    • [23]CTEIF6 (def=0x0) // Channel 6 Transfer Error clear
    • [27]CTEIF7 (def=0x0) // Channel 7 Transfer Error clear
    • [31]CTEIF8 (def=0x0) // Channel 8 Transfer Error clear
  • 0x40020408CFGR1// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
    • [15]DOUBLE_MODE (def=0x0) // Double buffer mode enable bit
    • [16]FLAG_CUR_MEM (def=0x0) // Memory address selection setting
  • 0x4002040CCNTR1// DMA channel 1 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020410PADDR1// DMA channel 1 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020414MADDR1// DMA channel 1 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020418M1ADDR1// DMA channel 1 memory address1 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x4002041CCFGR2// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020420CNTR2// DMA channel 2 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020424PADDR2// DMA channel 2 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020428MADDR2// DMA channel 2 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002042CM1ADDR2// DMA channel 2 memory address 1 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020430CFGR3// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020434CNTR3// DMA channel 3 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020438PADDR3// DMA channel 3 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x4002043CMADDR3// DMA channel 3 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020440M1ADDR3// DMA channel 3 memory address 1 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020444CFGR4// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020448CNTR4// DMA channel 4 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x4002044CPADDR4// DMA channel 4 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020450MADDR4// DMA channel 4 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020454M1ADDR4// DMA channel 4 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020458CFGR5// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x4002045CCNTR5// DMA channel 5 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020460PADDR5// DMA channel 5 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020464MADDR5// DMA channel 5 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020468M1ADDR5// DMA channel 5 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x4002046CCFGR6// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020470CNTR6// DMA channel 6 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020474PADDR6// DMA channel 6 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x40020478MADDR6// DMA channel 6 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x4002047CM1ADDR6// DMA channel 6 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020480CFGR7// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020484CNTR7// DMA channel 7 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x40020488PADDR7// DMA channel 7 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x4002048CMADDR7// DMA channel 7 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x40020490M1ADDR7// DMA channel 7 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  • 0x40020494CFGR8// DMA channel configuration register (DMA_CFGR)

    • [0]EN (def=0x0) // Channel enable
    • [1]TCIE (def=0x0) // Transfer complete interrupt enable
    • [2]HTIE (def=0x0) // Half Transfer interrupt enable
    • [3]TEIE (def=0x0) // Transfer error interrupt enable
    • [4]DIR (def=0x0) // Data transfer direction
    • [5]CIRC (def=0x0) // Circular mode
    • [6]PINC (def=0x0) // Peripheral increment mode
    • [7]MINC (def=0x0) // Memory increment mode
    • [8:9]PSIZE (def=0x0) // Peripheral size
    • [10:11]MSIZE (def=0x0) // Memory size
    • [12:13]PL (def=0x0) // Channel Priority level
    • [14]MEM2MEM (def=0x0) // Memory to memory mode
  • 0x40020498CNTR8// DMA channel 8 number of data register

    • [0:15]NDT (def=0x0) // Number of data to transfer
  • 0x4002049CPADDR8// DMA channel 8 peripheral address register

    • [0:31]PA (def=0x0) // Peripheral address
  • 0x400204A0MADDR8// DMA channel 8 memory address register

    • [0:31]MA (def=0x0) // Memory address
  • 0x400204A4M1ADDR8// DMA channel 8 memory address 2 register

    • [0:31]M1A (def=0x0) // Memory address
  interrupts:
  • [102] DMA2_CH1 // DMA2 Channel1 global interrupt
  • [103] DMA2_CH2 // DMA2 Channel2 global interrupt
  • [104] DMA2_CH3 // DMA2 Channel3 global interrupt
  • [105] DMA2_CH4 // DMA2 Channel4 global interrupt
  • [106] DMA2_CH5 // DMA2 Channel5 global interrupt
  • [107] DMA2_CH6 // DMA2 Channel6 global interrupt
  • [108] DMA2_CH7 // DMA2 Channel7 global interrupt
  • [109] DMA2_CH8 // DMA2 Channel8 global interrupt
• 0x40020800DMAMUX// DMA request multiplexer

  • 0x40020800DMAMUX1_4_CFGR// DMA request multiplexer channels 1 to 4 configuration registers

    • [0:6]CHANNEL1_MUX (def=0x0) // DMA request multiplexer channels 1 intput to the volunteer configuration
    • [8:14]CHANNEL2_MUX (def=0x0) // DMA request multiplexer channels 2 intput to the volunteer configuration
    • [16:22]CHANNEL3_MUX (def=0x0) // DMA request multiplexer channels 3 intput to the volunteer configuration
    • [24:30]CHANNEL4_MUX (def=0x0) // DMA request multiplexer channels 4 intput to the volunteer configuration
  • 0x40020804DMAMUX5_8_CFGR// DMA request multiplexer channels 5 to 8 configuration registers

    • [0:6]CHANNEL5_MUX (def=0x0) // DMA request multiplexer channels 5 intput to the volunteer configuration
    • [8:14]CHANNEL6_MUX (def=0x0) // DMA request multiplexer channels 6 intput to the volunteer configuration
    • [16:22]CHANNEL7_MUX (def=0x0) // DMA request multiplexer channels 7 intput to the volunteer configuration
    • [24:30]CHANNEL8_MUX (def=0x0) // DMA request multiplexer channels 8 intput to the volunteer configuration
  • 0x40020808DMAMUX9_12_CFGR// DMA request multiplexer channels 9 to 12 configuration registers

    • [0:6]CHANNEL9_MUX (def=0x0) // DMA request multiplexer channels 9 intput to the volunteer configuration
    • [8:14]CHANNEL10_MUX (def=0x0) // DMA request multiplexer channels 10 intput to the volunteer configuration
    • [16:22]CHANNEL11_MUX (def=0x0) // DMA request multiplexer channels 11 intput to the volunteer configuration
    • [24:30]CHANNEL12_MUX (def=0x0) // DMA request multiplexer channels 12 intput to the volunteer configuration
  • 0x4002080CDMAMUX13_16_CFGR// DMA request multiplexer channels 13 to 16 configuration registers

    • [0:6]CHANNEL13_MUX (def=0x0) // DMA request multiplexer channels 13 intput to the volunteer configuration
    • [8:14]CHANNEL14_MUX (def=0x0) // DMA request multiplexer channels 14 intput to the volunteer configuration
    • [16:22]CHANNEL15_MUX (def=0x0) // DMA request multiplexer channels 15 intput to the volunteer configuration
    • [24:30]CHANNEL16_MUX (def=0x0) // DMA request multiplexer channels 16 intput to the volunteer configuration
• 0x1FFFF7E0ESIG// ESIG configuration

  • 0x1FFFF7E0FLACAP// Flash capecity register

    • [0:15]F_SIZE (def=0x0) // F_SIZE/kByte
  • 0x1FFFF7E8UNIID1// UID register

    • [0:31]U_ID (def=0x0) // U_ID value
  • 0x1FFFF7ECUNIID2// UID register

    • [0:31]U_ID (def=0x0) // U_ID value
  • 0x1FFFF7F0UNIID3// Div register

    • [0:31]U_ID (def=0x0) // U_ID value
• 0x40012400ADC1// Analog to digital converter

  • 0x40012400STATR// status register

    • [4]STRT (def=0x0) // Regular channel start flag
    • [3]JSTRT (def=0x0) // Injected channel start flag
    • [2]JEOC (def=0x0) // Injected channel end of conversion
    • [1]EOC (def=0x0) // Regular channel end of conversion
    • [0]AWD (def=0x0) // Analog watchdog flag
  • 0x40012404CTLR1// control register 1/TKEY_V_CTLR

    • [31]SW_PRE (def=0x0) // Channel pre-handoff is closed
    • [30]ANA_RST (def=0x0) // simulation module reset enabled
    • [27:28]PGA (def=0x0) // ADC_PGA
    • [26]BUFEN (def=0x0) // TKEY_BUF_Enable
    • [25]TKITUNE (def=0x0) // TKEY_I enable
    • [24]TKENABLE (def=0x0) // TKEY enable, including TKEY_F and TKEY_V
    • [23]AWDEN (def=0x0) // Analog watchdog enable on regular channels
    • [22]JAWDEN (def=0x0) // Analog watchdog enable on injected channels
    • [16:19]DUALMOD (def=0x0) // Dual mode selection
    • [13:15]DISCNUM (def=0x0) // Discontinuous mode channel count
    • [12]JDISCEN (def=0x0) // Discontinuous mode on injected channels
    • [11]DISCEN (def=0x0) // Discontinuous mode on regular channels
    • [10]JAUTO (def=0x0) // Automatic injected group conversion
    • [9]AWDSGL (def=0x0) // Enable the watchdog on a single channel in scan mode
    • [8]SCAN (def=0x0) // Scan mode enable
    • [7]JEOCIE (def=0x0) // Interrupt enable for injected channels
    • [6]AWDIE (def=0x0) // Analog watchdog interrupt enable
    • [5]EOCIE (def=0x0) // Interrupt enable for EOC
    • [0:4]AWDCH (def=0x0) // Analog watchdog channel select bits
  • 0x40012408CTLR2// control register 2

    • [23]TSVREFE (def=0x0) // Temperature sensor and VREFINT enable
    • [22]SWSTART (def=0x0) // Start conversion of regular channels
    • [21]JSWSTART (def=0x0) // Start conversion of injected channels
    • [20]EXTTRIG (def=0x0) // External trigger conversion mode for regular channels
    • [17:19]EXTSEL (def=0x0) // External event select for regular group
    • [15]JEXTTRIG (def=0x0) // External trigger conversion mode for injected channels
    • [12:14]JEXTSEL (def=0x0) // External event select for injected group
    • [11]ALIGN (def=0x0) // Data alignment
    • [8]DMA (def=0x0) // Direct memory access mode
    • [7]ADC_LP (def=0x0) // ADC low power mode control
    • [6]CAL_AUTO (def=0x0) // the hardware automatic calibration
    • [4:5]CAL_VOL (def=0x0) // calibration voltage configuration
    • [3]RSTCAL (def=0x0) // Reset calibration
    • [2]CAL (def=0x0) // A/D calibration
    • [1]CONT (def=0x0) // Continuous conversion
    • [0]ADON (def=0x0) // A/D converter ON / OFF
  • 0x4001240CSAMPTR1_CHARGE1// sample time register 1

    • [0:2]SMP10_TKCG10 (def=0x0) // Channel 10 sample time selection
    • [3:5]SMP11_TKCG11 (def=0x0) // Channel 11 sample time selection
    • [6:8]SMP12_TKCG12 (def=0x0) // Channel 12 sample time selection
    • [9:11]SMP13_TKCG13 (def=0x0) // Channel 13 sample time selection
    • [12:14]SMP14_TKCG14 (def=0x0) // Channel 14 sample time selection
    • [15:17]SMP15_TKCG15 (def=0x0) // Channel 15 sample time selection
    • [18:20]SMP16 (def=0x0) // Channel 16 sample time selection
    • [21:23]SMP17 (def=0x0) // Channel 17 sample time selection
  • 0x40012410SAMPTR2_CHARGE2// sample time register 2

    • [0:2]SMP0_TKCG0 (def=0x0) // Channel 0 sample time selection
    • [3:5]SMP1_TKCG1 (def=0x0) // Channel 1 sample time selection
    • [6:8]SMP2_TKCG2 (def=0x0) // Channel 2 sample time selection
    • [9:11]SMP3_TKCG3 (def=0x0) // Channel 3 sample time selection
    • [12:14]SMP4_TKCG4 (def=0x0) // Channel 4 sample time selection
    • [15:17]SMP5_TKCG5 (def=0x0) // Channel 5 sample time selection
    • [18:20]SMP6_TKCG6 (def=0x0) // Channel 6 sample time selection
    • [21:23]SMP7_TKCG7 (def=0x0) // Channel 7 sample time selection
    • [24:26]SMP8_TKCG8 (def=0x0) // Channel 8 sample time selection
    • [27:29]SMP9_TKCG9 (def=0x0) // Channel 9 sample time selection
  • 0x40012414IOFR1// injected channel data offset register x

    • [0:11]JOFFSET1 (def=0x0) // Data offset for injected channel x
  • 0x40012418IOFR2// injected channel data offset register x

    • [0:11]JOFFSET2 (def=0x0) // Data offset for injected channel x
  • 0x4001241CIOFR3// injected channel data offset register x

    • [0:11]JOFFSET3 (def=0x0) // Data offset for injected channel x
  • 0x40012420IOFR4// injected channel data offset register x

    • [0:11]JOFFSET4 (def=0x0) // Data offset for injected channel x
  • 0x40012424WDHTR// watchdog higher threshold register

    • [0:11]HT (def=0xFFF) // Analog watchdog higher threshold
  • 0x40012428WDLTR// watchdog lower threshold register

    • [0:11]LT (def=0x0) // Analog watchdog lower threshold
  • 0x4001242CRSQR1// regular sequence register 1

    • [20:23]L (def=0x0) // Regular channel sequence length
    • [15:19]SQ16 (def=0x0) // 16th conversion in regular sequence
    • [10:14]SQ15 (def=0x0) // 15th conversion in regular sequence
    • [5:9]SQ14 (def=0x0) // 14th conversion in regular sequence
    • [0:4]SQ13 (def=0x0) // 13th conversion in regular sequence
  • 0x40012430RSQR2// regular sequence register 2

    • [25:29]SQ12 (def=0x0) // 12th conversion in regular sequence
    • [20:24]SQ11 (def=0x0) // 11th conversion in regular sequence
    • [15:19]SQ10 (def=0x0) // 10th conversion in regular sequence
    • [10:14]SQ9 (def=0x0) // 9th conversion in regular sequence
    • [5:9]SQ8 (def=0x0) // 8th conversion in regular sequence
    • [0:4]SQ7 (def=0x0) // 7th conversion in regular sequence
  • 0x40012434RSQR3// regular sequence register 3

    • [25:29]SQ6 (def=0x0) // 6th conversion in regular sequence
    • [20:24]SQ5 (def=0x0) // 5th conversion in regular sequence
    • [15:19]SQ4 (def=0x0) // 4th conversion in regular sequence
    • [10:14]SQ3 (def=0x0) // 3rd conversion in regular sequence
    • [5:9]SQ2 (def=0x0) // 2nd conversion in regular sequence
    • [0:4]SQ1 (def=0x0) // 1st conversion in regular sequence
  • 0x40012438ISQR// injected sequence register

    • [20:21]JL (def=0x0) // Injected sequence length
    • [15:19]JSQ4 (def=0x0) // 4th conversion in injected sequence
    • [10:14]JSQ3 (def=0x0) // 3rd conversion in injected sequence
    • [5:9]JSQ2 (def=0x0) // 2nd conversion in injected sequence
    • [0:4]JSQ1 (def=0x0) // 1st conversion in injected sequence
  • 0x4001243CIDATAR1_CHGOFFSET// injected data register x_Charge data offset for injected channel x

    • [0:15]IDATA_TKCGOFFSET (def=0x0) // Injected data_Touch key charge data offset for injected channel x
  • 0x40012440IDATAR2// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012444IDATAR3// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012448IDATAR4// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x4001244CRDATAR_DR// regular data register

    • [0:7]DATA0_7 (def=0x0) // Regular data
    • [8:15]DATA8_15 (def=0x0) // Regular data
    • [16:31]ADC2DATA (def=0x0) // converter data
  • 0x4001244CACT_DCG// start and discharge time register

    • [0:15]TKACT_DCG (def=0x0) // Touch key start and discharge time register
  • 0x40012454AUX// ADC time register

    • [0]ADC_SMP_SEL0 (def=0x0) // channel sampling time optional enable bit
    • [1]ADC_SMP_SEL1 (def=0x0) // channel sampling time optional enable bit
    • [2]ADC_SMP_SEL2 (def=0x0) // channel sampling time optional enable bit
    • [3]ADC_SMP_SEL3 (def=0x0) // channel sampling time optional enable bit
    • [4]ADC_SMP_SEL4 (def=0x0) // channel sampling time optional enable bit
    • [5]ADC_SMP_SEL5 (def=0x0) // channel sampling time optional enable bit
    • [6]ADC_SMP_SEL6 (def=0x0) // channel sampling time optional enable bit
    • [7]ADC_SMP_SEL7 (def=0x0) // channel sampling time optional enable bit
    • [8]ADC_SMP_SEL8 (def=0x0) // channel sampling time optional enable bit
    • [9]ADC_SMP_SEL9 (def=0x0) // channel sampling time optional enable bit
    • [10]ADC_SMP_SEL10 (def=0x0) // channel sampling time optional enable bit
    • [11]ADC_SMP_SEL11 (def=0x0) // channel sampling time optional enable bit
    • [12]ADC_SMP_SEL12 (def=0x0) // channel sampling time optional enable bit
    • [13]ADC_SMP_SEL13 (def=0x0) // channel sampling time optional enable bit
    • [14]ADC_SMP_SEL14 (def=0x0) // channel sampling time optional enable bit
    • [15]ADC_SMP_SEL15 (def=0x0) // channel sampling time optional enable bit
    • [16]ADC_SMP_SEL16 (def=0x0) // channel sampling time optional enable bit
    • [17]ADC_SMP_SEL17 (def=0x0) // channel sampling time optional enable bit
    • [31]ADC_TO_DFSDM (def=0x0) // ADC module samples data to DFSDM
  interrupts:
  • [69] ADC // ADC global interrupt
• 0x40012800ADC2//

  • 0x40012858ADC2_DRV// ADC TOUCHKEY shielded register

    • [0:15]TKEY_DRV_OUTEN (def=0x0) // TOUCHKEY shielded each channel enable
    • [16]TKEY_DRV_EN (def=0x0) // TOUCHKEY shielded enable
  • 0x40012800STATR// status register

    • [4]STRT (def=0x0) // Regular channel start flag
    • [3]JSTRT (def=0x0) // Injected channel start flag
    • [2]JEOC (def=0x0) // Injected channel end of conversion
    • [1]EOC (def=0x0) // Regular channel end of conversion
    • [0]AWD (def=0x0) // Analog watchdog flag
  • 0x40012804CTLR1// control register 1/TKEY_V_CTLR

    • [31]SW_PRE (def=0x0) // Channel pre-handoff is closed
    • [30]ANA_RST (def=0x0) // simulation module reset enabled
    • [27:28]PGA (def=0x0) // ADC_PGA
    • [26]BUFEN (def=0x0) // TKEY_BUF_Enable
    • [25]TKITUNE (def=0x0) // TKEY_I enable
    • [24]TKENABLE (def=0x0) // TKEY enable, including TKEY_F and TKEY_V
    • [23]AWDEN (def=0x0) // Analog watchdog enable on regular channels
    • [22]JAWDEN (def=0x0) // Analog watchdog enable on injected channels
    • [16:19]DUALMOD (def=0x0) // Dual mode selection
    • [13:15]DISCNUM (def=0x0) // Discontinuous mode channel count
    • [12]JDISCEN (def=0x0) // Discontinuous mode on injected channels
    • [11]DISCEN (def=0x0) // Discontinuous mode on regular channels
    • [10]JAUTO (def=0x0) // Automatic injected group conversion
    • [9]AWDSGL (def=0x0) // Enable the watchdog on a single channel in scan mode
    • [8]SCAN (def=0x0) // Scan mode enable
    • [7]JEOCIE (def=0x0) // Interrupt enable for injected channels
    • [6]AWDIE (def=0x0) // Analog watchdog interrupt enable
    • [5]EOCIE (def=0x0) // Interrupt enable for EOC
    • [0:4]AWDCH (def=0x0) // Analog watchdog channel select bits
  • 0x40012808CTLR2// control register 2

    • [23]TSVREFE (def=0x0) // Temperature sensor and VREFINT enable
    • [22]SWSTART (def=0x0) // Start conversion of regular channels
    • [21]JSWSTART (def=0x0) // Start conversion of injected channels
    • [20]EXTTRIG (def=0x0) // External trigger conversion mode for regular channels
    • [17:19]EXTSEL (def=0x0) // External event select for regular group
    • [15]JEXTTRIG (def=0x0) // External trigger conversion mode for injected channels
    • [12:14]JEXTSEL (def=0x0) // External event select for injected group
    • [11]ALIGN (def=0x0) // Data alignment
    • [8]DMA (def=0x0) // Direct memory access mode
    • [7]ADC_LP (def=0x0) // ADC low power mode control
    • [6]CAL_AUTO (def=0x0) // the hardware automatic calibration
    • [4:5]CAL_VOL (def=0x0) // calibration voltage configuration
    • [3]RSTCAL (def=0x0) // Reset calibration
    • [2]CAL (def=0x0) // A/D calibration
    • [1]CONT (def=0x0) // Continuous conversion
    • [0]ADON (def=0x0) // A/D converter ON / OFF
  • 0x4001280CSAMPTR1_CHARGE1// sample time register 1

    • [0:2]SMP10_TKCG10 (def=0x0) // Channel 10 sample time selection
    • [3:5]SMP11_TKCG11 (def=0x0) // Channel 11 sample time selection
    • [6:8]SMP12_TKCG12 (def=0x0) // Channel 12 sample time selection
    • [9:11]SMP13_TKCG13 (def=0x0) // Channel 13 sample time selection
    • [12:14]SMP14_TKCG14 (def=0x0) // Channel 14 sample time selection
    • [15:17]SMP15_TKCG15 (def=0x0) // Channel 15 sample time selection
    • [18:20]SMP16 (def=0x0) // Channel 16 sample time selection
    • [21:23]SMP17 (def=0x0) // Channel 17 sample time selection
  • 0x40012810SAMPTR2_CHARGE2// sample time register 2

    • [0:2]SMP0_TKCG0 (def=0x0) // Channel 0 sample time selection
    • [3:5]SMP1_TKCG1 (def=0x0) // Channel 1 sample time selection
    • [6:8]SMP2_TKCG2 (def=0x0) // Channel 2 sample time selection
    • [9:11]SMP3_TKCG3 (def=0x0) // Channel 3 sample time selection
    • [12:14]SMP4_TKCG4 (def=0x0) // Channel 4 sample time selection
    • [15:17]SMP5_TKCG5 (def=0x0) // Channel 5 sample time selection
    • [18:20]SMP6_TKCG6 (def=0x0) // Channel 6 sample time selection
    • [21:23]SMP7_TKCG7 (def=0x0) // Channel 7 sample time selection
    • [24:26]SMP8_TKCG8 (def=0x0) // Channel 8 sample time selection
    • [27:29]SMP9_TKCG9 (def=0x0) // Channel 9 sample time selection
  • 0x40012814IOFR1// injected channel data offset register x

    • [0:11]JOFFSET1 (def=0x0) // Data offset for injected channel x
  • 0x40012818IOFR2// injected channel data offset register x

    • [0:11]JOFFSET2 (def=0x0) // Data offset for injected channel x
  • 0x4001281CIOFR3// injected channel data offset register x

    • [0:11]JOFFSET3 (def=0x0) // Data offset for injected channel x
  • 0x40012820IOFR4// injected channel data offset register x

    • [0:11]JOFFSET4 (def=0x0) // Data offset for injected channel x
  • 0x40012824WDHTR// watchdog higher threshold register

    • [0:11]HT (def=0xFFF) // Analog watchdog higher threshold
  • 0x40012828WDLTR// watchdog lower threshold register

    • [0:11]LT (def=0x0) // Analog watchdog lower threshold
  • 0x4001282CRSQR1// regular sequence register 1

    • [20:23]L (def=0x0) // Regular channel sequence length
    • [15:19]SQ16 (def=0x0) // 16th conversion in regular sequence
    • [10:14]SQ15 (def=0x0) // 15th conversion in regular sequence
    • [5:9]SQ14 (def=0x0) // 14th conversion in regular sequence
    • [0:4]SQ13 (def=0x0) // 13th conversion in regular sequence
  • 0x40012830RSQR2// regular sequence register 2

    • [25:29]SQ12 (def=0x0) // 12th conversion in regular sequence
    • [20:24]SQ11 (def=0x0) // 11th conversion in regular sequence
    • [15:19]SQ10 (def=0x0) // 10th conversion in regular sequence
    • [10:14]SQ9 (def=0x0) // 9th conversion in regular sequence
    • [5:9]SQ8 (def=0x0) // 8th conversion in regular sequence
    • [0:4]SQ7 (def=0x0) // 7th conversion in regular sequence
  • 0x40012834RSQR3// regular sequence register 3

    • [25:29]SQ6 (def=0x0) // 6th conversion in regular sequence
    • [20:24]SQ5 (def=0x0) // 5th conversion in regular sequence
    • [15:19]SQ4 (def=0x0) // 4th conversion in regular sequence
    • [10:14]SQ3 (def=0x0) // 3rd conversion in regular sequence
    • [5:9]SQ2 (def=0x0) // 2nd conversion in regular sequence
    • [0:4]SQ1 (def=0x0) // 1st conversion in regular sequence
  • 0x40012838ISQR// injected sequence register

    • [20:21]JL (def=0x0) // Injected sequence length
    • [15:19]JSQ4 (def=0x0) // 4th conversion in injected sequence
    • [10:14]JSQ3 (def=0x0) // 3rd conversion in injected sequence
    • [5:9]JSQ2 (def=0x0) // 2nd conversion in injected sequence
    • [0:4]JSQ1 (def=0x0) // 1st conversion in injected sequence
  • 0x4001283CIDATAR1_CHGOFFSET// injected data register x_Charge data offset for injected channel x

    • [0:15]IDATA_TKCGOFFSET (def=0x0) // Injected data_Touch key charge data offset for injected channel x
  • 0x40012840IDATAR2// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012844IDATAR3// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x40012848IDATAR4// injected data register x

    • [0:15]JDATA (def=0x0) // Injected data
  • 0x4001284CRDATAR_DR// regular data register

    • [0:7]DATA0_7 (def=0x0) // Regular data
    • [8:15]DATA8_15 (def=0x0) // Regular data
    • [16:31]ADC2DATA (def=0x0) // converter data
  • 0x4001284CACT_DCG// start and discharge time register

    • [0:15]TKACT_DCG (def=0x0) // Touch key start and discharge time register
  • 0x40012854AUX// ADC time register

    • [0]ADC_SMP_SEL0 (def=0x0) // channel sampling time optional enable bit
    • [1]ADC_SMP_SEL1 (def=0x0) // channel sampling time optional enable bit
    • [2]ADC_SMP_SEL2 (def=0x0) // channel sampling time optional enable bit
    • [3]ADC_SMP_SEL3 (def=0x0) // channel sampling time optional enable bit
    • [4]ADC_SMP_SEL4 (def=0x0) // channel sampling time optional enable bit
    • [5]ADC_SMP_SEL5 (def=0x0) // channel sampling time optional enable bit
    • [6]ADC_SMP_SEL6 (def=0x0) // channel sampling time optional enable bit
    • [7]ADC_SMP_SEL7 (def=0x0) // channel sampling time optional enable bit
    • [8]ADC_SMP_SEL8 (def=0x0) // channel sampling time optional enable bit
    • [9]ADC_SMP_SEL9 (def=0x0) // channel sampling time optional enable bit
    • [10]ADC_SMP_SEL10 (def=0x0) // channel sampling time optional enable bit
    • [11]ADC_SMP_SEL11 (def=0x0) // channel sampling time optional enable bit
    • [12]ADC_SMP_SEL12 (def=0x0) // channel sampling time optional enable bit
    • [13]ADC_SMP_SEL13 (def=0x0) // channel sampling time optional enable bit
    • [14]ADC_SMP_SEL14 (def=0x0) // channel sampling time optional enable bit
    • [15]ADC_SMP_SEL15 (def=0x0) // channel sampling time optional enable bit
    • [16]ADC_SMP_SEL16 (def=0x0) // channel sampling time optional enable bit
    • [17]ADC_SMP_SEL17 (def=0x0) // channel sampling time optional enable bit
    • [31]ADC_TO_DFSDM (def=0x0) // ADC module samples data to DFSDM
• 0x40012C00TIM1// Advanced timer

  • 0x40012C00CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40012C04CTLR2// control register 2

    • [14]OIS4 (def=0x0) // Output Idle state 4
    • [13]OIS3N (def=0x0) // Output Idle state 3
    • [12]OIS3 (def=0x0) // Output Idle state 3
    • [11]OIS2N (def=0x0) // Output Idle state 2
    • [10]OIS2 (def=0x0) // Output Idle state 2
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x40012C08SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x40012C0CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40012C10INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [7]BIF (def=0x0) // Break interrupt flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40012C14SWEVGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [6]TG (def=0x0) // Trigger generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40012C18CHCTLR1_Output// capture/compare mode register (output mode)

    • [15]OC2CE (def=0x0) // Output Compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40012C18CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PCS (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40012C1CCHCTLR2_Output// capture/compare mode register (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40012C1CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/compare 3 selection
  • 0x40012C20CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [10]CC3NE (def=0x0) // Capture/Compare 3 complementary output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [6]CC2NE (def=0x0) // Capture/Compare 2 complementary output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40012C24CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40012C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x40012C2CATRLR// auto-reload register

    • [0:15]ATRLR (def=0xFFFF) // Auto-reload value
  • 0x40012C30RPTCR// repetition counter register

    • [0:7]RPTCR (def=0x0) // Repetition counter value
  • 0x40012C34CH1CVR// capture/compare register 1

    • [0:15]CH1CVR (def=0x0) // Capture/Compare 1 value
    • [16]LEVEL1 (def=0x0) // Level indicating bit
  • 0x40012C38CH2CVR// capture/compare register 2

    • [0:15]CH2CVR (def=0x0) // Capture/Compare 2 value
    • [16]LEVEL2 (def=0x0) // Level indicating bit
  • 0x40012C3CCH3CVR// capture/compare register 3

    • [0:15]CH3CVR (def=0x0) // Capture/Compare value
    • [16]LEVEL3 (def=0x0) // Level indicating bit
  • 0x40012C40CH4CVR// capture/compare register 4

    • [0:15]CH4CVR (def=0x0) // Capture/Compare value
    • [16]LEVEL4 (def=0x0) // Level indicating bit
  • 0x40012C44BDTR// break and dead-time register

    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  • 0x40012C48DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x40012C4CDMAADR// DMA address for full transfer

    • [0:15]DMAB (def=0x0) // DMA register for burst accesses
  • 0x40012C50AUX// Double-side egde capture register

    • [0]CAP_ED_CH2 (def=0x0) // Double-side egde capture is enable for channel2
    • [1]CAP_ED_CH3 (def=0x0) // Double-side egde capture is enable for channel3
    • [2]CAP_ED_CH4 (def=0x0) // Double-side egde capture is enable for channel4
    • [3:5]BK_SEL (def=0x0) // Break source selection
    • [6]DT_MODE (def=0x0) // The dead-time duration of the DT_VLU2 enabled setting occurs on the rising edge of OCXREF
    • [7]DTN_MODE (def=0x0) // The dead-time duration of the DT_VLU2 enabled setting occurs on the falling edge of OCXREF
    • [8:15]DT_VLU2 (def=0x0) // set the duration of the dead zone
  interrupts:
  • [70] TIM1_BRK // TIM1 Break interrupt
  • [71] TIM1_UP_ // TIM1 Update interrupt
  • [72] TIM1_TRG_COM // TIM1 Trigger and Commutation interrupts
  • [73] TIM1_CC // TIM1 Capture Compare interrupt
• 0x40013400TIM8//

  • 0x40013400CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40013404CTLR2// control register 2

    • [14]OIS4 (def=0x0) // Output Idle state 4
    • [13]OIS3N (def=0x0) // Output Idle state 3
    • [12]OIS3 (def=0x0) // Output Idle state 3
    • [11]OIS2N (def=0x0) // Output Idle state 2
    • [10]OIS2 (def=0x0) // Output Idle state 2
    • [9]OIS1N (def=0x0) // Output Idle state 1
    • [8]OIS1 (def=0x0) // Output Idle state 1
    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [2]CCUS (def=0x0) // Capture/compare control update selection
    • [0]CCPC (def=0x0) // Capture/compare preloaded control
  • 0x40013408SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4001340CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [13]COMDE (def=0x0) // COM DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [7]BIE (def=0x0) // Break interrupt enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [5]COMIE (def=0x0) // COM interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40013410INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [7]BIF (def=0x0) // Break interrupt flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [5]COMIF (def=0x0) // COM interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40013414SWEVGR// event generation register

    • [7]BG (def=0x0) // Break generation
    • [6]TG (def=0x0) // Trigger generation
    • [5]COMG (def=0x0) // Capture/Compare control update generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40013418CHCTLR1_Output// capture/compare mode register (output mode)

    • [15]OC2CE (def=0x0) // Output Compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output Compare 2 mode
    • [11]OC2PE (def=0x0) // Output Compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output Compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output Compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output Compare 1 mode
    • [3]OC1PE (def=0x0) // Output Compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output Compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40013418CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PCS (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4001341CCHCTLR2_Output// capture/compare mode register (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4001341CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/compare 3 selection
  • 0x40013420CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [11]CC3NP (def=0x0) // Capture/Compare 3 output Polarity
    • [10]CC3NE (def=0x0) // Capture/Compare 3 complementary output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [7]CC2NP (def=0x0) // Capture/Compare 2 output Polarity
    • [6]CC2NE (def=0x0) // Capture/Compare 2 complementary output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [3]CC1NP (def=0x0) // Capture/Compare 1 output Polarity
    • [2]CC1NE (def=0x0) // Capture/Compare 1 complementary output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40013424CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40013428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4001342CATRLR// auto-reload register

    • [0:15]ATRLR (def=0xFFFF) // Auto-reload value
  • 0x40013430RPTCR// repetition counter register

    • [0:7]RPTCR (def=0x0) // Repetition counter value
  • 0x40013434CH1CVR// capture/compare register 1

    • [0:15]CH1CVR (def=0x0) // Capture/Compare 1 value
    • [16]LEVEL1 (def=0x0) // Level indicating bit
  • 0x40013438CH2CVR// capture/compare register 2

    • [0:15]CH2CVR (def=0x0) // Capture/Compare 2 value
    • [16]LEVEL2 (def=0x0) // Level indicating bit
  • 0x4001343CCH3CVR// capture/compare register 3

    • [0:15]CH3CVR (def=0x0) // Capture/Compare value
    • [16]LEVEL3 (def=0x0) // Level indicating bit
  • 0x40013440CH4CVR// capture/compare register 4

    • [0:15]CH4CVR (def=0x0) // Capture/Compare value
    • [16]LEVEL4 (def=0x0) // Level indicating bit
  • 0x40013444BDTR// break and dead-time register

    • [15]MOE (def=0x0) // Main output enable
    • [14]AOE (def=0x0) // Automatic output enable
    • [13]BKP (def=0x0) // Break polarity
    • [12]BKE (def=0x0) // Break enable
    • [11]OSSR (def=0x0) // Off-state selection for Run mode
    • [10]OSSI (def=0x0) // Off-state selection for Idle mode
    • [8:9]LOCK (def=0x0) // Lock configuration
    • [0:7]DTG (def=0x0) // Dead-time generator setup
  • 0x40013448DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4001344CDMAADR// DMA address for full transfer

    • [0:15]DMAB (def=0x0) // DMA register for burst accesses
  • 0x40013450AUX// Double-side egde capture register

    • [0]CAP_ED_CH2 (def=0x0) // Double-side egde capture is enable for channel2
    • [1]CAP_ED_CH3 (def=0x0) // Double-side egde capture is enable for channel3
    • [2]CAP_ED_CH4 (def=0x0) // Double-side egde capture is enable for channel4
    • [3:5]BK_SEL (def=0x0) // Break source selection
    • [6]DT_MODE (def=0x0) // The dead-time duration of the DT_VLU2 enabled setting occurs on the rising edge of OCXREF
    • [7]DTN_MODE (def=0x0) // The dead-time duration of the DT_VLU2 enabled setting occurs on the falling edge of OCXREF
    • [8:15]DT_VLU2 (def=0x0) // set the duration of the dead zone
  interrupts:
  • [86] TIM8_BRK // TIM8 Break interrupt
  • [87] TIM8_UP // TIM8 Update interrupt
  • [88] TIM8_TRG_COM // TIM8 Trigger and Commutation interrupts
  • [89] TIM8_CC // TIM8 Capture Compare interrupt
• 0x40000000TIM2// General purpose timer

  • 0x40000000CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000004CTLR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [0]CCPC (def=0x0) // Compare selection
  • 0x40000008SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000000CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000010INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000014SWEVGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000018CHCTLR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000018CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4000001CCHCTLR2_Output// capture/compare mode register 2 (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4000001CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000020CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000024CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40000028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000002CATRLR// auto-reload register

    • [0:15]ARR (def=0xFFFF) // Auto-reload value
  • 0x40000034CH1CVR// capture/compare register 1

    • [0:15]CH1CVR (def=0x0) // Capture/Compare 1 value
    • [16]LEVEL1 (def=0x0) // Level indicating bit
  • 0x40000038CH2CVR// capture/compare register 2

    • [0:15]CH2CVR (def=0x0) // Capture/Compare 2 value
    • [16]LEVEL2 (def=0x0) // Level indicating bit
  • 0x4000003CCH3CVR// capture/compare register 3

    • [0:15]CH3CVR (def=0x0) // Capture/Compare 3 value
    • [16]LEVEL3 (def=0x0) // Level indicating bit
  • 0x40000040CH4CVR// capture/compare register 4

    • [0:15]CH4CVR (def=0x0) // Capture/Compare 4 value
    • [16]LEVEL4 (def=0x0) // Level indicating bit
  • 0x40000048DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4000004CDMAADR// DMA address for full transfer

    • [0:15]DMAADR (def=0x0) // DMA register for burst accesses
  • 0x40000050AUX// Double-side egde capture register

    • [0]CAP_ED_CH2 (def=0x0) // Double-side egde capture is enable for channel2
    • [1]CAP_ED_CH3 (def=0x0) // Double-side egde capture is enable for channel3
    • [2]CAP_ED_CH4 (def=0x0) // Double-side egde capture is enable for channel4
  interrupts:
  • [74] TIM2 // TIM2 global interrupt
• 0x40000400TIM3//

  • 0x40000400CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000404CTLR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [0]CCPC (def=0x0) // Compare selection
  • 0x40000408SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000040CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000410INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000414SWEVGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000418CHCTLR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000418CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4000041CCHCTLR2_Output// capture/compare mode register 2 (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4000041CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000420CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000424CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40000428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000042CATRLR// auto-reload register

    • [0:15]ARR (def=0xFFFF) // Auto-reload value
  • 0x40000434CH1CVR// capture/compare register 1

    • [0:15]CH1CVR (def=0x0) // Capture/Compare 1 value
    • [16]LEVEL1 (def=0x0) // Level indicating bit
  • 0x40000438CH2CVR// capture/compare register 2

    • [0:15]CH2CVR (def=0x0) // Capture/Compare 2 value
    • [16]LEVEL2 (def=0x0) // Level indicating bit
  • 0x4000043CCH3CVR// capture/compare register 3

    • [0:15]CH3CVR (def=0x0) // Capture/Compare 3 value
    • [16]LEVEL3 (def=0x0) // Level indicating bit
  • 0x40000440CH4CVR// capture/compare register 4

    • [0:15]CH4CVR (def=0x0) // Capture/Compare 4 value
    • [16]LEVEL4 (def=0x0) // Level indicating bit
  • 0x40000448DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4000044CDMAADR// DMA address for full transfer

    • [0:15]DMAADR (def=0x0) // DMA register for burst accesses
  • 0x40000450AUX// Double-side egde capture register

    • [0]CAP_ED_CH2 (def=0x0) // Double-side egde capture is enable for channel2
    • [1]CAP_ED_CH3 (def=0x0) // Double-side egde capture is enable for channel3
    • [2]CAP_ED_CH4 (def=0x0) // Double-side egde capture is enable for channel4
  interrupts:
  • [75] TIM3 // TIM3 global interrupt
• 0x40000800TIM4//

  • 0x40000800CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000804CTLR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [0]CCPC (def=0x0) // Compare selection
  • 0x40000808SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4000080CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000810INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000814SWEVGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000818CHCTLR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000818CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4000081CCHCTLR2_Output// capture/compare mode register 2 (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4000081CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000820CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000824CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40000828PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000082CATRLR// auto-reload register

    • [0:15]ARR (def=0xFFFF) // Auto-reload value
  • 0x40000834CH1CVR// capture/compare register 1

    • [0:15]CH1CVR (def=0x0) // Capture/Compare 1 value
    • [16]LEVEL1 (def=0x0) // Level indicating bit
  • 0x40000838CH2CVR// capture/compare register 2

    • [0:15]CH2CVR (def=0x0) // Capture/Compare 2 value
    • [16]LEVEL2 (def=0x0) // Level indicating bit
  • 0x4000083CCH3CVR// capture/compare register 3

    • [0:15]CH3CVR (def=0x0) // Capture/Compare 3 value
    • [16]LEVEL3 (def=0x0) // Level indicating bit
  • 0x40000840CH4CVR// capture/compare register 4

    • [0:15]CH4CVR (def=0x0) // Capture/Compare 4 value
    • [16]LEVEL4 (def=0x0) // Level indicating bit
  • 0x40000848DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4000084CDMAADR// DMA address for full transfer

    • [0:15]DMAADR (def=0x0) // DMA register for burst accesses
  • 0x40000850AUX// Double-side egde capture register

    • [0]CAP_ED_CH2 (def=0x0) // Double-side egde capture is enable for channel2
    • [1]CAP_ED_CH3 (def=0x0) // Double-side egde capture is enable for channel3
    • [2]CAP_ED_CH4 (def=0x0) // Double-side egde capture is enable for channel4
  interrupts:
  • [76] TIM4 // TIM4 global interrupt
• 0x40000C00TIM5//

  • 0x40000C00CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40000C04CTLR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [0]CCPC (def=0x0) // Compare selection
  • 0x40000C08SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x40000C0CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40000C10INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40000C14SWEVGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40000C18CHCTLR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000C18CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40000C1CCHCTLR2_Output// capture/compare mode register 2 (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000C1CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40000C20CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40000C24CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40000C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x40000C2CATRLR// auto-reload register

    • [0:15]ARR (def=0xFFFF) // Auto-reload value
  • 0x40000C34CH1CVR// capture/compare register 1

    • [0:15]CH1CVR (def=0x0) // Capture/Compare 1 value
    • [16]LEVEL1 (def=0x0) // Level indicating bit
  • 0x40000C38CH2CVR// capture/compare register 2

    • [0:15]CH2CVR (def=0x0) // Capture/Compare 2 value
    • [16]LEVEL2 (def=0x0) // Level indicating bit
  • 0x40000C3CCH3CVR// capture/compare register 3

    • [0:15]CH3CVR (def=0x0) // Capture/Compare 3 value
    • [16]LEVEL3 (def=0x0) // Level indicating bit
  • 0x40000C40CH4CVR// capture/compare register 4

    • [0:15]CH4CVR (def=0x0) // Capture/Compare 4 value
    • [16]LEVEL4 (def=0x0) // Level indicating bit
  • 0x40000C48DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x40000C4CDMAADR// DMA address for full transfer

    • [0:15]DMAADR (def=0x0) // DMA register for burst accesses
  • 0x40000C50AUX// Double-side egde capture register

    • [0]CAP_ED_CH2 (def=0x0) // Double-side egde capture is enable for channel2
    • [1]CAP_ED_CH3 (def=0x0) // Double-side egde capture is enable for channel3
    • [2]CAP_ED_CH4 (def=0x0) // Double-side egde capture is enable for channel4
  interrupts:
  • [77] TIM5 // TIM5 global interrupt
• 0x40014C00TIM9// General purpose timer

  • 0x40014C00CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40014C04CTLR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [0]CCPC (def=0x0) // Compare selection
  • 0x40014C08SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x40014C0CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40014C10INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40014C14SWEVGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40014C18CHCTLR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014C18CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40014C1CCHCTLR2_Output// capture/compare mode register 2 (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40014C1CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40014C20CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40014C24CNT// counter

    • [0:31]CNT (def=0x0) // counter value
  • 0x40014C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x40014C2CATRLR// auto-reload register

    • [0:31]ARR (def=0xFFFF) // Auto-reload value
  • 0x40014C34CH1CVR// capture/compare register 1

    • [0:31]CH1CVR (def=0x0) // Capture/Compare 1 value
  • 0x40014C38CH2CVR// capture/compare register 2

    • [0:31]CH2CVR (def=0x0) // Capture/Compare 2 value
  • 0x40014C3CCH3CVR// capture/compare register 3

    • [0:31]CH3CVR (def=0x0) // Capture/Compare 3 value
  • 0x40014C40CH4CVR// capture/compare register 4

    • [0:31]CH4CVR (def=0x0) // Capture/Compare 4 value
  • 0x40014C48DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x40014C4CDMAADR// DMA address for full transfer

    • [0:15]DMAADR (def=0x0) // DMA register for burst accesses
  interrupts:
  • [90] TIM9 // TIM9 global interrupt
• 0x40015000TIM10//

  • 0x40015000CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40015004CTLR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [0]CCPC (def=0x0) // Compare selection
  • 0x40015008SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4001500CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40015010INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40015014SWEVGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40015018CHCTLR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40015018CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4001501CCHCTLR2_Output// capture/compare mode register 2 (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4001501CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40015020CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40015024CNT// counter

    • [0:31]CNT (def=0x0) // counter value
  • 0x40015028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4001502CATRLR// auto-reload register

    • [0:31]ARR (def=0xFFFF) // Auto-reload value
  • 0x40015034CH1CVR// capture/compare register 1

    • [0:31]CH1CVR (def=0x0) // Capture/Compare 1 value
  • 0x40015038CH2CVR// capture/compare register 2

    • [0:31]CH2CVR (def=0x0) // Capture/Compare 2 value
  • 0x4001503CCH3CVR// capture/compare register 3

    • [0:31]CH3CVR (def=0x0) // Capture/Compare 3 value
  • 0x40015040CH4CVR// capture/compare register 4

    • [0:31]CH4CVR (def=0x0) // Capture/Compare 4 value
  • 0x40015048DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4001504CDMAADR// DMA address for full transfer

    • [0:15]DMAADR (def=0x0) // DMA register for burst accesses
  interrupts:
  • [91] TIM10 // TIM10 global interrupt
• 0x40015400TIM11//

  • 0x40015400CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40015404CTLR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [0]CCPC (def=0x0) // Compare selection
  • 0x40015408SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x4001540CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40015410INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40015414SWEVGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40015418CHCTLR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40015418CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x4001541CCHCTLR2_Output// capture/compare mode register 2 (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x4001541CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40015420CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40015424CNT// counter

    • [0:31]CNT (def=0x0) // counter value
  • 0x40015428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4001542CATRLR// auto-reload register

    • [0:31]ARR (def=0xFFFF) // Auto-reload value
  • 0x40015434CH1CVR// capture/compare register 1

    • [0:31]CH1CVR (def=0x0) // Capture/Compare 1 value
  • 0x40015438CH2CVR// capture/compare register 2

    • [0:31]CH2CVR (def=0x0) // Capture/Compare 2 value
  • 0x4001543CCH3CVR// capture/compare register 3

    • [0:31]CH3CVR (def=0x0) // Capture/Compare 3 value
  • 0x40015440CH4CVR// capture/compare register 4

    • [0:31]CH4CVR (def=0x0) // Capture/Compare 4 value
  • 0x40015448DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x4001544CDMAADR// DMA address for full transfer

    • [0:15]DMAADR (def=0x0) // DMA register for burst accesses
  interrupts:
  • [92] TIM11 // TIM11 global interrupt
• 0x40013C00TIM12//

  • 0x40013C00CTLR1// control register 1

    • [15]CAPLVL (def=0x0) // Timer capture level indication enable
    • [14]CAPOV (def=0x0) // Timer capture value configuration enable
    • [8:9]CKD (def=0x0) // Clock division
    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [5:6]CMS (def=0x0) // Center-aligned mode selection
    • [4]DIR (def=0x0) // Direction
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40013C04CTLR2// control register 2

    • [7]TI1S (def=0x0) // TI1 selection
    • [4:6]MMS (def=0x0) // Master mode selection
    • [3]CCDS (def=0x0) // Capture/compare DMA selection
    • [0]CCPC (def=0x0) // Compare selection
  • 0x40013C08SMCFGR// slave mode control register

    • [15]ETP (def=0x0) // External trigger polarity
    • [14]ECE (def=0x0) // External clock enable
    • [12:13]ETPS (def=0x0) // External trigger prescaler
    • [8:11]ETF (def=0x0) // External trigger filter
    • [7]MSM (def=0x0) // Master/Slave mode
    • [4:6]TS (def=0x0) // Trigger selection
    • [0:2]SMS (def=0x0) // Slave mode selection
  • 0x40013C0CDMAINTENR// DMA/Interrupt enable register

    • [14]TDE (def=0x0) // Trigger DMA request enable
    • [12]CC4DE (def=0x0) // Capture/Compare 4 DMA request enable
    • [11]CC3DE (def=0x0) // Capture/Compare 3 DMA request enable
    • [10]CC2DE (def=0x0) // Capture/Compare 2 DMA request enable
    • [9]CC1DE (def=0x0) // Capture/Compare 1 DMA request enable
    • [8]UDE (def=0x0) // Update DMA request enable
    • [6]TIE (def=0x0) // Trigger interrupt enable
    • [4]CC4IE (def=0x0) // Capture/Compare 4 interrupt enable
    • [3]CC3IE (def=0x0) // Capture/Compare 3 interrupt enable
    • [2]CC2IE (def=0x0) // Capture/Compare 2 interrupt enable
    • [1]CC1IE (def=0x0) // Capture/Compare 1 interrupt enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40013C10INTFR// status register

    • [12]CC4OF (def=0x0) // Capture/Compare 4 overcapture flag
    • [11]CC3OF (def=0x0) // Capture/Compare 3 overcapture flag
    • [10]CC2OF (def=0x0) // Capture/compare 2 overcapture flag
    • [9]CC1OF (def=0x0) // Capture/Compare 1 overcapture flag
    • [6]TIF (def=0x0) // Trigger interrupt flag
    • [4]CC4IF (def=0x0) // Capture/Compare 4 interrupt flag
    • [3]CC3IF (def=0x0) // Capture/Compare 3 interrupt flag
    • [2]CC2IF (def=0x0) // Capture/Compare 2 interrupt flag
    • [1]CC1IF (def=0x0) // Capture/compare 1 interrupt flag
    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40013C14SWEVGR// event generation register

    • [6]TG (def=0x0) // Trigger generation
    • [4]CC4G (def=0x0) // Capture/compare 4 generation
    • [3]CC3G (def=0x0) // Capture/compare 3 generation
    • [2]CC2G (def=0x0) // Capture/compare 2 generation
    • [1]CC1G (def=0x0) // Capture/compare 1 generation
    • [0]UG (def=0x0) // Update generation
  • 0x40013C18CHCTLR1_Output// capture/compare mode register 1 (output mode)

    • [15]OC2CE (def=0x0) // Output compare 2 clear enable
    • [12:14]OC2M (def=0x0) // Output compare 2 mode
    • [11]OC2PE (def=0x0) // Output compare 2 preload enable
    • [10]OC2FE (def=0x0) // Output compare 2 fast enable
    • [8:9]CC2S (def=0x0) // Capture/Compare 2 selection
    • [7]OC1CE (def=0x0) // Output compare 1 clear enable
    • [4:6]OC1M (def=0x0) // Output compare 1 mode
    • [3]OC1PE (def=0x0) // Output compare 1 preload enable
    • [2]OC1FE (def=0x0) // Output compare 1 fast enable
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40013C18CHCTLR1_Input// capture/compare mode register 1 (input mode)

    • [12:15]IC2F (def=0x0) // Input capture 2 filter
    • [10:11]IC2PSC (def=0x0) // Input capture 2 prescaler
    • [8:9]CC2S (def=0x0) // Capture/compare 2 selection
    • [4:7]IC1F (def=0x0) // Input capture 1 filter
    • [2:3]IC1PSC (def=0x0) // Input capture 1 prescaler
    • [0:1]CC1S (def=0x0) // Capture/Compare 1 selection
  • 0x40013C1CCHCTLR2_Output// capture/compare mode register 2 (output mode)

    • [15]OC4CE (def=0x0) // Output compare 4 clear enable
    • [12:14]OC4M (def=0x0) // Output compare 4 mode
    • [11]OC4PE (def=0x0) // Output compare 4 preload enable
    • [10]OC4FE (def=0x0) // Output compare 4 fast enable
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [7]OC3CE (def=0x0) // Output compare 3 clear enable
    • [4:6]OC3M (def=0x0) // Output compare 3 mode
    • [3]OC3PE (def=0x0) // Output compare 3 preload enable
    • [2]OC3FE (def=0x0) // Output compare 3 fast enable
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40013C1CCHCTLR2_Input// capture/compare mode register 2 (input mode)

    • [12:15]IC4F (def=0x0) // Input capture 4 filter
    • [10:11]IC4PSC (def=0x0) // Input capture 4 prescaler
    • [8:9]CC4S (def=0x0) // Capture/Compare 4 selection
    • [4:7]IC3F (def=0x0) // Input capture 3 filter
    • [2:3]IC3PSC (def=0x0) // Input capture 3 prescaler
    • [0:1]CC3S (def=0x0) // Capture/Compare 3 selection
  • 0x40013C20CCER// capture/compare enable register

    • [13]CC4P (def=0x0) // Capture/Compare 3 output Polarity
    • [12]CC4E (def=0x0) // Capture/Compare 4 output enable
    • [9]CC3P (def=0x0) // Capture/Compare 3 output Polarity
    • [8]CC3E (def=0x0) // Capture/Compare 3 output enable
    • [5]CC2P (def=0x0) // Capture/Compare 2 output Polarity
    • [4]CC2E (def=0x0) // Capture/Compare 2 output enable
    • [1]CC1P (def=0x0) // Capture/Compare 1 output Polarity
    • [0]CC1E (def=0x0) // Capture/Compare 1 output enable
  • 0x40013C24CNT// counter

    • [0:31]CNT (def=0x0) // counter value
  • 0x40013C28PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x40013C2CATRLR// auto-reload register

    • [0:31]ARR (def=0xFFFF) // Auto-reload value
  • 0x40013C34CH1CVR// capture/compare register 1

    • [0:31]CH1CVR (def=0x0) // Capture/Compare 1 value
  • 0x40013C38CH2CVR// capture/compare register 2

    • [0:31]CH2CVR (def=0x0) // Capture/Compare 2 value
  • 0x40013C3CCH3CVR// capture/compare register 3

    • [0:31]CH3CVR (def=0x0) // Capture/Compare 3 value
  • 0x40013C40CH4CVR// capture/compare register 4

    • [0:31]CH4CVR (def=0x0) // Capture/Compare 4 value
  • 0x40013C48DMACFGR// DMA control register

    • [8:12]DBL (def=0x0) // DMA burst length
    • [0:4]DBA (def=0x0) // DMA base address
  • 0x40013C4CDMAADR// DMA address for full transfer

    • [0:15]DMAADR (def=0x0) // DMA register for burst accesses
  interrupts:
  • [93] TIM12 // TIM12 global interrupt
• 0x40001000TIM6// Basic timer

  • 0x40001000CTLR1// control register 1

    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40001004CTLR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x4000100CDMAINTENR// DMA/Interrupt enable register

    • [8]UDE (def=0x0) // Update DMA request enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40001010INTFR// status register

    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40001014SWEVGR// event generation register

    • [0]UG (def=0x0) // Update generation
  • 0x40001024CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40001028PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000102CATRLR// auto-reload register

    • [0:15]ARR (def=0xFFFF) // Auto-reload value
  interrupts:
  • [100] TIM6 // TIM6 global interrupt
• 0x40001400TIM7//

  • 0x40001400CTLR1// control register 1

    • [7]ARPE (def=0x0) // Auto-reload preload enable
    • [3]OPM (def=0x0) // One-pulse mode
    • [2]URS (def=0x0) // Update request source
    • [1]UDIS (def=0x0) // Update disable
    • [0]CEN (def=0x0) // Counter enable
  • 0x40001404CTLR2// control register 2

    • [4:6]MMS (def=0x0) // Master mode selection
  • 0x4000140CDMAINTENR// DMA/Interrupt enable register

    • [8]UDE (def=0x0) // Update DMA request enable
    • [0]UIE (def=0x0) // Update interrupt enable
  • 0x40001410INTFR// status register

    • [0]UIF (def=0x0) // Update interrupt flag
  • 0x40001414SWEVGR// event generation register

    • [0]UG (def=0x0) // Update generation
  • 0x40001424CNT// counter

    • [0:15]CNT (def=0x0) // counter value
  • 0x40001428PSC// prescaler

    • [0:15]PSC (def=0x0) // Prescaler value
  • 0x4000142CATRLR// auto-reload register

    • [0:15]ARR (def=0xFFFF) // Auto-reload value
  interrupts:
  • [101] TIM7 // TIM7 global interrupt
• 0x40002400LPTIM1// Low-power timer 1

  • 0x40002400ISR// interrupt status register

    • [7]DIR_SYNC (def=0x0) // direction of count
    • [6]DOWN (def=0x0) // count down
    • [5]UP (def=0x0) // count-up
    • [4]ARROK (def=0x0) // Aoto-reload register data update successfully
    • [3]CMPOK (def=0x0) // compare register data update successfully
    • [2]EXTTRIG (def=0x0) // Edge event are triggerd externally
    • [1]ARRM (def=0x0) // DATA of Aoto-reload register and LPTIM_CNT match
    • [0]CMPM (def=0x0) // DATA of compare register and LPTIM_CNT match
  • 0x40002404ICR// interrupt clear register

    • [6]DOWNCF (def=0x0) // clear down flag
    • [5]UPCF (def=0x0) // clear up flag
    • [4]ARROKCF (def=0x0) // clear Aoto-reload register data update flag
    • [3]CMPOKCF (def=0x0) // clear compare register data update flag
    • [2]EXTTRIGCF (def=0x0) // clear Edge event are triggerd externally flag
    • [1]ARRMCF (def=0x0) // clear Aoto-reload register match flag
    • [0]CMPMCF (def=0x0) // clear compare register match flag
  • 0x40002408IER// interrupt enable register

    • [6]DOWNIE (def=0x0) // Down interrupt enable
    • [5]UPIE (def=0x0) // UP interrupt enable
    • [4]ARROKIE (def=0x0) // Aoto-reload register data update successfully interrupts enable
    • [3]CMPOKIE (def=0x0) // compare register data update successfully interrupts enable
    • [2]EXTTRIGIE (def=0x0) // Edge event are triggerd externally successfully interrupts enable
    • [1]ARRMIE (def=0x0) // Aoto-reload register match successfully interrupts enable
    • [0]CMPMIE (def=0x0) // compare register match successfully interrupts enable
  • 0x4000240CCFGR// configuration register

    • [27]FORCE_PWM (def=0x0) // Forcing pwm output
    • [25:26]CLKMX_SEL (def=0x0) // clock selection
    • [24]ENC (def=0x0) // coder mode
    • [23]COUNTMODE (def=0x0) // count clock selection
    • [22]PRELOAD (def=0x0) // update mode control
    • [21]WAVPOL (def=0x0) // PWM polarity
    • [20]WAVE (def=0x0) // PWM
    • [19]TIMOUT (def=0x0) // TIMEOUT control
    • [17:18]TRIGEN (def=0x0) // trigger configuration
    • [13]TRIGSEL (def=0x0) // trigger source selection
    • [9:11]PRESC (def=0x0) // prescaler configuration
    • [6:7]TRGFLT (def=0x0) // digital filter for flip-flops
    • [3:4]CKFLT (def=0x0) // digital filter for ex-clock
    • [1:2]CKPOL (def=0x0) // configure effective edges
    • [0]CKSEL (def=0x0) // effective edge configuration
  • 0x40002410CR// control register

    • [4]DIR_EXTEN (def=0x0) // externally trigger count direction enable
    • [3]OUTEN (def=0x0) // pwm output enable
    • [2]CNTSTRT (def=0x0) // start in continuous mode
    • [1]SNGSTRT (def=0x0) // start in one trigger mode
    • [0]ENABLE (def=0x0) // timer enable
  • 0x40002414CMP// compare register

    • [0:15]CMP (def=0x0) // compare value
  • 0x40002418ARR// aoto-reload register

    • [0:15]ARR (def=0x1) // aoto-reload count value
  • 0x4000241CCNT// COUNT register

    • [0:15]COUNT (def=0x0) // Timer count value
  interrupts:
  • [141] LPTIM1WakeUP // LPTIM wake-up interrupt
  • [96] LPTIM1 // LPTIM global interrupt
• 0x40003400LPTIM2//

  • 0x40003400ISR// interrupt status register

    • [7]DIR_SYNC (def=0x0) // direction of count
    • [6]DOWN (def=0x0) // count down
    • [5]UP (def=0x0) // count-up
    • [4]ARROK (def=0x0) // Aoto-reload register data update successfully
    • [3]CMPOK (def=0x0) // compare register data update successfully
    • [2]EXTTRIG (def=0x0) // Edge event are triggerd externally
    • [1]ARRM (def=0x0) // DATA of Aoto-reload register and LPTIM_CNT match
    • [0]CMPM (def=0x0) // DATA of compare register and LPTIM_CNT match
  • 0x40003404ICR// interrupt clear register

    • [6]DOWNCF (def=0x0) // clear down flag
    • [5]UPCF (def=0x0) // clear up flag
    • [4]ARROKCF (def=0x0) // clear Aoto-reload register data update flag
    • [3]CMPOKCF (def=0x0) // clear compare register data update flag
    • [2]EXTTRIGCF (def=0x0) // clear Edge event are triggerd externally flag
    • [1]ARRMCF (def=0x0) // clear Aoto-reload register match flag
    • [0]CMPMCF (def=0x0) // clear compare register match flag
  • 0x40003408IER// interrupt enable register

    • [6]DOWNIE (def=0x0) // Down interrupt enable
    • [5]UPIE (def=0x0) // UP interrupt enable
    • [4]ARROKIE (def=0x0) // Aoto-reload register data update successfully interrupts enable
    • [3]CMPOKIE (def=0x0) // compare register data update successfully interrupts enable
    • [2]EXTTRIGIE (def=0x0) // Edge event are triggerd externally successfully interrupts enable
    • [1]ARRMIE (def=0x0) // Aoto-reload register match successfully interrupts enable
    • [0]CMPMIE (def=0x0) // compare register match successfully interrupts enable
  • 0x4000340CCFGR// configuration register

    • [27]FORCE_PWM (def=0x0) // Forcing pwm output
    • [25:26]CLKMX_SEL (def=0x0) // clock selection
    • [24]ENC (def=0x0) // coder mode
    • [23]COUNTMODE (def=0x0) // count clock selection
    • [22]PRELOAD (def=0x0) // update mode control
    • [21]WAVPOL (def=0x0) // PWM polarity
    • [20]WAVE (def=0x0) // PWM
    • [19]TIMOUT (def=0x0) // TIMEOUT control
    • [17:18]TRIGEN (def=0x0) // trigger configuration
    • [13]TRIGSEL (def=0x0) // trigger source selection
    • [9:11]PRESC (def=0x0) // prescaler configuration
    • [6:7]TRGFLT (def=0x0) // digital filter for flip-flops
    • [3:4]CKFLT (def=0x0) // digital filter for ex-clock
    • [1:2]CKPOL (def=0x0) // configure effective edges
    • [0]CKSEL (def=0x0) // effective edge configuration
  • 0x40003410CR// control register

    • [4]DIR_EXTEN (def=0x0) // externally trigger count direction enable
    • [3]OUTEN (def=0x0) // pwm output enable
    • [2]CNTSTRT (def=0x0) // start in continuous mode
    • [1]SNGSTRT (def=0x0) // start in one trigger mode
    • [0]ENABLE (def=0x0) // timer enable
  • 0x40003414CMP// compare register

    • [0:15]CMP (def=0x0) // compare value
  • 0x40003418ARR// aoto-reload register

    • [0:15]ARR (def=0x1) // aoto-reload count value
  • 0x4000341CCNT// COUNT register

    • [0:15]COUNT (def=0x0) // Timer count value
  interrupts:
  • [140] LPTIM2WakeUP // LPTIM2 wake-up interrupt
  • [97] LPTIM2 // LPTIM2 global interrupt
• 0x40007400DAC// Digital to analog converter

  • 0x40007400CTLR// Control register (DAC_CR)

    • [0]EN1 (def=0x0) // DAC channel1 enable
    • [1]BOFF1 (def=0x0) // DAC channel1 output buffer disable
    • [2]TEN1 (def=0x0) // DAC channel1 trigger enable
    • [3:5]TSEL1 (def=0x0) // DAC channel1 trigger selection
    • [6:7]WAVE1 (def=0x0) // DAC channel1 noise/triangle wave generation enable
    • [8:11]MAMP1 (def=0x0) // DAC channel1 mask/amplitude selector
    • [12]DMAEN1 (def=0x0) // DAC channel1 DMA enable
    • [16]EN2 (def=0x0) // DAC channel2 enable
    • [17]BOFF2 (def=0x0) // DAC channel2 output buffer disable
    • [18]TEN2 (def=0x0) // DAC channel2 trigger enable
    • [19:21]TSEL2 (def=0x0) // DAC channel2 trigger selection
    • [22:23]WAVE2 (def=0x0) // DAC channel2 noise/triangle wave generation enable
    • [24:27]MAMP2 (def=0x0) // DAC channel2 mask/amplitude selector
    • [28]DMAEN2 (def=0x0) // DAC channel2 DMA enable
  • 0x40007404SWTR// DAC software trigger register (DAC_SWTRIGR)

    • [0]SWTRIG1 (def=0x0) // DAC channel1 software trigger
    • [1]SWTRIG2 (def=0x0) // DAC channel2 software trigger
  • 0x40007408R12BDHR1// DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)

    • [0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
  • 0x4000740CL12BDHR1// DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)

    • [4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
  • 0x40007410R8BDHR1// DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)

    • [0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
  • 0x40007414R12BDHR2// DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)

    • [0:11]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x40007418L12BDHR2// DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)

    • [4:15]DACC2DHR (def=0x0) // DAC channel2 12-bit left-aligned data
  • 0x4000741CR8BDHR2// DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)

    • [0:7]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
  • 0x40007420RD12BDHR// Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, B

    • [0:11]DACC1DHR (def=0x0) // DAC channel1 12-bit right-aligned data
    • [16:27]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x40007424LD12BDHR// DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bi

    • [4:15]DACC1DHR (def=0x0) // DAC channel1 12-bit left-aligned data
    • [20:31]DACC2DHR (def=0x0) // DAC channel2 12-bit right-aligned data
  • 0x40007428RD8BDHR// DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

    • [0:7]DACC1DHR (def=0x0) // DAC channel1 8-bit right-aligned data
    • [8:15]DACC2DHR (def=0x0) // DAC channel2 8-bit right-aligned data
  • 0x4000742CDOR1// DAC channel1 data output register (DAC_DOR1)

    • [0:11]DACC1DOR (def=0x0) // DAC channel1 data output
  • 0x40007430DOR2// DAC channel2 data output register (DAC_DOR2)

    • [0:11]DACC2DOR (def=0x0) // DAC channel2 data output
• 0x40013800USART1// Universal synchronous asynchronous receiver transmitter

  • 0x40013800STATR// Status register

    • [15]LPWKUP_ACT_FLAG (def=0x0) // Low power wake-up indicator flag
    • [11]MS_ERR (def=0x0) // MARK or SPACE check error flag
    • [10]RX_BUSY (def=0x0) // receive status indication bit
    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40013804DATAR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40013808BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x4001380CCTLR1// Control register 1

    • [14:15]M_EXT (def=0x0) // data length extension bit
    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40013810CTLR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40013814CTLR3// Control register 3

    • [13:15]LPWKUP_DLY_CFG (def=0x0) // Low power wake-up reception delay configuration
    • [12]LPWKUP_CK_SRC (def=0x0) // Low power wake-up clock source selection
    • [11]LPWKUP_EN (def=0x0) // Low power wake-up enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40013818GPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x4001381CCTLR4// Control register 4

    • [2:3]CHECK_SEL (def=0x0) // check function selection bit
    • [1]MS_ERRIE (def=0x0) // SPACE or mark check error enable bit
  interrupts:
  • [48] USART1 // USART1 global interrupt
• 0x40004400USART2//

  • 0x40004400STATR// Status register

    • [15]LPWKUP_ACT_FLAG (def=0x0) // Low power wake-up indicator flag
    • [11]MS_ERR (def=0x0) // MARK or SPACE check error flag
    • [10]RX_BUSY (def=0x0) // receive status indication bit
    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40004404DATAR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40004408BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x4000440CCTLR1// Control register 1

    • [14:15]M_EXT (def=0x0) // data length extension bit
    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40004410CTLR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40004414CTLR3// Control register 3

    • [13:15]LPWKUP_DLY_CFG (def=0x0) // Low power wake-up reception delay configuration
    • [12]LPWKUP_CK_SRC (def=0x0) // Low power wake-up clock source selection
    • [11]LPWKUP_EN (def=0x0) // Low power wake-up enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40004418GPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x4000441CCTLR4// Control register 4

    • [2:3]CHECK_SEL (def=0x0) // check function selection bit
    • [1]MS_ERRIE (def=0x0) // SPACE or mark check error enable bit
  interrupts:
  • [45] USART2 // USART2 global interrupt
• 0x40004800USART3//

  • 0x40004800STATR// Status register

    • [15]LPWKUP_ACT_FLAG (def=0x0) // Low power wake-up indicator flag
    • [11]MS_ERR (def=0x0) // MARK or SPACE check error flag
    • [10]RX_BUSY (def=0x0) // receive status indication bit
    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40004804DATAR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40004808BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x4000480CCTLR1// Control register 1

    • [14:15]M_EXT (def=0x0) // data length extension bit
    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40004810CTLR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40004814CTLR3// Control register 3

    • [13:15]LPWKUP_DLY_CFG (def=0x0) // Low power wake-up reception delay configuration
    • [12]LPWKUP_CK_SRC (def=0x0) // Low power wake-up clock source selection
    • [11]LPWKUP_EN (def=0x0) // Low power wake-up enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40004818GPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x4000481CCTLR4// Control register 4

    • [2:3]CHECK_SEL (def=0x0) // check function selection bit
    • [1]MS_ERRIE (def=0x0) // SPACE or mark check error enable bit
  interrupts:
  • [84] USART3 // USART3 global interrupt
• 0x40004C00USART4//

  • 0x40004C00STATR// Status register

    • [15]LPWKUP_ACT_FLAG (def=0x0) // Low power wake-up indicator flag
    • [11]MS_ERR (def=0x0) // MARK or SPACE check error flag
    • [10]RX_BUSY (def=0x0) // receive status indication bit
    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40004C04DATAR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40004C08BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x40004C0CCTLR1// Control register 1

    • [14:15]M_EXT (def=0x0) // data length extension bit
    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40004C10CTLR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40004C14CTLR3// Control register 3

    • [13:15]LPWKUP_DLY_CFG (def=0x0) // Low power wake-up reception delay configuration
    • [12]LPWKUP_CK_SRC (def=0x0) // Low power wake-up clock source selection
    • [11]LPWKUP_EN (def=0x0) // Low power wake-up enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40004C18GPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x40004C1CCTLR4// Control register 4

    • [2:3]CHECK_SEL (def=0x0) // check function selection bit
    • [1]MS_ERRIE (def=0x0) // SPACE or mark check error enable bit
  interrupts:
  • [85] USART4 // USART4 global interrupt
• 0x40005000USART5//

  • 0x40005000STATR// Status register

    • [15]LPWKUP_ACT_FLAG (def=0x0) // Low power wake-up indicator flag
    • [11]MS_ERR (def=0x0) // MARK or SPACE check error flag
    • [10]RX_BUSY (def=0x0) // receive status indication bit
    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40005004DATAR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40005008BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x4000500CCTLR1// Control register 1

    • [14:15]M_EXT (def=0x0) // data length extension bit
    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40005010CTLR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40005014CTLR3// Control register 3

    • [13:15]LPWKUP_DLY_CFG (def=0x0) // Low power wake-up reception delay configuration
    • [12]LPWKUP_CK_SRC (def=0x0) // Low power wake-up clock source selection
    • [11]LPWKUP_EN (def=0x0) // Low power wake-up enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40005018GPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x4000501CCTLR4// Control register 4

    • [2:3]CHECK_SEL (def=0x0) // check function selection bit
    • [1]MS_ERRIE (def=0x0) // SPACE or mark check error enable bit
  interrupts:
  • [98] USART5 // USART5 global interrupt
• 0x40001800USART6//

  • 0x40001800STATR// Status register

    • [15]LPWKUP_ACT_FLAG (def=0x0) // Low power wake-up indicator flag
    • [11]MS_ERR (def=0x0) // MARK or SPACE check error flag
    • [10]RX_BUSY (def=0x0) // receive status indication bit
    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40001804DATAR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40001808BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x4000180CCTLR1// Control register 1

    • [14:15]M_EXT (def=0x0) // data length extension bit
    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40001810CTLR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40001814CTLR3// Control register 3

    • [13:15]LPWKUP_DLY_CFG (def=0x0) // Low power wake-up reception delay configuration
    • [12]LPWKUP_CK_SRC (def=0x0) // Low power wake-up clock source selection
    • [11]LPWKUP_EN (def=0x0) // Low power wake-up enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40001818GPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x4000181CCTLR4// Control register 4

    • [2:3]CHECK_SEL (def=0x0) // check function selection bit
    • [1]MS_ERRIE (def=0x0) // SPACE or mark check error enable bit
  interrupts:
  • [99] USART6 // USART6 global interrupt
• 0x40001C00USART7//

  • 0x40001C00STATR// Status register

    • [15]LPWKUP_ACT_FLAG (def=0x0) // Low power wake-up indicator flag
    • [11]MS_ERR (def=0x0) // MARK or SPACE check error flag
    • [10]RX_BUSY (def=0x0) // receive status indication bit
    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40001C04DATAR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40001C08BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x40001C0CCTLR1// Control register 1

    • [14:15]M_EXT (def=0x0) // data length extension bit
    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40001C10CTLR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40001C14CTLR3// Control register 3

    • [13:15]LPWKUP_DLY_CFG (def=0x0) // Low power wake-up reception delay configuration
    • [12]LPWKUP_CK_SRC (def=0x0) // Low power wake-up clock source selection
    • [11]LPWKUP_EN (def=0x0) // Low power wake-up enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40001C18GPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x40001C1CCTLR4// Control register 4

    • [2:3]CHECK_SEL (def=0x0) // check function selection bit
    • [1]MS_ERRIE (def=0x0) // SPACE or mark check error enable bit
  interrupts:
  • [116] USART7 // UART7 global interrupt
• 0x40002000USART8//

  • 0x40002000STATR// Status register

    • [15]LPWKUP_ACT_FLAG (def=0x0) // Low power wake-up indicator flag
    • [11]MS_ERR (def=0x0) // MARK or SPACE check error flag
    • [10]RX_BUSY (def=0x0) // receive status indication bit
    • [9]CTS (def=0x0) // CTS flag
    • [8]LBD (def=0x0) // LIN break detection flag
    • [7]TXE (def=0x1) // Transmit data register empty
    • [6]TC (def=0x1) // Transmission complete
    • [5]RXNE (def=0x0) // Read data register not empty
    • [4]IDLE (def=0x0) // IDLE line detected
    • [3]ORE (def=0x0) // Overrun error
    • [2]NE (def=0x0) // Noise error flag
    • [1]FE (def=0x0) // Framing error
    • [0]PE (def=0x0) // Parity error
  • 0x40002004DATAR// Data register

    • [0:8]DR (def=0x0) // Data value
  • 0x40002008BRR// Baud rate register

    • [4:15]DIV_Mantissa (def=0x0) // mantissa of USARTDIV
    • [0:3]DIV_Fraction (def=0x0) // fraction of USARTDIV
  • 0x4000200CCTLR1// Control register 1

    • [14:15]M_EXT (def=0x0) // data length extension bit
    • [13]UE (def=0x0) // USART enable
    • [12]M (def=0x0) // Word length
    • [11]WAKE (def=0x0) // Wakeup method
    • [10]PCE (def=0x0) // Parity control enable
    • [9]PS (def=0x0) // Parity selection
    • [8]PEIE (def=0x0) // PE interrupt enable
    • [7]TXEIE (def=0x0) // TXE interrupt enable
    • [6]TCIE (def=0x0) // Transmission complete interrupt enable
    • [5]RXNEIE (def=0x0) // RXNE interrupt enable
    • [4]IDLEIE (def=0x0) // IDLE interrupt enable
    • [3]TE (def=0x0) // Transmitter enable
    • [2]RE (def=0x0) // Receiver enable
    • [1]RWU (def=0x0) // Receiver wakeup
    • [0]SBK (def=0x0) // Send break
  • 0x40002010CTLR2// Control register 2

    • [14]LINEN (def=0x0) // LIN mode enable
    • [12:13]STOP (def=0x0) // STOP bits
    • [11]CLKEN (def=0x0) // Clock enable
    • [10]CPOL (def=0x0) // Clock polarity
    • [9]CPHA (def=0x0) // Clock phase
    • [8]LBCL (def=0x0) // Last bit clock pulse
    • [6]LBDIE (def=0x0) // LIN break detection interrupt enable
    • [5]LBDL (def=0x0) // lin break detection length
    • [0:3]ADD (def=0x0) // Address of the USART node
  • 0x40002014CTLR3// Control register 3

    • [13:15]LPWKUP_DLY_CFG (def=0x0) // Low power wake-up reception delay configuration
    • [12]LPWKUP_CK_SRC (def=0x0) // Low power wake-up clock source selection
    • [11]LPWKUP_EN (def=0x0) // Low power wake-up enable
    • [10]CTSIE (def=0x0) // CTS interrupt enable
    • [9]CTSE (def=0x0) // CTS enable
    • [8]RTSE (def=0x0) // RTS enable
    • [7]DMAT (def=0x0) // DMA enable transmitter
    • [6]DMAR (def=0x0) // DMA enable receiver
    • [5]SCEN (def=0x0) // Smartcard mode enable
    • [4]NACK (def=0x0) // Smartcard NACK enable
    • [3]HDSEL (def=0x0) // Half-duplex selection
    • [2]IRLP (def=0x0) // IrDA low-power
    • [1]IREN (def=0x0) // IrDA mode enable
    • [0]EIE (def=0x0) // Error interrupt enable
  • 0x40002018GPR// Guard time and prescaler register

    • [8:15]GT (def=0x0) // Guard time value
    • [0:7]PSC (def=0x0) // Prescaler value
  • 0x4000201CCTLR4// Control register 4

    • [2:3]CHECK_SEL (def=0x0) // check function selection bit
    • [1]MS_ERRIE (def=0x0) // SPACE or mark check error enable bit
  interrupts:
  • [117] USART8 // USART8 global interrupt
• 0x40005400I2C1// Inter integrated circuit

  • 0x40005400CTLR1// Control register 1

    • [15]SWRST (def=0x0) // Software reset
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]PEC (def=0x0) // Packet error checking
    • [11]POS (def=0x0) // Acknowledge/PEC Position (for data reception)
    • [10]ACK (def=0x0) // Acknowledge enable
    • [9]STOP (def=0x0) // Stop generation
    • [8]START (def=0x0) // Start generation
    • [7]NOSTRETCH (def=0x0) // Clock stretching disable (Slave mode)
    • [6]ENGC (def=0x0) // General call enable
    • [5]ENPEC (def=0x0) // PEC enable
    • [4]ENARP (def=0x0) // ARP enable
    • [3]SMBTYPE (def=0x0) // SMBus type
    • [1]SMBUS (def=0x0) // SMBus mode
    • [0]PE (def=0x0) // Peripheral enable
  • 0x40005404CTLR2// Control register 2

    • [12]LAST (def=0x0) // DMA last transfer
    • [11]DMAEN (def=0x0) // DMA requests enable
    • [10]ITBUFEN (def=0x0) // Buffer interrupt enable
    • [9]ITEVTEN (def=0x0) // Event interrupt enable
    • [8]ITERREN (def=0x0) // Error interrupt enable
    • [0:5]FREQ (def=0x0) // Peripheral clock frequency
  • 0x40005408OADDR1// Own address register 1

    • [15]ADDMODE (def=0x0) // Addressing mode (slave mode)
    • [8:9]ADD9_8 (def=0x0) // Interface address
    • [1:7]ADD7_1 (def=0x0) // Interface address
    • [0]ADD0 (def=0x0) // Interface address
  • 0x4000540COADDR2// Own address register 2

    • [1:7]ADD2 (def=0x0) // Interface address
    • [0]ENDUAL (def=0x0) // Dual addressing mode enable
  • 0x40005410DATAR// Data register

    • [0:7]DATAR (def=0x0) // 8-bit data register
  • 0x40005414STAR1// Status register 1

    • [15]SMBALERT (def=0x0) // SMBus alert
    • [14]TIMEOUT (def=0x0) // Timeout or Tlow error
    • [12]PECERR (def=0x0) // PEC Error in reception
    • [11]OVR (def=0x0) // Overrun/Underrun
    • [10]AF (def=0x0) // Acknowledge failure
    • [9]ARLO (def=0x0) // Arbitration lost (master mode)
    • [8]BERR (def=0x0) // Bus error
    • [7]TxE (def=0x0) // Data register empty (transmitters)
    • [6]RxNE (def=0x0) // Data register not empty (receivers)
    • [4]STOPF (def=0x0) // Stop detection (slave mode)
    • [3]ADD10 (def=0x0) // 10-bit header sent (Master mode)
    • [2]BTF (def=0x0) // Byte transfer finished
    • [1]ADDR (def=0x0) // Address sent (master mode)/matched (slave mode)
    • [0]SB (def=0x0) // Start bit (Master mode)
  • 0x40005418STAR2// Status register 2

    • [8:15]PEC (def=0x0) // acket error checking register
    • [7]DUALF (def=0x0) // Dual flag (Slave mode)
    • [6]SMBHOST (def=0x0) // SMBus host header (Slave mode)
    • [5]SMBDEFAULT (def=0x0) // SMBus device default address (Slave mode)
    • [4]GENCALL (def=0x0) // General call address (Slave mode)
    • [2]TRA (def=0x0) // Transmitter/receiver
    • [1]BUSY (def=0x0) // Bus busy
    • [0]MSL (def=0x0) // Master/slave
  • 0x4000541CCKCFGR// Clock control register

    • [15]F_S (def=0x0) // I2C master mode selection
    • [14]DUTY (def=0x0) // Fast mode duty cycle
    • [0:11]CCR (def=0x0) // Clock control register in Fast/Standard mode (Master mode)
  • 0x40005420RTR// Raise time register

    • [0:5]TRISE (def=0x2) // Maximum rise time in Fast/Standard mode (Master mode)
  interrupts:
  • [46] I2C1_EV // I2C1 event interrupt
  • [47] I2C1_ER // I2C1 error interrupt
• 0x40005800I2C2//

  • 0x40005800CTLR1// Control register 1

    • [15]SWRST (def=0x0) // Software reset
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]PEC (def=0x0) // Packet error checking
    • [11]POS (def=0x0) // Acknowledge/PEC Position (for data reception)
    • [10]ACK (def=0x0) // Acknowledge enable
    • [9]STOP (def=0x0) // Stop generation
    • [8]START (def=0x0) // Start generation
    • [7]NOSTRETCH (def=0x0) // Clock stretching disable (Slave mode)
    • [6]ENGC (def=0x0) // General call enable
    • [5]ENPEC (def=0x0) // PEC enable
    • [4]ENARP (def=0x0) // ARP enable
    • [3]SMBTYPE (def=0x0) // SMBus type
    • [1]SMBUS (def=0x0) // SMBus mode
    • [0]PE (def=0x0) // Peripheral enable
  • 0x40005804CTLR2// Control register 2

    • [12]LAST (def=0x0) // DMA last transfer
    • [11]DMAEN (def=0x0) // DMA requests enable
    • [10]ITBUFEN (def=0x0) // Buffer interrupt enable
    • [9]ITEVTEN (def=0x0) // Event interrupt enable
    • [8]ITERREN (def=0x0) // Error interrupt enable
    • [0:5]FREQ (def=0x0) // Peripheral clock frequency
  • 0x40005808OADDR1// Own address register 1

    • [15]ADDMODE (def=0x0) // Addressing mode (slave mode)
    • [8:9]ADD9_8 (def=0x0) // Interface address
    • [1:7]ADD7_1 (def=0x0) // Interface address
    • [0]ADD0 (def=0x0) // Interface address
  • 0x4000580COADDR2// Own address register 2

    • [1:7]ADD2 (def=0x0) // Interface address
    • [0]ENDUAL (def=0x0) // Dual addressing mode enable
  • 0x40005810DATAR// Data register

    • [0:7]DATAR (def=0x0) // 8-bit data register
  • 0x40005814STAR1// Status register 1

    • [15]SMBALERT (def=0x0) // SMBus alert
    • [14]TIMEOUT (def=0x0) // Timeout or Tlow error
    • [12]PECERR (def=0x0) // PEC Error in reception
    • [11]OVR (def=0x0) // Overrun/Underrun
    • [10]AF (def=0x0) // Acknowledge failure
    • [9]ARLO (def=0x0) // Arbitration lost (master mode)
    • [8]BERR (def=0x0) // Bus error
    • [7]TxE (def=0x0) // Data register empty (transmitters)
    • [6]RxNE (def=0x0) // Data register not empty (receivers)
    • [4]STOPF (def=0x0) // Stop detection (slave mode)
    • [3]ADD10 (def=0x0) // 10-bit header sent (Master mode)
    • [2]BTF (def=0x0) // Byte transfer finished
    • [1]ADDR (def=0x0) // Address sent (master mode)/matched (slave mode)
    • [0]SB (def=0x0) // Start bit (Master mode)
  • 0x40005818STAR2// Status register 2

    • [8:15]PEC (def=0x0) // acket error checking register
    • [7]DUALF (def=0x0) // Dual flag (Slave mode)
    • [6]SMBHOST (def=0x0) // SMBus host header (Slave mode)
    • [5]SMBDEFAULT (def=0x0) // SMBus device default address (Slave mode)
    • [4]GENCALL (def=0x0) // General call address (Slave mode)
    • [2]TRA (def=0x0) // Transmitter/receiver
    • [1]BUSY (def=0x0) // Bus busy
    • [0]MSL (def=0x0) // Master/slave
  • 0x4000581CCKCFGR// Clock control register

    • [15]F_S (def=0x0) // I2C master mode selection
    • [14]DUTY (def=0x0) // Fast mode duty cycle
    • [0:11]CCR (def=0x0) // Clock control register in Fast/Standard mode (Master mode)
  • 0x40005820RTR// Raise time register

    • [0:5]TRISE (def=0x2) // Maximum rise time in Fast/Standard mode (Master mode)
  interrupts:
  • [52] I2C2_EV // I2C2 event interrupt
  • [53] I2C2_ER // I2C2 error interrupt
• 0x40005C00I2C3//

  • 0x40005C00CTLR1// Control register 1

    • [15]SWRST (def=0x0) // Software reset
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]PEC (def=0x0) // Packet error checking
    • [11]POS (def=0x0) // Acknowledge/PEC Position (for data reception)
    • [10]ACK (def=0x0) // Acknowledge enable
    • [9]STOP (def=0x0) // Stop generation
    • [8]START (def=0x0) // Start generation
    • [7]NOSTRETCH (def=0x0) // Clock stretching disable (Slave mode)
    • [6]ENGC (def=0x0) // General call enable
    • [5]ENPEC (def=0x0) // PEC enable
    • [4]ENARP (def=0x0) // ARP enable
    • [3]SMBTYPE (def=0x0) // SMBus type
    • [1]SMBUS (def=0x0) // SMBus mode
    • [0]PE (def=0x0) // Peripheral enable
  • 0x40005C04CTLR2// Control register 2

    • [12]LAST (def=0x0) // DMA last transfer
    • [11]DMAEN (def=0x0) // DMA requests enable
    • [10]ITBUFEN (def=0x0) // Buffer interrupt enable
    • [9]ITEVTEN (def=0x0) // Event interrupt enable
    • [8]ITERREN (def=0x0) // Error interrupt enable
    • [0:5]FREQ (def=0x0) // Peripheral clock frequency
  • 0x40005C08OADDR1// Own address register 1

    • [15]ADDMODE (def=0x0) // Addressing mode (slave mode)
    • [8:9]ADD9_8 (def=0x0) // Interface address
    • [1:7]ADD7_1 (def=0x0) // Interface address
    • [0]ADD0 (def=0x0) // Interface address
  • 0x40005C0COADDR2// Own address register 2

    • [1:7]ADD2 (def=0x0) // Interface address
    • [0]ENDUAL (def=0x0) // Dual addressing mode enable
  • 0x40005C10DATAR// Data register

    • [0:7]DATAR (def=0x0) // 8-bit data register
  • 0x40005C14STAR1// Status register 1

    • [15]SMBALERT (def=0x0) // SMBus alert
    • [14]TIMEOUT (def=0x0) // Timeout or Tlow error
    • [12]PECERR (def=0x0) // PEC Error in reception
    • [11]OVR (def=0x0) // Overrun/Underrun
    • [10]AF (def=0x0) // Acknowledge failure
    • [9]ARLO (def=0x0) // Arbitration lost (master mode)
    • [8]BERR (def=0x0) // Bus error
    • [7]TxE (def=0x0) // Data register empty (transmitters)
    • [6]RxNE (def=0x0) // Data register not empty (receivers)
    • [4]STOPF (def=0x0) // Stop detection (slave mode)
    • [3]ADD10 (def=0x0) // 10-bit header sent (Master mode)
    • [2]BTF (def=0x0) // Byte transfer finished
    • [1]ADDR (def=0x0) // Address sent (master mode)/matched (slave mode)
    • [0]SB (def=0x0) // Start bit (Master mode)
  • 0x40005C18STAR2// Status register 2

    • [8:15]PEC (def=0x0) // acket error checking register
    • [7]DUALF (def=0x0) // Dual flag (Slave mode)
    • [6]SMBHOST (def=0x0) // SMBus host header (Slave mode)
    • [5]SMBDEFAULT (def=0x0) // SMBus device default address (Slave mode)
    • [4]GENCALL (def=0x0) // General call address (Slave mode)
    • [2]TRA (def=0x0) // Transmitter/receiver
    • [1]BUSY (def=0x0) // Bus busy
    • [0]MSL (def=0x0) // Master/slave
  • 0x40005C1CCKCFGR// Clock control register

    • [15]F_S (def=0x0) // I2C master mode selection
    • [14]DUTY (def=0x0) // Fast mode duty cycle
    • [0:11]CCR (def=0x0) // Clock control register in Fast/Standard mode (Master mode)
  • 0x40005C20RTR// Raise time register

    • [0:5]TRISE (def=0x2) // Maximum rise time in Fast/Standard mode (Master mode)
  interrupts:
  • [78] I2C3_EV // I2C3 event interrupt
  • [79] I2C3_ER // I2C3 error interrupt
• 0x40014000I2C4//

  • 0x40014000CTLR1// Control register 1

    • [15]SWRST (def=0x0) // Software reset
    • [13]ALERT (def=0x0) // SMBus alert
    • [12]PEC (def=0x0) // Packet error checking
    • [11]POS (def=0x0) // Acknowledge/PEC Position (for data reception)
    • [10]ACK (def=0x0) // Acknowledge enable
    • [9]STOP (def=0x0) // Stop generation
    • [8]START (def=0x0) // Start generation
    • [7]NOSTRETCH (def=0x0) // Clock stretching disable (Slave mode)
    • [6]ENGC (def=0x0) // General call enable
    • [5]ENPEC (def=0x0) // PEC enable
    • [4]ENARP (def=0x0) // ARP enable
    • [3]SMBTYPE (def=0x0) // SMBus type
    • [1]SMBUS (def=0x0) // SMBus mode
    • [0]PE (def=0x0) // Peripheral enable
  • 0x40014004CTLR2// Control register 2

    • [12]LAST (def=0x0) // DMA last transfer
    • [11]DMAEN (def=0x0) // DMA requests enable
    • [10]ITBUFEN (def=0x0) // Buffer interrupt enable
    • [9]ITEVTEN (def=0x0) // Event interrupt enable
    • [8]ITERREN (def=0x0) // Error interrupt enable
    • [0:5]FREQ (def=0x0) // Peripheral clock frequency
  • 0x40014008OADDR1// Own address register 1

    • [15]ADDMODE (def=0x0) // Addressing mode (slave mode)
    • [8:9]ADD9_8 (def=0x0) // Interface address
    • [1:7]ADD7_1 (def=0x0) // Interface address
    • [0]ADD0 (def=0x0) // Interface address
  • 0x4001400COADDR2// Own address register 2

    • [1:7]ADD2 (def=0x0) // Interface address
    • [0]ENDUAL (def=0x0) // Dual addressing mode enable
  • 0x40014010DATAR// Data register

    • [0:7]DATAR (def=0x0) // 8-bit data register
  • 0x40014014STAR1// Status register 1

    • [15]SMBALERT (def=0x0) // SMBus alert
    • [14]TIMEOUT (def=0x0) // Timeout or Tlow error
    • [12]PECERR (def=0x0) // PEC Error in reception
    • [11]OVR (def=0x0) // Overrun/Underrun
    • [10]AF (def=0x0) // Acknowledge failure
    • [9]ARLO (def=0x0) // Arbitration lost (master mode)
    • [8]BERR (def=0x0) // Bus error
    • [7]TxE (def=0x0) // Data register empty (transmitters)
    • [6]RxNE (def=0x0) // Data register not empty (receivers)
    • [4]STOPF (def=0x0) // Stop detection (slave mode)
    • [3]ADD10 (def=0x0) // 10-bit header sent (Master mode)
    • [2]BTF (def=0x0) // Byte transfer finished
    • [1]ADDR (def=0x0) // Address sent (master mode)/matched (slave mode)
    • [0]SB (def=0x0) // Start bit (Master mode)
  • 0x40014018STAR2// Status register 2

    • [8:15]PEC (def=0x0) // acket error checking register
    • [7]DUALF (def=0x0) // Dual flag (Slave mode)
    • [6]SMBHOST (def=0x0) // SMBus host header (Slave mode)
    • [5]SMBDEFAULT (def=0x0) // SMBus device default address (Slave mode)
    • [4]GENCALL (def=0x0) // General call address (Slave mode)
    • [2]TRA (def=0x0) // Transmitter/receiver
    • [1]BUSY (def=0x0) // Bus busy
    • [0]MSL (def=0x0) // Master/slave
  • 0x4001401CCKCFGR// Clock control register

    • [15]F_S (def=0x0) // I2C master mode selection
    • [14]DUTY (def=0x0) // Fast mode duty cycle
    • [0:11]CCR (def=0x0) // Clock control register in Fast/Standard mode (Master mode)
  • 0x40014020RTR// Raise time register

    • [0:5]TRISE (def=0x2) // Maximum rise time in Fast/Standard mode (Master mode)
  interrupts:
  • [80] I2C4_EV // I2C4 event interrupt
  • [81] I2C4_ER // I2C4 error interrupt
• 0x40013000SPI1// Serial peripheral interface

  • 0x40013000CTLR1// control register 1

    • [15]BIDIMODE (def=0x0) // Bidirectional data mode enable
    • [14]BIDIOE (def=0x0) // Output enable in bidirectional mode
    • [13]CRCEN (def=0x0) // Hardware CRC calculation enable
    • [12]CRCNEXT (def=0x0) // CRC transfer next
    • [11]DFF (def=0x0) // Data frame format
    • [10]RXONLY (def=0x0) // Receive only
    • [9]SSM (def=0x0) // Software slave management
    • [8]SSI (def=0x0) // Internal slave select
    • [7]LSBFIRST (def=0x0) // Frame format
    • [6]SPE (def=0x0) // SPI enable
    • [3:5]BR (def=0x0) // Baud rate control
    • [2]MSTR (def=0x0) // Master selection
    • [1]CPOL (def=0x0) // Clock polarity
    • [0]CPHA (def=0x0) // Clock phase
  • 0x40013004CTLR2// control register 2

    • [7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
    • [6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
    • [5]ERRIE (def=0x0) // Error interrupt enable
    • [2]SSOE (def=0x0) // SS output enable
    • [1]TXDMAEN (def=0x0) // Tx buffer DMA enable
    • [0]RXDMAEN (def=0x0) // Rx buffer DMA enable
  • 0x40013008STATR// status register

    • [7]BSY (def=0x0) // Busy flag
    • [6]OVR (def=0x0) // Overrun flag
    • [5]MODF (def=0x0) // Mode fault
    • [4]CRCERR (def=0x0) // CRC error flag
    • [3]UDR (def=0x0) // Underrun flag
    • [2]CHSID (def=0x0) // Channel side
    • [1]TXE (def=0x1) // Transmit buffer empty
    • [0]RXNE (def=0x0) // Receive buffer not empty
  • 0x4001300CDATAR// data register

    • [0:15]DR (def=0x0) // Data register
  • 0x40013010CRCR// CRCR polynomial register

    • [0:15]CRCPOLY (def=0x7) // CRC polynomial register
  • 0x40013014RCRCR// RX CRC register

    • [0:15]RXCRC (def=0x0) // Rx CRC register
  • 0x40013018TCRCR// TX CRC register

    • [0:15]TXCRC (def=0x0) // Tx CRC register
  • 0x40013024HSCR// high speed control register

    • [0]HSRXEN (def=0x0) // High speed mode read enable
    • [2]HSRXEN2 (def=0x0) // High speed mode 2 read enable
  interrupts:
  • [37] SPI1 // SPI1 global interrupt
• 0x40004000SPI4//

  • 0x40004000CTLR1// control register 1

    • [15]BIDIMODE (def=0x0) // Bidirectional data mode enable
    • [14]BIDIOE (def=0x0) // Output enable in bidirectional mode
    • [13]CRCEN (def=0x0) // Hardware CRC calculation enable
    • [12]CRCNEXT (def=0x0) // CRC transfer next
    • [11]DFF (def=0x0) // Data frame format
    • [10]RXONLY (def=0x0) // Receive only
    • [9]SSM (def=0x0) // Software slave management
    • [8]SSI (def=0x0) // Internal slave select
    • [7]LSBFIRST (def=0x0) // Frame format
    • [6]SPE (def=0x0) // SPI enable
    • [3:5]BR (def=0x0) // Baud rate control
    • [2]MSTR (def=0x0) // Master selection
    • [1]CPOL (def=0x0) // Clock polarity
    • [0]CPHA (def=0x0) // Clock phase
  • 0x40004004CTLR2// control register 2

    • [7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
    • [6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
    • [5]ERRIE (def=0x0) // Error interrupt enable
    • [2]SSOE (def=0x0) // SS output enable
    • [1]TXDMAEN (def=0x0) // Tx buffer DMA enable
    • [0]RXDMAEN (def=0x0) // Rx buffer DMA enable
  • 0x40004008STATR// status register

    • [7]BSY (def=0x0) // Busy flag
    • [6]OVR (def=0x0) // Overrun flag
    • [5]MODF (def=0x0) // Mode fault
    • [4]CRCERR (def=0x0) // CRC error flag
    • [3]UDR (def=0x0) // Underrun flag
    • [2]CHSID (def=0x0) // Channel side
    • [1]TXE (def=0x1) // Transmit buffer empty
    • [0]RXNE (def=0x0) // Receive buffer not empty
  • 0x4000400CDATAR// data register

    • [0:15]DR (def=0x0) // Data register
  • 0x40004010CRCR// CRCR polynomial register

    • [0:15]CRCPOLY (def=0x7) // CRC polynomial register
  • 0x40004014RCRCR// RX CRC register

    • [0:15]RXCRC (def=0x0) // Rx CRC register
  • 0x40004018TCRCR// TX CRC register

    • [0:15]TXCRC (def=0x0) // Tx CRC register
  • 0x40004024HSCR// high speed control register

    • [0]HSRXEN (def=0x0) // High speed mode read enable
    • [2]HSRXEN2 (def=0x0) // High speed mode 2 read enable
  interrupts:
  • [51] SPI4 // SPI4 global interrupt
• 0x40003C00SPI3// Serial peripheral interface

  • 0x40003C00CTLR1// control register 1

    • [15]BIDIMODE (def=0x0) // Bidirectional data mode enable
    • [14]BIDIOE (def=0x0) // Output enable in bidirectional mode
    • [13]CRCEN (def=0x0) // Hardware CRC calculation enable
    • [12]CRCNEXT (def=0x0) // CRC transfer next
    • [11]DFF (def=0x0) // Data frame format
    • [10]RXONLY (def=0x0) // Receive only
    • [9]SSM (def=0x0) // Software slave management
    • [8]SSI (def=0x0) // Internal slave select
    • [7]LSBFIRST (def=0x0) // Frame format
    • [6]SPE (def=0x0) // SPI enable
    • [3:5]BR (def=0x0) // Baud rate control
    • [2]MSTR (def=0x0) // Master selection
    • [1]CPOL (def=0x0) // Clock polarity
    • [0]CPHA (def=0x0) // Clock phase
  • 0x40003C04CTLR2// control register 2

    • [7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
    • [6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
    • [5]ERRIE (def=0x0) // Error interrupt enable
    • [2]SSOE (def=0x0) // SS output enable
    • [1]TXDMAEN (def=0x0) // Tx buffer DMA enable
    • [0]RXDMAEN (def=0x0) // Rx buffer DMA enable
  • 0x40003C08STATR// status register

    • [7]BSY (def=0x0) // Busy flag
    • [6]OVR (def=0x0) // Overrun flag
    • [5]MODF (def=0x0) // Mode fault
    • [4]CRCERR (def=0x0) // CRC error flag
    • [3]UDR (def=0x0) // Underrun flag
    • [2]CHSID (def=0x0) // Channel side
    • [1]TXE (def=0x1) // Transmit buffer empty
    • [0]RXNE (def=0x0) // Receive buffer not empty
  • 0x40003C0CDATAR// data register

    • [0:15]DR (def=0x0) // Data register
  • 0x40003C10CRCR// CRCR polynomial register

    • [0:15]CRCPOLY (def=0x7) // CRC polynomial register
  • 0x40003C14RCRCR// RX CRC register

    • [0:15]RXCRC (def=0x0) // Rx CRC register
  • 0x40003C18TCRCR// TX CRC register

    • [0:15]TXCRC (def=0x0) // Tx CRC register
  • 0x40003C1CSPI_I2S_CFGR// SPI_I2S configure register

    • [0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
    • [1:2]DATLEN (def=0x0) // DATLEN[1:0] bits (Data length to be transferred)
    • [3]CKPOL (def=0x0) // steady state clock polarity
    • [4:5]I2SSTD (def=0x0) // I2SSTD[1:0] bits (I2S standard selection)
    • [7]PCMSYNC (def=0x0) // PCM frame synchronization
    • [8:9]I2SCFG (def=0x0) // I2SCFG[1:0] bits (I2S configuration mode)
    • [10]I2SE (def=0x0) // I2S Enable
    • [11]I2SMOD (def=0x0) // I2S mode selection
  • 0x40003C20SPI_I2SPR// I2S prescaler register

    • [9]MCKOE (def=0x0) // Master clock output enable
    • [8]ODD (def=0x0) // Odd factor for the prescaler
    • [0:7]I2SDIV (def=0x0) // I2S Linear prescaler
  • 0x40003C24HSCR// high speed control register

    • [0]HSRXEN (def=0x0) // High speed mode read enable
    • [2]HSRXEN2 (def=0x0) // High speed mode 2 read enable
  interrupts:
  • [50] SPI3 // SPI3 global interrupt
• 0x40003800SPI2//

  • 0x40003800CTLR1// control register 1

    • [15]BIDIMODE (def=0x0) // Bidirectional data mode enable
    • [14]BIDIOE (def=0x0) // Output enable in bidirectional mode
    • [13]CRCEN (def=0x0) // Hardware CRC calculation enable
    • [12]CRCNEXT (def=0x0) // CRC transfer next
    • [11]DFF (def=0x0) // Data frame format
    • [10]RXONLY (def=0x0) // Receive only
    • [9]SSM (def=0x0) // Software slave management
    • [8]SSI (def=0x0) // Internal slave select
    • [7]LSBFIRST (def=0x0) // Frame format
    • [6]SPE (def=0x0) // SPI enable
    • [3:5]BR (def=0x0) // Baud rate control
    • [2]MSTR (def=0x0) // Master selection
    • [1]CPOL (def=0x0) // Clock polarity
    • [0]CPHA (def=0x0) // Clock phase
  • 0x40003804CTLR2// control register 2

    • [7]TXEIE (def=0x0) // Tx buffer empty interrupt enable
    • [6]RXNEIE (def=0x0) // RX buffer not empty interrupt enable
    • [5]ERRIE (def=0x0) // Error interrupt enable
    • [2]SSOE (def=0x0) // SS output enable
    • [1]TXDMAEN (def=0x0) // Tx buffer DMA enable
    • [0]RXDMAEN (def=0x0) // Rx buffer DMA enable
  • 0x40003808STATR// status register

    • [7]BSY (def=0x0) // Busy flag
    • [6]OVR (def=0x0) // Overrun flag
    • [5]MODF (def=0x0) // Mode fault
    • [4]CRCERR (def=0x0) // CRC error flag
    • [3]UDR (def=0x0) // Underrun flag
    • [2]CHSID (def=0x0) // Channel side
    • [1]TXE (def=0x1) // Transmit buffer empty
    • [0]RXNE (def=0x0) // Receive buffer not empty
  • 0x4000380CDATAR// data register

    • [0:15]DR (def=0x0) // Data register
  • 0x40003810CRCR// CRCR polynomial register

    • [0:15]CRCPOLY (def=0x7) // CRC polynomial register
  • 0x40003814RCRCR// RX CRC register

    • [0:15]RXCRC (def=0x0) // Rx CRC register
  • 0x40003818TCRCR// TX CRC register

    • [0:15]TXCRC (def=0x0) // Tx CRC register
  • 0x4000381CSPI_I2S_CFGR// SPI_I2S configure register

    • [0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
    • [1:2]DATLEN (def=0x0) // DATLEN[1:0] bits (Data length to be transferred)
    • [3]CKPOL (def=0x0) // steady state clock polarity
    • [4:5]I2SSTD (def=0x0) // I2SSTD[1:0] bits (I2S standard selection)
    • [7]PCMSYNC (def=0x0) // PCM frame synchronization
    • [8:9]I2SCFG (def=0x0) // I2SCFG[1:0] bits (I2S configuration mode)
    • [10]I2SE (def=0x0) // I2S Enable
    • [11]I2SMOD (def=0x0) // I2S mode selection
  • 0x40003820SPI_I2SPR// I2S prescaler register

    • [9]MCKOE (def=0x0) // Master clock output enable
    • [8]ODD (def=0x0) // Odd factor for the prescaler
    • [0:7]I2SDIV (def=0x0) // I2S Linear prescaler
  • 0x40003824HSCR// high speed control register

    • [0]HSRXEN (def=0x0) // High speed mode read enable
    • [2]HSRXEN2 (def=0x0) // High speed mode 2 read enable
  interrupts:
  • [49] SPI2 // SPI2 global interrupt
• 0x40024400USBPD// USBPD configuration

  • 0x40024400CONFIG// PD interrupt enable register

    • [0]PD_FILT_EN (def=0x0) // control PD pin input filter enable
    • [1]PD_ALL_CLR (def=0x1) // PD ITClear
    • [2]CC_SEL (def=0x0) // PD Commutation port
    • [3]PD_DMA_EN (def=0x0) // PD DMA Enable
    • [4]PD_RST_EN (def=0x0) // PD RST Enable
    • [5]WAKE_POLAR (def=0x0) // wakeup polarity
    • [6]CC_TR (def=0x0) // TR conditioning of the CC LV waveform
    • [7]CC_INC (def=0x0) // CC bias current adjustment bit
    • [8]RX_MULTI_0 (def=0x0) // Continuously receive several bits of 0 indicator flag
    • [10]IE_PD_IO (def=0x0) // IO Enable
    • [11]IE_RX_BIT (def=0x0) // bit interrupt Enable
    • [12]IE_RX_BYTE (def=0x0) // Receive byte register
    • [13]IE_RX_ACT (def=0x0) // Receive complete register
    • [14]IE_RX_RESET (def=0x0) // Receive complete rst register
    • [15]IE_TX_END (def=0x0) // transfer complete register
  • 0x40024402BMC_CLK_CNT// BMC sampling clock counter

    • [0:8]BMC_CLK_CNT (def=0x0) // R/T counter
  • 0x40024404CONTROL// PD Send and receive enable register

    • [0]PD_TX_EN (def=0x0) // PD_TX_EN value
    • [1]BMC_START (def=0x0) // BMC_START value
    • [2:4]RX_STATE (def=0x0) // PD receive status identification
    • [5]DATA_FLAG (def=0x0) // DATA_FLAG value
    • [6]TX_BIT_BACK (def=0x0) // TX_BIT_BACK value
    • [7]BMC_BYTE_HI (def=0x0) // BMC_BYTE_HI value
  • 0x40024405TX_SEL// SOP port selection register

    • [0]TX_SEL1 (def=0x0) // TX_SEL1 value
    • [2:3]TX_SEL2 (def=0x0) // TX_SEL2 value
    • [4:5]TX_SEL3 (def=0x0) // TX_SEL3 value
    • [6:7]TX_SEL4 (def=0x0) // TX_SEL4 value
  • 0x40024406BMC_TX_SZ// PD send length register

    • [0:8]BMC_TX_SZ (def=0x0) // BMC_TX_SZ value
  • 0x40024408DATA_BUF// DMA cache data register

    • [0:7]DATA_BUF (def=0x0) // DATA_BUF value
  • 0x40024409STATUS// PD interrupt flag register

    • [0:1]BMC_AUX (def=0x0) // BMC_AUX value
    • [2]BUF_ERR (def=0x0) // BUF_ERR value
    • [3]IF_RX_BIT (def=0x0) // IF_RX_BIT value
    • [4]IF_RX_BYTE (def=0x0) // IF_RX_BYTE value
    • [5]IF_RX_ACT (def=0x0) // IF_RX_ACT value
    • [6]IF_RX_RESET (def=0x0) // IF_RX_RESET value
    • [7]IF_TX_END (def=0x0) // IF_TX_END value
  • 0x4002440ABMC_BYTE_CNT// Byte counter

    • [0:8]BMC_BYTE_CNT (def=0x0) // BMC_BYTE_CNT value
  • 0x4002440CPORT_CC1// CC1 port control register

    • [0]PA_CC1_AI (def=0x1) // PA_CC1_AI value
    • [1]CC1_PD (def=0x1) // port pull-down resistor enable
    • [2:3]CC1_PU (def=0x0) // CC1_PU value
    • [4]CC1_LVE (def=0x0) // CC1_LVE value
    • [5:7]CC1_CE (def=0x0) // CC1_CE value
  • 0x4002440EPORT_CC2// CC2 port control register

    • [0]PA_CC2_AI (def=0x0) // PA_CC2_AI value
    • [1]CC2_PD (def=0x0) // port pull-down resistor enable
    • [2:3]CC2_PU (def=0x0) // CC2_PU value
    • [4]CC2_LVE (def=0x0) // CC2_LVE value
    • [5:7]CC2_CE (def=0x0) // CC2_CE value
  • 0x40024410DMA// PD buffer start address register

    • [0:20]USBPD_DMA_ADDR (def=0x0) // USBPD_DMA_ADDR value
  interrupts:
  • [55] USBPDWakeUP // USBPD_WKUP global interrupt
  • [54] USBPD // USBPD global interrupt
• 0x50000000USB_OTG_FS// USB FS OTG register

  • 0x50000000R8_USB_CTRL// USB base control

    • [0]RB_UC_DMA_EN (def=0x0) // DMA enable and DMA interrupt enable for USB
    • [1]RB_UC_CLR_ALL (def=0x0) // force clear FIFO and count of USB
    • [2]RB_UC_RST_SIE (def=0x0) // force reset USB SIE, need software clear
    • [3]RB_UC_INT_BUSY (def=0x0) // enable automatic responding busy for device mode or automatic pause for host mode during interrupt
    • [4:5]MASK_UC_SYS_CTRL_RB_UC_DEV_PU_EN (def=0x0) // USB device enable and internal pullup resistance enable
    • [6]RB_UC_LOW_SPEED (def=0x0) // enable USB low speed: 0=12Mbps, 1=1.5Mbps
    • [7]RB_UC_HOST_MODE (def=0x0) // enable USB host mode: 0=device mode, 1=host mode
  • 0x50000001UDEV_CTRL__UHOST_CTRL// USB device/host physical prot control

    • [0]RB_UH_PORT_EN__RB_UD_PORT_EN (def=0x0) // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
    • [1]RB_UH_BUS_RESET__RB_UD_GP_BIT (def=0x0) // force clear FIFO and count of USB
    • [2]RB_UH_LOW_SPEED__RB_UD_LOW_SPEED (def=0x0) // enable USB port low speed: 0=full speed, 1=low speed
    • [4]RB_UH_DM_PIN__RB_UD_DM_PIN (def=0x0) // ReadOnly: indicate current UDM pin level
    • [5]RB_UH_DP_PIN__RB_UD_DP_PIN (def=0x0) // USB device enable and internal pullup resistance enable
    • [7]RB_UH_PD_DIS__RB_UD_PD_DIS (def=0x0) // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
  • 0x50000002R8_USB_INT_EN// USB interrupt enable

    • [0]RB_UIE_BUS_RST__RB_UIE_DETECT (def=0x0) // enable interrupt for USB bus reset event for USB device mode
    • [1]RB_UIE_TRANSFER (def=0x0) // enable interrupt for USB transfer completion
    • [2]RB_UIE_SUSPEND (def=0x0) // enable interrupt for USB suspend or resume event
    • [3]RB_UIE_HST_SOF (def=0x0) // enable interrupt for host SOF timer action for USB host mode
    • [4]RB_UIE_FIFO_OV (def=0x0) // enable interrupt for FIFO overflow
    • [6]RB_UIE_DEV_NAK (def=0x0) // enable interrupt for NAK responded for USB device mode
    • [7]RB_UIE_DEV_SOF (def=0x0) // enable interrupt for SOF received for USB device mode
  • 0x50000003R8_USB_DEV_AD// USB device address

    • [0:6]MASK_USB_ADDR (def=0x0) // bit mask for USB device address
    • [7]RB_UDA_GP_BIT (def=0x0) // general purpose bit
  • 0x50000005R8_USB_MIS_ST// USB miscellaneous status

    • [0]RB_UMS_DEV_ATTACH (def=0x0) // RO, indicate device attached status on USB host
    • [1]RB_UMS_DM_LEVEL (def=0x0) // RO, indicate UDM level saved at device attached to USB host
    • [2]RB_UMS_SUSPEND (def=0x0) // RO, indicate USB suspend status
    • [3]RB_UMS_BUS_RESET (def=0x0) // RO, indicate USB bus reset status
    • [4]RB_UMS_R_FIFO_RDY (def=0x0) // RO, indicate USB receiving FIFO ready status (not empty)
    • [5]RB_UMS_SIE_FREE (def=0x0) // RO, indicate USB SIE free status
    • [6]RB_UMS_SOF_ACT (def=0x0) // RO, indicate host SOF timer action status for USB host
    • [7]RB_UMS_SOF_PRES (def=0x0) // RO, indicate host SOF timer presage status
  • 0x50000006R8_USB_INT_FG// USB interrupt flag

    • [0]RB_UIF_BUS_RST__RB_UIF_DETECT (def=0x0) // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;de
    • [1]RB_UIF_TRANSFER (def=0x0) // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
    • [2]RB_UIF_SUSPEND (def=0x0) // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
    • [3]RB_UIF_HST_SOF (def=0x0) // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
    • [4]RB_UIF_FIFO_OV (def=0x0) // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
    • [5]RB_U_SIE_FREE (def=0x0) // RO, indicate USB SIE free status
    • [6]RB_U_TOG_OK (def=0x0) // RO, indicate current USB transfer toggle is OK
    • [7]RB_U_IS_NAK (def=0x0) // RO, indicate current USB transfer is NAK received
  • 0x50000007R8_USB_INT_ST// USB interrupt status

    • [0:3]MASK_UIS_H_RES__MASK_UIS_ENDP (def=0x0) // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out f
    • [4:5]MASK_UIS_TOKEN (def=0x0) // RO, bit mask of current token PID code received for USB device mode
    • [6]RB_UIS_TOG_OK (def=0x0) // RO, indicate current USB transfer toggle is OK
    • [7]RB_UIS_IS_NAK (def=0x0) // RO, indicate current USB transfer is NAK received for USB device mode
  • 0x50000008R16_USB_RX_LEN// USB receiving length
  • 0x5000000CR8_UEP4_1_MOD// endpoint 4/1 mode

    • [2]RB_UEP4_TX_EN (def=0x0) // enable USB endpoint 4 transmittal (IN)
    • [3]RB_UEP4_RX_EN (def=0x0) // enable USB endpoint 4 receiving (OUT)
    • [4]RB_UEP1_BUF_MOD (def=0x0) // buffer mode of USB endpoint 1
    • [6]RB_UEP1_TX_EN (def=0x0) // enable USB endpoint 1 transmittal (IN)
    • [7]RB_UEP1_RX_EN (def=0x0) // enable USB endpoint 1 receiving (OUT)
  • 0x5000000DR8_UEP2_3_MOD__R8_UH_EP_MOD// endpoint 2/3 mode;host endpoint mode

    • [0]RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD (def=0x0) // buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint
    • [2]RB_UEP2_TX_EN (def=0x0) // enable USB endpoint 2 transmittal (IN)
    • [3]RB_UEP2_RX_EN__RB_UH_EP_RX_EN (def=0x0) // enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving
    • [4]RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD (def=0x0) // buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint
    • [6]RB_UEP3_TX_EN__RB_UH_EP_TX_EN (def=0x0) // enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal
    • [7]RB_UEP3_RX_EN (def=0x0) // enable USB endpoint 3 receiving (OUT)
  • 0x5000000ER8_UEP5_6_MOD// endpoint 5/6 mode

    • [0]RB_UEP5_BUF_MOD (def=0x0) // buffer mode of USB endpoint 5
    • [2]RB_UEP5_TX_EN (def=0x0) // enable USB endpoint 5 transmittal (IN)
    • [3]RB_UEP5_RX_EN (def=0x0) // enable USB endpoint 5 receiving (OUT)
    • [4]RB_UEP6_BUF_MOD (def=0x0) // buffer mode of USB endpoint 6
    • [6]RB_UEP6_TX_EN (def=0x0) // enable USB endpoint 6 transmittal (IN)
    • [7]RB_UEP3_RX_EN (def=0x0) // enable USB endpoint 6 receiving (OUT)
  • 0x5000000FR8_UEP7_MOD// endpoint 7 mode

    • [0]RB_UEP7_BUF_MOD (def=0x0) // buffer mode of USB endpoint 7
    • [2]RB_UEP7_TX_EN (def=0x0) // enable USB endpoint 7 transmittal (IN)
    • [3]RB_UEP7_RX_EN (def=0x0) // enable USB endpoint 7 receiving (OUT)
  • 0x50000010R32_UEP0_DMA// endpoint 0 DMA buffer address
  • 0x50000014R32_UEP1_DMA// endpoint 1 DMA buffer address
  • 0x50000018R32_UEP2_DMA__R32_UH_RX_DMA// endpoint 2 DMA buffer address;host rx endpoint buffer high address
  • 0x5000001CR32_UEP3_DMA__R32_UH_TX_DMA// endpoint 3 DMA buffer address;host tx endpoint buffer high address
  • 0x50000020R32_UEP4_DMA// endpoint 4 DMA buffer address
  • 0x50000024R32_UEP5_DMA// endpoint 5 DMA buffer address
  • 0x50000028R32_UEP6_DMA// endpoint 6 DMA buffer address
  • 0x5000002CR32_UEP7_DMA// endpoint 7 DMA buffer address
  • 0x50000030R8_UEP0_T_LEN// endpoint 0 transmittal length
  • 0x50000032R8_UEP0_T_CTRL// endpoint 0 control

    • [0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
    • [2]RB_UEP_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x50000033R8_UEP0_R_CTRL// endpoint 0 control

    • [0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
    • [2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x50000034R8_UEP1_T_LEN// endpoint 1 transmittal length
  • 0x50000036R8_UEP1_T_CTRL___USBHD_UH_SETUP// endpoint 1 control

    • [0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
    • [2]RB_UEP_T_TOG_ (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
    • [6]RB_UH_SOF_EN (def=0x0) // USB host automatic SOF enable
    • [7]RB_UH_PRE_PID_EN (def=0x0) // USB host PRE PID enable for low speed device via hub
  • 0x50000037R8_UEP1_R_CTRL// endpoint 1 control

    • [0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
    • [2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x50000038R8_UEP2_T_LEN__USBHD_UH_EP_PID// endpoint 2 transmittal length

    • [0:3]RB_UH_ENDP_MASK (def=0x0) // bit mask of endpoint number for USB host transfer
    • [4:7]RB_UH_TOKEN_MASK (def=0x0) // bit mask of token PID for USB host transfer
  • 0x5000003AR8_UEP2_T_CTRL// endpoint 2 control

    • [0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
    • [2]RB_UEP_T_TOG_ (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x5000003BR8_UEP2_R_CTRL__USBHD_UH_RX_CTRL// endpoint 2 control

    • [0:1]MASK_UEP_R_RES___RB_UH_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
    • [2]RB_UEP_R_TOG___RB_UH_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG___RB_UH_R_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x5000003CR8_UEP3_T_LEN__USBHD_UH_TX_LEN// endpoint 3 transmittal length
  • 0x5000003ER8_UEP3_T_CTRL__USBHD_UH_TX_CTRL// endpoint 3 control

    • [0:1]MASK_UEP_T_RES___RB_UH_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
    • [2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x5000003FR8_UEP3_R_CTRL_// endpoint 3 control

    • [0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
    • [2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x50000040R8_UEP4_T_LEN// endpoint 4 transmittal length
  • 0x50000042R8_UEP4_T_CTRL// endpoint 4 control

    • [0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
    • [2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x50000043R8_UEP4_R_CTRL_// endpoint 4 control

    • [0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
    • [2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x50000044R8_UEP5_T_LEN// endpoint 5 transmittal length
  • 0x50000046R8_UEP5_T_CTRL// endpoint 5 control

    • [0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
    • [2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x50000047R8_UEP5_R_CTRL_// endpoint 5 control

    • [0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
    • [2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x50000048R8_UEP6_T_LEN// endpoint 6 transmittal length
  • 0x5000004AR8_UEP6_T_CTRL// endpoint 6 control

    • [0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
    • [2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x5000004BR8_UEP6_R_CTRL_// endpoint 6 control

    • [0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
    • [2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x5000004CR8_UEP7_T_LEN// endpoint 7 transmittal length
  • 0x5000004ER8_UEP7_T_CTRL// endpoint 7 control

    • [0:1]MASK_UEP_T_RES (def=0x0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
    • [2]RB_UEP_T_TOG___RB_UH_T_TOG (def=0x0) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG__RB_UH_T_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x5000004FR8_UEP7_R_CTRL_// endpoint 7 control

    • [0:1]MASK_UEP_R_RES (def=0x0) // bit mask of handshake response type for USB endpoint X receiving (OUT)
    • [2]RB_UEP_R_TOG (def=0x0) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
    • [3]RB_UEP_AUTO_TOG (def=0x0) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=
  • 0x50000054USB_OTG_CR// usb otg control

    • [0]USB_OTG_CR_DISCHARGEVBUS (def=0x0) // usb otg control
    • [1]USB_OTG_CR_CHARGEVBUS (def=0x0) // usb otg control
    • [2]USB_OTG_CR_IDPU (def=0x0) // usb otg control
    • [3]USB_OTG_CR_OTG_EN (def=0x0) // usb otg control
    • [4]USB_OTG_CR_VBUS (def=0x0) // usb otg control
    • [5]USB_OTG_CR_SESS (def=0x0) // usb otg control
  • 0x50000058USB_OTG_SR// usb otg status

    • [0]USB_OTG_SR_VBUS_VLD (def=0x0) // usb otg status
    • [1]USB_OTG_SR_SESS_VLD (def=0x0) // usb otg status
    • [2]USB_OTG_SR_SESS_END (def=0x0) // usb otg status
    • [3]USB_OTG_SR_ID_DIG (def=0x0) // usb otg status
  interrupts:
  • [68] USBFSWakeup // USBFSWakeUP
  • [67] USBFS // USBFS global interrupt
• 0x40030000USBHS// USB register

  • 0x40030000R8_USB_CTRL// USB base control register

    • [0]RB_UD_RST_LINK (def=0x1) // LINK layer reset,highly effective
    • [1]RB_UD_RST_SIE (def=0x1) // USB protocol processor reset
    • [2]RB_UD_CLR_ALL (def=0x1) // clear all interrupt flags
    • [3]RB_UD_PHY_SUSPENDM (def=0x0) // USB PHY suspend
    • [4]RB_UD_DMA_EN (def=0x0) // DMA transfer enabled
    • [5]RB_UD_DEV_EN (def=0x0) // USB device enabled
    • [7]RB_UD_LPM_EN (def=0x0) // LPM enable
  • 0x40030001R8_USB_BASE_MODE// USB mode control register

    • [0:1]RB_UD_SPEED_TYPE (def=0x0) // The desired speed mode of the device
  • 0x40030002R8_USB_INT_EN// USB interrupt enable register

    • [0]RB_UDIE_BUS_RST (def=0x0) // USB bus reset interrupt enabled
    • [1]RB_UDIE_SUSPEND (def=0x0) // USB bus pause interrupt enabled
    • [2]RB_UDIE_BUS_SLEEP (def=0x0) // USB bus sleep interrupt enabled
    • [3]RB_UDIE_LPM_ACT (def=0x0) // LMP transfer end interrupt enabled
    • [4]RB_UDIE_TRANSFER (def=0x0) // USB transfer end interrupt enabled
    • [5]RB_UDIE_SOF_ACT (def=0x0) // Receive SOF packet interrupt enable
    • [6]RB_UDIE_LINK_RDY (def=0x0) // USB connection interrupt enable
    • [7]RB_UDIE_FIFO_OVER (def=0x0) // USB Overflow interrupt enable
  • 0x40030003R8_USB_DEV_AD// USB device address

    • [0:6]RB_MASK_USB_ADDR (def=0x0) // bit mask for USB device address
  • 0x40030004R8_USB_WAKE_CTRL// USB remote wake up register

    • [0]RB_UD_REMOTE_WKUP (def=0x0) // remote wake up
  • 0x40030005R8_USB_TEST_MODE// USB test mode register

    • [0]RB_UD_TEST_J (def=0x0) // test mode,output J
    • [1]RB_UD_TEST_K (def=0x0) // test mode,output K
    • [2]RB_UD_TEST_PKT (def=0x0) // test mode,output a packet
    • [3]RB_UD_TEST_SE0NAK (def=0x0) // test mode,output SEO
    • [7]RB_UD_TEST_EN (def=0x0) // test mode enable
  • 0x40030006R16_USB_LPM_DATA// USB power management register

    • [0:10]RB_UD_LPM_DATA (def=0x0) // power management data
    • [15]RB_UD_LPM_BUSY (def=0x1) // power management busy
  • 0x40030008R8_USB_INT_FG// USB interrupt flag register

    • [0]RB_UDIF_BUS_RST (def=0x0) // USB bus reset interrupt flag
    • [1]RB_UDIF_SUSPEND (def=0x0) // USB bus suspend interrupt flag
    • [2]RB_UDIF_BUS_SLEEP (def=0x0) // USB bus sleep interrupt flag
    • [3]RB_UDIF_LPM_ACT (def=0x0) // LPM transmission end interrupt flag
    • [4]RB_UDIF_RTX_ACT (def=0x0) // USB transmission end interrupt flag
    • [5]RB_UDIF_RX_SOF (def=0x0) // Receive SOF packet interrupt flag
    • [6]RB_UDIF_LINK_RDY (def=0x0) // USB connection interrupt flag
    • [7]RB_UDIF_FIFO_OV (def=0x0) // USB Overflow interrupt flag
  • 0x40030009R8_USB_INT_ST// USB interrupt status

    • [0:2]RB_UDIS_EP_ID_MASK (def=0x0) // The endpoint number at which the data transfer occurs
    • [4]RB_UDIS_EP_DIR (def=0x0) // Endpoint data transmission direction
  • 0x4003000AR8_USB_MIS_ST// USB miscellaneous status

    • [0]RB_UDMS_READY (def=0x0) // USB connection status
    • [1]RB_UDMS_SUSPEND (def=0x0) // USB suspend status
    • [2]RB_UDMS_SLEEP (def=0x0) // USB sleep status
    • [3]RB_UDMS_SIE_FREE (def=0x0) // USB free status
    • [4]RB_UDMS_SUSP_REQ (def=0x0) // USB suspends the request
    • [7]RB_UDMS_HS_MOD (def=0x0) // whether the host is high-speed
  • 0x4003000CR16_USB_FRAM_NO// USB frame number

    • [13:15]RB_UD_MFRAME_NO (def=0x0) // Received micro frame number
    • [0:10]RB_UD_FRAME_NO (def=0x0) // Received frame number
  • 0x4003000ER16_USB_BUS// USB bus

    • [3]RB_USB_DM_ST (def=0x0) // UDM status
    • [2]RB_USB_DP_ST (def=0x0) // UDP status
    • [0]RB_USB_WAKEUP (def=0x0) // USB wakeup
  • 0x40030010UEP_TX_EN// USB endpoint sends the enable register

    • [0:15]RB_UEP_TX_EN (def=0x0) // Endpoint 0 to 15 sends enable
  • 0x40030012UEP_RX_EN// USB endpoint receive the enable registers

    • [0:15]RB_UEP_RX_EN (def=0x0) // Endpoint 0 to 15 receive enable
  • 0x40030014R16_UEP_T_TOG_AUTO// USB endpoint sends the auto-filp enable register

    • [0:7]RB_UEP_T_TOG_AUTO (def=0x0) // 0 to 7 endpoint synchronization triggers bit auto-filp enable
  • 0x40030016R16_UEP_R_TOG_AUTO// USB endpoint receive the auto-filp enable register

    • [0:7]RB_UEP_R_TOG_AUTO (def=0x0) // 0 to 7 endpoint synchronization triggers bit auto-filp enable
  • 0x40030018R8_UEP_T_BURST// USB endpoint sends a burst register

    • [0:7]RB_UEP_T_BURST_EN (def=0x0) // 0 to 7 endpoint send burst enable
  • 0x40030019R16_UEP_T_BURST_MODE// USB endpoint send the mode register

    • [0:7]RB_UEP_T_BURST_MODE (def=0x0) // 0 to 7 endpoint send the mode enable
  • 0x4003001AR8_UEP_R_BURST// USB endpoint receives the burst register

    • [0:7]RB_UEP_R_BURST_EN (def=0x0) // 0 to 7 endpoint receive burst enable
  • 0x4003001BR8_UEP_R_RES_MODE// USB endpoint reply mode register

    • [0:7]RB_UEP_R_RES_MODE (def=0x0) // 0 to 7 endpoint reply mode
  • 0x4003001CR32_UEP_AF_MODE// USB endpoint muitiplexing register

    • [1:7]RB_UEP_T_AF (def=0x0) // 1 to 7 endpoint muitiplexing enables
  • 0x40030020R32_UEP0_DMA// The start address register of the endpoint 0 buffer

    • [0:23]UEP0_DMA (def=0x0) // The start address of the endpoint 0 buffer
  • 0x40030024R32_UEP1_RX_DMA// endpoint 1 receives the start address register of the buffer

    • [0:23]UEP1_RX_DMA (def=0x0) // endpoint receives the start address register of the buffer
  • 0x40030028R32_UEP2_RX_DMA// endpoint 2 receives the start address register of the buffer

    • [0:23]UEP2_RX_DMA (def=0x0) // endpoint receives the start address register of the buffer
  • 0x4003002CR32_UEP3_RX_DMA// endpoint 3 receives the start address register of the buffer

    • [0:23]UEP3_RX_DMA (def=0x0) // endpoint receives the start address register of the buffer
  • 0x40030030R32_UEP4_RX_DMA// endpoint 4 receives the start address register of the buffer

    • [0:23]UEP4_RX_DMA (def=0x0) // endpoint receives the start address register of the buffer
  • 0x40030034R32_UEP5_RX_DMA// endpoint 5 receives the start address register of the buffer

    • [0:23]UEP5_RX_DMA (def=0x0) // endpoint receives the start address register of the buffer
  • 0x40030038R32_UEP6_RX_DMA// endpoint 6 receives the start address register of the buffer

    • [0:23]UEP6_RX_DMA (def=0x0) // endpoint receives the start address register of the buffer
  • 0x4003003CR32_UEP7_RX_DMA// endpoint 7 receives the start address register of the buffer

    • [0:23]UEP7_RX_DMA (def=0x0) // endpoint receives the start address register of the buffer
  • 0x40030040R32_UEP1_TX_DMA// endpoint 1 sends the start address register of the buffer

    • [0:23]UEP1_TX_DMA (def=0x0) // endpoint sends the start address register of the buffer
  • 0x40030044R32_UEP2_TX_DMA// endpoint 2 sends the start address register of the buffer

    • [0:23]UEP2_TX_DMA (def=0x0) // endpoint sends the start address register of the buffer
  • 0x40030048R32_UEP3_TX_DMA// endpoint 3 sends the start address register of the buffer

    • [0:23]UEP3_TX_DMA (def=0x0) // endpoint sends the start address register of the buffer
  • 0x4003004CR32_UEP4_TX_DMA// endpoint 4 sends the start address register of the buffer

    • [0:23]UEP4_TX_DMA (def=0x0) // endpoint sends the start address register of the buffer
  • 0x40030050R32_UEP5_TX_DMA// endpoint 5 sends the start address register of the buffer

    • [0:23]UEP5_TX_DMA (def=0x0) // endpoint sends the start address register of the buffer
  • 0x40030054R32_UEP6_TX_DMA// endpoint 6 sends the start address register of the buffer

    • [0:23]UEP6_TX_DMA (def=0x0) // endpoint sends the start address register of the buffer
  • 0x40030058R32_UEP7_TX_DMA// endpoint 7 sends the start address register of the buffer

    • [0:23]UEP7_TX_DMA (def=0x0) // endpoint sends the start address register of the buffer
  • 0x4003005CR32_UEP0_MAX_LEN// endpoint 0 max length packet register

    • [0:10]UEP0_MAX_LEN (def=0x0) // endpoint 0 max acceptable offset length
  • 0x40030060R32_UEP1_MAX_LEN// endpoint 1 max length packet register

    • [0:6]UEP1_MAX_LEN (def=0x0) // endpoint 1 max acceptable offset length
  • 0x40030064R32_UEP2_MAX_LEN// endpoint 2 max length packet register

    • [0:6]UEP2_MAX_LEN (def=0x0) // endpoint 2 max acceptable offset length
  • 0x40030068R32_UEP3_MAX_LEN// endpoint 3 max length packet register

    • [0:6]UEP3_MAX_LEN (def=0x0) // endpoint 3 max acceptable offset length
  • 0x4003006CR32_UEP4_MAX_LEN// endpoint 4 max length packet register

    • [0:6]UEP4_MAX_LEN (def=0x0) // endpoint 4 max acceptable offset length
  • 0x40030070R32_UEP5_MAX_LEN// endpoint 5 max length packet register

    • [0:6]UEP5_MAX_LEN (def=0x0) // endpoint 5 max acceptable offset length
  • 0x40030074R32_UEP6_MAX_LEN// endpoint 6 max length packet register

    • [0:6]UEP6_MAX_LEN (def=0x0) // endpoint 6 max acceptable offset length
  • 0x40030078R32_UEP7_MAX_LEN// endpoint 7 max length packet register

    • [0:6]UEP7_MAX_LEN (def=0x0) // endpoint 7 max acceptable offset length
  • 0x4003007CR16_UEP0_RX_LEN// endpoint 0 acceptable length

    • [0:6]UEP0_RX_LEN (def=0x0) // endpoint 0 acceptable data length
  • 0x40030080R16_UEP1_RX_LEN// endpoint 1 receives the lenth register in a single pass

    • [0:15]UEP1_RX_LEN (def=0x0) // the length of data received by endpoint 1 in a single pass
  • 0x40030084R16_UEP2_RX_LEN// endpoint 2 receives the lenth register in a single pass

    • [0:15]UEP2_RX_LEN (def=0x0) // the length of data received by endpoint 2 in a single pass
  • 0x40030088R16_UEP3_RX_LEN// endpoint 3 receives the lenth register in a single pass

    • [0:15]UEP3_RX_LEN (def=0x0) // the length of data received by endpoint 3 in a single pass
  • 0x4003008CR16_UEP4_RX_LEN// endpoint 4 receives the lenth register in a single pass

    • [0:15]UEP4_RX_LEN (def=0x0) // the length of data received by endpoint 4 in a single pass
  • 0x40030090R16_UEP5_RX_LEN// endpoint 5 receives the lenth register in a single pass

    • [0:15]UEP5_RX_LEN (def=0x0) // the length of data received by endpoint 5 in a single pass
  • 0x40030094UEP6_RX_LEN// endpoint 6 receives the lenth register in a single pass

    • [0:15]UEP6_RX_LEN (def=0x0) // the length of data received by endpoint 6 in a single pass
  • 0x40030098R16_UEP7_RX_LEN// endpoint 7 receives the lenth register in a single pass

    • [0:15]UEP7_RX_LEN (def=0x0) // the length of data received by endpoint 7 in a single pass
  • 0x40030082R16_UEP1_R_SIZE// the length register of the total received data at endpoint 1

    • [0:15]UEP1_R_SIZE (def=0x0) // the length of the total received data at endpoint 1
  • 0x40030086R16_UEP2_R_SIZE// the length register of the total received data at endpoint 2

    • [0:15]UEP2_R_SIZE (def=0x0) // the length of the total received data at endpoint 2
  • 0x4003008AR16_UEP3_R_SIZE// the length register of the total received data at endpoint 3

    • [0:15]UEP3_R_SIZE (def=0x0) // the length of the total received data at endpoint 3
  • 0x4003008ER16_UEP4_R_SIZE// the length register of the total received data at endpoint 4

    • [0:15]UEP4_R_SIZE (def=0x0) // the length of the total received data at endpoint 4
  • 0x40030092R16_UEP5_R_SIZE// the length register of the total received data at endpoint 5

    • [0:15]UEP5_R_SIZE (def=0x0) // the length of the total received data at endpoint 5
  • 0x40030096R16_UEP6_R_SIZE// the length register of the total received data at endpoint 6

    • [0:15]UEP6_R_SIZE (def=0x0) // the length of the total received data at endpoint 6
  • 0x4003009AR16_UEP7_R_SIZE// the length register of the total received data at endpoint 7

    • [0:15]UEP7_R_SIZE (def=0x0) // the length of the total received data at endpoint 7
  • 0x4003009CR16_UEP0_T_LEN// endpoint 0 send the length

    • [0:6]UEP0_T_LEN (def=0x0) // endpoint 0 send the length
  • 0x4003009ER8_UEP0_TX_CTRL// endpoint 0 send control register

    • [0:1]RB_UEP_T_RES_MASK (def=0x0) // endpoint 0 control of the send response to IN transactions
    • [2]RB_UEP_T_TOG_MASK (def=0x0) // endpoint 0 synchronous trigger bit for the sender to prepare
    • [6]RB_UEP_T_NAK_ACT (def=0x0) // endpoint 0 sends the end flag
    • [7]RB_UEP_T_DONE (def=0x0) // endpoint 0 sends the end of NAK flag
  • 0x4003009FR8_UEP0_RX_CTRL// endpoint 0 send control register

    • [0:1]RB_UEP_R_RES_MASK (def=0x0) // endpoint 0 has control over the received response
    • [2]RB_UEP_R_TOG_MASK (def=0x0) // the reception of endpoint 0 expects a synchronous trigger bit
    • [3]RB_UEP_R_SETUP_IS (def=0x0) // whether endpoint 0 receives a SETUP transaction
    • [4]RB_UEP_R_TOG_MATCH (def=0x0) // received synchronization trigger bit matches the desired synchronization trigger bit state
    • [5]RB_UEP_R_NAK_TOG (def=0x0) // endpoint 0 for the received return NAK,packet type
    • [6]RB_UEP_R_NAK_ACT (def=0x0) // endpoint 0 receives the end of NAK flag
    • [7]RB_UEP_R_DONE (def=0x0) // endpoint 0 receives the end flag
  • 0x400300A0R16_UEP1_T_LEN// endpoint 1 send the length register

    • [0:15]UEP1_T_LEN (def=0x0) // endpoint 1 send the length
  • 0x400300A2R8_UEP1_TX_CTRL// endpoint 1 send control register

    • [0:1]RB_UEP_T_RES_MASK (def=0x0) // endpoint 1 control of the send response to IN transactions
    • [2:3]RB_UEP_T_TOG_MASK (def=0x0) // endpoint 1 synchronous trigger bit for the sender to prepare
    • [6]RB_UEP_T_NAK_ACT (def=0x0) // endpoint 1 sends the end flag
    • [7]RB_UEP_T_DONE (def=0x0) // endpoint 1 sends the end of NAK flag
  • 0x400300A3R8_UEP1_RX_CTRL// endpoint 1 receive control

    • [0:1]RB_UEP_R_RES_MASK (def=0x0) // endpoint 1 has control over the received response
    • [2:3]RB_UEP_R_TOG_MASK (def=0x0) // the reception of endpoint 1 expects a synchronous trigger bit
    • [4]RB_UEP_R_TOG_MATCH (def=0x0) // received synchronization trigger bit matches the desired synchronization trigger bit state
    • [5]RB_UEP_R_NAK_TOG (def=0x0) // endpoint 1 for the received return NAK,packet type
    • [6]RB_UEP_R_NAK_ACT (def=0x0) // endpoint 1 receives the end of NAK flag
    • [7]RB_UEP_R_DONE (def=0x0) // endpoint 1 receives the end flag
  • 0x400300A4R16_UEP2_T_LEN// endpoint 2 send the length register

    • [0:15]UEP2_T_LEN (def=0x0) // endpoint 2 send the length
  • 0x400300A6UEP2_TX_CTRL// endpoint 2 send control register

    • [0:1]RB_UEP_T_RES_MASK (def=0x0) // endpoint 2 control of the send response to IN transactions
    • [2:3]RB_UEP_T_TOG_MAS (def=0x0) // endpoint 2 synchronous trigger bit for the sender to prepare
    • [6]RB_UEP_T_NAK_ACT (def=0x0) // endpoint 2 sends the end flag
    • [7]RB_UEP_T_DONE (def=0x0) // endpoint 2 sends the end of NAK flag
  • 0x400300A7R8_UEP2_RX_CTRL// endpoint 2 receive control

    • [0:1]RB_UEP_R_RES_MASK (def=0x0) // endpoint 2 has control over the received response
    • [2:3]RB_UEP_R_TOG_MASK (def=0x0) // the reception of endpoint 2 expects a synchronous trigger bit
    • [4]RB_UEP_R_TOG_MATCH (def=0x0) // received synchronization trigger bit matches the desired synchronization trigger bit state
    • [5]RB_UEP_R_NAK_TOG (def=0x0) // endpoint 2 for the received return NAK,packet type
    • [6]RB_UEP_R_NAK_ACT (def=0x0) // endpoint 2 receives the end of NAK flag
    • [7]RB_UEP_R_DONE (def=0x0) // endpoint 2 receives the end flag
  • 0x400300A8R16_UEP3_T_LEN// endpoint 3 send the length register

    • [0:15]UEP3_T_LEN (def=0x0) // endpoint 3 send the length
  • 0x400300AAR8_UEP3_TX_CTRL// endpoint 3 send control register

    • [0:1]RB_UEP_T_RES_MASK (def=0x0) // endpoint 3 control of the send response to IN transactions
    • [2:3]RB_UEP_T_TOG_MASK (def=0x0) // endpoint 3 synchronous trigger bit for the sender to prepare
    • [6]RB_UEP_T_NAK_ACT (def=0x0) // endpoint 3 sends the end flag
    • [7]RB_UEP_T_DONE (def=0x0) // endpoint 3 sends the end of NAK flag
  • 0x400300ABUEP3_RX_CTRL// endpoint 3 receive control

    • [0:1]RB_UEP_R_RES_MASK (def=0x0) // endpoint 3 has control over the received response
    • [2:3]RB_UEP_R_TOG_MASK (def=0x0) // the reception of endpoint 3 expects a synchronous trigger bit
    • [4]RB_UEP_R_TOG_MATCH (def=0x0) // received synchronization trigger bit matches the desired synchronization trigger bit state
    • [5]RB_UEP_R_NAK_TOG (def=0x0) // endpoint 3 for the received return NAK,packet type
    • [6]RB_UEP_R_NAK_ACT (def=0x0) // endpoint 3 receives the end of NAK flag
    • [7]RB_UEP_R_DONE (def=0x0) // endpoint 3 receives the end flag
  • 0x400300ACR16_UEP4_T_LEN// endpoint 4 send the length register

    • [0:15]UEP4_T_LEN (def=0x0) // endpoint 4 send the length
  • 0x400300AEUEP4_TX_CTRL// endpoint 4 send control register

    • [0:1]RB_UEP_T_RES_MASK (def=0x0) // endpoint 4 control of the send response to IN transactions
    • [2:3]RB_UEP_T_TOG_MASK (def=0x0) // endpoint 4 synchronous trigger bit for the sender to prepare
    • [6]RB_UEP_T_NAK_ACT (def=0x0) // endpoint 4 sends the end flag
    • [7]RB_UEP_T_DONE (def=0x0) // endpoint 4 sends the end of NAK flag
  • 0x400300AFR8_UEP4_RX_CTRL// endpoint 4 receive control

    • [0:1]RB_UEP_R_RES_MASK (def=0x0) // endpoint 4 has control over the received response
    • [2:3]RB_UEP_R_TOG_MASK (def=0x0) // the reception of endpoint 4 expects a synchronous trigger bit
    • [4]RB_UEP_R_TOG_MATCH (def=0x0) // received synchronization trigger bit matches the desired synchronization trigger bit state
    • [5]RB_UEP_R_NAK_TOG (def=0x0) // endpoint 4 for the received return NAK,packet type
    • [6]RB_UEP_R_NAK_ACT (def=0x0) // endpoint 4 receives the end of NAK flag
    • [7]RB_UEP_R_DONE (def=0x0) // endpoint 4 receives the end flag
  • 0x400300B0R16_UEP5_T_LEN// endpoint 5 send the length register

    • [0:15]UEP5_T_LEN (def=0x0) // endpoint 5 send the length
  • 0x400300B2R8_UEP5_TX_CTRL// endpoint 5 send control register

    • [0:1]RB_UEP_T_RES_MASK (def=0x0) // endpoint 5 control of the send response to IN transactions
    • [2:3]RB_UEP_T_TOG_MASK (def=0x0) // endpoint 5 synchronous trigger bit for the sender to prepare
    • [6]RB_UEP_T_NAK_ACT (def=0x0) // endpoint 5 sends the end flag
    • [7]RB_UEP_T_DONE (def=0x0) // endpoint 5 sends the end of NAK flag
  • 0x400300B3R8_UEP5_RX_CTRL// endpoint 5 receive control

    • [0:1]RB_UEP_R_RES_MASK (def=0x0) // endpoint 5 has control over the received response
    • [2:3]RB_UEP_R_TOG_MASK (def=0x0) // the reception of endpoint 5 expects a synchronous trigger bit
    • [4]RB_UEP_R_TOG_MATCH (def=0x0) // received synchronization trigger bit matches the desired synchronization trigger bit state
    • [5]RB_UEP_R_NAK_TOG (def=0x0) // endpoint 5 for the received return NAK,packet type
    • [6]RB_UEP_R_NAK_ACT (def=0x0) // endpoint 5 receives the end of NAK flag
    • [7]RB_UEP_R_DONE (def=0x0) // endpoint 5 receives the end flag
  • 0x400300B4R16_UEP6_T_LEN// endpoint 6 send the length register

    • [0:15]UEP6_T_LEN (def=0x0) // endpoint 6 send the length
  • 0x400300B6R8_UEP6_TX_CTRL// endpoint 6 send control register

    • [0:1]RB_UEP_T_RES_MASK (def=0x0) // endpoint 6 control of the send response to IN transactions
    • [2:3]RB_UEP_T_TOG_MASK (def=0x0) // endpoint 6 synchronous trigger bit for the sender to prepare
    • [6]RB_UEP_T_NAK_ACT (def=0x0) // endpoint 6 sends the end flag
    • [7]RB_UEP_T_DONE (def=0x0) // endpoint 6 sends the end of NAK flag
  • 0x400300B7R8_UEP6_RX_CTRL// endpoint 6 receive control

    • [0:1]RB_UEP_R_RES_MASK (def=0x0) // endpoint 6 has control over the received response
    • [2:3]RB_UEP_R_TOG_MASK (def=0x0) // the reception of endpoint 6 expects a synchronous trigger bit
    • [4]RB_UEP_R_TOG_MATCH (def=0x0) // received synchronization trigger bit matches the desired synchronization trigger bit state
    • [5]RB_UEP_R_NAK_TOG (def=0x0) // endpoint 6 for the received return NAK,packet type
    • [6]RB_UEP_R_NAK_ACT (def=0x0) // endpoint 6 receives the end of NAK flag
    • [7]RB_UEP_R_DONE (def=0x0) // endpoint 6 receives the end flag
  • 0x400300B8R16_UEP7_T_LEN// endpoint 7 send the length register

    • [0:15]UEP7_T_LEN (def=0x0) // endpoint 7 send the length
  • 0x400300BAR8_UEP7_TX_CTRL// endpoint 7 send control register

    • [0:1]RB_UEP_T_RES_MASK (def=0x0) // endpoint 7 control of the send response to IN transactions
    • [2:3]RB_UEP_T_TOG_MASK (def=0x0) // endpoint 7 synchronous trigger bit for the sender to prepare
    • [6]RB_UEP_T_NAK_ACT (def=0x0) // endpoint 7 sends the end flag
    • [7]RB_UEP_T_DONE (def=0x0) // endpoint 7 sends the end of NAK flag
  • 0x400300BBR8_UEP7_RX_CTRL// endpoint 7 receive control

    • [0:1]RB_UEP_R_RES_MASK (def=0x0) // endpoint 7 has control over the received response
    • [2:3]RB_UEP_R_TOG_MASK (def=0x0) // the reception of endpoint 7 expects a synchronous trigger bit
    • [4]RB_UEP_R_TOG_MATCH (def=0x0) // received synchronization trigger bit matches the desired synchronization trigger bit state
    • [5]RB_UEP_R_NAK_TOG (def=0x0) // endpoint 7 for the received return NAK,packet type
    • [6]RB_UEP_R_NAK_ACT (def=0x0) // endpoint 7 receives the end of NAK flag
    • [7]RB_UEP_R_DONE (def=0x0) // endpoint 7 receives the end flag
  • 0x400300BCR16_UEP_T_ISO// usb endpoint sends a synchronous mode enable register

    • [9:15]RB_UEP_T_FIFO_EN (def=0x0) // The FIFO mode of the TX of the endpoint is enabled
    • [1:7]RB_UEPn_T_ISO_EN (def=0x0) // upload endpoint(IN) synchronization mode enabled
  • 0x400300BER16_UEP_R_ISO// usb endpoint receives a synchronous mode enable register

    • [9:15]RB_UEP_R_FIFO_EN (def=0x0) // The FIFO mode of the TX of the endpoint is enabled
    • [1:7]RB_UEPn_R_ISO_EN (def=0x0) // down endpoint(OUT) synchronization mode enabled
  • 0x400300C0R32_UEP1_RX_FIFO// Receive FIFO address of usb endpoint 1

    • [16:31]RB_UEP_RX_FIFO_E (def=0x0) // The end FIFO address of the receiving endpoint
    • [0:15]RB_UEP_RX_FIFO_S (def=0x0) // The FIFO start address of the receiving endpoint
  • 0x400300C4R32_UEP2_RX_FIFO// Receive FIFO address of usb endpoint 2

    • [16:31]RB_UEP_RX_FIFO_E (def=0x0) // The end FIFO address of the receiving endpoint
    • [0:15]RB_UEP_RX_FIFO_S (def=0x0) // The FIFO start address of the receiving endpoint
  • 0x400300C8R32_UEP3_RX_FIFO// Receive FIFO address of usb endpoint 3

    • [16:31]RB_UEP_RX_FIFO_E (def=0x0) // The end FIFO address of the receiving endpoint
    • [0:15]RB_UEP_RX_FIFO_S (def=0x0) // The FIFO start address of the receiving endpoint
  • 0x400300CCR32_UEP4_RX_FIFO// Receive FIFO address of usb endpoint 4

    • [16:31]RB_UEP_RX_FIFO_E (def=0x0) // The end FIFO address of the receiving endpoint
    • [0:15]RB_UEP_RX_FIFO_S (def=0x0) // The FIFO start address of the receiving endpoint
  • 0x400300D0R32_UEP5_RX_FIFO// Receive FIFO address of usb endpoint 5

    • [16:31]RB_UEP_RX_FIFO_E (def=0x0) // The end FIFO address of the receiving endpoint
    • [0:15]RB_UEP_RX_FIFO_S (def=0x0) // The FIFO start address of the receiving endpoint
  • 0x400300D4R32_UEP6_RX_FIFO// Receive FIFO address of usb endpoint 6

    • [16:31]RB_UEP_RX_FIFO_E (def=0x0) // The end FIFO address of the receiving endpoint
    • [0:15]RB_UEP_RX_FIFO_S (def=0x0) // The FIFO start address of the receiving endpoint
  • 0x400300D8R32_UEP7_RX_FIFO// Receive FIFO address of usb endpoint 7

    • [16:31]RB_UEP_RX_FIFO_E (def=0x0) // The end FIFO address of the receiving endpoint
    • [0:15]RB_UEP_RX_FIFO_S (def=0x0) // The FIFO start address of the receiving endpoint
  • 0x400300DCR32_UEP1_TX_FIFO// The sending FIFO address of usb endpoint 1

    • [16:31]RB_UEP_TX_FIFO_E (def=0x0) // The end FIFO address of the sending endpoint
    • [0:15]RB_UEP_TX_FIFO_S (def=0x0) // The FIFO start address of the sending endpoint
  • 0x400300E0R32_UEP2_TX_FIFO// The sending FIFO address of usb endpoint 2

    • [16:31]RB_UEP_TX_FIFO_E (def=0x0) // The end FIFO address of the sending endpoint
    • [0:15]RB_UEP_TX_FIFO_S (def=0x0) // The FIFO start address of the sending endpoint
  • 0x400300E4R32_UEP3_TX_FIFO// The sending FIFO address of usb endpoint 3

    • [16:31]RB_UEP_TX_FIFO_E (def=0x0) // The end FIFO address of the sending endpoint
    • [0:15]RB_UEP_TX_FIFO_S (def=0x0) // The FIFO start address of the sending endpoint
  • 0x400300E8R32_UEP4_TX_FIFO// The sending FIFO address of usb endpoint 4

    • [16:31]RB_UEP_TX_FIFO_E (def=0x0) // The end FIFO address of the sending endpoint
    • [0:15]RB_UEP_TX_FIFO_S (def=0x0) // The FIFO start address of the sending endpoint
  • 0x400300ECR32_UEP5_TX_FIFO// The sending FIFO address of usb endpoint 5

    • [16:31]RB_UEP_TX_FIFO_E (def=0x0) // The end FIFO address of the sending endpoint
    • [0:15]RB_UEP_TX_FIFO_S (def=0x0) // The FIFO start address of the sending endpoint
  • 0x400300F0R32_UEP6_TX_FIFO// The sending FIFO address of usb endpoint 6

    • [16:31]RB_UEP_TX_FIFO_E (def=0x0) // The end FIFO address of the sending endpoint
    • [0:15]RB_UEP_TX_FIFO_S (def=0x0) // The FIFO start address of the sending endpoint
  • 0x400300F4R32_UEP7_TX_FIFO// The sending FIFO address of usb endpoint 7

    • [16:31]RB_UEP_TX_FIFO_E (def=0x0) // The end FIFO address of the sending endpoint
    • [0:15]RB_UEP_TX_FIFO_S (def=0x0) // The FIFO start address of the sending endpoint
  • 0x40030100R8_UH_CFG// USB host Configuration register

    • [0]RB_UH_RST_LINK (def=0x1) // USB connection controller module resets
    • [1]RB_UH_RST_SIE (def=0x1) // USB protocol processor reset
    • [2]RB_UH_CLR_ALL (def=0x1) // clear all interrupt flags
    • [3]RB_UH_PHY_SUSPENDM (def=0x0) // PHY suspend,close utmi clock
    • [4]RB_UH_DMA_EN (def=0x0) // DMA transfer enabled
    • [5]RB_UH_SOF_EN (def=0x0) // sof packet sending function enabled
    • [6]RB_UH_FORCE_FS (def=0x0) // forced full speed FS
    • [7]RB_UH_LPM_EN (def=0x0) // LPM enable
  • 0x40030102R8_UH_INT_EN// USB host interrupt enable register

    • [2]RB_UHIE_WKUP_ACT (def=0x0) // Wakeup interrupt enabled
    • [3]RB_UHIE_RESUME_ACT (def=0x0) // bus recovery interrupt was enabled
    • [4]RB_UHIE_TRANSFER (def=0x0) // USB transfer end interrupt enabled
    • [5]RB_UHIE_SOF_ACT (def=0x0) // sof packet sending interruption is enabled
    • [6]RB_UHIE_TX_HALT (def=0x0) // send pause interrupt enable
    • [7]RB_UHIE_FIFO_OVER (def=0x0) // FIFO overflow interrupt enable
  • 0x40030103R8_UH_DEV_AD// USB host device address register

    • [0:6]RB_UH_DEV_ADDR (def=0x0) // device address
  • 0x40030104R32_UH_CONTROL// USB host control register

    • [23]RB_UH_RX_NO_RES (def=0x0) // IN-DATA no answer,used for synchronous transfer or high-speed SPLIT packets
    • [22]RB_UH_TX_NO_RES (def=0x0) // OUT or SETUP DATA no reply is extended and is used for synchronous transmission or hign-spe
    • [21]RB_UH_RX_NO_DATA (def=0x0) // DATA packets are not expected after IN token packets and are used for high-speed SP
    • [20]RB_UH_TX_NO_DATA (def=0x0) // OUT or SETUP token packet packets are followed by no data packets for hign-speed SPLIT pack
    • [19]RB_UH_PRE_PID_EN (def=0x0) // this bit is enabled when the port is operating at full speed and needs to send low speed pa
    • [18]RB_UH_SPLIT_VALID (def=0x0) // valid to send SPLIT packet
    • [17]RB_UH_LPM_VALID (def=0x0) // valid to send LMP packet
    • [16]RB_UH_HOST_ACTION (def=0x0) // host enables the transaction
    • [10]RB_UH_BUF_MODE (def=0x0) // DATA cache control bit
    • [8:9]RB_UH_T_TOG_MASK (def=0x0) // send data PID
    • [4:7]RB_UH_T_ENDP_MASK (def=0x0) // transaction token packet endpoint number
    • [0:3]RB_UH_T_TOKEN_MASK (def=0x0) // transaction token packet PID
  • 0x40030108R8_UH_INT_FLAG// USB HOST interrupt flag register

    • [2]RB_UHIF_WKUP_ACT (def=0x0) // Wakeup interrupt flag
    • [3]RB_UHIF_RESUME_ACT_IF (def=0x0) // bus recovery interrupt flag
    • [4]RB_UHIF_TRANSFER (def=0x0) // USB transaction transfer completion interrupt flag
    • [5]RB_UHIF_SOF_ACT (def=0x0) // sof packet delivert completion interrupt flag
    • [6]RB_UHIF_TX_HALT (def=0x0) // send pause interrupt flag
    • [7]RB_UHIF_FIFO_OVER (def=0x0) // FIFO overflow interrupt flag
  • 0x40030109R8_UH_INT_ST// USB host interrupt status

    • [0:3]RB_UH_R_TOKEN_MASK (def=0x0) // received PID
    • [4]RB_UHIS_PORT_RX_RESUME (def=0x0) // A bit of indicates that the port received a wakeup signal
  • 0x4003010AR8_UH_MIS_ST// USB host miscellaneous status

    • [0]RB_UHMS_SOF_FREE (def=0x0) // port enabled state
    • [1]RB_UHMS_SOF_PRE (def=0x0) // The state of the USB SOF packet is indicated as follows
    • [2]RB_UHMS_SOF_ACT (def=0x0) // USB bus SOF status
    • [3]RB_UHMS_USB_WAKEUP (def=0x0) // USB bus wakes up
    • [4:5]RB_UHMS_LINESTATE (def=0x0) // USB bus status
    • [6]RB_UHMS_BUS_J (def=0x0) // J on USB bus
    • [7]RB_UHMS_BUS_SE0 (def=0x0) // SE0 on USB bus
  • 0x4003010CR32_UH_LPM_DATA// USB host power management data register

    • [0:10]RB_UH_LPM_DATA (def=0x0) // power management data
  • 0x40030110R32_UH_SPLIT_DATA// USB host SPLIT register

    • [0:18]RB_UH_SPLIT_DATA (def=0x0) // SPLIT management data
  • 0x40030114R32_UH_FRAME// USB host frame register

    • [0:10]RB_UH_FRAME_NO (def=0x0) // the frame number
    • [16:18]RB_UH_MFRAME_NO (def=0x0) // microfame number
    • [24]RB_UH_SOF_CNT_EN (def=0x0) // SOF count enabled
    • [25]RB_UH_SOF_CNT_CLR (def=0x0) // the SOF count is cleared
  • 0x40030118R32_UH_TX_LEN// USB host send length register

    • [0:10]RB_UH_TX_LEN (def=0x0) // send data length
  • 0x4003011CR32_UH_RX_LEN// USB host receive length register

    • [0:10]RB_UH_RX_LEN (def=0x0) // Received data length
  • 0x40030120R32_UH_RX_MAX_LEN// USB host receives the maximum length register

    • [0:10]RB_UH_RX_MAX_LEN (def=0x0) // receives the maximum length
  • 0x40030124R32_UH_RX_DMA// DMA receive address register

    • [0:23]R32_UH_RX_DMA (def=0x0) // Received address
  • 0x40030128R32_UH_TX_DMA// DMA send address register

    • [0:23]R32_UH_TX_DMA (def=0x0) // Send address
  • 0x4003012CR32_UH_PORT_CTRL// USB host port control register

    • [16]RB_UH_BUS_RST_LONG (def=0x0) // BUS reset time selection
    • [12:15]RB_UH_PORT_SLEEP_BESL (def=0x0) // wake-up time control
    • [8]RB_UH_CLR_PORT_SLEEP (def=0x0) // the PORT exits the sleep state (LPM)
    • [5]RB_UH_CLR_PORT_CONNECT (def=0x0) // bring the PORT into the port state
    • [4]RB_UH_CLR_PORT_EN (def=0x0) // PORT exits the enabled state and enters the DISABLED state
    • [3]RB_UH_SET_PORT_SLEEP (def=0x0) // the PORT goes to sleep(LPM)
    • [2]RB_UH_CLR_PORT_SUSP (def=0x0) // the PORT exits the suspended state
    • [1]RB_UH_SET_PORT_SUSP (def=0x0) // the PORT is in a suspended state
    • [0]RB_UH_SET_PORT_RESET (def=0x0) // PORT send reset
  • 0x40030130R8_UH_PORT_CFG// USB host port Configuration register

    • [7]RB_UH_PD_EN (def=0x0) // the 15k resistance drop-down function is enable in host mode
    • [0]RB_UH_HOST_EN (def=0x0) // USB port mode selection
  • 0x40030132R8_UH_PORT_INT_EN// USB host port interrupt enable register

    • [5]RB_UHIE_PORT_SLP (def=0x0) // port sleep state change interrupt enabled
    • [4]RB_UHIE_PORT_RESET (def=0x0) // port reset state change interrupt enabled
    • [2]RB_UHIE_PORT_SUSP (def=0x0) // port pause state change interrupt enabled
    • [1]RB_UHIE_PORT_EN (def=0x0) // port enable state change interrupt enabled
    • [0]RB_UHIE_PORT_CONNECT (def=0x0) // port connection state change interrupt enabled
  • 0x40030133R8_UH_PORT_TEST_CT// USB host port test mode register

    • [4]RB_UH_TEST_SE0_NAK (def=0x0) // test SE0 NAK
    • [3]RB_UH_TEST_PACKET (def=0x0) // test packet
    • [2]RB_UH_TEST_FORCE_EN (def=0x0) // test mode was enabled
    • [1]RB_UH_TEST_K (def=0x0) // test output K
    • [0]RB_UH_TEST_J (def=0x0) // test output J
  • 0x40030134R16_UH_PORT_ST// USB host port status register

    • [11]RB_UHIS_PORT_TEST (def=0x0) // whether the port is in test mode
    • [10]RB_UHIS_PORT_HS (def=0x0) // whether the port connection speed is hign
    • [9]RB_UHIS_PORT_LS (def=0x0) // whether the port connection speed is low
    • [5]RB_UHIS_PORT_SLP (def=0x0) // port sleep
    • [4]RB_UHIS_PORT_RST (def=0x1) // port reset status
    • [2]RB_UHIS_PORT_SUSP (def=0x0) // port pause state
    • [1]RB_UHIS_PORT_EN (def=0x0) // port enabled
    • [0]RB_UHIS_PORT_C0NNECT (def=0x0) // port connection state
  • 0x40030136R8_UH_PORT_CHG// USB host port state charge register

    • [5]RB_UHIF_PORT_SLP (def=0x0) // port sleep state charge
    • [4]RB_UHIF_PORT_RESET (def=0x1) // port reset state charge
    • [2]RB_UHIF_PORT_SUSP (def=0x0) // port pause state charge
    • [1]RB_UHIF_PORT_EN (def=0x0) // port enable state charge
    • [0]RB_UHIF_PORT_CONNECT (def=0x0) // port connection state charge
  • 0x4003013CR32_UH_BC_CTRL// USB host BC charging control register

    • [10]RB_UDM_VSRC_ACT (def=0x0) // In automatic mode, UDP outputs VBC_SRC ,otherwise it is controlled by UDM_BC_CMPE
    • [9]RB_UDM_BC_VSRC (def=0x0) // UDM pin BC protocol source voltage enabled
    • [8]RB_UDP_BC_VSRC (def=0x0) // UDP pin BC protocol source voltage enabled
    • [6]RB_BC_AUTO_MODE (def=0x0) // Automatic mode enables
    • [5]RB_UDM_BC_CMPE (def=0x0) // UDM pin BC protocol comparator enables
    • [4]RB_UDP_BC_CMPE (def=0x0) // UDP pin BC protocol comparator enables
    • [1]RB_UDM_BC_CMPO (def=0x0) // UDM pin BC protocol comparator status
    • [0]RB_UDP_BC_CMPO (def=0x0) // UDP pin BC protocol comparator status
  interrupts:
  • [56] USBHS // USBHS global interrupt
  • [64] USBHSWakeUP // USBHS Wakeup interrupt
• 0x40006400CAN1// Controller area network

  • 0x40006400CTLR// CAN Master control register

    • [17]CFGCANM (def=0x0) // Configure CAN offline recovery time
    • [16]DBF (def=0x1) // Debug freeze
    • [15]RST (def=0x0) // Software master reset
    • [7]TTCM (def=0x0) // Time triggered communication mode
    • [6]ABOM (def=0x0) // Automatic bus-off management
    • [5]AWUM (def=0x0) // Automatic wakeup mode
    • [4]NART (def=0x0) // No automatic retransmission
    • [3]RFLM (def=0x0) // Receive FIFO locked mode
    • [2]TXFP (def=0x0) // Transmit FIFO priority
    • [1]SLEEP (def=0x1) // Sleep mode request bit
    • [0]INRQ (def=0x0) // Initialization request
  • 0x40006404STATR// CAN master status register

    • [11]RX (def=0x0) // Rx signal
    • [10]SAMP (def=0x0) // Last sample point
    • [9]RXM (def=0x0) // Receive mode
    • [8]TXM (def=0x0) // Transmit mode
    • [4]SLAKI (def=0x0) // Sleep acknowledge interrupt
    • [3]WKUI (def=0x0) // Wakeup interrupt
    • [2]ERRI (def=0x0) // Error interrupt
    • [1]SLAK (def=0x1) // Sleep acknowledge
    • [0]INAK (def=0x0) // Initialization acknowledge
  • 0x40006408TSTATR// CAN transmit status register

    • [31]LOW2 (def=0x0) // Lowest priority flag for mailbox2
    • [30]LOW1 (def=0x0) // Lowest priority flag for mailbox1
    • [29]LOW0 (def=0x0) // Lowest priority flag for mailbox0
    • [28]TME2 (def=0x1) // Transmit mailbox 2 empty
    • [27]TME1 (def=0x1) // Transmit mailbox 1 empty
    • [26]TME0 (def=0x1) // Transmit mailbox 0 empty
    • [24:25]CODE (def=0x0) // Mailbox code
    • [23]ABRQ2 (def=0x0) // Abort request for mailbox 2
    • [19]TERR2 (def=0x0) // Transmission error of mailbox 2
    • [18]ALST2 (def=0x0) // Arbitration lost for mailbox 2
    • [17]TXOK2 (def=0x0) // Transmission OK of mailbox 2
    • [16]RQCP2 (def=0x0) // Request completed mailbox2
    • [15]ABRQ1 (def=0x0) // Abort request for mailbox 1
    • [11]TERR1 (def=0x0) // Transmission error of mailbox1
    • [10]ALST1 (def=0x0) // Arbitration lost for mailbox1
    • [9]TXOK1 (def=0x0) // Transmission OK of mailbox1
    • [8]RQCP1 (def=0x0) // Request completed mailbox1
    • [7]ABRQ0 (def=0x0) // Abort request for mailbox0
    • [3]TERR0 (def=0x0) // Transmission error of mailbox0
    • [2]ALST0 (def=0x0) // Arbitration lost for mailbox0
    • [1]TXOK0 (def=0x0) // Transmission OK of mailbox0
    • [0]RQCP0 (def=0x0) // Request completed mailbox0
  • 0x4000640CRFIFO0// CAN receive FIFO 0 register

    • [5]RFOM0 (def=0x0) // Release FIFO 0 output mailbox
    • [4]FOVR0 (def=0x0) // FIFO 0 overrun
    • [3]FULL0 (def=0x0) // FIFO 0 full
    • [0:1]FMP0 (def=0x0) // FIFO 0 message pending
  • 0x40006414INTENR// CAN interrupt enable register

    • [17]SLKIE (def=0x0) // Sleep interrupt enable
    • [16]WKUIE (def=0x0) // Wakeup interrupt enable
    • [15]ERRIE (def=0x0) // Error interrupt enable
    • [11]LECIE (def=0x0) // Last error code interrupt enable
    • [10]BOFIE (def=0x0) // Bus-off interrupt enable
    • [9]EPVIE (def=0x0) // Error passive interrupt enable
    • [8]EWGIE (def=0x0) // Error warning interrupt enable
    • [6]FOVIE1 (def=0x0) // FIFO overrun interrupt enable
    • [5]FFIE1 (def=0x0) // FIFO full interrupt enable
    • [4]FMPIE1 (def=0x0) // FIFO message pending interrupt enable
    • [3]FOVIE0 (def=0x0) // FIFO overrun interrupt enable
    • [2]FFIE0 (def=0x0) // FIFO full interrupt enable
    • [1]FMPIE0 (def=0x0) // FIFO message pending interrupt enable
    • [0]TMEIE (def=0x0) // Transmit mailbox empty interrupt enable
  • 0x40006418ERRSR// CAN error status register

    • [24:31]REC (def=0x0) // Receive error counter
    • [16:23]TEC (def=0x0) // Least significant byte of the 9-bit transmit error counter
    • [4:6]LEC (def=0x0) // Last error code
    • [2]BOFF (def=0x0) // Bus-off flag
    • [1]EPVF (def=0x0) // Error passive flag
    • [0]EWGF (def=0x0) // Error warning flag
  • 0x4000641CBTIMR// CAN bit timing register

    • [31]SILM (def=0x0) // Silent mode (debug)
    • [30]LBKM (def=0x0) // Loop back mode (debug)
    • [24:27]SJW (def=0x1) // Resynchronization jump width
    • [20:23]TS2 (def=0x2) // Time segment 2
    • [16:19]TS1 (def=0x3) // Time segment 1
    • [12:15]BTR_TS1_T (def=0x0) // CLAS_LONG_TS1=0;TS1 is TS[3:0](4bit);CLAS_LONG_TS1=1,TS1 is TS[1:0]+BTR_TS1_T[15:12](6bit)
    • [0:9]BRP (def=0x0) // minimum time unit length setting value
  • 0x40006420TTCTLR// CAN time trigger control register

    • [17]MODE (def=0x0) // Time-triggered mode selection
    • [16]TIMRST (def=0x0) // Internal counter reset control
    • [0:15]TIMCMV (def=0xFFFF) // Internal counter count end value
  • 0x40006424TTCNT// CAN Time Trigger Count Value Register

    • [0:15]TIMCNT (def=0x0) // time-triggered count value
  • 0x40006428TERR_CNT// CAN offline recovery error counter

    • [0:8]TX_ERR_CNT (def=0x0) // Offline recovery error count values
  • 0x40006580TXMI0R// CAN TX mailbox identifier register

    • [21:31]STID_EXID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
    • [0]TXRQ (def=0x0) // Transmit mailbox request
  • 0x40006584TXMDT0R// CAN mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8]TGT (def=0x0) // Transmit global time
    • [0:3]DLC (def=0x0) // Data length code
  • 0x40006588TXMDL0R// CAN mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data byte 3
    • [16:23]DATA2 (def=0x0) // Data byte 2
    • [8:15]DATA1 (def=0x0) // Data byte 1
    • [0:7]DATA0 (def=0x0) // Data byte 0
  • 0x4000658CTXMDH0R// CAN mailbox data high register

    • [24:31]DATA7 (def=0x0) // Data byte 7
    • [16:23]DATA6 (def=0x0) // Data byte 6
    • [8:15]DATA5 (def=0x0) // Data byte 5
    • [0:7]DATA4 (def=0x0) // Data byte 4
  • 0x40006590TXMI1R// CAN TX mailbox identifier register

    • [21:31]STID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
    • [0]TXRQ (def=0x0) // Transmit mailbox request
  • 0x40006594TXMDT1R// CAN mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8]TGT (def=0x0) // Transmit global time
    • [0:3]DLC (def=0x0) // Data length code
  • 0x40006598TXMDL1R// CAN mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data byte 3
    • [16:23]DATA2 (def=0x0) // Data byte 2
    • [8:15]DATA1 (def=0x0) // Data byte 1
    • [0:7]DATA0 (def=0x0) // Data byte 0
  • 0x4000659CTXMDH1R// CAN mailbox data high register

    • [24:31]DATA7 (def=0x0) // Data byte 7
    • [16:23]DATA6 (def=0x0) // Data byte 6
    • [8:15]DATA5 (def=0x0) // Data byte 5
    • [0:7]DATA4 (def=0x0) // Data byte 4
  • 0x400065A0TXMI2R// CAN TX mailbox identifier register

    • [21:31]STID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
    • [0]TXRQ (def=0x0) // Transmit mailbox request
  • 0x400065A4TXMDT2R// CAN mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8]TGT (def=0x0) // Transmit global time
    • [0:3]DLC (def=0x0) // Data length code
  • 0x400065A8TXMDL2R// CAN mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data byte 3
    • [16:23]DATA2 (def=0x0) // Data byte 2
    • [8:15]DATA1 (def=0x0) // Data byte 1
    • [0:7]DATA0 (def=0x0) // Data byte 0
  • 0x400065ACTXMDH2R// CAN mailbox data high register

    • [24:31]DATA7 (def=0x0) // Data byte 7
    • [16:23]DATA6 (def=0x0) // Data byte 6
    • [8:15]DATA5 (def=0x0) // Data byte 5
    • [0:7]DATA4 (def=0x0) // Data byte 4
  • 0x400065B0RXMI0R// CAN receive FIFO mailbox identifier register

    • [21:31]STID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
  • 0x400065B4RXMDT0R// CAN receive FIFO mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8:15]FMI (def=0x0) // Filter match index
    • [6]RES (def=0x0) // RES bit of the received frame
    • [5]ESI (def=0x0) // ESI bit of the received frame
    • [4]BRS (def=0x0) // BRS bit of the received frame
    • [0:3]DLC (def=0x0) // Data length code
  • 0x400065B8RXMDL0R// CAN receive FIFO mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data Byte 3
    • [16:23]DATA2 (def=0x0) // Data Byte 2
    • [8:15]DATA1 (def=0x0) // Data Byte 1
    • [0:7]DATA0 (def=0x0) // Data Byte 0
  • 0x400065BCRXMDH0R// CAN receive FIFO mailbox data high register

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  interrupts:
  • [59] CAN1_TX // CAN TX interrupts
  • [60] CAN1_RX0 // CAN RX0 interrupts
  • [58] CAN1_SCE // CAN SCE interrupt
• 0x40006800CAN2//

  • 0x40006800CTLR// CAN Master control register

    • [17]CFGCANM (def=0x0) // Configure CAN offline recovery time
    • [16]DBF (def=0x1) // Debug freeze
    • [15]RST (def=0x0) // Software master reset
    • [7]TTCM (def=0x0) // Time triggered communication mode
    • [6]ABOM (def=0x0) // Automatic bus-off management
    • [5]AWUM (def=0x0) // Automatic wakeup mode
    • [4]NART (def=0x0) // No automatic retransmission
    • [3]RFLM (def=0x0) // Receive FIFO locked mode
    • [2]TXFP (def=0x0) // Transmit FIFO priority
    • [1]SLEEP (def=0x1) // Sleep mode request bit
    • [0]INRQ (def=0x0) // Initialization request
  • 0x40006804STATR// CAN master status register

    • [11]RX (def=0x0) // Rx signal
    • [10]SAMP (def=0x0) // Last sample point
    • [9]RXM (def=0x0) // Receive mode
    • [8]TXM (def=0x0) // Transmit mode
    • [4]SLAKI (def=0x0) // Sleep acknowledge interrupt
    • [3]WKUI (def=0x0) // Wakeup interrupt
    • [2]ERRI (def=0x0) // Error interrupt
    • [1]SLAK (def=0x1) // Sleep acknowledge
    • [0]INAK (def=0x0) // Initialization acknowledge
  • 0x40006808TSTATR// CAN transmit status register

    • [31]LOW2 (def=0x0) // Lowest priority flag for mailbox2
    • [30]LOW1 (def=0x0) // Lowest priority flag for mailbox1
    • [29]LOW0 (def=0x0) // Lowest priority flag for mailbox0
    • [28]TME2 (def=0x1) // Transmit mailbox 2 empty
    • [27]TME1 (def=0x1) // Transmit mailbox 1 empty
    • [26]TME0 (def=0x1) // Transmit mailbox 0 empty
    • [24:25]CODE (def=0x0) // Mailbox code
    • [23]ABRQ2 (def=0x0) // Abort request for mailbox 2
    • [19]TERR2 (def=0x0) // Transmission error of mailbox 2
    • [18]ALST2 (def=0x0) // Arbitration lost for mailbox 2
    • [17]TXOK2 (def=0x0) // Transmission OK of mailbox 2
    • [16]RQCP2 (def=0x0) // Request completed mailbox2
    • [15]ABRQ1 (def=0x0) // Abort request for mailbox 1
    • [11]TERR1 (def=0x0) // Transmission error of mailbox1
    • [10]ALST1 (def=0x0) // Arbitration lost for mailbox1
    • [9]TXOK1 (def=0x0) // Transmission OK of mailbox1
    • [8]RQCP1 (def=0x0) // Request completed mailbox1
    • [7]ABRQ0 (def=0x0) // Abort request for mailbox0
    • [3]TERR0 (def=0x0) // Transmission error of mailbox0
    • [2]ALST0 (def=0x0) // Arbitration lost for mailbox0
    • [1]TXOK0 (def=0x0) // Transmission OK of mailbox0
    • [0]RQCP0 (def=0x0) // Request completed mailbox0
  • 0x4000680CRFIFO0// CAN receive FIFO 0 register

    • [5]RFOM0 (def=0x0) // Release FIFO 0 output mailbox
    • [4]FOVR0 (def=0x0) // FIFO 0 overrun
    • [3]FULL0 (def=0x0) // FIFO 0 full
    • [0:1]FMP0 (def=0x0) // FIFO 0 message pending
  • 0x40006814INTENR// CAN interrupt enable register

    • [17]SLKIE (def=0x0) // Sleep interrupt enable
    • [16]WKUIE (def=0x0) // Wakeup interrupt enable
    • [15]ERRIE (def=0x0) // Error interrupt enable
    • [11]LECIE (def=0x0) // Last error code interrupt enable
    • [10]BOFIE (def=0x0) // Bus-off interrupt enable
    • [9]EPVIE (def=0x0) // Error passive interrupt enable
    • [8]EWGIE (def=0x0) // Error warning interrupt enable
    • [6]FOVIE1 (def=0x0) // FIFO overrun interrupt enable
    • [5]FFIE1 (def=0x0) // FIFO full interrupt enable
    • [4]FMPIE1 (def=0x0) // FIFO message pending interrupt enable
    • [3]FOVIE0 (def=0x0) // FIFO overrun interrupt enable
    • [2]FFIE0 (def=0x0) // FIFO full interrupt enable
    • [1]FMPIE0 (def=0x0) // FIFO message pending interrupt enable
    • [0]TMEIE (def=0x0) // Transmit mailbox empty interrupt enable
  • 0x40006818ERRSR// CAN error status register

    • [24:31]REC (def=0x0) // Receive error counter
    • [16:23]TEC (def=0x0) // Least significant byte of the 9-bit transmit error counter
    • [4:6]LEC (def=0x0) // Last error code
    • [2]BOFF (def=0x0) // Bus-off flag
    • [1]EPVF (def=0x0) // Error passive flag
    • [0]EWGF (def=0x0) // Error warning flag
  • 0x4000681CBTIMR// CAN bit timing register

    • [31]SILM (def=0x0) // Silent mode (debug)
    • [30]LBKM (def=0x0) // Loop back mode (debug)
    • [24:27]SJW (def=0x1) // Resynchronization jump width
    • [20:23]TS2 (def=0x2) // Time segment 2
    • [16:19]TS1 (def=0x3) // Time segment 1
    • [12:15]BTR_TS1_T (def=0x0) // CLAS_LONG_TS1=0;TS1 is TS[3:0](4bit);CLAS_LONG_TS1=1,TS1 is TS[1:0]+BTR_TS1_T[15:12](6bit)
    • [0:9]BRP (def=0x0) // minimum time unit length setting value
  • 0x40006820TTCTLR// CAN time trigger control register

    • [17]MODE (def=0x0) // Time-triggered mode selection
    • [16]TIMRST (def=0x0) // Internal counter reset control
    • [0:15]TIMCMV (def=0xFFFF) // Internal counter count end value
  • 0x40006824TTCNT// CAN Time Trigger Count Value Register

    • [0:15]TIMCNT (def=0x0) // time-triggered count value
  • 0x40006828TERR_CNT// CAN offline recovery error counter

    • [0:8]TX_ERR_CNT (def=0x0) // Offline recovery error count values
  • 0x40006980TXMI0R// CAN TX mailbox identifier register

    • [21:31]STID_EXID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
    • [0]TXRQ (def=0x0) // Transmit mailbox request
  • 0x40006984TXMDT0R// CAN mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8]TGT (def=0x0) // Transmit global time
    • [0:3]DLC (def=0x0) // Data length code
  • 0x40006988TXMDL0R// CAN mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data byte 3
    • [16:23]DATA2 (def=0x0) // Data byte 2
    • [8:15]DATA1 (def=0x0) // Data byte 1
    • [0:7]DATA0 (def=0x0) // Data byte 0
  • 0x4000698CTXMDH0R// CAN mailbox data high register

    • [24:31]DATA7 (def=0x0) // Data byte 7
    • [16:23]DATA6 (def=0x0) // Data byte 6
    • [8:15]DATA5 (def=0x0) // Data byte 5
    • [0:7]DATA4 (def=0x0) // Data byte 4
  • 0x40006990TXMI1R// CAN TX mailbox identifier register

    • [21:31]STID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
    • [0]TXRQ (def=0x0) // Transmit mailbox request
  • 0x40006994TXMDT1R// CAN mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8]TGT (def=0x0) // Transmit global time
    • [0:3]DLC (def=0x0) // Data length code
  • 0x40006998TXMDL1R// CAN mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data byte 3
    • [16:23]DATA2 (def=0x0) // Data byte 2
    • [8:15]DATA1 (def=0x0) // Data byte 1
    • [0:7]DATA0 (def=0x0) // Data byte 0
  • 0x4000699CTXMDH1R// CAN mailbox data high register

    • [24:31]DATA7 (def=0x0) // Data byte 7
    • [16:23]DATA6 (def=0x0) // Data byte 6
    • [8:15]DATA5 (def=0x0) // Data byte 5
    • [0:7]DATA4 (def=0x0) // Data byte 4
  • 0x400069A0TXMI2R// CAN TX mailbox identifier register

    • [21:31]STID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
    • [0]TXRQ (def=0x0) // Transmit mailbox request
  • 0x400069A4TXMDT2R// CAN mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8]TGT (def=0x0) // Transmit global time
    • [0:3]DLC (def=0x0) // Data length code
  • 0x400069A8TXMDL2R// CAN mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data byte 3
    • [16:23]DATA2 (def=0x0) // Data byte 2
    • [8:15]DATA1 (def=0x0) // Data byte 1
    • [0:7]DATA0 (def=0x0) // Data byte 0
  • 0x400069ACTXMDH2R// CAN mailbox data high register

    • [24:31]DATA7 (def=0x0) // Data byte 7
    • [16:23]DATA6 (def=0x0) // Data byte 6
    • [8:15]DATA5 (def=0x0) // Data byte 5
    • [0:7]DATA4 (def=0x0) // Data byte 4
  • 0x400069B0RXMI0R// CAN receive FIFO mailbox identifier register

    • [21:31]STID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
  • 0x400069B4RXMDT0R// CAN receive FIFO mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8:15]FMI (def=0x0) // Filter match index
    • [6]RES (def=0x0) // RES bit of the received frame
    • [5]ESI (def=0x0) // ESI bit of the received frame
    • [4]BRS (def=0x0) // BRS bit of the received frame
    • [0:3]DLC (def=0x0) // Data length code
  • 0x400069B8RXMDL0R// CAN receive FIFO mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data Byte 3
    • [16:23]DATA2 (def=0x0) // Data Byte 2
    • [8:15]DATA1 (def=0x0) // Data Byte 1
    • [0:7]DATA0 (def=0x0) // Data Byte 0
  • 0x400069BCRXMDH0R// CAN receive FIFO mailbox data high register

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  interrupts:
  • [113] CAN2_TX // CAN TX interrupts
  • [114] CAN2_RX0 // CAN RX0 interrupts
  • [112] CAN2_SCE // CAN SCE interrupt
• 0x40007800CAN3//

  • 0x40007800CTLR// CAN Master control register

    • [17]CFGCANM (def=0x0) // Configure CAN offline recovery time
    • [16]DBF (def=0x1) // Debug freeze
    • [15]RST (def=0x0) // Software master reset
    • [7]TTCM (def=0x0) // Time triggered communication mode
    • [6]ABOM (def=0x0) // Automatic bus-off management
    • [5]AWUM (def=0x0) // Automatic wakeup mode
    • [4]NART (def=0x0) // No automatic retransmission
    • [3]RFLM (def=0x0) // Receive FIFO locked mode
    • [2]TXFP (def=0x0) // Transmit FIFO priority
    • [1]SLEEP (def=0x1) // Sleep mode request bit
    • [0]INRQ (def=0x0) // Initialization request
  • 0x40007804STATR// CAN master status register

    • [11]RX (def=0x0) // Rx signal
    • [10]SAMP (def=0x0) // Last sample point
    • [9]RXM (def=0x0) // Receive mode
    • [8]TXM (def=0x0) // Transmit mode
    • [4]SLAKI (def=0x0) // Sleep acknowledge interrupt
    • [3]WKUI (def=0x0) // Wakeup interrupt
    • [2]ERRI (def=0x0) // Error interrupt
    • [1]SLAK (def=0x1) // Sleep acknowledge
    • [0]INAK (def=0x0) // Initialization acknowledge
  • 0x40007808TSTATR// CAN transmit status register

    • [31]LOW2 (def=0x0) // Lowest priority flag for mailbox2
    • [30]LOW1 (def=0x0) // Lowest priority flag for mailbox1
    • [29]LOW0 (def=0x0) // Lowest priority flag for mailbox0
    • [28]TME2 (def=0x1) // Transmit mailbox 2 empty
    • [27]TME1 (def=0x1) // Transmit mailbox 1 empty
    • [26]TME0 (def=0x1) // Transmit mailbox 0 empty
    • [24:25]CODE (def=0x0) // Mailbox code
    • [23]ABRQ2 (def=0x0) // Abort request for mailbox 2
    • [19]TERR2 (def=0x0) // Transmission error of mailbox 2
    • [18]ALST2 (def=0x0) // Arbitration lost for mailbox 2
    • [17]TXOK2 (def=0x0) // Transmission OK of mailbox 2
    • [16]RQCP2 (def=0x0) // Request completed mailbox2
    • [15]ABRQ1 (def=0x0) // Abort request for mailbox 1
    • [11]TERR1 (def=0x0) // Transmission error of mailbox1
    • [10]ALST1 (def=0x0) // Arbitration lost for mailbox1
    • [9]TXOK1 (def=0x0) // Transmission OK of mailbox1
    • [8]RQCP1 (def=0x0) // Request completed mailbox1
    • [7]ABRQ0 (def=0x0) // Abort request for mailbox0
    • [3]TERR0 (def=0x0) // Transmission error of mailbox0
    • [2]ALST0 (def=0x0) // Arbitration lost for mailbox0
    • [1]TXOK0 (def=0x0) // Transmission OK of mailbox0
    • [0]RQCP0 (def=0x0) // Request completed mailbox0
  • 0x4000780CRFIFO0// CAN receive FIFO 0 register

    • [5]RFOM0 (def=0x0) // Release FIFO 0 output mailbox
    • [4]FOVR0 (def=0x0) // FIFO 0 overrun
    • [3]FULL0 (def=0x0) // FIFO 0 full
    • [0:1]FMP0 (def=0x0) // FIFO 0 message pending
  • 0x40007814INTENR// CAN interrupt enable register

    • [17]SLKIE (def=0x0) // Sleep interrupt enable
    • [16]WKUIE (def=0x0) // Wakeup interrupt enable
    • [15]ERRIE (def=0x0) // Error interrupt enable
    • [11]LECIE (def=0x0) // Last error code interrupt enable
    • [10]BOFIE (def=0x0) // Bus-off interrupt enable
    • [9]EPVIE (def=0x0) // Error passive interrupt enable
    • [8]EWGIE (def=0x0) // Error warning interrupt enable
    • [6]FOVIE1 (def=0x0) // FIFO overrun interrupt enable
    • [5]FFIE1 (def=0x0) // FIFO full interrupt enable
    • [4]FMPIE1 (def=0x0) // FIFO message pending interrupt enable
    • [3]FOVIE0 (def=0x0) // FIFO overrun interrupt enable
    • [2]FFIE0 (def=0x0) // FIFO full interrupt enable
    • [1]FMPIE0 (def=0x0) // FIFO message pending interrupt enable
    • [0]TMEIE (def=0x0) // Transmit mailbox empty interrupt enable
  • 0x40007818ERRSR// CAN error status register

    • [24:31]REC (def=0x0) // Receive error counter
    • [16:23]TEC (def=0x0) // Least significant byte of the 9-bit transmit error counter
    • [4:6]LEC (def=0x0) // Last error code
    • [2]BOFF (def=0x0) // Bus-off flag
    • [1]EPVF (def=0x0) // Error passive flag
    • [0]EWGF (def=0x0) // Error warning flag
  • 0x4000781CBTIMR// CAN bit timing register

    • [31]SILM (def=0x0) // Silent mode (debug)
    • [30]LBKM (def=0x0) // Loop back mode (debug)
    • [24:27]SJW (def=0x1) // Resynchronization jump width
    • [20:23]TS2 (def=0x2) // Time segment 2
    • [16:19]TS1 (def=0x3) // Time segment 1
    • [12:15]BTR_TS1_T (def=0x0) // CLAS_LONG_TS1=0;TS1 is TS[3:0](4bit);CLAS_LONG_TS1=1,TS1 is TS[1:0]+BTR_TS1_T[15:12](6bit)
    • [0:9]BRP (def=0x0) // minimum time unit length setting value
  • 0x40007820TTCTLR// CAN time trigger control register

    • [17]MODE (def=0x0) // Time-triggered mode selection
    • [16]TIMRST (def=0x0) // Internal counter reset control
    • [0:15]TIMCMV (def=0xFFFF) // Internal counter count end value
  • 0x40007824TTCNT// CAN Time Trigger Count Value Register

    • [0:15]TIMCNT (def=0x0) // time-triggered count value
  • 0x40007828TERR_CNT// CAN offline recovery error counter

    • [0:8]TX_ERR_CNT (def=0x0) // Offline recovery error count values
  • 0x40007980TXMI0R// CAN TX mailbox identifier register

    • [21:31]STID_EXID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
    • [0]TXRQ (def=0x0) // Transmit mailbox request
  • 0x40007984TXMDT0R// CAN mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8]TGT (def=0x0) // Transmit global time
    • [0:3]DLC (def=0x0) // Data length code
  • 0x40007988TXMDL0R// CAN mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data byte 3
    • [16:23]DATA2 (def=0x0) // Data byte 2
    • [8:15]DATA1 (def=0x0) // Data byte 1
    • [0:7]DATA0 (def=0x0) // Data byte 0
  • 0x4000798CTXMDH0R// CAN mailbox data high register

    • [24:31]DATA7 (def=0x0) // Data byte 7
    • [16:23]DATA6 (def=0x0) // Data byte 6
    • [8:15]DATA5 (def=0x0) // Data byte 5
    • [0:7]DATA4 (def=0x0) // Data byte 4
  • 0x40007990TXMI1R// CAN TX mailbox identifier register

    • [21:31]STID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
    • [0]TXRQ (def=0x0) // Transmit mailbox request
  • 0x40007994TXMDT1R// CAN mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8]TGT (def=0x0) // Transmit global time
    • [0:3]DLC (def=0x0) // Data length code
  • 0x40007998TXMDL1R// CAN mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data byte 3
    • [16:23]DATA2 (def=0x0) // Data byte 2
    • [8:15]DATA1 (def=0x0) // Data byte 1
    • [0:7]DATA0 (def=0x0) // Data byte 0
  • 0x4000799CTXMDH1R// CAN mailbox data high register

    • [24:31]DATA7 (def=0x0) // Data byte 7
    • [16:23]DATA6 (def=0x0) // Data byte 6
    • [8:15]DATA5 (def=0x0) // Data byte 5
    • [0:7]DATA4 (def=0x0) // Data byte 4
  • 0x400079A0TXMI2R// CAN TX mailbox identifier register

    • [21:31]STID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
    • [0]TXRQ (def=0x0) // Transmit mailbox request
  • 0x400079A4TXMDT2R// CAN mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8]TGT (def=0x0) // Transmit global time
    • [0:3]DLC (def=0x0) // Data length code
  • 0x400079A8TXMDL2R// CAN mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data byte 3
    • [16:23]DATA2 (def=0x0) // Data byte 2
    • [8:15]DATA1 (def=0x0) // Data byte 1
    • [0:7]DATA0 (def=0x0) // Data byte 0
  • 0x400079ACTXMDH2R// CAN mailbox data high register

    • [24:31]DATA7 (def=0x0) // Data byte 7
    • [16:23]DATA6 (def=0x0) // Data byte 6
    • [8:15]DATA5 (def=0x0) // Data byte 5
    • [0:7]DATA4 (def=0x0) // Data byte 4
  • 0x400079B0RXMI0R// CAN receive FIFO mailbox identifier register

    • [21:31]STID (def=0x0) // Standard identifier
    • [3:20]EXID (def=0x0) // extended identifier
    • [2]IDE (def=0x0) // Identifier extension
    • [1]RTR (def=0x0) // Remote transmission request
  • 0x400079B4RXMDT0R// CAN receive FIFO mailbox data length control and time stamp register

    • [16:31]TIME (def=0x0) // Message time stamp
    • [8:15]FMI (def=0x0) // Filter match index
    • [6]RES (def=0x0) // RES bit of the received frame
    • [5]ESI (def=0x0) // ESI bit of the received frame
    • [4]BRS (def=0x0) // BRS bit of the received frame
    • [0:3]DLC (def=0x0) // Data length code
  • 0x400079B8RXMDL0R// CAN receive FIFO mailbox data low register

    • [24:31]DATA3 (def=0x0) // Data Byte 3
    • [16:23]DATA2 (def=0x0) // Data Byte 2
    • [8:15]DATA1 (def=0x0) // Data Byte 1
    • [0:7]DATA0 (def=0x0) // Data Byte 0
  • 0x400079BCRXMDH0R// CAN receive FIFO mailbox data high register

    • [24:31]DATA7 (def=0x0) // DATA7
    • [16:23]DATA6 (def=0x0) // DATA6
    • [8:15]DATA5 (def=0x0) // DATA5
    • [0:7]DATA4 (def=0x0) // DATA4
  interrupts:
  • [137] CAN3_TX // CAN TX interrupts
  • [138] CAN3_RX0 // CAN RX0 interrupts
  • [136] CAN3_SCE // CAN SCE interrupt
• 0x40025800DVP// Digital Video Port

  • 0x40025800CR0// Digital Video control register (DVP_CR0)

    • [0]RB_DVP_ENABLE (def=0x0) // DVP enable
    • [1]RB_DVP_V_POLAR (def=0x0) // DVP VSYNC polarity control
    • [2]RB_DVP_H_POLAR (def=0x0) // DVP HSYNC polarity control
    • [3]RB_DVP_P_POLAR (def=0x0) // DVP PCLK polarity control
    • [4:5]RB_DVP_MSK_DAT_MOD (def=0x0) // DVP data mode
    • [6]RB_DVP_JPEG (def=0x0) // DVP JPEG mode
  • 0x40025801CR1// Digital Video control register (DVP_CR1)

    • [0]RB_DVP_DMA_ENABLE (def=0x0) // DVP dma enable
    • [1]RB_DVP_ALL_CLR (def=0x1) // DVP all clear
    • [2]RB_DVP_RCV_CLR (def=0x1) // DVP receive logic clear
    • [3]RB_DVP_BUF_TOG (def=0x0) // DVP bug toggle by software
    • [4]RB_DVP_CM (def=0x0) // DVP capture mode
    • [5]RB_DVP_CROP (def=0x0) // DVP Crop feature enable
    • [6:7]RB_DVP_FCRC (def=0x0) // DVP frame capture rate control
  • 0x40025802IER// Digital Video Interrupt register (DVP_IER)

    • [0]RB_DVP_IE_STR_FRM (def=0x0) // DVP frame start interrupt enable
    • [1]RB_DVP_IE_ROW_DONE (def=0x0) // DVP row received done interrupt enable
    • [2]RB_DVP_IE_FRM_DONE (def=0x0) // DVP frame received done interrupt enable
    • [3]RB_DVP_IE_FIFO_OV (def=0x0) // DVP receive fifo overflow interrupt enable
    • [4]RB_DVP_IE_STP_FRM (def=0x0) // DVP frame stop interrupt enable
  • 0x40025804ROW_NUM// Image line count configuration register (DVP_ROW_NUM)

    • [0:15]RB_DVP_ROW_NUM (def=0x0) // The number of rows of frame image data
  • 0x40025806COL_NUM// Image column number configuration register (DVP_COL_NUM)

    • [0:15]RB_DVP_COL_NUM (def=0x0) // Number of PCLK cycles for row data
  • 0x40025808DMA_BUF0// Digital Video DMA address register (DVP_DMA_BUF0)

    • [0:31]RB_DVP_DMA_BUF0 (def=0x0) // DMA receive address 0
  • 0x4002580CDMA_BUF1// Digital Video DMA address register (DVP_DMA_BUF1)

    • [0:31]RB_DVP_DMA_BUF1 (def=0x0) // DMA receive address 1
  • 0x40025810IFR// Digital Video Flag register (DVP_IFR)

    • [0]RB_DVP_IF_STR_FRM (def=0x0) // DVP frame start interrupt enable
    • [1]RB_DVP_IF_ROW_DONE (def=0x0) // DVP row received done interrupt enable
    • [2]RB_DVP_IF_FRM_DONE (def=0x0) // DVP frame received done interrupt enable
    • [3]RB_DVP_IF_FIFO_OV (def=0x0) // DVP receive fifo overflow interrupt enable
    • [4]RB_DVP_IF_STP_FRM (def=0x0) // DVP frame stop interrupt enable
  • 0x40025811STATUS// Digital Video STATUS register (DVP_STATUS)

    • [0]RB_DVP_FIFO_RDY (def=0x0) // DVP frame start interrupt enable
    • [1]RB_DVP_FIFO_FULL (def=0x0) // DVP row received done interrupt enable
    • [2]RB_DVP_FIFO_OV (def=0x0) // DVP frame received done interrupt enable
    • [4:6]RB_DVP_MSK_FIFO_CNT (def=0x0) // DVP receive fifo overflow interrupt enable
  • 0x40025814ROW_CNT// Digital Video line counter register (DVP_ROW_CNT)

    • [0:15]RB_DVP_ROW_CNT (def=0x0) // The number of rows of frame image data
  • 0x40025818HOFFCNT// Digital Video horizontal displacement register (DVP_HOFFCNT)

    • [0:15]RB_DVP_HOFFCNT (def=0x0) // Number of PCLK cycles for row data
  • 0x4002581AVST// Digital Video line number register (DVP_VST)

    • [0:15]RB_DVP_VST (def=0x0) // The number of lines captured by the image
  • 0x4002581CCAPCNT// Digital Video Capture count register (DVP_CAPCNT)

    • [0:15]RB_DVP_CAPCNT (def=0x0) // Number of PCLK cycles captured by clipping window
  • 0x4002581EVLINE// Digital Video Vertical line count register (DVP_VLINE)

    • [0:15]RB_DVP_VLINE (def=0x0) // Crop the number of rows captured by window
  • 0x40025820DR// Digital Video Data register (DVP_DR)

    • [0:31]RB_DVP_DR (def=0x0) // Prevent DMA overflow
  interrupts:
  • [120] DVP // DVP global Interrupt interrupt
• 0x40023C00RNG// Random number generator

  • 0x40023C00CR// control register

    • [3]IE (def=0x0) // Interrupt enable
    • [2]RNGEN (def=0x0) // Random number generator enable
  • 0x40023C04SR// status register

    • [6]SEIS (def=0x0) // Seed error interrupt status
    • [5]CEIS (def=0x0) // Clock error interrupt status
    • [2]SECS (def=0x0) // Seed error current status
    • [1]CECS (def=0x0) // Clock error current status
    • [0]DRDY (def=0x0) // Data ready
  • 0x40023C08DR// data register

    • [0:31]RNDATA (def=0x0) // Random data
  interrupts:
  • [146] RNG // RNG interrupt
• 0x40027C00SERDES// Serial-parallel interconversion controller and transceiver

  • 0x40027C00SERDES1_CTRL// SERDESx Control Register

    • [18]ALIGN_EN (def=0x1) // A ALIGN signal is inserted at the time of transmission, and it is highly effective to solve t
    • [17]CONT_EN (def=0x0) // Replace the SYNC at idle with CONT and scrambling data to reduce EMI
    • [15]TX_PWR_UP (def=0x0) // Power-on enable bit of transmit module
    • [14]RX_PWR_UP (def=0x0) // Receiver module power-up enable bit
    • [7]DMA_EN (def=0x0) // DMA enables
    • [6]TX_EN (def=0x0) // Send Enable
    • [5]RX_EN (def=0x0) // Receiver Enable
    • [4]RX_POLARITY (def=0x0) // RXN/RXP signal exchange
    • [3]INT_BUSY_EN (def=0x0) // The SERDES transmission is complete, and the interruption flag is not cleared
    • [2]RESET_PHY (def=0x1) // SERDES Physical Layer Software Reset Control Bits
    • [1]RESET_LINK (def=0x1) // SERDES Link Layer Software Reset Control Bits
    • [0]CLR_ALL (def=0x1) // Clear the SERDES interrupt flag and FIFO
  • 0x40027C04SERDES1_INT_EN// SERDESx interrupt enable register

    • [5]COMINIT_IE (def=0x0) // COMIT RECEIVE INTERRUPT ENABLES
    • [3]FIFO_OV_IE (def=0x0) // FIFO overflow interrupt enabled
    • [2]RECV_DONE_IE (def=0x0) // Receive Completion Interrupt Enables
    • [1]TRAN_DONE_IE_RECV_ERR_IE (def=0x0) // Transmission Mode: Interrupt Enabled for Transmission Completion; Receive Mode: Receive CRC Err
    • [0]PHYRDY_IE (def=0x0) // PHYS-LAYER READY INTERRUPT ENABLES
  • 0x40027C08SERDES1_INT_FS// SERDESx Interrupt Flag/Status Register

    • [28:31]TX_SEQ_NUM (def=0x0) // LINK_INIT automatically clears when it is valid
    • [24:27]RX_SEQ_NUM (def=0x0) // In the receive mode, the received COMINT is automatically cleared
    • [21]R_FIFO_RDY (def=0x0) // SERDES receives FIFO data readiness status
    • [20]LINK_FREE (def=0x0) // The SERDES link layer sends the idle status bits
    • [19]PLL_LOCK (def=0x0) // The PLL locks the status bit
    • [18]RECV_CRC_OK (def=0x0) // The receive dataframe checks the status bit, detects it after RECV_DONE interrupt, and update
    • [17]RX_SEQ_MATCH (def=0x0) // Receive SEQ_NUM match status bits
    • [16]PHYRDY (def=0x0) // The physical layer READY status bit
    • [5]COMINIT_IF (def=0x0) // COMIT receives the interrupt flag
    • [3]FIFO_OV_IF (def=0x0) // FIFO overflows the interrupt flag
    • [2]RECV_DONE_IF (def=0x0) // Receive the Interrupt Completion flag
    • [1]TRAN_DONE_IF_RECV_ERR_IF (def=0x0) // Sending Mode: The signal of the interrupt is completed. Receive Mode: Receives the CRC error in
    • [0]PHYRDY_IF (def=0x0) // The physical layer READY interrupt flag
  • 0x40027C0CSERDES1_RTX_CTRL// SERDESx Transceiver Controller

    • [18]BUF_MODE (def=0x0) // Double-buffered control bit
    • [17]TX_VLD (def=0x0) // The sent packet is valid, zeroed by the software, and the bit is returned and synchronized with the
    • [16]LINK_INIT (def=0x0) // This bit is 1 and sends a LINK initialization packet
    • [0:15]SERDES_TX_LEN (def=0x0) // Number of data bytes sent, the lower 2 bits are fixed at 0 (4-byte aligned)
  • 0x40027C10SERDES1_RX_LEN0// SERDESx Receive Length 0 Register

    • [0:15]SERDES_RX_LEN0 (def=0x0) // The packet length of the last received data, with the lowest 2 digits fixed at 0
  • 0x40027C14SERDES1_DATA0// SERDESx Data 0 Buffer Register

    • [0:31]SERDES_DATA0 (def=0x0) // SERDES data buffer 0
  • 0x40027C18SERDES1_DMA0// Start address register

    • [0:31]SERDES_DMA0 (def=0x0) // Buffer 0 start address, in receive mode, the software needs to align the lower 4 fixed bits 0
  • 0x40027C1CSERDES1_RX_LEN1// SERDESx Receive Length 1 Register

    • [0:15]SERDES_RX_LEN1 (def=0x0) // The packet length of the last received data, with the lowest 2 digits fixed at 1
  • 0x40027C20SERDES1_DATA1// SERDESx Data 1 Buffer Register

    • [0:31]SERDES_DATA1 (def=0x0) // SERDES data buffer 1
  • 0x40027C24SERDES1_DMA1// Start address register

    • [0:31]SERDES_DMA1 (def=0x0) // Buffer 0 start address, in receive mode, the software needs to align the lower 4 fixed bits 0
  • 0x40027C40SERDES2_CTRL// SERDESx Control Register

    • [18]ALIGN_EN (def=0x1) // A ALIGN signal is inserted at the time of transmission, and it is highly effective to solve t
    • [17]CONT_EN (def=0x0) // Replace the SYNC at idle with CONT and scrambling data to reduce EMI
    • [16]PHY_PWR_UP (def=0x0) // Enable bits on the physical layer
    • [15]TX_PWR_UP (def=0x0) // Power-on enable bit of transmit module
    • [14]RX_PWR_UP (def=0x0) // Receiver module power-up enable bit
    • [8:12]PLL_FACTOR (def=0x12) // PLL Clock Control Coefficient
    • [7]DMA_EN (def=0x0) // DMA enables
    • [6]TX_EN (def=0x0) // Send Enable
    • [5]RX_EN (def=0x0) // Receiver Enable
    • [4]RX_POLARITY (def=0x0) // RXN/RXP signal exchange
    • [3]INT_BUSY_EN (def=0x0) // The SERDES transmission is complete, and the interruption flag is not cleared
    • [2]RESET_PHY (def=0x1) // SERDES Physical Layer Software Reset Control Bits
    • [1]RESET_LINK (def=0x1) // SERDES Link Layer Software Reset Control Bits
    • [0]CLR_ALL (def=0x1) // Clear the SERDES interrupt flag and FIFO
  • 0x40027C44SERDES2_INT_EN// SERDESx interrupt enable register

    • [5]COMINIT_IE (def=0x0) // COMIT RECEIVE INTERRUPT ENABLES
    • [3]FIFO_OV_IE (def=0x0) // FIFO overflow interrupt enabled
    • [2]RECV_DONE_IE (def=0x0) // Receive Completion Interrupt Enables
    • [1]TRAN_DONE_IE_RECV_ERR_IE (def=0x0) // Transmission Mode: Interrupt Enabled for Transmission Completion; Receive Mode: Receive CRC Err
    • [0]PHYRDY_IE (def=0x0) // PHYS-LAYER READY INTERRUPT ENABLES
  • 0x40027C48SERDES2_INT_FS// SERDESx Interrupt Flag/Status Register

    • [28:31]TX_SEQ_NUM (def=0x0) // LINK_INIT automatically clears when it is valid
    • [24:27]RX_SEQ_NUM (def=0x0) // In the receive mode, the received COMINT is automatically cleared
    • [21]R_FIFO_RDY (def=0x0) // SERDES receives FIFO data readiness status
    • [20]LINK_FREE (def=0x0) // The SERDES link layer sends the idle status bits
    • [19]PLL_LOCK (def=0x0) // The PLL locks the status bit
    • [18]RECV_CRC_OK (def=0x0) // The receive dataframe checks the status bit, detects it after RECV_DONE interrupt, and update
    • [17]RX_SEQ_MATCH (def=0x0) // Receive SEQ_NUM match status bits
    • [16]PHYRDY (def=0x0) // The physical layer READY status bit
    • [5]COMINIT_IF (def=0x0) // COMIT receives the interrupt flag
    • [3]FIFO_OV_IF (def=0x0) // FIFO overflows the interrupt flag
    • [2]RECV_DONE_IF (def=0x0) // Receive the Interrupt Completion flag
    • [1]TRAN_DONE_IF_RECV_ERR_IF (def=0x0) // Sending Mode: The signal of the interrupt is completed. Receive Mode: Receives the CRC error in
    • [0]PHYRDY_IF (def=0x0) // The physical layer READY interrupt flag
  • 0x40027C4CSERDES2_RTX_CTRL// SERDESx Transceiver Controller

    • [18]BUF_MODE (def=0x0) // Double-buffered control bit
    • [17]TX_VLD (def=0x0) // The sent packet is valid, zeroed by the software, and the bit is returned and synchronized with the
    • [16]LINK_INIT (def=0x0) // This bit is 1 and sends a LINK initialization packet
    • [0:15]SERDES_TX_LEN (def=0x0) // Number of data bytes sent, the lower 2 bits are fixed at 0 (4-byte aligned)
  • 0x40027C50SERDES2_RX_LEN0// SERDESx Receive Length 0 Register

    • [0:15]SERDES_RX_LEN0 (def=0x0) // The packet length of the last received data, with the lowest 2 digits fixed at 0
  • 0x40027C54SERDES2_DATA0// SERDESx Data 0 Buffer Register

    • [0:31]SERDES_DATA0 (def=0x0) // SERDES data buffer 0
  • 0x40027C58SERDES2_DMA0// Start address register

    • [0:31]SERDES_DMA0 (def=0x0) // Buffer 0 start address, in receive mode, the software needs to align the lower 4 fixed bits 0
  • 0x40027C5CSERDES2_RX_LEN1// SERDESx Receive Length 1 Register

    • [0:15]SERDES_RX_LEN1 (def=0x0) // The packet length of the last received data, with the lowest 2 digits fixed at 1
  • 0x40027C60SERDES2_DATA1// SERDESx Data 1 Buffer Register

    • [0:31]SERDES_DATA1 (def=0x0) // SERDES data buffer 1
  • 0x40027C64SERDES2_DMA1// Start address register

    • [0:31]SERDES_DMA1 (def=0x0) // Buffer 0 start address, in receive mode, the software needs to align the lower 4 fixed bits 0
  interrupts:
  • [83] SERDES // SERDES global interrupt
• 0x40034000USBSS// USB3.0 ultra-high speed host /device controller

  • 0x40034070R32_USBSS_CTRL// USBSS Control Register

    • [24:30]RB_DEV_ADDR (def=0x0) // Host Mode
    • [23]RB_UIE_FIFO_RXOV (def=0x0) // Receive FIFO overflow interrupt enabled
    • [22]RB_UIE_FIFO_TXOV (def=0x0) // Sending FIFO overflow interrupt enables
    • [20]RB_UIE_ITP (def=0x0) // Send ITP to complete interrupt enable
    • [19]RB_UIE_RX_PING (def=0x0) // Interrupt Enabled for Receiving PING-TP
    • [18]RB_UDIE_STATUS__RB_UHIE_NOTIF (def=0x0) // Device mode: Receiving STATUS transaction completion interrupt enabled; Host mode: Interrupt
    • [17]RB_UDIE_SETUP__RB_UHIE_ERDY (def=0x0) // Device Mode: Receive SETUP Transaction Completion Interrupt Enabled; Host mode:Receive SETUP
    • [16]RB_UIE_TRANSFER (def=0x0) // USB Transaction Completion Interrupt Enabled
    • [14]RB_TX_ERDY_MODE (def=0x0) // Use in device mode
    • [8:9]RB_REG_HP_PEND (def=0x0) // Packet Pending control bit for sending TP/DP packets
    • [7]RB_HOST_MODE (def=0x0) // USB Operating Mode Selection Bits
    • [6]RB_ITP_EN (def=0x0) // In host mode, send ITP enabled
    • [5]RB_SETUP_FLOW (def=0x0) // SETUP transaction throttling
    • [3]RB_DMA_MODE (def=0x0) // When DPH is transmitted in bursts, the next packet of data status
    • [2]RB_FORCE_RST (def=0x1) // The protocol layer and FIFO module are reset and need to be cleared by software.
    • [1]RB_USB_CLR_ALL (def=0x1) // Reset all software configuration registers, high validity, software clearance required
    • [0]RB_DMA_EN (def=0x0) // Enable DMA
  • 0x40034074STATUS// USBSS Status Register

    • [30:31]RB_HRX_RES (def=0x0) // A reply TP is received from the device back
    • [22:23]RB_HTX_RES (def=0x0) // Received a reply TP from the device returning
    • [16:20]RB_HOST_ACK_NUMP (def=0x0) // This bit is invalid for synchronous transmission, and is defined as follows in Control Transfer,
    • [12]RB_EP_DIR (def=0x0) // The direction of the endpoint that currently has an interrupt flag for transmission completion,
    • [8:10]RB_EP_ID (def=0x0) // If multiple endpoints have interrupt flags at the same time, the order of endpoint priority is as f
    • [7]RB_UIF_FIFO_RXOV (def=0x0) // Receive FIFO overflow interrupt flag
    • [6]RB_UIF_FIFO_TXOV (def=0x0) // Send FIFO overflow interrupt flag
    • [4]RB_UIF_ITP (def=0x0) // Send the ITP Complete Interrupt flag
    • [3]RB_UIF_RX_PING (def=0x0) // Receive PING-TP Complete Interrupt Flag
    • [2]RB_UHIF_NOTIF__RB_UDIF_STATUS (def=0x0) // Host Mode: Receive DEV_NOTIF-TP Complete Interrupt Flag; Device Mode: Receive STATUS Transac
    • [1]RB_UHIF_ERDY__RB_UDIF_SETUP (def=0x0) // Host Mode: Receive ERDY-TP Complete Interrupt Flag; Device Mode: Receive SETUP Transaction C
    • [0]RB_UIF_TRANSFER (def=0x0) // USB Transaction Completion Interrupt Flag
  • 0x4003408CUH_TX_DMA_U3EP0_TX_DMA// Send buffer address registers

    • [0:31]U3EP0_TX_DMA (def=0x0) // Host Mode:The start address of the host sending buffer. Device Mode:Endpoint 0 sends the
  • 0x40034090UH_RX_DMA_U3EP0_RX_DMA// Receive buffer address registers

    • [0:31]U3EP0_RX_DMA (def=0x0) // Host Mode:The start address of the host receiving buffer. Device Mode:Endpoint 0 receive
  • 0x40034078ITP// Interval Registers for ITP packets in USB

    • [0:13]REG_ITP_INTERVAL (def=0x0) // Bus interval Counter field in the received ITP.
  • 0x4003407CITP_ADJ// Interval Adaptive Registers for ITP packets in USB

    • [8:20]ITP_DELTA (def=0x0) // The higher 13-bit delta of the ITS in the ITP received in device mode indicates the time di
    • [7]ITP_DELAYED (def=0x0) // In device mode, the Delayed bit of Link Control Word in the received ITP is 1 when the ITP is delay
    • [0:6]ITP_ADJ_CR (def=0x0) // In device mode, the Bus Interval Adjustment Control field in the received ITP should be 0 after pow
  • 0x40034080UEP_TX_EN// Endpoint Sends Enable Register

    • [1:15]RB_EP_TX_EN (def=0x0) // Endpoints 1~15 upload enabled
  • 0x40034082UEP_RX_EN// Endpoint Receive Enable Register

    • [1:15]RB_EP_RX_EN (def=0x0) // Endpoints 1~15 downpass enabled
  • 0x40034084UEP0_TX_CTRL// Endpoint 0 sends control registers

    • [31]RB_UIF_EP0_TX_ACT (def=0x0) // The upload transaction is interrupted, the software writes 0 to zero, and the hardware sets 1.
    • [25]RB_EP0_TX_FLOW (def=0x0) // A sign that completes the NRDY-TP send (answer)
    • [24]RB_EP0_TX_PP (def=0x0) // The PP bit in the received ACK-TP
    • [21:22]RB_EP0_TX_RES (def=0x0) // Response to ACK-TP
    • [0:10]RB_EP0_TX_LEN (def=0x0) // Endpoint transmits length registers with a maximum value of 512B
  • 0x40034088UEP0_RX_CTRL// Endpoint 0 receives control registers

    • [31]RB_UIF_EP0_RX_ACT (def=0x0) // Upload the transaction completion interrupt flag, the software writes 0 to zero, and the hardware s
    • [24]RB_EP0_RX_PP (def=0x0) // PP bits in the received DPH
    • [21:22]RB_EP0_RX_RES (def=0x0) // Response to DPH
    • [0:10]RB_EP0_RX_LEN (def=0x0) // The endpoint receives the length register
  • 0x400340C0UEP1_TX_CFG// Endpoint 1 Configuration Register

    • [7]RB_EP_TX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_TX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of th
    • [5]RB_EP_TX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [3]RB_EP_TX_EOB_MODE (def=0x0) // If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP
    • [2]RB_EP_TX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_TX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_TX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x400340C1UEP1_TX_CR// Endpoint 1 control register

    • [7]RB_EP_TX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_TX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_TX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_TX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x400340C2UEP1_TX_SEQ// Endpoint 1 Serial Number Register

    • [0:4]RB_TX_EP_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x400340C3UEP1_TX_ST// Endpoint 1 status register

    • [7]RB_TX_EP_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_TX_EP_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_TX_EP_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_TX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_TX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x400340C4UEP1_TX_CHAIN_CR// Endpoint 1 CHAIN control register

    • [6:7]RB_TX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_TX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_TX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_TX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x400340C5UEP1_TX_CHAIN_ST// Endpoint 1 CHAIN state register

    • [7]RB_TX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_TX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_TX_EOB_LPF (def=0x0) // EOB/LPF bits in the last packet of DPH in the current CHAIN
    • [3]RB_TX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_TX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_TX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x400340C6UEP1_TX_CHAIN_LEN// Endpoint 1 CHAIN sends the last packet length

    • [0:10]CHAIN_TX_LEN (def=0x0) // The length of the last packet sent by the CHAIN
  • 0x400340C8UEP1_TX_CHAIN_EXP_NUMP// Number of NUMPs expected to be sent by endpoint 1

    • [0:7]TX_CHAIN_EXP_NUMP (def=0x0) // The number of DPP packets that can be sent by the currently completed CHAIN
  • 0x400340C9UEP1_TX_CHAIN_NUMP// Number of NUMPs has been sent by endpoint n

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that have been transmitted
  • 0x400340CAUEP1_TX_DMA_OFS// DMA offset length for endpoint 1

    • [0:15]CHAIN_TX_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x400340CCUEP1_TX_DMA// DMA start address for endpoint 1

    • [0:31]CHAIN_TX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to send data. FIFO mode:16~23 bits of the FIF
  • 0x400340E0UEP2_TX_CFG// Endpoint 2 Configuration Register

    • [7]RB_EP_TX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_TX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of th
    • [5]RB_EP_TX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [3]RB_EP_TX_EOB_MODE (def=0x0) // If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP
    • [2]RB_EP_TX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_TX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_TX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x400340E1UEP2_TX_CR// Endpoint 2 control register

    • [7]RB_EP_TX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_TX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_TX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_TX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x400340E2UEP2_TX_SEQ// Endpoint 2 Serial Number Register

    • [0:4]RB_TX_EP_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x400340E3UEP2_TX_ST// Endpoint 2 status register

    • [7]RB_TX_EP_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_TX_EP_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_TX_EP_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_TX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_TX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x400340E4UEP2_TX_CHAIN_CR// Endpoint 2 CHAIN control register

    • [6:7]RB_TX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_TX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_TX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_TX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x400340E5UEP2_TX_CHAIN_ST// Endpoint 2 CHAIN state register

    • [7]RB_TX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_TX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_TX_EOB_LPF (def=0x0) // EOB/LPF bits in the last packet of DPH in the current CHAIN
    • [3]RB_TX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_TX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_TX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x400340E6UEP2_TX_CHAIN_LEN// Endpoint 2 CHAIN sends the last packet length

    • [0:10]CHAIN_TX_LEN (def=0x0) // The length of the last packet sent by the CHAIN
  • 0x400340E8UEP2_TX_CHAIN_EXP_NUMP// Number of NUMPs expected to be sent by endpoint 2

    • [0:7]TX_CHAIN_EXP_NUMP (def=0x0) // The number of DPP packets that can be sent by the currently completed CHAIN
  • 0x400340E9UEP2_TX_CHAIN_NUMP// Number of NUMPs has been sent by endpoint 2

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that have been transmitted
  • 0x400340EAUEP2_TX_DMA_OFS// DMA offset length for endpoint 2

    • [0:15]CHAIN_TX_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x400340ECUEP2_TX_DMA// DMA start address for endpoint 2

    • [0:31]CHAIN_TX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to send data. FIFO mode:16~23 bits of the FIF
  • 0x40034100UEP3_TX_CFG// Endpoint 3 Configuration Register

    • [7]RB_EP_TX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_TX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of th
    • [5]RB_EP_TX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [3]RB_EP_TX_EOB_MODE (def=0x0) // If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP
    • [2]RB_EP_TX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_TX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_TX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034101UEP3_TX_CR// Endpoint 3 control register

    • [7]RB_EP_TX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_TX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_TX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_TX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034102UEP3_TX_SEQ// Endpoint 3 Serial Number Register

    • [0:4]RB_TX_EP_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034103UEP3_TX_ST// Endpoint 3 status register

    • [7]RB_TX_EP_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_TX_EP_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_TX_EP_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_TX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_TX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034104UEP3_TX_CHAIN_CR// Endpoint 3 CHAIN control register

    • [6:7]RB_TX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_TX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_TX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_TX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034105UEP3_TX_CHAIN_ST// Endpoint 3 CHAIN state register

    • [7]RB_TX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_TX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_TX_EOB_LPF (def=0x0) // EOB/LPF bits in the last packet of DPH in the current CHAIN
    • [3]RB_TX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_TX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_TX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034106UEP3_TX_CHAIN_LEN// Endpoint 3 CHAIN sends the last packet length

    • [0:10]CHAIN_TX_LEN (def=0x0) // The length of the last packet sent by the CHAIN
  • 0x40034108UEP3_TX_CHAIN_EXP_NUMP// Number of NUMPs expected to be sent by endpoint 3

    • [0:7]TX_CHAIN_EXP_NUMP (def=0x0) // The number of DPP packets that can be sent by the currently completed CHAIN
  • 0x40034109UEP3_TX_CHAIN_NUMP// Number of NUMPs has been sent by endpoint 3

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that have been transmitted
  • 0x4003410AUEP3_TX_DMA_OFS// DMA offset length for endpoint 3

    • [0:15]CHAIN_TX_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003410CUEP3_TX_DMA// DMA start address for endpoint 3

    • [0:31]CHAIN_TX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to send data. FIFO mode:16~23 bits of the FIF
  • 0x40034120UEP4_TX_CFG// Endpoint 4 Configuration Register

    • [7]RB_EP_TX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_TX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of th
    • [5]RB_EP_TX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [3]RB_EP_TX_EOB_MODE (def=0x0) // If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP
    • [2]RB_EP_TX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_TX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_TX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034121UEP4_TX_CR// Endpoint 4 control register

    • [7]RB_EP_TX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_TX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_TX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_TX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034122UEP4_TX_SEQ// Endpoint 4 Serial Number Register

    • [0:4]RB_TX_EP_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034123UEP4_TX_ST// Endpoint 4 status register

    • [7]RB_TX_EP_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_TX_EP_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_TX_EP_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_TX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_TX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034124UEP4_TX_CHAIN_CR// Endpoint 4 CHAIN control register

    • [6:7]RB_TX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_TX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_TX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_TX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034125UEP4_TX_CHAIN_ST// Endpoint 4 CHAIN state register

    • [7]RB_TX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_TX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_TX_EOB_LPF (def=0x0) // EOB/LPF bits in the last packet of DPH in the current CHAIN
    • [3]RB_TX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_TX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_TX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034126UEP4_TX_CHAIN_LEN// Endpoint 4 CHAIN sends the last packet length

    • [0:10]CHAIN_TX_LEN (def=0x0) // The length of the last packet sent by the CHAIN
  • 0x40034128UEP4_TX_CHAIN_EXP_NUMP// Number of NUMPs expected to be sent by Endpoint 4

    • [0:7]TX_CHAIN_EXP_NUMP (def=0x0) // The number of DPP packets that can be sent by the currently completed CHAIN
  • 0x40034129UEP4_TX_CHAIN_NUMP// Number of NUMPs has been sent by Endpoint 4

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that have been transmitted
  • 0x4003412AUEP4_TX_DMA_OFS// DMA offset length for Endpoint 4

    • [0:15]CHAIN_TX_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003412CUEP4_TX_DMA// DMA start address for Endpoint 4

    • [0:31]CHAIN_TX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to send data. FIFO mode:16~23 bits of the FIF
  • 0x40034140UEP5_TX_CFG// Endpoint 5 Configuration Register

    • [7]RB_EP_TX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_TX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of th
    • [5]RB_EP_TX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [3]RB_EP_TX_EOB_MODE (def=0x0) // If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP
    • [2]RB_EP_TX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_TX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_TX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034141UEP5_TX_CR// Endpoint 5 control register

    • [7]RB_EP_TX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_TX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_TX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_TX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034142UEP5_TX_SEQ// Endpoint 5 Serial Number Register

    • [0:4]RB_TX_EP_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034143UEP5_TX_ST// Endpoint 5 status register

    • [7]RB_TX_EP_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_TX_EP_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_TX_EP_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_TX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_TX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034144UEP5_TX_CHAIN_CR// Endpoint 5 CHAIN control register

    • [6:7]RB_TX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_TX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_TX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_TX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034145UEP5_TX_CHAIN_ST// Endpoint 5 CHAIN state register

    • [7]RB_TX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_TX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_TX_EOB_LPF (def=0x0) // EOB/LPF bits in the last packet of DPH in the current CHAIN
    • [3]RB_TX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_TX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_TX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034146UEP5_TX_CHAIN_LEN// Endpoint 5 CHAIN sends the last packet length

    • [0:10]CHAIN_TX_LEN (def=0x0) // The length of the last packet sent by the CHAIN
  • 0x40034148UEP5_TX_CHAIN_EXP_NUMP// Number of NUMPs expected to be sent by Endpoint 5

    • [0:7]TX_CHAIN_EXP_NUMP (def=0x0) // The number of DPP packets that can be sent by the currently completed CHAIN
  • 0x40034149UEP5_TX_CHAIN_NUMP// Number of NUMPs has been sent by Endpoint 5

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that have been transmitted
  • 0x4003414AUEP5_TX_DMA_OFS// DMA offset length for Endpoint 5

    • [0:15]CHAIN_TX_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003414CUEP5_TX_DMA// DMA start address for Endpoint 5

    • [0:31]CHAIN_TX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to send data. FIFO mode:16~23 bits of the FIF
  • 0x40034160UEP6_TX_CFG// Endpoint 6 Configuration Register

    • [7]RB_EP_TX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_TX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of th
    • [5]RB_EP_TX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [3]RB_EP_TX_EOB_MODE (def=0x0) // If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP
    • [2]RB_EP_TX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_TX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_TX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034161UEP6_TX_CR// Endpoint 6 control register

    • [7]RB_EP_TX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_TX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_TX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_TX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034162UEP6_TX_SEQ// Endpoint 6 Serial Number Register

    • [0:4]RB_TX_EP_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034163UEP6_TX_ST// Endpoint 6 status register

    • [7]RB_TX_EP_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_TX_EP_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_TX_EP_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_TX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_TX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034164UEP6_TX_CHAIN_CR// Endpoint 6 CHAIN control register

    • [6:7]RB_TX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_TX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_TX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_TX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034165UEP6_TX_CHAIN_ST// Endpoint 6 CHAIN state register

    • [7]RB_TX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_TX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_TX_EOB_LPF (def=0x0) // EOB/LPF bits in the last packet of DPH in the current CHAIN
    • [3]RB_TX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_TX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_TX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034166UEP6_TX_CHAIN_LEN// Endpoint 6 CHAIN sends the last packet length

    • [0:10]CHAIN_TX_LEN (def=0x0) // The length of the last packet sent by the CHAIN
  • 0x40034168UEP6_TX_CHAIN_EXP_NUMP// Number of NUMPs expected to be sent by Endpoint 6

    • [0:7]TX_CHAIN_EXP_NUMP (def=0x0) // The number of DPP packets that can be sent by the currently completed CHAIN
  • 0x40034169UEP6_TX_CHAIN_NUMP// Number of NUMPs has been sent by Endpoint 6

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that have been transmitted
  • 0x4003416AUEP6_TX_DMA_OFS// DMA offset length for Endpoint 6

    • [0:15]CHAIN_TX_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003416CUEP6_TX_DMA// DMA start address for Endpoint 6

    • [0:31]CHAIN_TX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to send data. FIFO mode:16~23 bits of the FIF
  • 0x40034180UEP7_TX_CFG// Endpoint 7 Configuration Register

    • [7]RB_EP_TX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_TX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of th
    • [5]RB_EP_TX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [3]RB_EP_TX_EOB_MODE (def=0x0) // If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP
    • [2]RB_EP_TX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_TX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_TX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034181UEP7_TX_CR// Endpoint 7 control register

    • [7]RB_EP_TX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_TX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_TX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_TX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034182UEP7_TX_SEQ// Endpoint 7 Serial Number Register

    • [0:4]RB_TX_EP_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034183UEP7_TX_ST// Endpoint 7 status register

    • [7]RB_TX_EP_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_TX_EP_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_TX_EP_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_TX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_TX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034184UEP7_TX_CHAIN_CR// Endpoint 7 CHAIN control register

    • [6:7]RB_TX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_TX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_TX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_TX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034185UEP7_TX_CHAIN_ST// Endpoint 7 CHAIN state register

    • [7]RB_TX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_TX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_TX_EOB_LPF (def=0x0) // EOB/LPF bits in the last packet of DPH in the current CHAIN
    • [3]RB_TX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_TX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_TX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034186UEP7_TX_CHAIN_LEN// Endpoint 7 CHAIN sends the last packet length

    • [0:10]CHAIN_TX_LEN (def=0x0) // The length of the last packet sent by the CHAIN
  • 0x40034188UEP7_TX_CHAIN_EXP_NUMP// Number of NUMPs expected to be sent by Endpoint 7

    • [0:7]TX_CHAIN_EXP_NUMP (def=0x0) // The number of DPP packets that can be sent by the currently completed CHAIN
  • 0x40034189UEP7_TX_CHAIN_NUMP// Number of NUMPs has been sent by Endpoint 7

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that have been transmitted
  • 0x4003418AUEP7_TX_DMA_OFS// DMA offset length for Endpoint 7

    • [0:15]CHAIN_TX_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003418CUEP7_TX_DMA// DMA start address for Endpoint 7

    • [0:31]CHAIN_TX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to send data. FIFO mode:16~23 bits of the FIF
  • 0x400340D0UEP1_RX_CFG// Endpoint 1 Configuration Register

    • [7]RB_EP_RX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_RX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of the
    • [5]RB_EP_RX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [4]RB_EP_RX_TOUT_MODE (def=0x0) // This bit is 1, and when a continuous burst packet is received, PP=1 and not a short packet
    • [3]RB_EP_RX_EOB_MODE (def=0x0) // This bit is 1, and when a short packet or DP(PP=0) is received, clearing all CHAIN_EN will
    • [2]RB_EP_RX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_RX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_RX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x400340D1UEP1_RX_CR// Endpoint 1 control register

    • [7]RB_EP_RX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_RX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_RX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_RX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x400340D2UEP1_RX_SEQ// Endpoint 1 Serial Number Register

    • [0:4]RB_EP_RX_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x400340D3UEP1_RX_ST// Endpoint 1 status register

    • [7]RB_EP_RX_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_EP_RX_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_EP_RX_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_EP_RX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_ER_RX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x400340D4UEP1_RX_CHAIN_CR// Endpoint 1 CHAIN control register

    • [6:7]RB_EP_RX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_EP_RX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_EP_RX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_EP_RX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x400340D5UEP1_RX_CHAIN_ST// Endpoint 1 CHAIN state register

    • [7]RB_EP_RX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_EP_RX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_EP_RX_LPF_FLAG (def=0x0) // Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH.
    • [3]RB_EP_RX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_EP_RX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_EP_RX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x400340D6UEP1_RX_CHAIN_LEN// Endpoint 1 CHAIN sends the last packet length

    • [0:10]RB_EP_RX_CHAIN_RX_LEN (def=0x0) // The length of the currently completed CHAIN to the last packet.
  • 0x400340D8UEP1_RX_CHAIN_MAX_NUMP// Number of NUMPs that Endpoint 1 can receive

    • [0:7]RX_CHAIN_MAX_NUMP (def=0x0) // The number of DPP packets that can be received by the CHAIN
  • 0x400340D9UEP1_RX_CHAIN_NUMP// Number of NUMPs has been received by endpoint 1

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that has received
  • 0x400340DAUEP1_RX_DMA_OFS// DMA offset length for endpoint 1

    • [0:15]CHAIN_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x400340DCUEP1_RX_DMA// DMA start address for endpoint 1

    • [0:31]CHAIN_RX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to receive data. FIFO mode:16~23 bits of the
  • 0x400340F0UEP2_RX_CFG// Endpoint 2 Configuration Register

    • [7]RB_EP_RX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_RX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of the
    • [5]RB_EP_RX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [4]RB_EP_RX_TOUT_MODE (def=0x0) // This bit is 1, and when a continuous burst packet is received, PP=1 and not a short packet
    • [3]RB_EP_RX_EOB_MODE (def=0x0) // This bit is 1, and when a short packet or DP(PP=0) is received, clearing all CHAIN_EN will
    • [2]RB_EP_RX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_RX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_RX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x400340F1UEP2_RX_CR// Endpoint 2 control register

    • [7]RB_EP_RX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_RX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_RX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_RX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x400340F2UEP2_RX_SEQ// Endpoint 2 Serial Number Register

    • [0:4]RB_EP_RX_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x400340F3UEP2_RX_ST// Endpoint 2 status register

    • [7]RB_EP_RX_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_EP_RX_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_EP_RX_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_EP_RX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_ER_RX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x400340F4UEP2_RX_CHAIN_CR// Endpoint 2 CHAIN control register

    • [6:7]RB_EP_RX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_EP_RX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_EP_RX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_EP_RX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x400340F5UEP2_RX_CHAIN_ST// Endpoint 2 CHAIN state register

    • [7]RB_EP_RX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_EP_RX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_EP_RX_LPF_FLAG (def=0x0) // Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH.
    • [3]RB_EP_RX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_EP_RX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_EP_RX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x400340F6UEP2_RX_CHAIN_LEN// Endpoint 2 CHAIN sends the last packet length

    • [0:10]RB_EP_RX_CHAIN_RX_LEN (def=0x0) // The length of the currently completed CHAIN to the last packet.
  • 0x400340F8UEP2_RX_CHAIN_MAX_NUMP// Number of NUMPs that Endpoint 2 can receive

    • [0:7]RX_CHAIN_MAX_NUMP (def=0x0) // The number of DPP packets that can be received by the CHAIN
  • 0x400340F9UEP2_RX_CHAIN_NUMP// Number of NUMPs has been received by endpoint 2

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that has received
  • 0x400340FAUEP2_RX_DMA_OFS// DMA offset length for Endpoint 2

    • [0:15]CHAIN_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x400340FCUEP2_RX_DMA// DMA start address for Endpoint 2

    • [0:31]CHAIN_RX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to receive data. FIFO mode:16~23 bits of the
  • 0x40034110UEP3_RX_CFG// Endpoint 3 Configuration Register

    • [7]RB_EP_RX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_RX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of the
    • [5]RB_EP_RX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [4]RB_EP_RX_TOUT_MODE (def=0x0) // This bit is 1, and when a continuous burst packet is received, PP=1 and not a short packet
    • [3]RB_EP_RX_EOB_MODE (def=0x0) // This bit is 1, and when a short packet or DP(PP=0) is received, clearing all CHAIN_EN will
    • [2]RB_EP_RX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_RX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_RX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034111UEP3_RX_CR// Endpoint 3 control register

    • [7]RB_EP_RX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_RX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_RX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_RX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034112UEP3_RX_SEQ// Endpoint 3 Serial Number Register

    • [0:4]RB_EP_RX_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034113UEP3_RX_ST// Endpoint 3 status register

    • [7]RB_EP_RX_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_EP_RX_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_EP_RX_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_EP_RX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_ER_RX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034114UEP3_RX_CHAIN_CR// Endpoint 3 CHAIN control register

    • [6:7]RB_EP_RX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_EP_RX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_EP_RX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_EP_RX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034115UEP3_RX_CHAIN_ST// Endpoint 3 CHAIN state register

    • [7]RB_EP_RX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_EP_RX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_EP_RX_LPF_FLAG (def=0x0) // Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH.
    • [3]RB_EP_RX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_EP_RX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_EP_RX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034116UEP3_RX_CHAIN_LEN// Endpoint 3 CHAIN sends the last packet length

    • [0:10]RB_EP_RX_CHAIN_RX_LEN (def=0x0) // The length of the currently completed CHAIN to the last packet.
  • 0x40034118UEP3_RX_CHAIN_MAX_NUMP// Number of NUMPs that Endpoint 3 can receive

    • [0:7]RX_CHAIN_MAX_NUMP (def=0x0) // The number of DPP packets that can be received by the CHAIN
  • 0x40034119UEP3_RX_CHAIN_NUMP// Number of NUMPs has been received by Endpoint 3

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that has received
  • 0x4003411AUEP3_RX_DMA_OFS// DMA offset length for Endpoint 3

    • [0:15]CHAIN_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003411CUEP3_RX_DMA// DMA start address for Endpoint 3

    • [0:31]CHAIN_RX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to receive data. FIFO mode:16~23 bits of the
  • 0x40034130UEP4_RX_CFG// Endpoint 4 Configuration Register

    • [7]RB_EP_RX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_RX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of the
    • [5]RB_EP_RX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [4]RB_EP_RX_TOUT_MODE (def=0x0) // This bit is 1, and when a continuous burst packet is received, PP=1 and not a short packet
    • [3]RB_EP_RX_EOB_MODE (def=0x0) // This bit is 1, and when a short packet or DP(PP=0) is received, clearing all CHAIN_EN will
    • [2]RB_EP_RX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_RX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_RX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034131UEP4_RX_CR// Endpoint 4 control register

    • [7]RB_EP_RX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_RX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_RX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_RX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034132UEP4_RX_SEQ// Endpoint 4 Serial Number Register

    • [0:4]RB_EP_RX_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034133UEP4_RX_ST// Endpoint 4 status register

    • [7]RB_EP_RX_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_EP_RX_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_EP_RX_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_EP_RX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_ER_RX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034134UEP4_RX_CHAIN_CR// Endpoint 4 CHAIN control register

    • [6:7]RB_EP_RX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_EP_RX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_EP_RX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_EP_RX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034135UEP4_RX_CHAIN_ST// Endpoint 4 CHAIN state register

    • [7]RB_EP_RX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_EP_RX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_EP_RX_LPF_FLAG (def=0x0) // Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH.
    • [3]RB_EP_RX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_EP_RX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_EP_RX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034136UEP4_RX_CHAIN_LEN// Endpoint 4 CHAIN sends the last packet length

    • [0:10]RB_EP_RX_CHAIN_RX_LEN (def=0x0) // The length of the currently completed CHAIN to the last packet.
  • 0x40034138UEP4_RX_CHAIN_MAX_NUMP// Number of NUMPs that Endpoint 4 can receive

    • [0:7]RX_CHAIN_MAX_NUMP (def=0x0) // The number of DPP packets that can be received by the CHAIN
  • 0x40034139UEP4_RX_CHAIN_NUMP// Number of NUMPs has been received by Endpoint 4

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that has received
  • 0x4003413AUEP4_RX_DMA_OFS// DMA offset length for Endpoint 4

    • [0:15]CHAIN_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003413CUEP4_RX_DMA// DMA start address for Endpoint 4

    • [0:31]CHAIN_RX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to receive data. FIFO mode:16~23 bits of the
  • 0x40034150UEP5_RX_CFG// Endpoint 5 Configuration Register

    • [7]RB_EP_RX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_RX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of the
    • [5]RB_EP_RX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [4]RB_EP_RX_TOUT_MODE (def=0x0) // This bit is 1, and when a continuous burst packet is received, PP=1 and not a short packet
    • [3]RB_EP_RX_EOB_MODE (def=0x0) // This bit is 1, and when a short packet or DP(PP=0) is received, clearing all CHAIN_EN will
    • [2]RB_EP_RX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_RX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_RX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034151UEP5_RX_CR// Endpoint 5 control register

    • [7]RB_EP_RX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_RX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_RX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_RX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034152UEP5_RX_SEQ// Endpoint 5 Serial Number Register

    • [0:4]RB_EP_RX_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034153UEP5_RX_ST// Endpoint 5 status register

    • [7]RB_EP_RX_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_EP_RX_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_EP_RX_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_EP_RX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_ER_RX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034154UEP5_RX_CHAIN_CR// Endpoint 5 CHAIN control register

    • [6:7]RB_EP_RX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_EP_RX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_EP_RX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_EP_RX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034155UEP5_RX_CHAIN_ST// Endpoint 5 CHAIN state register

    • [7]RB_EP_RX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_EP_RX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_EP_RX_LPF_FLAG (def=0x0) // Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH.
    • [3]RB_EP_RX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_EP_RX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_EP_RX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034156UEP5_RX_CHAIN_LEN// Endpoint 5 CHAIN sends the last packet length

    • [0:10]RB_EP_RX_CHAIN_RX_LEN (def=0x0) // The length of the currently completed CHAIN to the last packet.
  • 0x40034158UEP5_RX_CHAIN_MAX_NUMP// Number of NUMPs that Endpoint 5 can receive

    • [0:7]RX_CHAIN_MAX_NUMP (def=0x0) // The number of DPP packets that can be received by the CHAIN
  • 0x40034159UEP5_RX_CHAIN_NUMP// Number of NUMPs has been received by Endpoint 5

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that has received
  • 0x4003415AUEP5_RX_DMA_OFS// DMA offset length for Endpoint 5

    • [0:15]CHAIN_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003415CUEP5_RX_DMA// DMA start address for Endpoint 5

    • [0:31]CHAIN_RX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to receive data. FIFO mode:16~23 bits of the
  • 0x40034170UEP6_RX_CFG// Endpoint 6 Configuration Register

    • [7]RB_EP_RX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_RX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of the
    • [5]RB_EP_RX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [4]RB_EP_RX_TOUT_MODE (def=0x0) // This bit is 1, and when a continuous burst packet is received, PP=1 and not a short packet
    • [3]RB_EP_RX_EOB_MODE (def=0x0) // This bit is 1, and when a short packet or DP(PP=0) is received, clearing all CHAIN_EN will
    • [2]RB_EP_RX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_RX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_RX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034171UEP6_RX_CR// Endpoint 6 control register

    • [7]RB_EP_RX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_RX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_RX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_RX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034172UEP6_RX_SEQ// Endpoint 6 Serial Number Register

    • [0:4]RB_EP_RX_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034173UEP6_RX_ST// Endpoint 6 status register

    • [7]RB_EP_RX_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_EP_RX_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_EP_RX_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_EP_RX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_ER_RX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034174UEP6_RX_CHAIN_CR// Endpoint 6 CHAIN control register

    • [6:7]RB_EP_RX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_EP_RX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_EP_RX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_EP_RX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034175UEP6_RX_CHAIN_ST// Endpoint 6 CHAIN state register

    • [7]RB_EP_RX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_EP_RX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_EP_RX_LPF_FLAG (def=0x0) // Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH.
    • [3]RB_EP_RX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_EP_RX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_EP_RX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034176UEP6_RX_CHAIN_LEN// Endpoint 6 CHAIN sends the last packet length

    • [0:10]RB_EP_RX_CHAIN_RX_LEN (def=0x0) // The length of the currently completed CHAIN to the last packet.
  • 0x40034178UEP6_RX_CHAIN_MAX_NUMP// Number of NUMPs that Endpoint 6 can receive

    • [0:7]RX_CHAIN_MAX_NUMP (def=0x0) // The number of DPP packets that can be received by the CHAIN
  • 0x40034179UEP6_RX_CHAIN_NUMP// Number of NUMPs has been received by Endpoint 6

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that has received
  • 0x4003417AUEP6_RX_DMA_OFS// DMA offset length for Endpoint 6

    • [0:15]CHAIN_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003417CUEP6_RX_DMA// DMA start address for Endpoint 6

    • [0:31]CHAIN_RX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to receive data. FIFO mode:16~23 bits of the
  • 0x40034190UEP7_RX_CFG// Endpoint 7 Configuration Register

    • [7]RB_EP_RX_CHAIN_AUTO (def=0x1) // CHAIN automatically switches modes, and this mode is recommended
    • [6]RB_EP_RX_FIFO_MODE (def=0x0) // If the bit is 1, the current endpoint uses FIFO mode, and the start and end addresses of the
    • [5]RB_EP_RX_FIFO_CFG (def=0x0) // Access offset address 0xC~0xF, and the operation object
    • [4]RB_EP_RX_TOUT_MODE (def=0x0) // This bit is 1, and when a continuous burst packet is received, PP=1 and not a short packet
    • [3]RB_EP_RX_EOB_MODE (def=0x0) // This bit is 1, and when a short packet or DP(PP=0) is received, clearing all CHAIN_EN will
    • [2]RB_EP_RX_ERDY_AUTO (def=0x1) // ERDY automatic mode, the hardware will send ERDY, no software control required; It is recomm
    • [1]RB_EP_RX_SEQ_AUTO (def=0x1) // 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; 0: allows the software to wr
    • [0]RB_EP_RX_ISO_MODE (def=0x0) // A value of 1 indicates that the current endpoint is a synchronous endpoint
  • 0x40034191UEP7_RX_CR// Endpoint 7 control register

    • [7]RB_EP_RX_HALT (def=0x0) // Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH.
    • [6]RB_EP_RX_CLR (def=0x0) // Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG.
    • [5]RB_EP_RX_CHAIN_CLR (def=0x0) // Write 1 clears all CHAIN configuration values and statuses
    • [0:4]RB_EP_RX_ERDY_NUMP (def=0x10) // The nump field of ERDY-TP is sent by the hardware, and the value is generally set to the nu
  • 0x40034192UEP7_RX_SEQ// Endpoint 7 Serial Number Register

    • [0:4]RB_EP_RX_SEQ_NUM (def=0x0) // The current serial number of the endpoint, writable in non-SEQ_AUTO mode, read-only i
  • 0x40034193UEP7_RX_ST// Endpoint 7 status register

    • [7]RB_EP_RX_INT_FLAG (def=0x0) // The current break flag for the endpoint, the bit is read-only, and all CHAIN_IF are 0 if the
    • [6]RB_EP_RX_FC_ST (def=0x0) // The endpoint is in the current throttling state, and write 1 is cleared to zero.
    • [5]RB_EP_RX_ERDY_REQ (def=0x0) // Indicates that the ERDY is currently being sent; Writing 1 to that bit will send ERDY, which
    • [4]RB_EP_RX_CHAIN_RES (def=0x0) // CHAIN response state, corresponding to 4 separate CHAINS
    • [0:3]RB_ER_RX_CHAIN_EN (def=0x0) // The CHAIN enabled state, which corresponds to 4 independent CHAINS.
  • 0x40034194UEP7_RX_CHAIN_CR// Endpoint 7 CHAIN control register

    • [6:7]RB_EP_RX_CUR_USE (def=0x0) // The CHAIN serial number currently in use
    • [4:5]RB_EP_RX_CUR_CFG (def=0x0) // The chain serial number of the current configuration.
    • [2]RB_EP_RX_FORCE_RET (def=0x0) // This bit effectively forces the return of the selected CHAIN state machine configuration
    • [0:1]RB_EP_RX_RET_SEL (def=0x0) // When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration
  • 0x40034195UEP7_RX_CHAIN_ST// Endpoint 7 CHAIN state register

    • [7]RB_EP_RX_CHAIN_EN (def=0x0) // The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP regis
    • [6]RB_EP_RX_CHAIN_IF (def=0x0) // This bit is only written, and 1 is written to release the current CHAIN_IF
    • [5]RB_EP_RX_LPF_FLAG (def=0x0) // Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH.
    • [3]RB_EP_RX_NUMP_EMPTY (def=0x0) // IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1
    • [2]RB_EP_RX_DPH_PP (def=0x0) // The status of the PP bits in the currently received DPH
    • [0:1]RB_EP_RX_CHAIN_NO (def=0x0) // The serial number of the CHAIN that is currently interrupting
  • 0x40034196UEP7_RX_CHAIN_LEN// Endpoint 7 CHAIN sends the last packet length

    • [0:10]RB_EP_RX_CHAIN_RX_LEN (def=0x0) // The length of the currently completed CHAIN to the last packet.
  • 0x40034198UEP7_RX_CHAIN_MAX_NUMP// Number of NUMPs that Endpoint 7 can receive

    • [0:7]RX_CHAIN_MAX_NUMP (def=0x0) // The number of DPP packets that can be received by the CHAIN
  • 0x40034199UEP7_RX_CHAIN_NUMP// Number of NUMPs has been received by Endpoint 7

    • [0:7]TX_CHAIN_NUMP (def=0x0) // The number of DPP packets that has received
  • 0x4003419AUEP7_RX_DMA_OFS// DMA offset length for Endpoint 7

    • [0:15]CHAIN_DMA_OFS (def=0x0) // The offset address of the DPP in that CHAIN
  • 0x4003419CUEP7_RX_DMA// DMA start address for Endpoint 7

    • [0:31]CHAIN_RX_DMA (def=0x0) // Normal mode:The DMA start address of the CHAIN to receive data. FIFO mode:16~23 bits of the
  • 0x40034084UH_TX_CTRL// Host Transmit Control Registers

    • [31]RB_UH_TX_ACT (def=0x0) // The IN transaction completes the interrupt flag, the software writes 0 to zero, and the hardware se
    • [30]RB_UH_TX_ISO (def=0x0) // The host prepares to send ISO packets.
    • [29]RB_UH_TX_SETUP (def=0x0) // Indicates that the packet sent by the host is a Setup packet, and the setup flag is set.
    • [28]RB_UH_TX_STATUS (def=0x0) // Indicates that the packet sent by the host is STATUS TP.
    • [23]RB_UH_TX_LPF (def=0x0) // For burst transmissions, this bit simply represents the LPF/EOB of the last packet, and the
    • [21:22]RB_UH_TX_RES (def=0x0) // Response to DPH+DPP
    • [16:20]RB_UH_TX_SEQ (def=0x0) // The SEQ _NUM for which the endpoint receives the packet, the hardware automatically adds 1, except
    • [12:15]RB_UH_TX_EP (def=0x0) // Indicates the destination of the packet sent in host mode (the target endpoint number of the device
    • [0:10]RB_UH_TX_LEN (def=0x0) // The endpoint receives the length register, which for burst transmissions indicates the pack
  • 0x40034088UH_RX_CTRL// Host receives control registers

    • [31]RB_UH_RX_ACT (def=0x0) // The OUT transaction completes the interrupt flag, the software writes 0 to zero, and the hardware s
    • [30]RB_UH_RX_ISO (def=0x0) // Received Packets (DPP) are transmitted synchronously
    • [24:28]RB_UH_RX_NUMP (def=0x0) // The number of packets (DPP) that the endpoint is capable of receiving (burst transmission)
    • [21:22]RB_UH_RX_RES (def=0x0) // Response to DPH+DPP or STATUS-TP
    • [16:20]RB_UH_RX_SEQ (def=0x0) // The SEQ _NUM that the endpoint expects to receive, the hardware automatically adds 1, except for en
    • [12:15]RB_UH_RX_EP (def=0x0) // Indicates the source (device endpoint number) from which the packet was received in host mode
    • [0:10]RB_UH_RX_LEN (def=0x0) // The endpoint receives the length register, which for burst transmissions indicates the packe
  • 0x40034094UH_TX_DMA_OFS// Host Transmit Address Offset Register

    • [0:31]RB_UH_TX_DMA_OFS (def=0x400) // After the host sends the DMA, the size of the DMA address offset
  • 0x40034098UH_RX_DMA_OFS// Host Receive Address Offset Register

    • [0:31]RB_UH_RX_DMA_OFS (def=0x400) // After the host receives it, the DMA's address is offset by a large amount.
  • 0x4003409EHOST_RX_NUMP// The host receives the NUMP register

    • [8:15]RB_UH_RX_DPP_NUM (def=0x0) // The number of DPPs that have been accepted by the host.
    • [0:7]RB_UH_RX_NUMP (def=0x0) // The number of packets that the host expects to receive, if it is a synchronous transmission
  • 0x400340A0HOST_STATUS// Host Status Registers

    • [18:19]RB_UH_ITP_PRESAGE (def=0x0) // In host mode, this bit indicates the time when the ITP packet was sent
    • [17]RB_UH_RX_ISO_PKT_ERR (def=0x0) // A CRC error was received for the packet (DPP) during synchronous transmission
    • [16]RB_UH_RX_EOB_LPF (def=0x0) // This bit represents the EOB/LPF status in the received packet
    • [15]RB_UH_RX_ERDY_DIR (def=0x0) // ERDY is received from the device, and the segment represents the direction of the endpoint
    • [8:12]RB_UH_RX_ERDY_NUMP (def=0x1) // ERDY received from the device, which indicates the number of packets that can be sent/recei
    • [4:7]RB_UH_RX_ERDY_EP (def=0x0) // ERDY is received from the device, and the segment represents the endpoint number of the device ERDY
  • 0x400340A4HOST_TX_FC_STATUS// The host endpoint sends flow control register

    • [1:15]EPx_TX_FC (def=0x0) // The flow control status of the host to send endpoints 1-15.
  • 0x400340A6HOST_RX_FC_STATUS// The host endpoint receives the flow control register

    • [1:15]EPx_RX_FC (def=0x0) // The flow control status of the host to receiving endpoints 1-15
  • 0x400340A8TP_RX_DATA0// DEV_NOTIF-TP Data 0 Register

    • [0:31]USB3_NOTIF_DATA0 (def=0x0) // After the DEV_NOTIF-TP is received, the HP data is stored in this register
  • 0x400340ACTP_RX_DATA1// DEV_NOTIF-TP Data 1 Register

    • [0:31]USB3_NOTIF_DATA1 (def=0x0) // After the DEV_NOTIF-TP is received, the HP data is stored in this register
  • 0x400340B0TP_RX_DATA2// DEV_NOTIF-TP Data 2 Register

    • [0:31]USB3_NOTIF_DATA2 (def=0x0) // After the DEV_NOTIF-TP is received, the HP data is stored in this register
  • 0x40034000LINK_CFG// LINK Configuration Register

    • [31]RB_LINK_RESET (def=0x1) // LINK reset, including the reset state machine and all interrupt flags, is highly effective
    • [21]RB_LINK_TOUT_MODE (def=0x0) // SPEC configure
    • [20]RB_LINK_U1_PING_EN (def=0x0) // Send PING_FPFS under U1 to enable
    • [17]RB_LINK_U2_ALLOW (def=0x0) // High validity, after receiving the LGO_U2, the response LXU allows to enter the U2 state, ot
    • [16]RB_LINK_U1_ALLOW (def=0x0) // High validity, after receiving the LGO_U1, the response LAU allows to enter the U1 state, o
    • [15]RB_LINK_LTSSM_MODE (def=0x0) // The link state machine enters DISABLE mode
    • [14]RB_LINK_LOOKBACK_ACT (def=0x0) // It is used in LOOPBACK mode for the LOOPBACK master to control the pattern transmission (the LOOPBA
    • [13]RB_LINK_LOOPBACK_EN (def=0x0) // The LOOPBACK enable bit is allowed, which is highly active, and can be used with the LOOKBACK enabl
    • [12]RB_LINK_U2_DET_EN (def=0x0) // Detection mode of connected devices in U2 state
    • [10:11]RB_LINK_CP78_SEL (def=0x0) // In Compliance Pattern 7/8, send a length of consecutive 0 or consecutive 1
    • [8:9]RB_LINK_TX_DEEMPH (def=0x1) // Transmitter de-emphasis control
    • [7]RB_LINK_TX_SWING (def=0x0) // The transmitter signal swing control, low swing power consumption, but affect the transmission dist
    • [6]RB_LINK_RX_EQ_EN (def=0x0) // Receiver equalization enable control, optional protocol specifications
    • [5]RB_LINK_LFPS_RX_PD (def=0x1) // LFPS receive control, this bit is 1 to disable LFPS reception
    • [4]RB_LINK_COMPLIANCE_EN (def=0x0) // POLLING_LFPS timeout is in COMPLIANCE mode
    • [3]RB_LINK_PHY_RESET (def=0x1) // The PIPE interface is reset
    • [2]RB_LINK_SS_PLR_SWAP (def=0x0) // Exchange SSTX and SSRX polarities as follows
    • [1]RB_LINK_RX_TERM_EN (def=0x0) // Receiver Termination Resistance Control
    • [0]RB_LINK_DOWN_MODE (def=0x0) // Peripheral Type
  • 0x40034004LINK_CTRL// LINK control registers

    • [24:31]LINK_RX_TS_CFG (def=0x0) // Received Link Control
    • [16:23]LINK_TX_TS_CFG (def=0x0) // Send the link configuration of the TS1/TS2 training sequence
    • [15]LINK_TX_LGO_U3 (def=0x0) // After the bit is valid, the LGO_U3 is transmitted, and the hardware is automatically cleared
    • [14]LINK_TX_LGO_U2 (def=0x0) // After the bit is valid, the LGO_U2 is sent, the high is active, and the hardware is automatically c
    • [13]LINK_TX_LGO_U1 (def=0x0) // After the bit is valid, the LGO_U1 is sent, the high is active, and the hardware is automatically c
    • [12]LINK_POLLING_EN (def=0x0) // If the TERM is detected by the SS.RX_DETECT, a POLLING handshake will be performed after th
    • [11]LINK_REG_ROUT_EN (def=0x0) // Enable the routing function of the HUB, which is highly effective, with registers and no interfaces
    • [10]LINK_LUP_LDN_EN (def=0x0) // In the U0 state, if there is no data, whether to send LUP and LDN packets every 10us
    • [9]LINK_TX_UX_EXIT (def=0x0) // High validity, hardware automatic zeroing
    • [8]LINK_TX_WARM_RST (def=0x0) // High validity, cleared by software. A valid bit will send a warm-reset
    • [7]LINK_GO_RX_DET (def=0x0) // Before setting this bit, the PD_MODE should be set to P2 mode, and the LINK should be set t
    • [6]LINK_GO_RECOVERY (def=0x0) // SET THE LINK TO ENTER SS.RECOVERY, WHICH IS HIGHLY EFFECTIVE, AND THE HARDWARE IS AUTOMATIC
    • [5]LINK_GO_INACTIVE (def=0x0) // SET THE LINK TO ENTER SS.INACTIVE, WHICH IS HIGHLY VALID, AND THE HARDWARE IS AUTOMATICALLY
    • [4]LINK_GO_DISABLED (def=0x1) // SET LINK TO ENTER SS.DISABLED, WHICH IS HIGHLY VALID, AND REQUIRES SOFTWARE TO CLEAR
    • [0:1]LINK_PD_MODE (def=0x3) // Configure the current power mode of the PHY, corresponding to PO/P1/P2/P3 in the PIPE
  • 0x40034008LINK_INT_CTRL// LINK interrupt enable register

    • [31]LINK_IE_STATE_CHG (def=0x0) // Link State Machine Change Flag Interrupt Enabled
    • [30]LINK_IE_U1_TOUT (def=0x0) // U1 Timeout Interrupt Enabled
    • [29]LINK_IE_U2_TOUT (def=0x0) // U2 Timeout Interrupt Enabled
    • [28]LINK_IE_UX_FAIL (def=0x0) // UX Conversion Failure Interrupt Enabled
    • [27]LINK_IE_TX_WARMRST (def=0x0) // Send warm_reset end interrupt enabled
    • [26]LINK_IE_UX_EXIT_FAIL (def=0x0) // Exit UX failed to interrupt enabled
    • [23]LINK_IE_RX_LMP_TOUT (def=0x0) // Receive LMP Timeout Interrupt Enabled
    • [22]LINK_IE_TX_LMP (def=0x0) // If you successfully enter U0, you can send an HP packet to interrupt enable
    • [21]LINK_IE_RX_LMP (def=0x0) // Received Link Command Flag Interrupt Enabled
    • [20]LINK_IE_RX_DET (def=0x0) // The link enters the Rx.Detect state and is interrupted
    • [19]LINK_IE_LOOPBACK (def=0x0) // The link goes into loopback mode for testing and error isolation interrupt enablement
    • [18]LINK_IE_COMPLIANCE (def=0x0) // The link enters the compliance test, and the interrupt is enabled by the compatibility test
    • [17]LINK_IE_HPBUF_FULL (def=0x0) // BUF sends FIFO full interrupt enable
    • [16]LINK_IE_HPBUF_EMPTY (def=0x0) // BUF sends FIFO null interrupt enable
    • [15]LINK_IE_HOT_RST (def=0x0) // hot reset, which uses the reset interrupt enable of the TS1/TS2 ordered set
    • [14]LINK_IE_U3_WAKEUP (def=0x0) // In the U3 state, the Low Frequency Periodic Signal (LFPS) is received to wake up interrupt enabled
    • [13]LINK_IE_WARM_RST (def=0x0) // Warm reset (not connected) interrupt enabled with LPFS
    • [12]LINK_IE_UX_EXIT (def=0x0) // Request to exit UX is received Interrupt Enable
    • [11]LINK_IE_TXEQ (def=0x0) // LINK enters the POLLING_RXEQ for receiver equalization training interrupt enable
    • [10]LINK_IE_TERM_PRES (def=0x0) // LINK enters the RX_DETECT to detect the impedance of the remote receiver trace segment and detect t
    • [9]LINK_IE_UX_REJ (def=0x0) // Transmit LGO_ Ux, receive LXU interrupt enabled that refuses to enter the Ux
    • [8]LINK_IE_U3_WK_TOUT (def=0x0) // Interrupt the U3 command when requesting to exit U3 command timeout
    • [7]LINK_IE_GO_U0 (def=0x0) // LINK is interrupted at U0 to enable the following
    • [6]LINK_IE_GO_U1 (def=0x0) // LINK is interrupted at U1 to enable the following
    • [5]LINK_IE_GO_U2 (def=0x0) // LINK is interrupted at U2 and enabled
    • [4]LINK_IE_GO_U3 (def=0x0) // LINK is enabled when the U3 interrupt is enabled
    • [3]LINK_IE_DISABLE (def=0x0) // LINK is disabled, interrupt enabled
    • [2]LINK_IE_INACTIVE (def=0x0) // LINK is enabled on INACTIVE interrupt
    • [1]LINK_IE_RECOVERY (def=0x0) // DUE TO ERROR LINK IN RECOVERY INTERRUPTED ENABLED
    • [0]LINK_IE_READY (def=0x0) // LINK is initialized, including two ports before (Header Sequence Number Advertisement) and
  • 0x4003400CLINK_INT_FLAG// LINK Interrupt Flag Register

    • [31]LINK_IF_STATE_CHG (def=0x0) // link_reset reset to 0
    • [30]LINK_IF_U1_TOUT (def=0x0) // U1 timeout interrupted
    • [29]LINK_IF_U2_TOUT (def=0x0) // U2 timeout interrupted
    • [28]LINK_IF_UX_FAIL (def=0x0) // Enter the Ux failed to interrupt
    • [27]LINK_IF_TX_WARMRST (def=0x0) // send warm_reset to end interrupt
    • [26]LINK_IF_UX_EXIT_FAIL (def=0x0) // Exit UX fails to interrupt
    • [23]LINK_IF_RX_LMP_TOUT (def=0x0) // After the LINK initialization is complete, the Port Capabilities/Configuration LMPs timeout
    • [22]LINK_IF_TX_LMP (def=0x0) // After the LINK initialization is completed, the software is configured to send Port Capabil
    • [21]LINK_IF_RX_LMP (def=0x0) // Receive LMP Interrupt Flag
    • [20]LINK_IF_RX_DET (def=0x0) // After entering the RX_DETECT state interrupt flag, this position 1, the software sets the PW
    • [19]LINK_IF_LOOPBACK (def=0x0) // LINK enters the LOOPBACK state and the LINK is interrupted.
    • [18]LINK_IF_COMPLIANCE (def=0x0) // LINK enters the COMPLIANCE state with an outage flag.
    • [17]LINK_IF_HPBUF_FULL (def=0x0) // Header Packet buffer full interrupt flag.
    • [16]LINK_IF_HPBUF_EMPTY (def=0x0) // he device receives the HOT RESET interrupt flag
    • [15]LINK_IF_HOT_RST (def=0x0) // The device receives the HOT RESET interrupt flag
    • [14]LINK_IF_WAKEUP (def=0x0) // The power supply is in P3 mode and the LFPS signal interrupt flag is detected.
    • [13]LINK_IF_WARM_RST (def=0x0) // The WARM RESET status change (active-> inactive, or invalid->active) interrupt flag receive
    • [12]LINK_IF_UX_EXIT (def=0x0) // LINK receives the LFPS ready to exit U1/U2/U3 request interrupt flag
    • [11]LINK_IF_TXEQ (def=0x0) // LINK enters TXEQ state interrupt flag: INDICATE THAT THE POLLING HANDSHAKE IS COMPLETE,
    • [10]LINK_IF_TERM_PRES (def=0x0) // The TERM disconnected or disconnected flag was detected
    • [9]LINK_IF_UX_REJ (def=0x0) // LINK refuses to enter the low-power mode (U1/U2) interrupt flag.
    • [8]LINK_IF_U3_WK_TOUT (def=0x0) // Wake up from U3 to timeout interrupt flag (10ms).
    • [7]LINK_IF_GO_U0 (def=0x0) // LINK enters the U0 state interrupt flag.
    • [6]LINK_IF_GO_U1 (def=0x0) // LINK enters the U1 state interrupt flag.
    • [5]LINK_IF_GO_U2 (def=0x0) // LINK enters the U2 state interrupt flag.
    • [4]LINK_IF_GO_U3 (def=0x0) // LINK enters the U3 state interrupt flag.
    • [3]LINK_IF_DISABLE (def=0x0) // LINK INTO SS.DISABLE STATE INTERRUPT FLAG
    • [2]LINK_IF_INACTIVE (def=0x0) // LINK ENTERS THE SS.ACTIVE STATE INTERRUPT FLAG
    • [1]LINK_IF_RECOVERY (def=0x0) // LINK INTO THE SS.RECOVERY STATE INTERRUPT FLAG
    • [0]LINK_IF_READY (def=0x0) // LINK enters the U0 state and completes LINK initialization of the interrupt flag.
  • 0x40034010LINK_STATUS// LINK Status Register

    • [31]LINK_HPBUF_EMPTY (def=0x0) // The HP buffer is empty.
    • [30]LINK_HPBUF_FULL (def=0x0) // The HP buffer is full.
    • [29]LINK_HPBUF_IDLE (def=0x0) // BUF sends the status of the FIFO IDLE
    • [22]LINK_U3_SLEEP_ALLOW (def=0x0) // The link is in the U3 state and sleep is allowed
    • [21]LINK_U2_SLEEP_ALLOW (def=0x0) // The link is in the U2 state and sleep is allowed.
    • [20]LINK_RXDET_SLEEP_ALLOW (def=0x0) // The link is in the RXDET state, allowing sleep.
    • [19]LINK_WAKUP (def=0x0) // A link wake-up signal is received.
    • [18]LINK_RX_LFPS (def=0x0) // The link receives an LFPS signal.
    • [17]LINK_RX_DETECT (def=0x0) // The link is at P2 and is in rx_detect.
    • [16]LINK_RX_UX_EXIT_REQ (def=0x0) // Received a request to exit Ux
    • [8:11]LINK_STATE (def=0x0) // Link Status
    • [6]LINK_TXEQ (def=0x0) // The link is in POLLING_RXEQ.
    • [4:5]LINK_PD_MODE_MASK (def=0x0) // Link Power Status
    • [3]LINK_READY (def=0x0) // When the LINK enters the U0 state, the position 1 exits the U0 state after the initialization
    • [2]LINK_BUSY (def=0x0) // When the LINK is busy, the bit is 1 when the switchover is PD_MODE, and the hardware will au
    • [1]LINK_RX_WARM_RST (def=0x0) // A valid warm-reset signal is received from the host (the hardware automatically pulls up af
    • [0]LINK_RX_TERM_PRES (def=0x0) // After RX_DETECT, if a receive termination resistor is present, the bit is 1
  • 0x40034017LINK_ITP_PRE// LINK ITP Timeout Mode Register

    • [0:7]ITP_PRE (def=0x80) // ITP Timeout Mode
  • 0x4003401DLINK_U2_INACT_TIMER// LINK U2 Inactivity Timeout Counter Threshold Register

    • [0:7]U2_INACTIVE_TIMER (def=0x0) // The value of the inactivity timeout counter threshold for U2
  • 0x40034028LINK_U1_WKUP_FILTER// U1 wakes up the LFPS Duration Register

    • [0:7]U1_WKUP_FILTER (def=0x4A) // The duration of the LFPS received by U1 when exiting. When the receiving LFPS reaches this
  • 0x4003402CLINK_U2_WKUP_FILTER// U2 wakes up the LFPS Duration Register

    • [0:7]U2_WKUP_FILTER (def=0x2) // When the receiving LFPS reaches this time, the sending LFPS_last is pulled up and the handshake is
  • 0x40034030LINK_U3_WKUP_FILTER// U3 wakes up the LFPS validity duration register

    • [0:7]U3_WKUP_FILTER (def=0x64) // When the receiving LFPS reaches this time, the LFPS_last is raised, and the handshake is successful
  • 0x40034040LINK_ISO_DLY// LINK Synchronous Delay Register

    • [0:15]LINK_ISOCH_DLY (def=0x28) // The delay time for the serial bitstream to parse to the parallel data is 40ns by default, a
  • 0x40034050LINK_LPM_CR// Link Power Management Registers

    • [15]PHY_TX_CHSEL (def=0x0) // Select the PHY layer transmission channel type of the downstream port of the HUB
    • [14]PHY_RX_CHSEL (def=0x0) // Select the receiving channel type of the PHY layer of the downstream port of the HUB
    • [13]PHY_CHSEL_AUTO (def=0x0) // Automatic selection of the PHY layer transceiver channel type
    • [12]LPM_RXDET_EN (def=0x0) // When the lpm count reaches the expected value RXDET_EXP it is confirmed that a device is con
    • [11]LPM_TERM_PRESENT (def=0x0) // The PHY layer detects a device connection.
    • [10]LPM_TERM_CHG (def=0x0) // The connected device changes, plugs in the device or unplugs the device.
    • [9]LPM_EN (def=0x0) // LPM Enable
    • [8]LPM_RST (def=0x1) // Reset signal for LPM related register
    • [0:7]RXDET_EXP (def=0x80) // Detects external device counter registers.
  • 0x40034054LINK_LMP_PORT_CAP// PORT_CAP Registers

    • [31]LINK_LMP_RX_CAP_VLD (def=0x0) // A valid PORT_CAP-LMP is received, and the protocol stipulates that the two LINK parties exc
    • [30]LINK_LMP_TX_CAP_VLD (def=0x0) // PORT Capability configuration completion flag
    • [24:29]LINK_SPEED (def=0x0) // [24] Position 1, indicating that the supported device supports USB3.2 Gen1 (5Gbps).
    • [0:23]LINK_REG_PORT_CAP (def=0x0) // link port configure
  • 0x40034058LINK_LMP_RX_DATA0// LMP receives data 0 register

    • [0:31]LINK_LMP_RX_DATA0 (def=0x0) // Once the LMP is received, the HP data is stored in this register [31:0]
  • 0x4003405CLINK_LMP_RX_DATA1// LMP receives data 1 register

    • [0:31]LINK_LMP_RX_DATA1 (def=0x0) // Once the LMP is received, the HP data is stored in this register [63:32]
  • 0x40034060LINK_LMP_RX_DATA2// LMP receives data 2 register

    • [0:31]LINK_LMP_RX_DATA1 (def=0x0) // Once the LMP is received, the HP data is stored in this register [95:64]
  • 0x40034064LINK_LMP_TX_DATA0// USB Custom HP Data 0 Register

    • [0:31]LINK_LMP_TX_DATA0 (def=0x0) // The data of the user-defined HP is sent [31:0]
  • 0x40034068LINK_LMP_TX_DATA1// USB Custom HP Data 1 Register

    • [0:31]LINK_LMP_TX_DATA1 (def=0x0) // The data of the user-defined HP is sent [63:32]
  • 0x4003406CLINK_LMP_TX_DATA2// USB Custom HP Data 2 Register

    • [0:31]LINK_LMP_TX_DATA2 (def=0x0) // The data of the user-defined HP is sent [95:64]
  interrupts:
  • [62] USBSS // USBSS global interrupt
  • [63] USBSS_LINK // USBSS LINK interrupt
  • [65] USBSSWakeUP // USBSS wake-up interrupt
• 0x40025C00PIOC// Programmable protocol I/O microcontroller

  • 0x40025C00SFR_INDIR_PORT// Indirectly addressed data read/write ports
  • 0x40025C01RSFR_INDIR_PORT2// Indirectly addresses the data read/write port of 2
  • 0x40025C02SFR_PRG_COUNT// Program counters for the low bytes of the PC
  • 0x40025C03SFR_STATUS_REG// Status registers

    • [5]SB_STACK_USED (def=0x0) // Current stack usage flags
    • [4]SB_EN_TOUT_RST (def=0x0) // Timer Timeout Reset Enabled
    • [3]SB_GP_BIT_Y (def=0x0) // a generic bit variable Y, defined and used by the application
    • [2]SB_FLAG_Z (def=0x0) // ALU zero flag, whether the result is 00H
    • [1]SB_GP_BIT_X (def=0x0) // A generic bit variable X, defined and used by the application
    • [0]SB_FLAG_C (def=0x0) // ALU carry flag, whether the result is carried or produced by displacement
  • 0x40025C04SFR_INDIR_ADDR// Indirectly addressed address registers
  • 0x40025C05SFR_TMR0_COUNT// The counter register of timer 0
  • 0x40025C06SFR_TIMER_CTRL// The control register of the timer
  • 0x40025C07SFR_TMR0_INIT// The initial register of timer 0
  • 0x40025C08SFR_BIT_CYCLE// Periodic registers for coded bits

    • [7]SB_BIT_TX_O0 (def=0x0) // The raw bit data of the encoded bit to be sent, which is a double-buffered structure
    • [0:6]SB_BIT_CYCLE (def=0x0) // Sets the width of the encoded bits in clock cycles, which is the actual number of bits minus 1
  • 0x40025C09SFR_INDIR_ADDR2// Address registers for indirect address 2
  • 0x40025C0ASFR_PORT_DIR// The port direction sets the register

    • [7]SB_PORT_MOD3 (def=0x0) // Pin mode control, host side defines the purpose
    • [6]SB_PORT_MOD2 (def=0x0) // Pin mode control, host side defines the purpose
    • [5]SB_PORT_MOD1 (def=0x0) // Pin mode control, host side defines the purpose
    • [4]SB_PORT_MOD0 (def=0x0) // Pin mode control, host side defines the purpose
    • [3]SB_PORT_PU1 (def=0x0) // IO1 Pin Pull-Up Enables
    • [2]SB_PORT_PU0 (def=0x0) // IO0 Pin Pull-Up Enables
    • [1]SB_PORT_DIR1 (def=0x0) // IO1 Pin Direction Control
    • [0]SB_PORT_DIR0 (def=0x0) // IO0 Pin Direction Control
  • 0x40025C0BSFR_PORT_IO// Port input and output registers
  • 0x40025C0CSFR_BIT_CONFIG// Coded bit configuration registers

    • [7]SB_BIT_TX_EN (def=0x0) // The transmission of the coded bits is enabled
    • [6]SB_BIT_CODE_MOD (def=0x0) // How the coded bits are modulated
    • [5]SB_PORT_IN_EDGE (def=0x0) // Pin input level sampling point selection
    • [4]SB_BIT_CYC_TAIL (def=0x0) // Periodic state of the encoded bits
    • [3]SB_BIT_CYC_CNT6 (def=0x0) // The periodic timing state of the encoded bits
    • [2]SB_BIT_CYC_CNT5 (def=0x0) // The periodic timing state of the encoded bits
    • [1]SB_BIT_CYC_CNT4 (def=0x0) // The periodic timing state of the encoded bits
    • [0]SB_BIT_CYC_CNT3 (def=0x0) // The periodic timing state of the encoded bits
  • 0x40025C1CSFR_SYS_CFG// System configuration registers

    • [7]SB_INT_REQ (def=0x0) // Interrupt Request Activation Bits
    • [6]SB_DATA_SW_MR (def=0x0) // SFR_CTRL_RD wait to read the status bit
    • [5]SB_DATA_MW_SR (def=0x0) // SFR_CTRL_WR waiting to read the status bit
    • [4]SB_MST_CFG_B4 (def=0x0) // Configure information bits, software-defined uses
    • [3]SB_MST_IO_EN1 (def=0x0) // Mode and output control switches for IO1 pins
    • [2]SB_MST_IO_EN0 (def=0x0) // Mode and output control switches for IO0 pins
    • [1]SB_MST_RESET (def=0x0) // Force eMCU Reset
    • [0]SB_MST_CLK_GATE (def=0x0) // Global Clock Control for eMCUs
  • 0x40025C1DSFR_CTRL_RD// The eMCU reads and writes and the host reads only the registers
  • 0x40025C1ESFR_CTRL_WR// The host reads and writes and the eMCU reads only registers
  • 0x40025C1FSFR_DATA_EXCH// Data exchange registers
  • 0x40025C20SFR_DATA_REG0// Data register 0
  • 0x40025C21SFR_DATA_REG1// Data register 1
  • 0x40025C22SFR_DATA_REG2// Data register 2
  • 0x40025C23SFR_DATA_REG3// Data register 3
  • 0x40025C24SFR_DATA_REG4// Data register 4
  • 0x40025C25SFR_DATA_REG5// Data register 5
  • 0x40025C26SFR_DATA_REG6// Data register 6
  • 0x40025C27SFR_DATA_REG7// Data register 7
  • 0x40025C28SFR_DATA_REG8// Data register 8
  • 0x40025C29SFR_DATA_REG9// Data register 9
  • 0x40025C2ASFR_DATA_REG10// Data register 10
  • 0x40025C2BSFR_DATA_REG11// Data register 11
  • 0x40025C2CSFR_DATA_REG12// Data register 12
  • 0x40025C2DSFR_DATA_REG13// Data register 13
  • 0x40025C2ESFR_DATA_REG14// Data register 14
  • 0x40025C2FSFR_DATA_REG15// Data register 15
  • 0x40025C30SFR_DATA_REG16// Data register 16
  • 0x40025C31SFR_DATA_REG17// Data register 17
  • 0x40025C32SFR_DATA_REG18// Data register 18
  • 0x40025C33SFR_DATA_REG19// Data register 19
  • 0x40025C34SFR_DATA_REG20// Data register 20
  • 0x40025C35SFR_DATA_REG21// Data register 21
  • 0x40025C36SFR_DATA_REG22// Data register 22
  • 0x40025C37SFR_DATA_REG23// Data register 23
  • 0x40025C38SFR_DATA_REG24// Data register 24
  • 0x40025C39SFR_DATA_REG25// Data register 25
  • 0x40025C3ASFR_DATA_REG26// Data register 26
  • 0x40025C3BSFR_DATA_REG27// Data register 27
  • 0x40025C3CSFR_DATA_REG28// Data register 28
  • 0x40025C3DSFR_DATA_REG29// Data register 29
  • 0x40025C3ESFR_DATA_REG30// Data register 30
  • 0x40025C3FSFR_DATA_REG31// Data register 31
  interrupts:
  • [122] PIOC // PIOC global interrupt
• 0x40038000UHSIF// Universal high speed interface

  interrupts:
  • [145] UHSIF // UHSIF global interrupt
• 0x40018000SDIO// Secure digital input/output interface

  • 0x40018000POWER// Bits 1:0 = PWRCTRL: Power supply control bits

    • [0:1]PWRCTRL (def=0x0) // Power supply control bits
  • 0x40018004CLKCR// SDI clock control register (SDIO_CLKCR)

    • [0:7]CLKDIV (def=0x0) // Clock divide factor
    • [8]CLKEN (def=0x0) // Clock enable bit
    • [9]PWRSAV (def=0x0) // Power saving configuration bit
    • [10]BYPASS (def=0x0) // Clock divider bypass enable bit
    • [11:12]WIDBUS (def=0x0) // Wide bus mode enable bit
    • [13]NEGEDGE (def=0x0) // SDIO_CK dephasing selection bit
    • [14]HWFC_EN (def=0x0) // HW Flow Control enable
  • 0x40018008ARG// Bits 31:0 = : Command argument

    • [0:31]CMDARG (def=0x0) // Command argument
  • 0x4001800CCMD// SDIO command register (SDIO_CMD)

    • [0:5]CMDINDEX (def=0x0) // Command index
    • [6:7]WAITRESP (def=0x0) // Wait for response bits
    • [8]WAITINT (def=0x0) // CPSM waits for interrupt request
    • [9]WAITPEND (def=0x0) // CPSM Waits for ends of data transfer (CmdPend internal signal)
    • [10]CPSMEN (def=0x0) // Command path state machine (CPSM) Enable bit
    • [11]SDIOSuspend (def=0x0) // SD I/O suspend command
    • [12]ENCMDcompl (def=0x0) // Enable CMD completion
    • [13]NIEN (def=0x0) // not Interrupt Enable
    • [14]ATACMD (def=0x0) // CE-ATA command
  • 0x40018010RESPCMD// SDIO command register

    • [0:5]RESPCMD (def=0x0) // Response command index
  • 0x40018014RESP1// Bits 127:96 = CARDSTATUS1

    • [0:31]CARDSTATUS1 (def=0x0) // Card status 1
  • 0x40018018RESP2// Bits 95:64 = CARDSTATUS2

    • [0:31]CARDSTATUS2 (def=0x0) // Card status 2
  • 0x4001801CRESP3// Bits 63:32 = CARDSTATUS3

    • [0:31]CARDSTATUS3 (def=0x0) // Card status 3
  • 0x40018020RESP4// Bits 31:0 = CARDSTATUS4

    • [0:31]CARDSTATUS4 (def=0x0) // Card status 4
  • 0x40018024DTIMER// Bits 31:0 = DATATIME: Data timeout period

    • [0:31]DATATIME (def=0x0) // Data timeout period
  • 0x40018028DLEN// Bits 24:0 = DATALENGTH: Data length value

    • [0:24]DATALENGTH (def=0x0) // Data length value
  • 0x4001802CDCTRL// SDIO data control register (SDIO_DCTRL)

    • [0]DTEN (def=0x0) // Data transfer enabled bit
    • [1]DTDIR (def=0x0) // Data transfer direction selection
    • [2]DTMODE (def=0x0) // Data transfer mode selection 1: Stream or SDIO multibyte data transfer
    • [3]DMAEN (def=0x0) // DMA enable bit
    • [4:7]DBLOCKSIZE (def=0x0) // Data block size
    • [8]PWSTART (def=0x0) // Read wait start
    • [9]PWSTOP (def=0x0) // Read wait stop
    • [10]RWMOD (def=0x0) // Read wait mode
    • [11]SDIOEN (def=0x0) // SD I/O enable functions
  • 0x40018030DCOUNT// Bits 24:0 = DATACOUNT: Data count value

    • [0:24]DATACOUNT (def=0x0) // Data count value
  • 0x40018034STA// SDIO status register (SDIO_STA)

    • [0]CCRCFAIL (def=0x0) // Command response received (CRC check failed)
    • [1]DCRCFAIL (def=0x0) // Data block sent/received (CRC check failed)
    • [2]CTIMEOUT (def=0x0) // Command response timeout
    • [3]DTIMEOUT (def=0x0) // Data timeout
    • [4]TXUNDERR (def=0x0) // Transmit FIFO underrun error
    • [5]RXOVERR (def=0x0) // Received FIFO overrun error
    • [6]CMDREND (def=0x0) // Command response received (CRC check passed)
    • [7]CMDSENT (def=0x0) // Command sent (no response required)
    • [8]DATAEND (def=0x0) // Data end (data counter, SDIDCOUNT, is zero)
    • [9]STBITERR (def=0x0) // Start bit not detected on all data signals in wide bus mode
    • [10]DBCKEND (def=0x0) // Data block sent/received (CRC check passed)
    • [11]CMDACT (def=0x0) // Command transfer in progress
    • [12]TXACT (def=0x0) // Data transmit in progress
    • [13]RXACT (def=0x0) // Data receive in progress
    • [14]TXFIFOHE (def=0x0) // Transmit FIFO half empty: at least 8 words can be written into the FIFO
    • [15]RXFIFOHF (def=0x0) // Receive FIFO half full: there are at least 8 words in the FIFO
    • [16]TXFIFOF (def=0x0) // Transmit FIFO full
    • [17]RXFIFOF (def=0x0) // Receive FIFO full
    • [18]TXFIFOE (def=0x0) // Transmit FIFO empty
    • [19]RXFIFOE (def=0x0) // Receive FIFO empty
    • [20]TXDAVL (def=0x0) // Data available in transmit FIFO
    • [21]RXDAVL (def=0x0) // Data available in receive FIFO
    • [22]SDIOIT (def=0x0) // SDIO interrupt received
    • [23]CEATAEND (def=0x0) // CE-ATA command completion signal received for CMD61
  • 0x40018038ICR// SDIO interrupt clear register (SDIO_ICR)

    • [0]CCRCFAILC (def=0x0) // CCRCFAIL flag clear bit
    • [1]DCRCFAILC (def=0x0) // DCRCFAIL flag clear bit
    • [2]CTIMEOUTC (def=0x0) // CTIMEOUT flag clear bit
    • [3]DTIMEOUTC (def=0x0) // DTIMEOUT flag clear bit
    • [4]TXUNDERRC (def=0x0) // TXUNDERR flag clear bit
    • [5]RXOVERRC (def=0x0) // RXOVERR flag clear bit
    • [6]CMDRENDC (def=0x0) // CMDREND flag clear bit
    • [7]CMDSENTC (def=0x0) // CMDSENT flag clear bit
    • [8]DATAENDC (def=0x0) // DATAEND flag clear bit
    • [9]STBITERRC (def=0x0) // STBITERR flag clear bit
    • [10]DBCKENDC (def=0x0) // DBCKEND flag clear bit
    • [22]SDIOITC (def=0x0) // SDIOIT flag clear bit
    • [23]CEATAENDC (def=0x0) // CEATAEND flag clear bit
  • 0x4001803CMASK// SDIO mask register (SDIO_MASK)

    • [0]CCRCFAILIE (def=0x0) // Command CRC fail interrupt enable
    • [1]DCRCFAILIE (def=0x0) // Data CRC fail interrupt enable
    • [2]CTIMEOUTIE (def=0x0) // Command timeout interrupt enable
    • [3]DTIMEOUTIE (def=0x0) // Data timeout interrupt enable
    • [4]TXUNDERRIE (def=0x0) // Tx FIFO underrun error interrupt enable
    • [5]RXOVERRIE (def=0x0) // Rx FIFO overrun error interrupt enable
    • [6]CMDRENDIE (def=0x0) // Command response received interrupt enable
    • [7]CMDSENTIE (def=0x0) // Command sent interrupt enable
    • [8]DATAENDIE (def=0x0) // Data end interrupt enable
    • [9]STBITERRIE (def=0x0) // Start bit error interrupt enable
    • [10]DBACKENDIE (def=0x0) // Data block end interrupt enable
    • [11]CMDACTIE (def=0x0) // Command acting interrupt enable
    • [12]TXACTIE (def=0x0) // Data transmit acting interrupt enable
    • [13]RXACTIE (def=0x0) // Data receive acting interrupt enable
    • [14]TXFIFOHEIE (def=0x0) // Tx FIFO half empty interrupt enable
    • [15]RXFIFOHFIE (def=0x0) // Rx FIFO half full interrupt enable
    • [16]TXFIFOFIE (def=0x0) // Tx FIFO full interrupt enable
    • [17]RXFIFOFIE (def=0x0) // Rx FIFO full interrupt enable
    • [18]TXFIFOEIE (def=0x0) // Tx FIFO empty interrupt enable
    • [19]RXFIFOEIE (def=0x0) // Rx FIFO empty interrupt enable
    • [20]TXDAVLIE (def=0x0) // Data available in Tx FIFO interrupt enable
    • [21]RXDAVLIE (def=0x0) // Data available in Rx FIFO interrupt enable
    • [22]SDIOITIE (def=0x0) // SDIO mode interrupt received interrupt enable
    • [23]CEATENDIE (def=0x0) // CE-ATA command completion signal received interrupt enable
  • 0x40018048FIFOCNT// Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the

    • [0:31]FIF0COUNT (def=0x0) // Remaining number of words to be written to or read from the FIFO
  • 0x40018060DCTRL2// Data control register 2

    • [26]SLV_CK_PHASE (def=0x0) // phase selection bit when DATA is output from the mode
    • [25]SLV_FORCE_ERR (def=0x0) // in slave mode software forces data block CRC errors
    • [24]SLV_MODE (def=0x0) // slave mode enable bit
    • [16]RANDOM_LEN_EN (def=0x0) // data block arbirary byte length enable bit
    • [0:11]DBLOCKSIZE2 (def=0x0) // data block length field of arbirary byte length pattern
  • 0x40018080FIFO// bits 31:0 = FIFOData: Receive and transmit FIFO data

    • [0:31]FIFODATA (def=0x0) // Receive and transmit FIFO data
  interrupts:
  • [147] SDIO // SDIO global interrupt
• 0x40024000EMMC// EMMC register

  • 0x40024000R32_EMMC_ARGUMENT// SD 32bits command argument register

    • [0:31]EMMC_ARGUMENT (def=0x0) // 32 bit command parameter register
  • 0x40024004R16_EMMC_CMD_SET// SD 16bits cmd setting register

    • [0:5]RB_EMMC_CMDIDX_MASK (def=0x0) // the index number of the currently sent command
    • [8:9]RB_EMMC_RPTY_MASK (def=0x0) // current respone type
    • [10]RB_EMMC_CKCRC (def=0x0) // check the response CRC
    • [11]RB_EMMC_CKIDX (def=0x0) // check the response command index
  • 0x40024008R32_EMMC_RESPONSE0// SD 128bits response register, [31:0] 32bits

    • [0:31]R32_EMMC_RESPONSE0 (def=0x0) // response parameter register
  • 0x4002400CR32_EMMC_RESPONSE1// SD 128bits response register, [63:32] 32bits

    • [0:31]R32_EMMC_RESPONSE1 (def=0x0) // response parameter register
  • 0x40024010R32_EMMC_RESPONSE2// SD 128bits response register, [95:64] 32bits

    • [0:31]R32_EMMC_RESPONSE2 (def=0x0) // response parameter register
  • 0x40024014R32_EMMC_RESPONSE3// SD 128bits response register, [127:96] 32bits

    • [0:31]R32_EMMC_RESPONSE3 (def=0x0) // response parameter register
  • 0x40024014R32_EMMC_WRITE_CONT// Multiplexing register of the EMMC_RESPONSE3,[127:96] 32bits

    • [0:31]R32_EMMC_WRITE_CONT (def=0x0) // response parameter register
  • 0x40024018R16_EMMC_CONTROL// SD 8 bits control register

    • [0:1]RB_EMMC_LW_MASK (def=0x1) // effctive data width for sending or receiving data
    • [2]RB_EMMC_ALL_CLR (def=0x1) // reset all the inner logic, default is valid
    • [3]RB_EMMC_DMAEN (def=0x0) // enable the dma
    • [4]RB_EMMC_RST_LGC (def=0x1) // reset the data tran/recv logic
    • [5]RB_EMMC_NEGSMP (def=0x0) // controller use nagedge sample cmd
    • [8]RB_SLV_MODE (def=0x0) // enable Slave mode
    • [9]RB_SLV_FORCE_ERR (def=0x0) // Software forced data block CRC error in slave mode
  • 0x4002401CR8_EMMC_TIMEOUT// SD 8 bits data timeout value

    • [0:3]RB_EMMC_TOCNT_MASK (def=0xC) // response data timeout configuration
  • 0x40024020R32_EMMC_STATUS// SD status

    • [0:15]MASK_BLOCK_NUM (def=0x0) // the number of blocks successfully transmitted in the current multi-block transmission
    • [16]RB_EMMC_CMDSTA (def=0x0) // indicate cmd line is high level now
    • [17]RB_EMMC_DAT0STA (def=0x0) // indicate dat[0] line is high level now
  • 0x40024024R16_EMMC_INT_FG// SD 16bits interrupt flag register

    • [0]RB_EMMC_IF_RE_TMOUT (def=0x0) // indicate when expect the response, timeout
    • [1]RB_EMMC_IF_RECRC_WR (def=0x0) // indicate CRC error of the response
    • [2]RB_EMMC_IF_REIDX_ER (def=0x0) // indicate INDEX error of the response
    • [3]RB_EMMC_IF_CMDDONE (def=0x0) // when cmd hasn't response, indicate cmd has been sent, when cmd has a response, indicate cmd has bee
    • [4]RB_EMMC_IF_DATTMO (def=0x0) // data line busy timeout
    • [5]RB_EMMC_IF_TRANERR (def=0x0) // last block have encountered a CRC error
    • [6]RB_EMMC_IF_TRANDONE (def=0x0) // all the blocks have been tran/recv successfully
    • [7]RB_EMMC_IF_BKGAP (def=0x0) // every block gap interrupt when multiple read/write, allow drive change the DMA address at this mome
    • [8]RB_EMMC_IF_FIFO_OV (def=0x0) // fifo overflow, when write sd, indicate empty overflow, when read sd, indicate full overflow
    • [9]RB_EMMC_IF_SDIOINT (def=0x0) // interrupt from SDIO card inside
    • [10]RB_SIF_SLV_BUF_RELEASE (def=0x0) // In slave double buffer mode,BUF releases the flag bit
  • 0x40024028R16_EMMC_INT_EN// SD 16bits interrupt enable register

    • [0]RB_EMMC_IE_RE_TMOUT (def=0x0) // command response timeout interrupt enable
    • [1]RB_EMMC_IE_RECRC_WR (def=0x0) // response CRC check error interrupt enable
    • [2]RB_EMMC_IE_REIDX_ER (def=0x0) // response index check error interrupt enable
    • [3]RB_EMMC_IE_CMDDONE (def=0x0) // command completion interrupt enable
    • [4]RB_EMMC_IE_DATTMO (def=0x0) // data timeout interrupt enable
    • [5]RB_EMMC_IE_TRANERR (def=0x0) // blocks transfer CRC error interrupt enable
    • [6]RB_EMMC_IE_TRANDONE (def=0x0) // all blocks transfer complete interrupt enable
    • [7]RB_EMMC_IE_BKGAP (def=0x0) // single block transmission completion interrupt enable
    • [8]RB_EMMC_IE_FIFO_OV (def=0x0) // FIFO overflow interrupt enable
    • [9]RB_EMMC_IE_SDIOINT (def=0x0) // SDIO card interrupt enable
  • 0x4002402CR32_EMMC_DMA_BEG1// SD 32 bits DMA start address register when to operate

    • [0:31]RB_EMMC_DMAAD1_MASK (def=0x0) // start address of read-write data buffer,the lower 4 bits are fixed to 0
  • 0x40024030R32_EMMC_BLOCK_CFG// SD 32bits data counter, [15:0] number of blocks this time will tran/recv, [27:16] block sise(byte n

    • [0:15]RB_EMMC_BKNUM_MASK (def=0x0) // the number of blocks to be transferred
    • [16:27]RB_EMMC_BKSIZE_MASK (def=0x0) // single block transfer size
  • 0x40024034R32_EMMC_TRAN_MODE// SD TRANSFER MODE register

    • [0]RB_EMMC_DMA_DIR (def=0x0) // set DMA direction is controller to emmc card
    • [1]RB_EMMC_GAP_STOP (def=0x0) // clock stop mode after block completion
    • [2]RB_EMMC_MODE_BOOT (def=0x0) // enable emmc boot mode
    • [4]RB_EMMC_AUTOGAPSTOP (def=0x0) // enable auto set bTM_GAP_STOP when tran start
    • [8:14]RB_EMMC_DMATN_CNT (def=0x0) // in double buffer mode,set the block count value of buffer switch
    • [16]RB_EMMC_DULEDMA_EN (def=0x0) // enable double buffer dma
    • [17]RB_DDR_MODE (def=0x0) // enable DDR mode
    • [18]RB_CARE_NEG (def=0x0) // In DDR mode,check the falling edge of the clock
    • [19:20]RB_SW (def=0x0) // In DDR mode,the clock is switched
  • 0x40024038R16_EMMC_CLK_DIV// SD clock divider register

    • [0:4]RB_EMMC_DIV_MASK (def=0x13) // clk div
    • [8]RB_EMMC_CLKOE (def=0x0) // chip output sdclk oe
    • [9]RB_EMMC_CLKMode (def=0x1) // EMMC clock frequency mode selection bit
    • [10]RB_EMMC_PHASEINV (def=0x0) // invert chip output sdclk phase
  • 0x4002403CR32_EMMC_DMA_BEG2// SD 32bits DMA start address register when to operate

    • [0:31]RB_EMMC_DMAAD2_MASK (def=0x0) // start address of read-write data buffer,the lower 4 bits are fixed to 0
  • 0x40024040R32_EMMC_TUNE_DATO// data output delay register

    • [0:3]RB_TUNNE_DAT0_O (def=0x0) // the delay of data 0 output
    • [4:7]RB_TUNNE_DAT1_O (def=0x0) // the delay of data 1 output
    • [8:11]RB_TUNNE_DAT2_O (def=0x0) // the delay of data 2 output
    • [12:15]RB_TUNNE_DAT3_O (def=0x0) // the delay of data 3 output
    • [16:19]RB_TUNNE_DAT4_O (def=0x0) // the delay of data 4 output
    • [20:23]RB_TUNNE_DAT5_O (def=0x0) // the delay of data 5 output
    • [24:27]RB_TUNNE_DAT6_O (def=0x0) // the delay of data 6 output
    • [28:31]RB_TUNNE_DAT7_O (def=0x0) // the delay of data 7 output
  • 0x40024044R32_EMMC_TUNE_DATI// data input delay register

    • [0:3]RB_TUNNE_DAT0_I (def=0x0) // In DDR mode,the delay of data 0 input
    • [4:7]RB_TUNNE_DAT1_I (def=0x0) // In DDR mode,the delay of data 1 input
    • [8:11]RB_TUNNE_DAT2_I (def=0x0) // In DDR mode,the delay of data 2 input
    • [12:15]RB_TUNNE_DAT3_I (def=0x0) // In DDR mode,the delay of data 3 input
    • [16:19]RB_TUNNE_DAT4_I (def=0x0) // In DDR mode,the delay of data 4 input
    • [20:23]RB_TUNNE_DAT5_I (def=0x0) // In DDR mode,the delay of data 5 input
    • [24:27]RB_TUNNE_DAT6_I (def=0x0) // In DDR mode,the delay of data 6 input
    • [28:31]RB_TUNNE_DAT7_I (def=0x0) // In DDR mode,the delay of data 7 input
  • 0x40024048R32_EMMC_TUNE_CLK_CMD// clock and command delay registers

    • [0:3]RB_TUNNE_CLK_O (def=0x0) // In DDR mode,delay in command input
    • [4:7]RB_TUNNE_CLK_I (def=0x0) // In DDR mode,delay in command output
    • [16:19]RB_TUNNE_CMD_O (def=0x0) // In DDR mode,the delay of the clock input
    • [20:23]RB_TUNNE_CMD_I (def=0x0) // In DDR mode,the delay of the clock output
  interrupts:
  • [95] SDMMC // SDMMC global interrupt
• 0x40016C00ECDC// ECDC register

  • 0x40016C00R32_ECEC_CTRL// ECED AES/SM4 register

    • [0]RB_ECDC_KEYEX_EN (def=0x0) // enable key expansion
    • [1]RB_ECDC_NORMAL_EN (def=0x0) // Enable the encryption and decryption to work in the normal encryption and decryption mode
    • [3]RB_ECDC_MODE_SEL (def=0x0) // ECDC mode select
    • [4:6]RB_ECDC_CLKDIV_MASK (def=0x2) // Clock divide factor
    • [7]RB_ECDC_WRSRAM_EN (def=0x0) // module dma enable
    • [8]RB_ECDC_ALGRM_MOD (def=0x0) // Encryption and decryption algorithm mode selection
    • [9]RB_ECDC_CIPHER_MOD (def=0x0) // Block cipher mode selection
    • [10:11]RB_ECDC_KLEN_MASK (def=0x0) // Key length setting
    • [13]RB_ECDC_DAT_MOD (def=0x0) // source data and result data is bit endian
    • [16]RB_ECDC_IE_EKDONE (def=0x0) // Key extension completion interrupt enable
    • [17]RB_ECDC_IE_SINGLE (def=0x0) // Single encryption and decryption completion interrupt enable
    • [18]RB_ECDC_IE_WRSRAM (def=0x0) // Memory to memory encryption and decryption completion interrupt enable
    • [24]RB_ECDC_CLOCK_SELECT (def=0x0) // ECED AES/SM4 clock selection
    • [25]RB_ECDC_AES_SM4_CLOCK_EN (def=0x0) // ECED AES/SM4 clock enabled
  • 0x40016C04R32_ECDC_INT_FG// Interupt flag register

    • [16]RB_ECDC_IF_EKDONE (def=0x0) // Key extension completion interrupt flag
    • [17]RB_ECDC_IF_SINGLE (def=0x0) // Single encryption and decryption completion interrupt flag
    • [18]RB_ECDC_IF_WRSRAM (def=0x0) // Memory to memory encryption and decryption completion interrupt flag
  • 0x40016C08R32_ECDC_KEY_255T224// User key 224-255 register

    • [0:31]RB_ECDC_KEY_255T224 (def=0x0) // User key 224-255 register
  • 0x40016C0CR32_ECDC_KEY_223T192// User key 192-223 register

    • [0:31]RB_ECDC_KEY_223T192 (def=0x0) // User key 192-223 register
  • 0x40016C10R32_ECDC_KEY_191T160// User key 160-191 register

    • [0:31]RB_ECDC_KEY_191T160 (def=0x0) // User key 160-191 register
  • 0x40016C14R32_ECDC_KEY_159T128// User key 128-159 register

    • [0:31]RB_ECDC_KEY_159T128 (def=0x0) // User key 128-159 register
  • 0x40016C18R32_ECDC_KEY_127T96// User key 96-127 register

    • [0:31]RB_ECDC_KEY_127T96 (def=0x0) // User key 96-127 register
  • 0x40016C1CR32_ECDC_KEY_95T64// User key 64-95 register

    • [0:31]RB_ECDC_KEY_95T64 (def=0x0) // User key 64-95 register
  • 0x40016C20R32_ECDC_KEY_63T32// User key 32-63 register

    • [0:31]RB_ECDC_KEY_63T32 (def=0x0) // User key 32-63 register
  • 0x40016C24R32_ECDC_KEY_31T0// User key 0-31 register

    • [0:31]RB_ECDC_KEY_31T0 (def=0x0) // User key 0-31 register
  • 0x40016C28R32_ECDC_IV_127T96// CTR mode count 96-127 register

    • [0:31]RB_ECDC_IV_127T96 (def=0x0) // CTR mode count 96-127 register
  • 0x40016C2CR32_ECDC_IV_95T64// CTR mode count 64-95 register

    • [0:31]RB_ECDC_IV_95T64 (def=0x0) // CTR mode count 64-95 register
  • 0x40016C30R32_ECDC_IV_63T32// CTR mode count 32-63 register

    • [0:31]RB_ECDC_IV_63T32 (def=0x0) // CTR mode count 32-63 register
  • 0x40016C34R32_ECDC_IV_31T0// CTR mode count 0-31 register

    • [0:31]RB_ECDC_IV_31T0 (def=0x0) // CTR mode count 0-31 register
  • 0x40016C40R32_ECDC_SGSD_127T96// Single encryption and decryption of original data 96-127 register

    • [0:31]RB_ECDC_SGSD_127T96 (def=0x0) // Single encryption and decryption of original data 96-127 register
  • 0x40016C44R32_ECDC_SGSD_95T64// Single encryption and decryption of original data 64-95 register

    • [0:31]RB_ECDC_SGSD_95T64 (def=0x0) // Single encryption and decryption of original data 64-95 register
  • 0x40016C48R32_ECDC_SGSD_63T32// Single encryption and decryption of original data 32-63 register

    • [0:31]RB_ECDC_SGSD_63T32 (def=0x0) // Single encryption and decryption of original data 32-63 register
  • 0x40016C4CR32_ECDC_SGSD_31T0// Single encryption and decryption of original data 0-31 register

    • [0:31]RB_ECDC_SGSD_31T0 (def=0x0) // Single encryption and decryption of original data 0-31 register
  • 0x40016C50R32_ECDC_SGRT_127T96// Single encryption and decryption result 96-127 register

    • [0:31]RB_ECDC_SGRT_127T96 (def=0x0) // Single encryption and decryption result 96-127 register
  • 0x40016C54R32_ECDC_SGRT_95T64// Single encryption and decryption result 64-95 register

    • [0:31]RB_ECDC_SGRT_95T64 (def=0x0) // Single encryption and decryption result 64-95 register
  • 0x40016C58R32_ECDC_SGRT_63T32// Single encryption and decryption result 0-31 register

    • [0:31]RB_ECDC_SGRT_63T32 (def=0x0) // Single encryption and decryption result 0-31 register
  • 0x40016C5CRB_ECDC_SGRT_31T0// Single encryption and decryption result 0-31 register

    • [0:31]RB_ECDC_SGRT_31T0 (def=0x0) // Single encryption and decryption result 0-31 register
  • 0x40016C60R32_ECDC_SRC_ADDR// encryption and decryption sram start address register

    • [0:31]RB_ECDC_SRC_ADDR (def=0x0) // encryption and decryption sram start address register
  • 0x40016C64R32_ECDC_DST_ADDR// encryption and decryption sram destination address register

    • [0:31]RB_ECDC_DST_ADDR (def=0x0) // encryption and decryption sram destination address register
  • 0x40016C68R32_ECDC_SRAM_LEN// encryption and decryption sram size register

    • [0:12]RB_ECDC_SRAM_LEN (def=0x0) // encryption and decryption sram size register
  interrupts:
  • [121] ECDC // ECDC global Interrupt interrupt
• 0x40014400I3C// Improved inter-integrated circuit

  • 0x40014400I3C_CTLR// I3C control register

    • [0:15]DCNT (def=0x0) // count of data to transfer during a read or write message, in bytes (whatever I3C is acting as m
    • [16]RNW (def=0x0) // read / non-write message (when I3C is acting as master)
    • [17:23]ADD (def=0x0) // 7-bit I3C dynamic / I2C static slave address (when I3C is acting as master)
    • [27:30]MTYPE (def=0x0) // message type
    • [31]MEND (def=0x0) // message end type (when the I3C is acting as master)
  • 0x40014400I3C_CR_ALTERNATE// I3C message control register alternate

    • [0:15]DCNT (def=0x0) // count of data to transfer during a read or write message, in bytes (when I3C is acting as master)
    • [16:23]CCC (def=0x0) // 8-bit CCC code (when I3C is acting as master)
    • [27:30]MTYPE (def=0x0) // message type (when I3C is acting as master)
    • [31]MEND (def=0x0) // message end type (when I3C is acting as master)
  • 0x40014404I3C_CFGR// I3C configuration register

    • [0]EN (def=0x0) // I3C enable (whatever I3C is acting as master/slave)
    • [1]CRINIT (def=0x0) // initial master/slave role
    • [2]NOARBH (def=0x0) // no arbitrable header after a START (when I3C is acting as a master)
    • [3]RSTPTRN (def=0x0) // HDR reset pattern enable (when I3C is acting as a master)
    • [4]EXITPTRN (def=0x0) // HDR Exit Pattern enable (when I3C is acting as a master)
    • [7]HJACK (def=0x0) // Hot Join request acknowledge (when I3C is acting as a master)
    • [8]RXDMAEN (def=0x0) // RX-FIFO DMA request enable (whatever I3C is acting as master/slave)
    • [9]RXFLUSH (def=0x0) // RX-FIFO flush (whatever I3C is acting as master/slave)This bit can only be written.
    • [10]RXTHRES (def=0x0) // RX-FIFO threshold (whatever I3C is acting as master/slave)
    • [12]TXDMAEN (def=0x0) // TX-FIFO DMA request enable (whatever I3C is acting as master/slave)
    • [13]TXFLUSH (def=0x0) // TX-FIFO flush (whatever I3C is acting as master/slave)
    • [14]TXTHRES (def=0x0) // TX-FIFO threshold (whatever I3C is acting as master/slave)
    • [16]SDMAEN (def=0x0) // S-FIFO DMA request enable (when I3C is acting as master)
    • [17]SFLUSH (def=0x0) // S-FIFO flush (when I3C is acting as master)
    • [18]RMODE (def=0x0) // S-FIFO enable / status receive mode (when I3C is acting as master)
    • [19]TMODE (def=0x0) // transmit mode (when I3C is acting as master)
    • [20]CDMAEN (def=0x0) // C-FIFO DMA request enable (when I3C is acting as master)
    • [21]CFLUSH (def=0x0) // C-FIFO flush (when I3C is acting as master)
    • [30]TSFSET (def=0x0) // frame transfer set (a.k.a. software trigger) (when I3C is acting as master)
  • 0x40014410I3C_RDR// I3C receive data byte register

    • [0:7]RDB0 (def=0x0) // 8-bit received data on I3C bus.
  • 0x40014414I3C_RDWR// I3C receive data word register

    • [0:7]RDB0 (def=0x0) // 8-bit received data (earliest byte on I3C bus).
    • [8:15]RDB1 (def=0x0) // 8-bit received data (next byte after RDB0 on I3C bus).
    • [16:23]RDB2 (def=0x0) // 8-bit received data (next byte after RDB1 on I3C bus).
    • [24:31]RDB3 (def=0x0) // 8-bit received data (latest byte on I3C bus).
  • 0x40014418I3C_TDR// I3C transmit data byte register

    • [0:7]TDB0 (def=0x0) // 8-bit data to transmit on I3C bus.
  • 0x4001441CI3C_TDWR// I3C transmit data word register

    • [0:7]TDB0 (def=0x0) // 8-bit transmit data (earliest byte on I3C bus)
    • [8:15]TDB1 (def=0x0) // 8-bit transmit data (next byte after TDB0[7:0] on I3C bus).
    • [16:23]TDB2 (def=0x0) // 8-bit transmit data (next byte after TDB1[7:0] on I3C bus).
    • [24:31]TDB3 (def=0x0) // 8-bit transmit data (latest byte on I3C bus).
  • 0x40014420I3C_IBIDR// I3C IBI payload data register

    • [0:7]IBIDB0 (def=0x0) // 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte).
    • [8:15]IBIDB1 (def=0x0) // 8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0]).
    • [16:23]IBIDB2 (def=0x0) // 8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0]).
    • [24:31]IBIDB3 (def=0x0) // 8-bit IBI payload data (latest byte on I3C bus).
  • 0x40014424I3C_TGTTDR// I3C slave transmit configuration register

    • [0:15]TGTTDCNT (def=0x0) // transmit data counter, in bytes (when I3C is configured as slave)
    • [16]PRELOAD (def=0x0) // preload of the TX-FIFO (when I3C is configured as slave)
  • 0x4001442CI3C_RESET// I3C reset register

    • [24]HST_SIE_RST (def=0x1) // Reset Register of the Master
    • [25]TGT_SIE_RST (def=0x1) // Reset Register of the slave
  • 0x40014430I3C_STATR// I3C status register

    • [0:15]XDCNT (def=0x0) // data counter
    • [17]ABT (def=0x0) // a private read message is completed/aborted prematurely by the slave (when the I3C is acting as mas
    • [18]DIR (def=0x0) // message direction(whatever I3C is acting as master/slave)
    • [24:31]MID (def=0x0) // message identifier/counter of a given frame (when the I3C is acting as master)
  • 0x40014434I3C_STATER// I3C status error register

    • [0:3]CODERR (def=0x0) // protocol error code/type
    • [4]PERR (def=0x0) // protocol error
    • [5]STALL (def=0x0) // SCL stall error (when the I3C is acting as slave)
    • [6]DOVR (def=0x0) // RX-FIFO overrun or TX-FIFO underrun
    • [7]COVR (def=0x0) // C-FIFO underrun or S-FIFO overrun (when the I3C is acting as master)
    • [8]ANACK (def=0x0) // address not acknowledged (when the I3C is configured as master)
    • [9]DNACK (def=0x0) // data not acknowledged (when the I3C is acting as master)
    • [10]DERR (def=0x0) // data error (when the I3C is acting as master)
  • 0x40014440I3C_RMR// I3C received message register

    • [0:2]IBIRDCNT (def=0x0) // IBI received payload data count (when the I3C is configured as master)
    • [8:15]RCODE (def=0x0) // received CCC code (when the I3C is configured as slave)
    • [17:23]RADD (def=0x0) // received slave address (when the I3C is configured as master)
  • 0x40014450I3C_EVR// I3C event register

    • [0]CFEF (def=0x1) // C-FIFO empty flag (whatever the I3C is acting as master/slave)
    • [1]TXFEF (def=0x1) // TX-FIFO empty flag (whatever the I3C is acting as master/slave)
    • [2]CFNFF (def=0x0) // C-FIFO not full flag (when the I3C is acting as master)
    • [3]SFNEF (def=0x0) // S-FIFO not empty flag (when the I3C is acting as master)
    • [4]TXFNFF (def=0x0) // TX-FIFO not full flag (whatever the I3C is acting as master/slave)
    • [5]RXFNEF (def=0x0) // RX-FIFO not empty flag (whatever the I3C is acting as master/slave)
    • [6]TXLASTF (def=0x0) // last written data byte/word flag (whatever the I3C is acting as master/slave)
    • [7]RXLASTF (def=0x0) // last read data byte/word flag (whatever the I3C is acting as master/slave)
    • [9]FCF (def=0x0) // frame complete flag (whatever the I3C is acting as master/slave)
    • [10]RXTGTENDF (def=0x0) // slave-initiated read end flag (when the I3C is acting as master)
    • [11]ERRF (def=0x0) // flag (whatever the I3C is acting as master/slave)
    • [15]IBIF (def=0x0) // IBI flag (when the I3C is acting as master)
    • [16]IBIENDF (def=0x0) // IBI end flag (when the I3C is acting as slave)
    • [17]CRF (def=0x0) // master-role request flag (when the I3C is acting as master)
    • [18]CRUPDF (def=0x0) // master-role update flag (when the I3C is acting as slave)
    • [19]HJF (def=0x0) // hot-join flag (when the I3C is acting as master)
    • [21]WKPF (def=0x0) // wakeup/missed start flag (when the I3C is acting as slave)
    • [22]GETF (def=0x0) // get flag (when the I3C is acting as slave)
    • [23]STAF (def=0x0) // get status flag (when the I3C is acting as slave)
    • [24]DAUPDF (def=0x0) // dynamic address update flag (when the I3C is acting as slave)
    • [25]MWLUPDF (def=0x0) // maximum write length update flag (when the I3C is acting as slave)
    • [26]MRLUPDF (def=0x0) // maximum read length update flag (when the I3C is acting as slave)
    • [27]RSTF (def=0x0) // reset pattern flag (when the I3C is acting as slave)
    • [28]ASUPDF (def=0x0) // activity state update flag (when the I3C is acting as slave)
    • [29]INTUPDF (def=0x0) // interrupt/master-role/hot-join update flag (when the I3C is acting as slave)
    • [30]DEFF (def=0x0) // DEFTGTS flag (when the I3C is acting as slave)
    • [31]GRPF (def=0x0) // group addressing flag (when the I3C is acting as slave)
  • 0x40014454I3C_INTENR// I3C interrupt enable register

    • [2]CFNFIE (def=0x0) // C-FIFO not full interrupt enable (whatever the I3C is acting as master/slave)
    • [3]SFNEIE (def=0x0) // S-FIFO not empty interrupt enable (whatever the I3C is acting as master/slave)
    • [4]TXFNFIE (def=0x0) // TX-FIFO not full interrupt enable (whatever the I3C is acting as master/slave)
    • [5]RXFNEIE (def=0x0) // RX-FIFO not empty interrupt enable (whatever the I3C is acting as master/slave)
    • [9]FCIE (def=0x0) // frame complete interrupt enable (whatever the I3C is acting as master/slave)
    • [10]RXTGTENDIE (def=0x0) // slave-initiated read end interrupt enable (when the I3C is acting as master)
    • [11]ERRIE (def=0x0) // error interrupt enable (whatever the I3C is acting as master/slave)
    • [15]IBIIE (def=0x0) // IBI request interrupt enable (when the I3C is acting as master)
    • [16]IBIENDIE (def=0x0) // IBI end interrupt enable (when the I3C is acting as slave)
    • [17]CRIE (def=0x0) // master-role request interrupt enable (when the I3C is acting as master)
    • [18]CRUPDIE (def=0x0) // master-role update interrupt enable (when the I3C is acting as slave)
    • [19]HJIE (def=0x0) // hot-join interrupt enable (when the I3C is acting as master)
    • [21]WKPIE (def=0x0) // wakeup interrupt enable (when the I3C is acting as slave)
    • [22]GETIE (def=0x0) // GETxxx CCC interrupt enable (when the I3C is acting as slave)
    • [23]STAIE (def=0x0) // GETSTATUS CCC interrupt enable (when the I3C is acting as slave)
    • [24]DAUPDIE (def=0x0) // ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C is acting as slave)
    • [25]MWLUPDIE (def=0x0) // SETMWL CCC interrupt enable (when the I3C is acting as slave)
    • [26]MRLUPDIE (def=0x0) // SETMRL CCC interrupt enable (when the I3C is acting as slave)
    • [27]RSTIE (def=0x0) // reset pattern interrupt enable (when the I3C is acting as slave)
    • [28]ASUPDIE (def=0x0) // ENTASx CCC interrupt enable (when the I3C is acting as slave)
    • [29]INTUPDIE (def=0x0) // ENEC/DISEC CCC interrupt enable (when the I3C is acting as slave)
    • [30]DEFIE (def=0x0) // DEFTGTS CCC interrupt enable (when the I3C is acting as slave)
    • [31]GRPIE (def=0x0) // DEFGRPA CCC interrupt enable (when the I3C is acting as slave)
  • 0x40014458I3C_CEVR// I3C clear event register

    • [9]CFCF (def=0x0) // clear frame complete flag (whatever the I3C is acting as master/slave)
    • [10]CRXTGTENDF (def=0x0) // clear slave-initiated read end flag (when the I3C is acting as master)
    • [11]CERRF (def=0x0) // clear error flag (whatever the I3C is acting as master/slave)
    • [15]CIBIF (def=0x0) // clear IBI request flag (when the I3C is acting as master)
    • [16]CIBIENDF (def=0x0) // clear IBI end flag (when the I3C is acting as slave)
    • [17]CCRF (def=0x0) // clear master-role request flag (when the I3C is acting as master)
    • [18]CCRUPDF (def=0x0) // clear master-role update flag (when the I3C is acting as slave)
    • [19]CHJF (def=0x0) // clear hot-join flag (when the I3C is acting as master)
    • [21]CWKPF (def=0x0) // clear wakeup flag (when the I3C is acting as slave)
    • [22]CGETF (def=0x0) // clear GETxxx CCC flag (when the I3C is acting as slave)
    • [23]CSTAF (def=0x0) // clear GETSTATUS CCC flag (when the I3C is acting as slave)
    • [24]CDAUPDF (def=0x0) // clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C is acting as slave)
    • [25]CMWLUPDF (def=0x0) // clear SETMWL CCC flag (when the I3C is acting as slave)
    • [26]CMRLUPDF (def=0x0) // clear SETMRL CCC flag (when the I3C is acting as slave)
    • [27]CRSTF (def=0x0) // clear reset pattern flag (when the I3C is acting as slave)
    • [28]CASUPDF (def=0x0) // clear ENTASx CCC flag (when the I3C is acting as slave)
    • [29]CINTUPDF (def=0x0) // clear ENEC/DISEC CCC flag (when the I3C is acting as slave)
    • [30]CDEFF (def=0x0) // clear DEFTGTS CCC flag (when the I3C is acting as slave)
    • [31]CGRPF (def=0x0) // clear DEFGRPA CCC flag (when the I3C is acting as slave)
  • 0x40014460I3C_DEVR0// I3C own device characteristics register

    • [0]DAVAL (def=0x0) // dynamic address is valid (when the I3C is acting as slave)
    • [1:7]DA (def=0x0) // 7-bit dynamic address
    • [16]IBIEN (def=0x0) // IBI request enable (when the I3C is acting as slave)
    • [17]CREN (def=0x0) // master-role request enable (when the I3C is acting as slave)
    • [19]HJEN (def=0x0) // hot-join request enable (when the I3C is acting as slave)
    • [20:21]AS (def=0x0) // activity state (when the I3C is acting as slave)
    • [22:23]RSTACT (def=0x0) // reset action/level on received reset pattern (when the I3C is acting as slave)
    • [24]RSTVAL (def=0x0) // reset action is valid (when the I3C is acting as slave)
  • 0x40014464I3C_DEVR1// I3C device 1 characteristics register

    • [1:7]DA (def=0x0) // assigned I3C dynamic address to slave x (when the I3C is acting as master)
    • [16]IBIACK (def=0x0) // IBI request acknowledge (when the I3C is acting as master)
    • [17]CRACK (def=0x0) // master-role request acknowledge (when the I3C is acting as master)
    • [18]IBIDEN (def=0x0) // IBI data enable (when the I3C is acting as master)
    • [19]SUSP (def=0x0) // suspend/stop I3C transfer on received IBI (when the I3C is acting as master)
    • [31]DIS (def=0x0) // DA[6:0] write disabled (when the I3C is acting as master)
  • 0x40014468I3C_DEVR2// I3C device 2 characteristics register

    • [1:7]DA (def=0x0) // assigned I3C dynamic address to slave x (when the I3C is acting as master)
    • [16]IBIACK (def=0x0) // IBI request acknowledge (when the I3C is acting as master)
    • [17]CRACK (def=0x0) // master-role request acknowledge (when the I3C is acting as master)
    • [18]IBIDEN (def=0x0) // IBI data enable (when the I3C is acting as master)
    • [19]SUSP (def=0x0) // suspend/stop I3C transfer on received IBI (when the I3C is acting as master)
    • [31]DIS (def=0x0) // DA[6:0] write disabled (when the I3C is acting as master)
  • 0x4001446CI3C_DEVR3// I3C device 3 characteristics register

    • [1:7]DA (def=0x0) // assigned I3C dynamic address to slave x (when the I3C is acting as master)
    • [16]IBIACK (def=0x0) // IBI request acknowledge (when the I3C is acting as master)
    • [17]CRACK (def=0x0) // master-role request acknowledge (when the I3C is acting as master)
    • [18]IBIDEN (def=0x0) // IBI data enable (when the I3C is acting as master)
    • [19]SUSP (def=0x0) // suspend/stop I3C transfer on received IBI (when the I3C is acting as master)
    • [31]DIS (def=0x0) // DA[6:0] write disabled (when the I3C is acting as master)
  • 0x40014470I3C_DEVR4// I3C device 4 characteristics register

    • [1:7]DA (def=0x0) // assigned I3C dynamic address to slave x (when the I3C is acting as master)
    • [16]IBIACK (def=0x0) // IBI request acknowledge (when the I3C is acting as master)
    • [17]CRACK (def=0x0) // master-role request acknowledge (when the I3C is acting as master)
    • [18]IBIDEN (def=0x0) // IBI data enable (when the I3C is acting as master)
    • [19]SUSP (def=0x0) // suspend/stop I3C transfer on received IBI (when the I3C is acting as master)
    • [31]DIS (def=0x0) // DA[6:0] write disabled (when the I3C is acting as master)
  • 0x40014490I3C_MAXRLR// I3C maximum read length register

    • [0:15]MRL (def=0x0) // maximum data read length (when I3C is acting as slave)
    • [16:18]IBIP (def=0x0) // IBI payload data size, in bytes (when I3C is acting as slave)
  • 0x40014494I3C_MAXWLR// I3C maximum write length register

    • [0:15]MWL (def=0x0) // maximum data write length (when I3C is acting as slave)
  • 0x400144A0I3C_TIMINGR0// I3C timing register 0

    • [0:7]SCLL_PP (def=0x0) // SCL low duration in I3C push-pull phases, in number of kernel clocks cycles
    • [8:15]SCLH_I3C (def=0x0) // SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of ke
    • [16:23]SCLL_OD (def=0x0) // SCL low duration in open-drain phases, used for legacy I2C commands and for I3C open-drain phases (
    • [24:31]SCLH_I2C (def=0x0) // SCL high duration, used for legacy I2C commands, in number of kernel clocks cycles
  • 0x400144A4I3C_TIMINGR1// I3C timing register 1

    • [0:7]AVAL (def=0x0) // number of kernel clock cycles, that is used whatever I3C is acting as controller or slave, to set t
    • [8:9]ASNCR (def=0x0) // activity state of the new master (when I3C is acting as active- master)
    • [16:22]FREE (def=0x0) // number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (
    • [28]SDA_HD (def=0x0) // SDA hold time (when the I3C is acting as master), in number of kernel clocks cycles (refer to MIPI
  • 0x400144A8I3C_TIMINGR2// I3C timing register 2

    • [0]STALLT (def=0x0) // master clock stall on T-bit phase of Data enable
    • [1]STALLD (def=0x0) // master clock stall on PAR phase of Data enable
    • [2]STALLC (def=0x0) // master clock stall on PAR phase of CCC enable
    • [3]STALLA (def=0x0) // master clock stall enable on ACK phase
    • [8:15]STALL (def=0x0) // master clock stall time, in number of kernel clock cycles
  • 0x400144C0I3C_BCR// I3C bus characteristics register

    • [0]BCR0 (def=0x0) // max data speed limitation
    • [2]BCR2 (def=0x0) // in-band interrupt (IBI) payload
    • [6]BCR6 (def=0x0) // master capable
  • 0x400144C4I3C_DCR// I3C device characteristics register

    • [0:7]DCR (def=0x0) // device characteristics ID
  • 0x400144C8I3C_GETCAPR// I3C get capability register

    • [14]CAPPEND (def=0x0) // IBI MDB support for pending read notification
  • 0x400144CCI3C_CRCAPR// I3C master-role capability register

    • [3]CAPDHOFF (def=0x0) // delayed master-role hand-off
    • [9]CAPGRP (def=0x0) // group management support (when acting as master)
  • 0x400144D0I3C_GETMDSR// I3C get capability register

    • [0:1]HOFFAS (def=0x0) // master hand-off activity state
    • [8:9]FMT (def=0x0) // GETMXDS CCC format
    • [16:23]RDTURN (def=0x0) // programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte)
    • [24]TSCO (def=0x0) // clock-to-data turnaround time (tSCO)
  • 0x400144D4I3C_EPIDR// I3C extended provisioned ID register

    • [12:15]MIPIID (def=0x0) // 4-bit MIPI Instance ID
    • [16]IDTSEL (def=0x0) // provisioned ID type selector
    • [17:31]MIPIMID (def=0x104) // 15-bit MIPI manufacturer ID
  interrupts:
  • [118] I3C_EV // I3C event interrupt
  • [119] I3C_ER // I3C error interrupt
  • [142] I3CWakeUP // I3C wakeup interrupt
• 0x40017400HSADC// High speed ADC

  • 0x40017400CFGR// High-speed ADC configuration register

    • [0]EN (def=0x0) // High-speed ADC enable
    • [2:4]DMAEN (def=0x0) // Direct Storage Access (DMA) mode enable
    • [8:13]SETUP (def=0x24) // First Transition Establishment Time Configuration Bit
    • [14]PPMODE (def=0x0) // Ping Pong storage mode enable
    • [15]BURST_EN (def=0x0) // DMA transmission length configuration bit
    • [16:31]DMA_LEN (def=0x0) // DMA transmission length configuration bit
  • 0x40017404CTLR1// HSADC Control Register 1

    • [0]START (def=0x0) // Initiating High-Speed ADC Conversion
    • [1]BURST_END (def=0x0) // Abort a burst transmission
    • [8]EOCIE (def=0x0) // Transition Completion Interrupt Enables
    • [9]DMAIE (def=0x0) // Transition Completion Interrupt Enables
    • [10]BURSTIE (def=0x0) // Interrupt enables when the burst transmission is complete
  • 0x40017408CTLR2// HSADC Control Register 2

    • [0:15]BURST_LEN (def=0x0) // Burst transmission length configuration
    • [16:31]BURST_DMA_LEN (def=0x0) // The final DMA transmission length configuration bit for burst transmission. If the number of
  • 0x4001740CSTATR// HSADC Status Register

    • [0]EOCIF (def=0x0) // Transition Complete Interrupt flag
    • [1]DMAIF (def=0x0) // DMA Transmission Complete Interrupt flag
    • [2]BURSTIF (def=0x0) // Burst transfer completed interrupt flag
    • [3]RXNE (def=0x0) // The data register is not empty flag, that is, the conversion is completed and the data is sto
    • [4]PP_ADDR (def=0x0) // Ping-pong storage mode cache address indicator bit
    • [8]FIFO_RDY (def=0x1) // Receives a FIFO non-null status flag
    • [9]FIFO_FULL (def=0x0) // Receive FIFO full status flags
    • [10]FIFO_OV (def=0x0) // Receives the FIFO overflow status flag
    • [11:13]FIFO_CNT (def=0x0) // Receives the FIFO current count value
  • 0x40017410DATAR// HSADC Data Register

    • [0:9]DR (def=0x0) // Convert data register
  • 0x40017414ADDR0// HSADC DMA Receive Address Register 0

    • [0:31]DMA_ADDR0 (def=0x0) // The DMA transmission address is configured with the 0 configuration bit
  • 0x40017418ADDR1// HSADC DMA Receive Address Register 1

    • [0:31]DMA_ADDR1 (def=0x0) // DMA transport address 1 configuration bit
  interrupts:
  • [144] HSADC // HSADC global interrupt
• 0x40010400EXTI// EXTI

  • 0x40010400INTENR// Interrupt mask register (EXTI_INTENR)

    • [0]MR0 (def=0x0) // Interrupt Mask on line 0
    • [1]MR1 (def=0x0) // Interrupt Mask on line 1
    • [2]MR2 (def=0x0) // Interrupt Mask on line 2
    • [3]MR3 (def=0x0) // Interrupt Mask on line 3
    • [4]MR4 (def=0x0) // Interrupt Mask on line 4
    • [5]MR5 (def=0x0) // Interrupt Mask on line 5
    • [6]MR6 (def=0x0) // Interrupt Mask on line 6
    • [7]MR7 (def=0x0) // Interrupt Mask on line 7
    • [8]MR8 (def=0x0) // Interrupt Mask on line 8
    • [9]MR9 (def=0x0) // Interrupt Mask on line 9
    • [10]MR10 (def=0x0) // Interrupt Mask on line 10
    • [11]MR11 (def=0x0) // Interrupt Mask on line 11
    • [12]MR12 (def=0x0) // Interrupt Mask on line 12
    • [13]MR13 (def=0x0) // Interrupt Mask on line 13
    • [14]MR14 (def=0x0) // Interrupt Mask on line 14
    • [15]MR15 (def=0x0) // Interrupt Mask on line 15
    • [16]MR16 (def=0x0) // Interrupt Mask on line 16
    • [17]MR17 (def=0x0) // Interrupt Mask on line 17
    • [19]MR19 (def=0x0) // Interrupt Mask on line 19
    • [20]MR20 (def=0x0) // Interrupt Mask on line 20
    • [21]MR21 (def=0x0) // Interrupt Mask on line 21
    • [22]MR22 (def=0x0) // Interrupt Mask on line 22
    • [23]MR23 (def=0x0) // Interrupt Mask on line 23
    • [24]MR24 (def=0x0) // Interrupt Mask on line 24
    • [25]MR25 (def=0x0) // Interrupt Mask on line 25
    • [26]MR26 (def=0x0) // Interrupt Mask on line 26
  • 0x40010404EVENR// Event mask register (EXTI_EVENR)

    • [0]MR0 (def=0x0) // Event Mask on line 0
    • [1]MR1 (def=0x0) // Event Mask on line 1
    • [2]MR2 (def=0x0) // Event Mask on line 2
    • [3]MR3 (def=0x0) // Event Mask on line 3
    • [4]MR4 (def=0x0) // Event Mask on line 4
    • [5]MR5 (def=0x0) // Event Mask on line 5
    • [6]MR6 (def=0x0) // Event Mask on line 6
    • [7]MR7 (def=0x0) // Event Mask on line 7
    • [8]MR8 (def=0x0) // Event Mask on line 8
    • [9]MR9 (def=0x0) // Event Mask on line 9
    • [10]MR10 (def=0x0) // Event Mask on line 10
    • [11]MR11 (def=0x0) // Event Mask on line 11
    • [12]MR12 (def=0x0) // Event Mask on line 12
    • [13]MR13 (def=0x0) // Event Mask on line 13
    • [14]MR14 (def=0x0) // Event Mask on line 14
    • [15]MR15 (def=0x0) // Event Mask on line 15
    • [16]MR16 (def=0x0) // Event Mask on line 16
    • [17]MR17 (def=0x0) // Event Mask on line 17
    • [19]MR19 (def=0x0) // Event Mask on line 19
    • [20]MR20 (def=0x0) // Event Mask on line 20
    • [21]MR21 (def=0x0) // Event Mask on line 21
    • [22]MR22 (def=0x0) // Event Mask on line 22
    • [23]MR23 (def=0x0) // Event Mask on line 23
    • [24]MR24 (def=0x0) // Event Mask on line 24
    • [25]MR25 (def=0x0) // Event Mask on line 25
    • [26]MR26 (def=0x0) // Event Mask on line 26
  • 0x40010408RTENR// Rising Trigger selection register (EXTI_RTENR)

    • [0]TR0 (def=0x0) // Rising trigger event configuration of line 0
    • [1]TR1 (def=0x0) // Rising trigger event configuration of line 1
    • [2]TR2 (def=0x0) // Rising trigger event configuration of line 2
    • [3]TR3 (def=0x0) // Rising trigger event configuration of line 3
    • [4]TR4 (def=0x0) // Rising trigger event configuration of line 4
    • [5]TR5 (def=0x0) // Rising trigger event configuration of line 5
    • [6]TR6 (def=0x0) // Rising trigger event configuration of line 6
    • [7]TR7 (def=0x0) // Rising trigger event configuration of line 7
    • [8]TR8 (def=0x0) // Rising trigger event configuration of line 8
    • [9]TR9 (def=0x0) // Rising trigger event configuration of line 9
    • [10]TR10 (def=0x0) // Rising trigger event configuration of line 10
    • [11]TR11 (def=0x0) // Rising trigger event configuration of line 11
    • [12]TR12 (def=0x0) // Rising trigger event configuration of line 12
    • [13]TR13 (def=0x0) // Rising trigger event configuration of line 13
    • [14]TR14 (def=0x0) // Rising trigger event configuration of line 14
    • [15]TR15 (def=0x0) // Rising trigger event configuration of line 15
    • [16]TR16 (def=0x0) // Rising trigger event configuration of line 16
    • [17]TR17 (def=0x0) // Rising trigger event configuration of line 17
    • [19]TR19 (def=0x0) // Rising trigger event configuration of line 19
    • [20]TR20 (def=0x0) // Rising trigger event configuration of line 20
    • [21]TR21 (def=0x0) // Rising trigger event configuration of line 21
    • [22]TR22 (def=0x0) // Rising trigger event configuration of line 22
    • [23]TR23 (def=0x0) // Rising trigger event configuration of line 23
    • [24]TR24 (def=0x0) // Rising trigger event configuration of line 24
    • [25]TR25 (def=0x0) // Rising trigger event configuration of line 25
    • [26]TR26 (def=0x0) // Rising trigger event configuration of line 26
  • 0x4001040CFTENR// Falling Trigger selection register (EXTI_FTENR)

    • [0]TR0 (def=0x0) // Falling trigger event configuration of line 0
    • [1]TR1 (def=0x0) // Falling trigger event configuration of line 1
    • [2]TR2 (def=0x0) // Falling trigger event configuration of line 2
    • [3]TR3 (def=0x0) // Falling trigger event configuration of line 3
    • [4]TR4 (def=0x0) // Falling trigger event configuration of line 4
    • [5]TR5 (def=0x0) // Falling trigger event configuration of line 5
    • [6]TR6 (def=0x0) // Falling trigger event configuration of line 6
    • [7]TR7 (def=0x0) // Falling trigger event configuration of line 7
    • [8]TR8 (def=0x0) // Falling trigger event configuration of line 8
    • [9]TR9 (def=0x0) // Falling trigger event configuration of line 9
    • [10]TR10 (def=0x0) // Falling trigger event configuration of line 10
    • [11]TR11 (def=0x0) // Falling trigger event configuration of line 11
    • [12]TR12 (def=0x0) // Falling trigger event configuration of line 12
    • [13]TR13 (def=0x0) // Falling trigger event configuration of line 13
    • [14]TR14 (def=0x0) // Falling trigger event configuration of line 14
    • [15]TR15 (def=0x0) // Falling trigger event configuration of line 15
    • [16]TR16 (def=0x0) // Falling trigger event configuration of line 16
    • [17]TR17 (def=0x0) // Falling trigger event configuration of line 17
    • [19]TR19 (def=0x0) // Falling trigger event configuration of line 19
    • [20]TR20 (def=0x0) // Falling trigger event configuration of line 20
    • [21]TR21 (def=0x0) // Falling trigger event configuration of line 21
    • [22]TR22 (def=0x0) // Falling trigger event configuration of line 22
    • [23]TR23 (def=0x0) // Falling trigger event configuration of line 23
    • [24]TR24 (def=0x0) // Falling trigger event configuration of line 24
    • [25]TR25 (def=0x0) // Falling trigger event configuration of line 25
    • [26]TR26 (def=0x0) // Falling trigger event configuration of line 26
  • 0x40010410SWIEVR// Software interrupt event register (EXTI_SWIEVR)

    • [0]SWIER0 (def=0x0) // Software Interrupt on line 0
    • [1]SWIER1 (def=0x0) // Software Interrupt on line 1
    • [2]SWIER2 (def=0x0) // Software Interrupt on line 2
    • [3]SWIER3 (def=0x0) // Software Interrupt on line 3
    • [4]SWIER4 (def=0x0) // Software Interrupt on line 4
    • [5]SWIER5 (def=0x0) // Software Interrupt on line 5
    • [6]SWIER6 (def=0x0) // Software Interrupt on line 6
    • [7]SWIER7 (def=0x0) // Software Interrupt on line 7
    • [8]SWIER8 (def=0x0) // Software Interrupt on line 8
    • [9]SWIER9 (def=0x0) // Software Interrupt on line 9
    • [10]SWIER10 (def=0x0) // Software Interrupt on line 10
    • [11]SWIER11 (def=0x0) // Software Interrupt on line 11
    • [12]SWIER12 (def=0x0) // Software Interrupt on line 12
    • [13]SWIER13 (def=0x0) // Software Interrupt on line 13
    • [14]SWIER14 (def=0x0) // Software Interrupt on line 14
    • [15]SWIER15 (def=0x0) // Software Interrupt on line 15
    • [16]SWIER16 (def=0x0) // Software Interrupt on line 16
    • [17]SWIER17 (def=0x0) // Software Interrupt on line 17
    • [19]SWIER19 (def=0x0) // Software Interrupt on line 19
    • [20]SWIER20 (def=0x0) // Software Interrupt on line 20
    • [21]SWIER21 (def=0x0) // Software Interrupt on line 21
    • [22]SWIER22 (def=0x0) // Software Interrupt on line 22
    • [23]SWIER23 (def=0x0) // Software Interrupt on line 23
    • [24]SWIER24 (def=0x0) // Software Interrupt on line 24
    • [25]SWIER25 (def=0x0) // Software Interrupt on line 25
    • [26]SWIER26 (def=0x0) // Software Interrupt on line 26
  • 0x40010414INTFR// interrupt flag register (EXTI_INTFR)

    • [0]IF0 (def=0x0) // interrupt flag bit 0
    • [1]IF1 (def=0x0) // interrupt flag bit 1
    • [2]IF2 (def=0x0) // interrupt flag bit 2
    • [3]IF3 (def=0x0) // interrupt flag bit 3
    • [4]IF4 (def=0x0) // interrupt flag bit 4
    • [5]IF5 (def=0x0) // interrupt flag bit 5
    • [6]IF6 (def=0x0) // interrupt flag bit 6
    • [7]IF7 (def=0x0) // interrupt flag bit 7
    • [8]IF8 (def=0x0) // interrupt flag bit 8
    • [9]IF9 (def=0x0) // interrupt flag bit 9
    • [10]IF10 (def=0x0) // interrupt flag bit 10
    • [11]IF11 (def=0x0) // interrupt flag bit 11
    • [12]IF12 (def=0x0) // interrupt flag bit 12
    • [13]IF13 (def=0x0) // interrupt flag bit 13
    • [14]IF14 (def=0x0) // interrupt flag bit 14
    • [15]IF15 (def=0x0) // interrupt flag bit 15
    • [16]IF16 (def=0x0) // interrupt flag bit 16
    • [17]IF17 (def=0x0) // interrupt flag bit 17
    • [19]IF19 (def=0x0) // interrupt flag bit 19
    • [20]IF20 (def=0x0) // interrupt flag bit 20
    • [21]IF21 (def=0x0) // interrupt flag bit 21
    • [22]IF22 (def=0x0) // interrupt flag bit 22
    • [23]IF23 (def=0x0) // interrupt flag bit 23
    • [24]IF24 (def=0x0) // interrupt flag bit 24
    • [25]IF25 (def=0x0) // interrupt flag bit 25
    • [26]IF26 (def=0x0) // interrupt flag bit 26
  interrupts:
  • [36] EXTI7_0 // EXTI Line[7:0] interrupt
  • [33] EXTI15_8 // EXTI Line[15:8] interrupts
• 0x40017800OPA// OPA configuration

  • 0x40017800OPA_CTLR1// OPA Control Register 1

    • [0]EN1 (def=0x0) // OPA1 enable
    • [1:2]MODE1 (def=0x3) // OPA1 Output Channel Selection
    • [3]PSEL1 (def=0x0) // OPA1 Positive Channel Selection
    • [4:6]NSEL1 (def=0x7) // OPA1 Negative Channel Selection vs. PGA Gain Selection
    • [8]FB_EN1 (def=0x0) // OPA1's PGA mode feedback enable
    • [9]PGADIF1 (def=0x0) // OPA1 is used with NSEL1 as PGA and the N-terminal is connected to OPA1_CHN1 (PA7)
    • [10]HS1 (def=0x0) // OPA1 high-speed mode enables
  • 0x40017804OPA_CTLR2// OPA Control Register 2

    • [0]EN2 (def=0x0) // OPA2 enable
    • [1:2]MODE2 (def=0x0) // OPA2 Output Channel Selection
    • [3]PSEL2 (def=0x0) // OPA2 Positive Channel Selection
    • [4:6]NSEL2 (def=0x7) // OPA2 Negative Channel Selection vs. PGA Gain Selection
    • [8]FB_EN2 (def=0x0) // OPA2's PGA mode feedback enable
    • [9]PGADIF1 (def=0x0) // OPA2 is used with NSEL1 as PGA and the N-terminal is connected to OPA2_CHN1 (PA7)
    • [10]HS2 (def=0x0) // OPA2 high-speed mode enables
  • 0x40017808OPA_CTLR3// OPA Control Register 3

    • [0]EN3 (def=0x0) // OPA3 enable
    • [1:2]MODE3 (def=0x0) // OPA3 Output Channel Selection
    • [3]PSEL3 (def=0x0) // OPA3 Positive Channel Selection
    • [4:6]NSEL3 (def=0x7) // OPA3 Negative Channel Selection vs. PGA Gain Selection
    • [8]FB_EN3 (def=0x0) // OPA3's PGA mode feedback enable
    • [9]PGADIF3 (def=0x0) // OPA3 is used with NSEL1 as PGA and the N-terminal is connected to OPA3_CHN1 (PA7)
    • [10]HS3 (def=0x0) // OPA3 high-speed mode enables
  • 0x4001780CCMP_CTLR// CMP Control Registers

    • [0:1]PSEL (def=0x3) // CMP Positive Channel Selection Bits
    • [2:3]NSEL (def=0x3) // CMP Negative End Channel Selection Bits
    • [4:7]MODE (def=0xF) // CMP Output Channel Selection
    • [8]EN (def=0x0) // CMP enables
    • [9:10]HYPSEL (def=0x0) // CMP hysteresis voltage selector
    • [11:12]VREF (def=0x0) // CMP Internal Bias Voltage Selector
    • [13]FILT_EN (def=0x0) // CMP Digital Filtering Enable
    • [16:24]FILT_CFG (def=0x0) // CMP filter sampling interval configuration
    • [28:30]FILT_BASE (def=0x0) // CMP filtering sampling time base configuration
  • 0x40017810CMP_STATR// CMP Status Registers

    • [0]OUT_FILT (def=0x0) // CMP Output
• 0x40014800LTDC// LCD-TFT Controller

  • 0x40014800SSCR// Synchronization Size Configuration Register

    • [16:27]HSW (def=0x0) // Horizontal Synchronization Width (in units of pixel clock period)
    • [0:10]VSH (def=0x0) // Vertical Synchronization Height (in units of horizontal scan line)
  • 0x40014804BPCR// Back Porch Configuration Register

    • [16:27]AHBP (def=0x0) // Accumulated Horizontal back porch (in units of pixel clock period)
    • [0:10]AVBP (def=0x0) // Accumulated Vertical back porch (in units of horizontal scan line)
  • 0x40014808AWCR// Active Width Configuration Register

    • [16:27]AAW (def=0x0) // Accumulated Active Width (in units of pixel clock period)
    • [0:10]AAH (def=0x0) // Accumulated Active Height (in units of horizontal scan line)
  • 0x4001480CTWCR// Total Width Configuration Register

    • [16:27]TOTALW (def=0x0) // Total Width (in units of pixel clock period)
    • [0:10]TOTALH (def=0x0) // Total Height (in units of horizontal scan line)
  • 0x40014810GCR// Global Control Register

    • [31]HSPOL (def=0x0) // Horizontal Synchronization Polarity
    • [30]VSPOL (def=0x0) // Vertical Synchronization Polarity
    • [29]DEPOL (def=0x0) // Data Enable Polarity
    • [28]PCPOL (def=0x0) // Pixel Clock Polarity
    • [16]DEN (def=0x0) // Dither Enable
    • [12:14]DRW (def=0x2) // Dither Red Width
    • [8:10]DGW (def=0x2) // Dither Green Width
    • [4:6]DBW (def=0x2) // Dither Blue Width
    • [0]LTDCEN (def=0x0) // LCD-TFT controller enable bit
  • 0x40014814SRCR// Shadow Reload Configuration Register

    • [1]VBR (def=0x0) // Vertical Blanking Reload
    • [0]IMR (def=0x0) // Immediate Reload
  • 0x40014818BCCR// Background Color Configuration Register

    • [0:7]BCBLUE (def=0x0) // Background Color Blue value
    • [8:15]BCGREEN (def=0x0) // Background Color Green value
    • [16:23]BCRED (def=0x0) // Background Color Red value
  • 0x4001481CIER// Interrupt Enable Register

    • [3]RRIE (def=0x0) // Register Reload interrupt enable
    • [1]FUIE (def=0x0) // FIFO Underrun Interrupt Enable
    • [0]LIE (def=0x0) // Line Interrupt Enable
  • 0x40014820ISR// Interrupt Status Register

    • [3]RRIF (def=0x0) // Register Reload Interrupt Flag
    • [1]FUIF (def=0x0) // FIFO Underrun Interrupt flag
    • [0]LIF (def=0x0) // Line Interrupt flag
  • 0x40014824ICR// Interrupt Clear Register

    • [3]CRRIF (def=0x0) // Clears Register Reload Interrupt Flag
    • [1]CFUIF (def=0x0) // Clears the FIFO Underrun Interrupt flag
    • [0]CLIF (def=0x0) // Clears the Line Interrupt Flag
  • 0x40014828LIPCR// Line Interrupt Position Configuration Register

    • [0:10]LIPOS (def=0x0) // Line Interrupt Position
  • 0x4001482CCPSR// Current Position Status Register

    • [16:31]CXPOS (def=0x0) // Current X Position
    • [0:15]CYPOS (def=0x0) // Current Y Position
  • 0x40014830CDSR// Current Display Status Register

    • [3]HSYNCS (def=0x1) // Horizontal Synchronization display Status
    • [2]VSYNCS (def=0x1) // Vertical Synchronization display Status
    • [1]HDES (def=0x1) // Horizontal Data Enable display Status
    • [0]VDES (def=0x1) // Vertical Data Enable display Status
  • 0x40014834L1CR// Layerx Control Register

    • [4]CLUTEN (def=0x0) // Color Look-Up Table Enable
    • [1]COLKEN (def=0x0) // Color Keying Enable
    • [0]LEN (def=0x0) // Layer Enable
  • 0x40014838L1WHPCR// Layerx Window Horizontal Position Configuration Register

    • [16:27]WHSPPOS (def=0x0) // Window Horizontal Stop Position
    • [0:11]WHSTPOS (def=0x0) // Window Horizontal Start Position
  • 0x4001483CL1WVPCR// Layerx Window Vertical Position Configuration Register

    • [16:26]WVSPPOS (def=0x0) // Window Vertical Stop Position
    • [0:10]WVSTPOS (def=0x0) // Window Vertical Start Position
  • 0x40014840L1CKCR// Layerx Color Keying Configuration Register

    • [16:23]CKRED (def=0x0) // Color Key Red value
    • [8:15]CKGREEN (def=0x0) // Color Key Green value
    • [0:7]CKBLUE (def=0x0) // Color Key Blue value
  • 0x40014844L1PFCR// Layerx Pixel Format Configuration Register

    • [0:2]PF (def=0x0) // Pixel Format
  • 0x40014848L1CACR// Layerx Constant Alpha Configuration Register

    • [0:7]CONSTA (def=0x0) // Constant Alpha
  • 0x4001484CL1DCCR// Layerx Default Color Configuration Register

    • [24:31]DCALPHA (def=0x0) // Default Color Alpha
    • [16:23]DCRED (def=0x0) // Default Color Red
    • [8:15]DCGREEN (def=0x0) // Default Color Green
    • [0:7]DCBLUE (def=0x0) // Default Color Blue
  • 0x40014850L1BFCR// Layerx Blending Factors Configuration Register

    • [8:10]BF1 (def=0x6) // Blending Factor 1
    • [0:2]BF2 (def=0x7) // Blending Factor 2
  • 0x40014854L1CFBAR// Layerx Color Frame Buffer Address Register

    • [0:31]CFBADD (def=0x0) // Color Frame Buffer Start Address
  • 0x40014858L1CFBLR// Layerx Color Frame Buffer Length Register

    • [16:28]CFBP (def=0x0) // Color Frame Buffer Pitch in bytes
    • [0:12]CFBLL (def=0x0) // Color Frame Buffer Line Length
  • 0x4001485CL1CFBLNR// Layerx ColorFrame Buffer Line Number Register

    • [0:10]CFBLNBR (def=0x0) // Frame Buffer Line Number
  • 0x40014860L1CLUTWR// Layerx CLUT Write Register

    • [24:31]CLUTADD (def=0x0) // CLUT Address
    • [16:23]RED (def=0x0) // Red value
    • [8:15]GREEN (def=0x0) // Green value
    • [0:7]BLUE (def=0x0) // Blue value
  • 0x40014864L2CR// Layerx Control Register

    • [4]CLUTEN (def=0x0) // Color Look-Up Table Enable
    • [1]COLKEN (def=0x0) // Color Keying Enable
    • [0]LEN (def=0x0) // Layer Enable
  • 0x40014868L2WHPCR// Layerx Window Horizontal Position Configuration Register

    • [16:27]WHSPPOS (def=0x0) // Window Horizontal Stop Position
    • [0:11]WHSTPOS (def=0x0) // Window Horizontal Start Position
  • 0x4001486CL2WVPCR// Layerx Window Vertical Position Configuration Register

    • [16:26]WVSPPOS (def=0x0) // Window Vertical Stop Position
    • [0:10]WVSTPOS (def=0x0) // Window Vertical Start Position
  • 0x40014870L2CKCR// Layerx Color Keying Configuration Register

    • [16:23]CKRED (def=0x0) // Color Key Red value
    • [8:15]CKGREEN (def=0x0) // Color Key Green value
    • [0:7]CKBLUE (def=0x0) // Color Key Blue value
  • 0x40014874L2PFCR// Layerx Pixel Format Configuration Register

    • [0:2]PF (def=0x0) // Pixel Format
  • 0x40014878L2CACR// Layerx Constant Alpha Configuration Register

    • [0:7]CONSTA (def=0x0) // Constant Alpha
  • 0x4001487CL2DCCR// Layerx Default Color Configuration Register

    • [24:31]DCALPHA (def=0x0) // Default Color Alpha
    • [16:23]DCRED (def=0x0) // Default Color Red
    • [8:15]DCGREEN (def=0x0) // Default Color Green
    • [0:7]DCBLUE (def=0x0) // Default Color Blue
  • 0x40014880L2BFCR// Layerx Blending Factors Configuration Register

    • [8:10]BF1 (def=0x6) // Blending Factor 1
    • [0:2]BF2 (def=0x7) // Blending Factor 2
  • 0x40014884L2CFBAR// Layerx Color Frame Buffer Address Register

    • [0:31]CFBADD (def=0x0) // Color Frame Buffer Start Address
  • 0x40014888L2CFBLR// Layerx Color Frame Buffer Length Register

    • [16:28]CFBP (def=0x0) // Color Frame Buffer Pitch in bytes
    • [0:12]CFBLL (def=0x0) // Color Frame Buffer Line Length
  • 0x4001488CL2CFBLNR// Layerx ColorFrame Buffer Line Number Register

    • [0:10]CFBLNBR (def=0x0) // Frame Buffer Line Number
  • 0x40014890L2CLUTWR// Layerx CLUT Write Register

    • [24:31]CLUTADD (def=0x0) // CLUT Address
    • [16:23]RED (def=0x0) // Red value
    • [8:15]GREEN (def=0x0) // Green value
    • [0:7]BLUE (def=0x0) // Blue value
  interrupts:
  • [124] LTDC // LCD-TFT global interrupt
• 0x40016800GPHA// GPHA

  • 0x40016800CTLR// GPHA control register

    • [0]START (def=0x0) // Start This bit can be used to launch the GPHA according to the parameters loaded in t
    • [1]SUSP (def=0x0) // Suspend This bit can be used to suspend the current transfer.
    • [2]ABORT (def=0x0) // Abort This bit can be used to abort the current transfer.
    • [9]TCIE (def=0x0) // Transfer complete interrupt enable
    • [10]TWIE (def=0x0) // Transfer watermark interrupt enable
    • [11]CAEIE (def=0x0) // CLUT access error interrupt enable
    • [12]CTCIE (def=0x0) // CLUT transfer complete interrupt enable
    • [13]CEIE (def=0x0) // Configuration Error Interrupt Enable
    • [16:17]MODE (def=0x0) // GPHA mode
  • 0x40016804ISR// GPHA Interrupt Status Register

    • [1]TCIF (def=0x0) // Transfer complete interrupt flag
    • [2]TWIF (def=0x0) // Transfer watermark interrupt flag
    • [3]CAEIF (def=0x0) // CLUT access error interrupt flag
    • [4]CTCIF (def=0x0) // CLUT transfer complete interrupt flag
    • [5]CEIF (def=0x0) // Configuration error interrupt flag
  • 0x40016808IFCR// GPHA interrupt flag clear register

    • [1]CTCIF (def=0x0) // Clear transfer complete interrupt flag Programming
    • [2]CTWIF (def=0x0) // Clear transfer watermark interrupt flag Programming
    • [3]CAECIF (def=0x0) // Clear CLUT access error interrupt flag Programming
    • [4]CCTCIF (def=0x0) // Clear CLUT transfer complete interrupt flag Programming
    • [5]CCEIF (def=0x0) // Clear configuration error interrupt flag Programming
  • 0x4001680CFGMAR// GPHA foreground memory address register

    • [0:31]MA (def=0x0) // Memory address Address of the data used for the foreground image.
  • 0x40016810FGOR// GPHA foreground offset register

    • [0:13]LO (def=0x0) // Line offset Line offset used for the foreground expressed in pixel
  • 0x40016814BGMAR// GPHA background memory address register

    • [0:31]MA (def=0x0) // Memory address Address of the data used for the background image
  • 0x40016818BGOR// GPHA background offset register

    • [0:13]LO (def=0x0) // Line offset Line offset used for the background image (expressed in pixel)
  • 0x4001681CFGPFCCR// GPHA foreground PFC control register

    • [0:3]CM (def=0x0) // Color mode
    • [4]CCM (def=0x0) // CLUT color mode
    • [5]START (def=0x0) // Start This bit can be set to start the automatic loading of the CLUT
    • [8:15]CS (def=0x0) // CLUT size
    • [16:17]AM (def=0x0) // Alpha mode
    • [18:19]CSS (def=0x0) // Chroma Sub-Sampling
    • [20]AI (def=0x0) // Alpha Inverted
    • [21]RBS (def=0x0) // Red Blue Swap
    • [24:31]ALPHA (def=0x0) // Alpha value
  • 0x40016820FGCOLR// GPHA foreground color register

    • [0:7]BLUE (def=0x0) // Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground
    • [8:15]GREEN (def=0x0) // Green Value These bits defines the green value for the A4 or A8 mode of the foregroun
    • [16:23]RED (def=0x0) // Red Value These bits defines the red value for the A4 or A8 mode of the foreground im
  • 0x40016824BGPFCCR// GPHA background PFC control register

    • [0:3]CM (def=0x0) // Color mode
    • [4]CCM (def=0x0) // CLUT Color mode These bits define the color format of the CLUT
    • [5]START (def=0x0) // Start This bit is set to start the automatic loading of the CLUT
    • [8:15]CS (def=0x0) // CLUT size
    • [16:17]AM (def=0x0) // Alpha mode
    • [20]AI (def=0x0) // Alpha Inverted
    • [21]RBS (def=0x0) // Red Blue Swap
    • [24:31]ALPHA (def=0x0) // Alpha value
  • 0x40016828BGCOLR// GPHA background color register

    • [0:7]BLUE (def=0x0) // Blue Value These bits define the blue value for the A4 or A8 mode of the background
    • [8:15]GREEN (def=0x0) // Green Value These bits define the green value for the A4 or A8 mode of the background
    • [16:23]RED (def=0x0) // Red Value These bits define the red value for the A4 or A8 mode of the background
  • 0x4001682CFGCMAR// GPHA foreground CLUT memory address register

    • [0:31]MA (def=0x0) // Memory Address Address of the data used for the CLUT address dedicated to the foregro
  • 0x40016830BGCMAR// GPHA background CLUT memory address register

    • [0:31]MA (def=0x0) // Memory address Address of the data used for the CLUT address dedicated to the backgro
  • 0x40016834OPFCCR// GPHA output PFC control register

    • [0:2]CM (def=0x0) // Color mode These bits define the color format of the output image
    • [20]AI (def=0x0) // Alpha Inverted This bit inverts the alpha value
    • [21]RBS (def=0x0) // Red Blue Swap
  • 0x40016838OCOLR// GPHA output color register

    • [0:7]BLUE (def=0x0) // Blue Value These bits define the blue value of the output image
    • [8:15]GREEN (def=0x0) // Green Value These bits define the green value of the output image
    • [16:23]RED (def=0x0) // Red Value These bits define the red value of the output image
    • [24:31]ALPHA (def=0x0) // Alpha Channel Value These bits define the alpha channel of the output color
  • 0x4001683COMAR// GPHA output memory address register

    • [0:31]MA (def=0x0) // Memory Address Address of the data used for the output FIFO
  • 0x40016840OOR// GPHA output offset register

    • [0:13]LO (def=0x0) // Line Offset Line offset used for the output (expressed in pixels)
  • 0x40016844NLR// GPHA number of line register

    • [0:15]NL (def=0x0) // Number of lines Number of lines of the area to be transferred
    • [16:29]PL (def=0x0) // Pixel per lines Number of pixels per lines of the area to be transferred
  • 0x40016848LWR// GPHA line watermark register

    • [0:15]LW (def=0x0) // Line watermark These bits allow to configure the line watermark for interrupt
  • 0x4001684CAMTCR// GPHA HB master timer configuration register

    • [0]EN (def=0x0) // Enable Enables the dead time functionality.
    • [8:15]DT (def=0x0) // Dead Time Dead time value in the HB clock cycle inserted between two consecutive acce
  • 0x40016850FGCWRS// GPHA foreground layer CLUT read/write setting register

    • [0:7]FG_CLUT_INDEX (def=0x0) // set the address of the lookup table
    • [8]FG_CLUT_EN (def=0x0) // enable CPU read/write lookup table
  • 0x40016854FGCDAT// GPHA foreground layer CLUT read/write data register

    • [0:31]FG_CLUT_DATA (def=0x0) // read data or write SRAM data for lookup table
  • 0x40016858BGCWRS// GPHA background layer CLUT read/write setting register

    • [0:7]BG_CLUT_INDEX (def=0x0) // set the address of the lookup table
    • [8]BG_CLUT_EN (def=0x0) // enable CPU read/write lookup table
  • 0x4001685CBGCDAT// GPHA background layer CLUT read/write data register

    • [0:31]BG_CLUT_DATA (def=0x0) // read data or write SRAM data for lookup table
  interrupts:
  • [125] GPHA // GPHA global interrupt
• 0x40017000DFSDM// Digital filter for sigma delta modulators

  • 0x40017000CH0CFGR1// channel configuration 0 register

    • [31]DFSDMEN (def=0x0) // The DFSDM interface is globally enabled
    • [30]CKOUTSRC (def=0x0) // Output Serial Clock Source Selection
    • [16:23]CKOUTDIV (def=0x0) // Output Serial Clock Divider
    • [14:15]DATPACK (def=0x0) // R32_DFSDM_CHyDATINR register data encapsulation mode
    • [12:13]DATMPX (def=0x0) // Channel 0 Input Data Multiplexer
    • [8]CHINSEL (def=0x0) // Channel Input Selection
    • [7]CHEN (def=0x0) // Channel 0 enables
    • [6]CKABEN (def=0x0) // Channel 0 Clock Missing Detector Enables
    • [5]SCDEN (def=0x0) // Channel 0 Short Circuit Detector Enables
    • [2:3]SPICKSEL (def=0x0) // Channel 0 SPI Clock Selection
    • [0]SITP (def=0x0) // Channel 0 Serial Interface Type
  • 0x40017004CH1CFGR1// channel configuration 1 register

    • [31]DFSDMEN (def=0x0) // The DFSDM interface is globally enabled
    • [30]CKOUTSRC (def=0x0) // Output Serial Clock Source Selection
    • [16:23]CKOUTDIV (def=0x0) // Output Serial Clock Divider
    • [14:15]DATPACK (def=0x0) // R32_DFSDM_CHyDATINR register data encapsulation mode
    • [12:13]DATMPX (def=0x0) // Channel 1 Input Data Multiplexer
    • [8]CHINSEL (def=0x0) // Channel Input Selection
    • [7]CHEN (def=0x0) // Channel 1 enables
    • [6]CKABEN (def=0x0) // Channel 1 Clock Missing Detector Enables
    • [5]SCDEN (def=0x0) // Channel 1 Short Circuit Detector Enables
    • [2:3]SPICKSEL (def=0x0) // Channel 1 SPI Clock Selection
    • [0:1]SITP (def=0x0) // Channel 1 Serial Interface Type
  • 0x40017008CH0CFGR2// channel configuration 0 register

    • [8:31]OFFSET (def=0x0) // Channel 0 24-bit calibration offset
    • [3:7]DTRBS (def=0x0) // Channel 0 data right shift
  • 0x4001700CCH1CFGR2// channel configuration 1 register

    • [8:31]OFFSET (def=0x0) // Channel 1 24-bit calibration offset
    • [3:7]DTRBS (def=0x0) // Channel 1 data right shift
  • 0x40017010CH0AWSCDR// analog watchdog and short-circuit detector register

    • [22:23]AWFORD (def=0x0) // Channel 0 analog watchdog Sinc filter order
    • [16:20]AWFOSR (def=0x0) // Channel 0 analog watchdog filter oversampling rate
    • [12:15]BKSCD (def=0x0) // Channel 0 Short Circuit Detector Open Signal Distribution
    • [0:7]SCDT (def=0x0) // Short Circuit Detector Threshold for Channel 0
  • 0x40017014CH1AWSCDR// analog watchdog and short-circuit detector register

    • [22:23]AWFORD (def=0x0) // Channel 1 analog watchdog Sinc filter order
    • [16:20]AWFOSR (def=0x0) // Channel 1 analog watchdog filter oversampling rate
    • [12:15]BKSCD (def=0x0) // Channel 1 Short Circuit Detector Open Signal Distribution
    • [0:7]SCDT (def=0x0) // Short Circuit Detector Threshold for Channel 1
  • 0x40017018CH0WDATR// channel watchdog filter data register

    • [0:15]WDATA (def=0x0) // Enter channel 0 watchdog data
  • 0x4001701CCH1WDATR// channel watchdog filter data register

    • [0:15]WDATA (def=0x0) // Enter channel 1 watchdog data
  • 0x40017020CH0DATINR// channel data input register

    • [16:31]INDAT1 (def=0x0) // Input data for channel y or channel y+1
    • [0:15]INDAT0 (def=0x0) // Channel Y Input Data
  • 0x40017024CH1DATINR// channel data input register

    • [16:31]INDAT1 (def=0x0) // Input data for channel 1 or channel 2
    • [0:15]INDAT0 (def=0x0) // Channel 1 Input Data
  • 0x40017028DFSDM_FLT0CR1// control register 1

    • [30]AWFSEL (def=0x0) // Analog watchdog fast mode select
    • [29]FAST (def=0x0) // Fast conversion mode selection for regular conversions
    • [24:26]RCH (def=0x0) // Regular channel selection
    • [21]RDMAEN (def=0x0) // DMA channel enabled to read data for the regular conversion
    • [19]RSYNC (def=0x0) // Launch regular conversion synchronously with DFSDM0
    • [18]RCONT (def=0x0) // Continuous mode selection for regular conversions
    • [17]RSWSTART (def=0x0) // Software start of a conversion on the regular channel
    • [13:14]JEXTEN (def=0x0) // Trigger enable and trigger edge selection for injected conversions
    • [8:11]JEXTSEL (def=0x0) // Trigger signal selection for launching injected conversions
    • [5]JDMAEN (def=0x0) // DMA channel enabled to read data for the injected channel group
    • [4]JSCAN (def=0x0) // Scanning conversion mode for injected conversions
    • [3]JSYNC (def=0x0) // Launch an injected conversion synchronously with the DFSDM0 JSWSTART tr
    • [1]JSWSTART (def=0x0) // Start a conversion of the injected group of channels
    • [0]DFEN (def=0x0) // DFSDM enable
  • 0x40017030DFSDM_FLT0CR2// control register 2

    • [16:23]AWDCH (def=0x0) // Analog watchdog channel selection
    • [8:15]EXCH (def=0x0) // Extremes detector channel selection
    • [6]CKABIE (def=0x0) // Clock absence interrupt enable
    • [5]SCDIE (def=0x0) // Short-circuit detector interrupt enable
    • [4]AWDIE (def=0x0) // Analog watchdog interrupt enable
    • [3]ROVRIE (def=0x0) // Regular data overrun interrupt enable
    • [2]JOVRIE (def=0x0) // Injected data overrun interrupt enable
    • [1]REOCIE (def=0x0) // Regular end of conversion interrupt enable
    • [0]JEOCIE (def=0x0) // Injected end of conversion interrupt enable
  • 0x40017038DFSDM_FLT0ISR// interrupt and status register

    • [24:31]SCDF (def=0x0) // short-circuit detector flag
    • [16:23]CKABF (def=0x0) // Clock absence flag
    • [14]RCIP (def=0x0) // Regular conversion in progress status
    • [13]JCIP (def=0x0) // Injected conversion in progress status
    • [4]AWDF (def=0x0) // Analog watchdog
    • [3]ROVRF (def=0x0) // Regular conversion overrun flag
    • [2]JOVRF (def=0x0) // Injected conversion overrun flag
    • [1]REOCF (def=0x0) // End of regular conversion flag
    • [0]JEOCF (def=0x0) // End of injected conversion flag
  • 0x40017040DFSDM_FLT0ICR// interrupt flag clear register

    • [24:31]CLRSCDF (def=0x0) // Clear the short-circuit detector flag
    • [16:23]CLRCKABF (def=0x0) // Clear the clock absence flag
    • [3]CLRROVRF (def=0x0) // Clear the regular conversion overrun flag
    • [2]CLRJOVRF (def=0x0) // Clear the injected conversion overrun flag
  • 0x40017048DFSDM_FLT0JCHGR// injected channel group selection register

    • [0:1]JCHG (def=0x1) // Injected channel group selection
  • 0x40017050DFSDM_FLT0FCR3// control register 3

    • [29:31]FORD (def=0x0) // Sinc Filter Order
    • [16:25]FOSR (def=0x0) // Sinc filter oversampling rate
    • [0:3]IOSR (def=0x0) // The integrator oversampling rate is 2 to the power of IOSR
  • 0x40017058DFSDM_FLT0JDATAR// data register for injected group

    • [8:31]JDATA (def=0x0) // Injected group conversion data
    • [0]JDATACH (def=0x0) // Injected channel most recently converted
  • 0x40017060DFSDM_FLT0RDATAR// data register for the regular channel

    • [8:31]RDATA (def=0x0) // Regular channel conversion data
    • [4]RPEND (def=0x0) // Regular channel pending data
    • [0]RDATACH (def=0x0) // Regular channel most recently converted
  • 0x40017068DFSDM_FLT0AWHTR// analog watchdog high threshold register

    • [8:31]AWHT (def=0x0) // Analog watchdog high threshold
    • [0:3]BKAWH (def=0x0) // Break signal assignment to analog watchdog high threshold event
  • 0x40017070DFSDM_FLT0AWLTR// analog watchdog low threshold register

    • [8:31]AWLT (def=0x0) // Analog watchdog low threshold
    • [0:1]BKAWL (def=0x0) // Break signal assignment to analog watchdog low threshold event
  • 0x40017078DFSDM_FLT0AWSR// analog watchdog status register

    • [8:15]AWHTF (def=0x0) // Analog watchdog high threshold flag
    • [0:7]AWLTF (def=0x0) // Analog watchdog low threshold flag
  • 0x40017080DFSDM_FLT0AWCFR// analog watchdog clear flag register

    • [8:9]CLRAWHTF (def=0x0) // Clear the analog watchdog high threshold flag
    • [0:1]CLRAWLTF (def=0x0) // Clear the analog watchdog low threshold flag
  • 0x40017088DFSDM_FLT0EXMAX// Extremes detector maximum register

    • [8:31]EXMAX (def=0x0) // Extremes detector maximum value
    • [0]EXMAXCH (def=0x0) // Extremes detector maximum data channel
  • 0x40017090DFSDM_FLT0EXMIN// Extremes detector minimum register

    • [8:31]EXMIN (def=0x0) // EXMIN
    • [0]EXMINCH (def=0x0) // Extremes detector minimum data channel
  • 0x40017098DFSDM_FLT0CNVTIMR// conversion timer register

    • [4:31]CNVCNT (def=0x0) // 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
  • 0x4001702CDFSDM_FLT1CR1// control register 1

    • [30]AWFSEL (def=0x0) // Analog watchdog fast mode select
    • [29]FAST (def=0x0) // Fast conversion mode selection for regular conversions
    • [24:26]RCH (def=0x0) // Regular channel selection
    • [21]RDMAEN (def=0x0) // DMA channel enabled to read data for the regular conversion
    • [19]RSYNC (def=0x0) // Launch regular conversion synchronously with DFSDM0
    • [18]RCONT (def=0x0) // Continuous mode selection for regular conversions
    • [17]RSWSTART (def=0x0) // Software start of a conversion on the regular channel
    • [13:14]JEXTEN (def=0x0) // Trigger enable and trigger edge selection for injected conversions
    • [8:11]JEXTSEL (def=0x0) // Trigger signal selection for launching injected conversions
    • [5]JDMAEN (def=0x0) // DMA channel enabled to read data for the injected channel group
    • [4]JSCAN (def=0x0) // Scanning conversion mode for injected conversions
    • [3]JSYNC (def=0x0) // Launch an injected conversion synchronously with the DFSDM0 JSWSTART tr
    • [1]JSWSTART (def=0x0) // Start a conversion of the injected group of channels
    • [0]DFEN (def=0x0) // DFSDM enable
  • 0x40017034DFSDM_FLT1CR2// control register 2

    • [16:23]AWDCH (def=0x0) // Analog watchdog channel selection
    • [8:15]EXCH (def=0x0) // Extremes detector channel selection
    • [6]CKABIE (def=0x0) // Clock absence interrupt enable
    • [5]SCDIE (def=0x0) // Short-circuit detector interrupt enable
    • [4]AWDIE (def=0x0) // Analog watchdog interrupt enable
    • [3]ROVRIE (def=0x0) // Regular data overrun interrupt enable
    • [2]JOVRIE (def=0x0) // Injected data overrun interrupt enable
    • [1]REOCIE (def=0x0) // Regular end of conversion interrupt enable
    • [0]JEOCIE (def=0x0) // Injected end of conversion interrupt enable
  • 0x4001703CDFSDM_FLT1ISR// interrupt and status register

    • [24:31]SCDF (def=0x0) // short-circuit detector flag
    • [16:23]CKABF (def=0x0) // Clock absence flag
    • [14]RCIP (def=0x0) // Regular conversion in progress status
    • [13]JCIP (def=0x0) // Injected conversion in progress status
    • [4]AWDF (def=0x0) // Analog watchdog
    • [3]ROVRF (def=0x0) // Regular conversion overrun flag
    • [2]JOVRF (def=0x0) // Injected conversion overrun flag
    • [1]REOCF (def=0x0) // End of regular conversion flag
    • [0]JEOCF (def=0x0) // End of injected conversion flag
  • 0x40017044DFSDM_FLT1ICR// interrupt flag clear register

    • [24:31]CLRSCDF (def=0x0) // Clear the short-circuit detector flag
    • [16:23]CLRCKABF (def=0x0) // Clear the clock absence flag
    • [3]CLRROVRF (def=0x0) // Clear the regular conversion overrun flag
    • [2]CLRJOVRF (def=0x0) // Clear the injected conversion overrun flag
  • 0x4001704CDFSDM_FLT1JCHGR// injected channel group selection register

    • [0:1]JCHG (def=0x1) // Injected channel group selection
  • 0x40017054DFSDM_FLT1FCR3// control register 3

    • [29:31]FORD (def=0x0) // Sinc Filter Order
    • [16:25]FOSR (def=0x0) // Sinc filter oversampling rate
    • [0:3]IOSR (def=0x0) // The integrator oversampling rate is 2 to the power of IOSR
  • 0x4001705CDFSDM_FLT1JDATAR// data register for injected group

    • [8:31]JDATA (def=0x0) // Injected group conversion data
    • [0]JDATACH (def=0x0) // Injected channel most recently converted
  • 0x40017064DFSDM_FLT1RDATAR// data register for the regular channel

    • [8:31]RDATA (def=0x0) // Regular channel conversion data
    • [4]RPEND (def=0x0) // Regular channel pending data
    • [0]RDATACH (def=0x0) // Regular channel most recently converted
  • 0x4001706CDFSDM_FLT1AWHTR// analog watchdog high threshold register

    • [8:31]AWHT (def=0x0) // Analog watchdog high threshold
    • [0:3]BKAWH (def=0x0) // Break signal assignment to analog watchdog high threshold event
  • 0x40017074DFSDM_FLT1AWLTR// analog watchdog low threshold register

    • [8:31]AWLT (def=0x0) // Analog watchdog low threshold
    • [0:1]BKAWL (def=0x0) // Break signal assignment to analog watchdog low threshold event
  • 0x4001707CDFSDM_FLT1AWSR// analog watchdog status register

    • [8:15]AWHTF (def=0x0) // Analog watchdog high threshold flag
    • [0:7]AWLTF (def=0x0) // Analog watchdog low threshold flag
  • 0x40017084DFSDM_FLT1AWCFR// analog watchdog clear flag register

    • [8:9]CLRAWHTF (def=0x0) // Clear the analog watchdog high threshold flag
    • [0:1]CLRAWLTF (def=0x0) // Clear the analog watchdog low threshold flag
  • 0x4001708CDFSDM_FLT1EXMAX// Extremes detector maximum register

    • [8:31]EXMAX (def=0x0) // Extremes detector maximum value
    • [0]EXMAXCH (def=0x0) // Extremes detector maximum data channel
  • 0x40017094DFSDM_FLT1EXMIN// Extremes detector minimum register

    • [8:31]EXMIN (def=0x0) // EXMIN
    • [0]EXMINCH (def=0x0) // Extremes detector minimum data channel
  • 0x4001709CDFSDM_FLT1CNVTIMR// conversion timer register

    • [4:31]CNVCNT (def=0x0) // 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN
  interrupts:
  • [127] DFSDM0 // DFSDM0 global interrupt
  • [128] DFSDM1 // DFSDM1 global interrupt
• 0x40024C00QSPI1// QSPI1

  • 0x40024C00CR// QSPI control register

    • [0]EN (def=0x0) // Enable Enable the QSPI
    • [1]ABORT (def=0x0) // Abort request This bit aborts the on-going command sequence
    • [2]DMAEN (def=0x0) // DMA mode enabled
    • [3]TCEN (def=0x0) // Timeout counter enable
    • [5]START (def=0x0) // start the FLASH command sequence
    • [6]DFM (def=0x0) // Dual-flash mode This bit activates dual-flash mode
    • [7]FSEL (def=0x0) // Flash memory selection
    • [8:12]FTHRES (def=0x0) // FIFO threshold level Defines
    • [13]SIOXEN (def=0x0) // SIOX enable
    • [16]TEIE (def=0x0) // Transfer error interrupt enable This bit enables the transfer error interrupt.
    • [17]TCIE (def=0x0) // Transfer complete interrupt enable This bit enables the transfer complete
    • [18]FTIE (def=0x0) // FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt.
    • [19]SMIE (def=0x0) // Status match interrupt enable This bit enables the status match interrupt.
    • [20]TOIE (def=0x0) // TimeOut interrupt enable This bit enables the TimeOut interrupt.
    • [22]APMS (def=0x0) // Automatic poll mode stop
    • [23]PMM (def=0x0) // Polling match mode
    • [24:31]PRESCALER (def=0x0) // clock prescaler
  • 0x40024C04DCR// QSPI device configuration register

    • [0]CKMODE (def=0x0) // indicates the level that clk takes between command
    • [8:10]CSHT (def=0x0) // Chip select high time
    • [16:20]FSIZE (def=0x0) // Flash memory size
  • 0x40024C08SR// QSPI status register

    • [0]TEF (def=0x0) // Transfer error flag
    • [1]TCF (def=0x0) // Transfer complete flag
    • [2]FTF (def=0x0) // FIFO threshold flag
    • [3]SMF (def=0x0) // Status match flag
    • [4]TOF (def=0x0) // Timeout flag This bit is set when timeout occurs
    • [5]BUSY (def=0x0) // Busy This bit is set when an operation is on going
    • [8:13]FLEVEL (def=0x0) // FIFO level
  • 0x40024C0CFCR// QSPI flag clear register

    • [0]CTEF (def=0x0) // Clear transfer error flag Writing 1 clears the TEF flag in the QSPI_SR
    • [1]CTCF (def=0x0) // Clear transfer complete flag Writing 1 clears the TCF flag in the QSPI_SR
    • [3]CSMF (def=0x0) // Clear status match flag Writing 1 clears the SMF flag in the QSPI_SR register
    • [4]CTOF (def=0x0) // Clear timeout flag Writing 1 clears the TOF flag in the QSPI_SR register
  • 0x40024C10DLR// QSPI data length register

    • [0:31]DL (def=0x0) // Data length
  • 0x40024C14CCR// QSPI communication configuration register

    • [0:7]INSTRUCTION (def=0x0) // Instruction
    • [8:9]IMODE (def=0x0) // Instruction mode
    • [10:11]ADMODE (def=0x0) // Address mode
    • [12:13]ADSIZE (def=0x0) // Address size
    • [14:15]ABMODE (def=0x0) // Alternate bytes mode
    • [16:17]ABSIZE (def=0x0) // Alternate bytes size
    • [18:22]DCYC (def=0x0) // Number of dummy cycles
    • [24:25]DMODE (def=0x0) // Data mode
    • [26:27]FMODE (def=0x0) // Functional mode
    • [28]SIOO (def=0x0) // Send instruction only once mode
  • 0x40024C18AR// QSPI address register

    • [0:31]ADDRESS (def=0x0) // QSPI Address
  • 0x40024C1CABR// QSPI alternate bytes registers

    • [0:31]ALTERNATE (def=0x0) // Alternate Bytes Optional data to be send to the external SPI device right after the a
  • 0x40024C20DR// QSPI data register

    • [0:31]DATA (def=0x0) // Data
  • 0x40024C24PSMKR// QSPI polling status mask register

    • [0:31]MASK (def=0x0) // Status mask Mask to be applied to the status bytes received in polling mode
  • 0x40024C28PSMAR// QSPI polling status match register

    • [0:31]MATCH (def=0x0) // Status match Value to be compared with the masked status register to get a match. Thi
  • 0x40024C2CPIR// QSPI polling interval register

    • [0:15]INTERVAL (def=0x0) // Polling interval Number of CLK cycles between to read during automatic polling phases
  • 0x40024C30LPTR// QSPI low-power timeout register

    • [0:15]TIMEOUT (def=0x0) // Timeout
  interrupts:
  • [82] QSPI1 // QSPI1 global interrupt
• 0x40025000QSPI2//

  • 0x40025000CR// QSPI control register

    • [0]EN (def=0x0) // Enable Enable the QSPI
    • [1]ABORT (def=0x0) // Abort request This bit aborts the on-going command sequence
    • [2]DMAEN (def=0x0) // DMA mode enabled
    • [3]TCEN (def=0x0) // Timeout counter enable
    • [5]START (def=0x0) // start the FLASH command sequence
    • [6]DFM (def=0x0) // Dual-flash mode This bit activates dual-flash mode
    • [7]FSEL (def=0x0) // Flash memory selection
    • [8:12]FTHRES (def=0x0) // FIFO threshold level Defines
    • [13]SIOXEN (def=0x0) // SIOX enable
    • [16]TEIE (def=0x0) // Transfer error interrupt enable This bit enables the transfer error interrupt.
    • [17]TCIE (def=0x0) // Transfer complete interrupt enable This bit enables the transfer complete
    • [18]FTIE (def=0x0) // FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt.
    • [19]SMIE (def=0x0) // Status match interrupt enable This bit enables the status match interrupt.
    • [20]TOIE (def=0x0) // TimeOut interrupt enable This bit enables the TimeOut interrupt.
    • [22]APMS (def=0x0) // Automatic poll mode stop
    • [23]PMM (def=0x0) // Polling match mode
    • [24:31]PRESCALER (def=0x0) // clock prescaler
  • 0x40025004DCR// QSPI device configuration register

    • [0]CKMODE (def=0x0) // indicates the level that clk takes between command
    • [8:10]CSHT (def=0x0) // Chip select high time
    • [16:20]FSIZE (def=0x0) // Flash memory size
  • 0x40025008SR// QSPI status register

    • [0]TEF (def=0x0) // Transfer error flag
    • [1]TCF (def=0x0) // Transfer complete flag
    • [2]FTF (def=0x0) // FIFO threshold flag
    • [3]SMF (def=0x0) // Status match flag
    • [4]TOF (def=0x0) // Timeout flag This bit is set when timeout occurs
    • [5]BUSY (def=0x0) // Busy This bit is set when an operation is on going
    • [8:13]FLEVEL (def=0x0) // FIFO level
  • 0x4002500CFCR// QSPI flag clear register

    • [0]CTEF (def=0x0) // Clear transfer error flag Writing 1 clears the TEF flag in the QSPI_SR
    • [1]CTCF (def=0x0) // Clear transfer complete flag Writing 1 clears the TCF flag in the QSPI_SR
    • [3]CSMF (def=0x0) // Clear status match flag Writing 1 clears the SMF flag in the QSPI_SR register
    • [4]CTOF (def=0x0) // Clear timeout flag Writing 1 clears the TOF flag in the QSPI_SR register
  • 0x40025010DLR// QSPI data length register

    • [0:31]DL (def=0x0) // Data length
  • 0x40025014CCR// QSPI communication configuration register

    • [0:7]INSTRUCTION (def=0x0) // Instruction
    • [8:9]IMODE (def=0x0) // Instruction mode
    • [10:11]ADMODE (def=0x0) // Address mode
    • [12:13]ADSIZE (def=0x0) // Address size
    • [14:15]ABMODE (def=0x0) // Alternate bytes mode
    • [16:17]ABSIZE (def=0x0) // Alternate bytes size
    • [18:22]DCYC (def=0x0) // Number of dummy cycles
    • [24:25]DMODE (def=0x0) // Data mode
    • [26:27]FMODE (def=0x0) // Functional mode
    • [28]SIOO (def=0x0) // Send instruction only once mode
  • 0x40025018AR// QSPI address register

    • [0:31]ADDRESS (def=0x0) // QSPI Address
  • 0x4002501CABR// QSPI alternate bytes registers

    • [0:31]ALTERNATE (def=0x0) // Alternate Bytes Optional data to be send to the external SPI device right after the a
  • 0x40025020DR// QSPI data register

    • [0:31]DATA (def=0x0) // Data
  • 0x40025024PSMKR// QSPI polling status mask register

    • [0:31]MASK (def=0x0) // Status mask Mask to be applied to the status bytes received in polling mode
  • 0x40025028PSMAR// QSPI polling status match register

    • [0:31]MATCH (def=0x0) // Status match Value to be compared with the masked status register to get a match. Thi
  • 0x4002502CPIR// QSPI polling interval register

    • [0:15]INTERVAL (def=0x0) // Polling interval Number of CLK cycles between to read during automatic polling phases
  • 0x40025030LPTR// QSPI low-power timeout register

    • [0:15]TIMEOUT (def=0x0) // Timeout
  interrupts:
  • [134] QSPI2 // QSPI2 global interrupt
• 0x40008400SWPMI// Single Wire Protocol Master Interface

  • 0x40008400CR// SWPMI Configuration/Control register

    • [0]RXDMA (def=0x0) // Reception DMA enable
    • [1]TXDMA (def=0x0) // Transmission DMA enable
    • [2]RXMODE (def=0x0) // Reception buffering mode
    • [3]TXMODE (def=0x0) // Transmission buffering mode
    • [4]LPBK (def=0x0) // Loopback mode enable
    • [5]SWPACT (def=0x0) // Single wire protocol master interface activate
    • [10]DEACT (def=0x0) // Single wire protocol master interface deactivate
    • [11]SWPTEN (def=0x0) // Single wire protocol master transceiver enable
  • 0x40008404BRR// SWPMI Bitrate register

    • [0:7]BR (def=0x1) // Bitrate prescaler
  • 0x4000840CISR// SWPMI Interrupt and Status register

    • [0]RXBFF (def=0x0) // Receive buffer full flag
    • [1]TXBEF (def=0x1) // Transmit buffer empty flag
    • [2]RXBERF (def=0x0) // Receive CRC error flag
    • [3]RXOVRF (def=0x0) // Receive overrun error flag
    • [4]TXUNRF (def=0x0) // Transmit underrun error flag
    • [5]RXNE (def=0x0) // Receive data register not empty
    • [6]TXE (def=0x1) // Transmit data register empty
    • [7]TCF (def=0x1) // Transfer complete flag
    • [8]SRF (def=0x0) // Slave resume flag
    • [9]SUSP (def=0x1) // SUSPEND flag
    • [10]DEACTF (def=0x0) // DEACTIVATED flag
    • [11]RDYF (def=0x0) // transceiver ready flag
  • 0x40008410ICR// SWPMI Interrupt Flag Clear register

    • [0]CRXBFF (def=0x0) // Clear receive buffer full flag
    • [1]CTXBEF (def=0x0) // Clear transmit buffer empty flag
    • [2]CRXBERF (def=0x0) // Clear receive CRC error flag
    • [3]CRXOVRF (def=0x0) // Clear receive overrun error flag
    • [4]CTXUNRF (def=0x0) // Clear transmit underrun error flag
    • [7]CTCF (def=0x0) // Clear transfer complete flag
    • [8]CSRF (def=0x0) // Clear slave resume flag
    • [11]CRDYF (def=0x0) // Clear transceiver ready flag
  • 0x40008414IER// SWPMI Interrupt Enable register

    • [0]RXBFIE (def=0x0) // Receive buffer full interrupt enable
    • [1]TXBEIE (def=0x0) // Transmit buffer empty interrupt enable
    • [2]RXBERIE (def=0x0) // Receive CRC error interrupt enable
    • [3]RXOVRIE (def=0x0) // Receive overrun error interrupt enable
    • [4]TXUNRIE (def=0x0) // Transmit underrun error interrupt enable
    • [5]RIE (def=0x0) // Receive interrupt enable
    • [6]TIE (def=0x0) // Transmit interrupt enable
    • [7]TCIE (def=0x0) // Transmit complete interrupt enable
    • [8]SRIE (def=0x0) // Slave resume interrupt enable
    • [11]RDYIE (def=0x0) // Transceiver ready interrupt enable
  • 0x40008418RFL// SWPMI Receive Frame Length register

    • [0:4]RFL (def=0x0) // Receive frame length
  • 0x4000841CTDR// SWPMI Transmit data register

    • [0:31]TD (def=0x0) // Transmit data
  • 0x40008420RDR// SWPMI Receive data register

    • [0:31]RD (def=0x0) // received data
  • 0x40008424OR// SWPMI Option register

    • [0]SWP_TBYP (def=0x0) // SWP transceiver bypass
    • [2:3]SWP_ISEL (def=0x0) // SWP current selection
  interrupts:
  • [131] SWPMI // SWPMI global interrupt
  • [135] SWPMIWakeUP // SWPMI wake-up interrupt
• 0x40015800SAI// SAI

  • 0x40015804SAI_ACFGR1// Configuration register 1

    • [0:1]MODE (def=0x0) // SAIx audio block mode immediately
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [5:7]DS (def=0x2) // Data size
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [12]MONO (def=0x0) // Mono mode
    • [13]OUTDRIV (def=0x0) // Output drive
    • [16]SAIXEN (def=0x0) // Audio block enable
    • [17]DMAEN (def=0x0) // DMA enable
    • [19]NOMCK (def=0x0) // No divider
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [26]OSR (def=0x0) // Oversampling ratio for master clock
  • 0x40015808SAI_ACFGR2// Configuration register 2

    • [0:2]FTH (def=0x0) // FIFO threshold
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [5]MUTE (def=0x0) // Mute mode enable
    • [6]MUTEVAL (def=0x0) // Mute value
    • [7:12]MUTECNT (def=0x0) // Mute counter
    • [13]CPL (def=0x0) // Complement bit
    • [14:15]COMP (def=0x0) // Companding mode
  • 0x4001580CSAI_AFRCR// This register has no meaning in AC97 and SPDIF audio protocol

    • [0:7]FRL (def=0x7) // Frame length
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [18]FSOFF (def=0x0) // Frame synchronization offset
  • 0x40015810SAI_ASLOTR// This register has no meaning in AC97 and SPDIF audio protocol

    • [0:4]FBOFF (def=0x0) // First bit offset
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [16:31]SLOTEN (def=0x0) // Slot enable
  • 0x40015814SAI_AINTENR// Interrupt mask register 2

    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable (AC97).
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
  • 0x40015818SAI_ASR// Status register

    • [0]OVRUDR (def=0x0) // Overrun/underrun error flag
    • [1]MUTEDET (def=0x0) // Mute detection flag
    • [2]WCKCFG (def=0x0) // Wrong clock configuration error flag
    • [3]FREQ (def=0x1) // FIFO request flag
    • [4]CNRDY (def=0x0) // Codec not ready
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [16:18]FLVL (def=0x0) // FIFO level threshold
  • 0x40015820SAI_ADATAR// Data register

    • [0:31]DATA (def=0x0) // Data
  • 0x40015824SAI_BCFGR1// Configuration register 1

    • [0:1]MODE (def=0x0) // SAIx audio block mode immediately
    • [2:3]PRTCFG (def=0x0) // Protocol configuration
    • [5:7]DS (def=0x2) // Data size
    • [8]LSBFIRST (def=0x0) // Least significant bit first
    • [9]CKSTR (def=0x0) // Clock strobing edge
    • [10:11]SYNCEN (def=0x0) // Synchronization enable
    • [12]MONO (def=0x0) // Mono mode
    • [13]OUTDRIV (def=0x0) // Output drive
    • [16]SAIXEN (def=0x0) // Audio block enable
    • [17]DMAEN (def=0x0) // DMA enable
    • [19]NOMCK (def=0x0) // No divider
    • [20:25]MCKDIV (def=0x0) // Master clock divider
    • [26]OSR (def=0x0) // Oversampling ratio for master clock
  • 0x40015828SAI_BCFGR2// Configuration register 2

    • [0:2]FTH (def=0x0) // FIFO threshold
    • [3]FFLUSH (def=0x0) // FIFO flush
    • [4]TRIS (def=0x0) // Tristate management on data line
    • [5]MUTE (def=0x0) // Mute mode enable
    • [6]MUTEVAL (def=0x0) // Mute value
    • [7:12]MUTECNT (def=0x0) // Mute counter
    • [13]CPL (def=0x0) // Complement bit
    • [14:15]COMP (def=0x0) // Companding mode
  • 0x4001582CSAI_BFRCR// This register has no meaning in AC97 and SPDIF audio protocol

    • [0:7]FRL (def=0x7) // Frame length
    • [8:14]FSALL (def=0x0) // Frame synchronization active level length
    • [16]FSDEF (def=0x0) // Frame synchronization definition
    • [17]FSPOL (def=0x0) // Frame synchronization polarity
    • [18]FSOFF (def=0x0) // Frame synchronization offset
  • 0x40015830SAI_BSLOTR// This register has no meaning in AC97 and SPDIF audio protocol

    • [0:4]FBOFF (def=0x0) // First bit offset
    • [6:7]SLOTSZ (def=0x0) // Slot size
    • [8:11]NBSLOT (def=0x0) // Number of slots in an audio frame
    • [16:31]SLOTEN (def=0x0) // Slot enable
  • 0x40015834SAI_BINTENR// Interrupt mask register 2

    • [0]OVRUDRIE (def=0x0) // Overrun/underrun interrupt enable
    • [1]MUTEDETIE (def=0x0) // Mute detection interrupt enable
    • [2]WCKCFGIE (def=0x0) // Wrong clock configuration interrupt enable
    • [3]FREQIE (def=0x0) // FIFO request interrupt enable
    • [4]CNRDYIE (def=0x0) // Codec not ready interrupt enable (AC97).
    • [5]AFSDETIE (def=0x0) // Anticipated frame synchronization detection interrupt enable
    • [6]LFSDETIE (def=0x0) // Late frame synchronization detection interrupt enable
  • 0x40015838SAI_BSR// Status register

    • [0]OVRUDR (def=0x0) // Overrun/underrun error flag
    • [1]MUTEDET (def=0x0) // Mute detection flag
    • [2]WCKCFG (def=0x0) // Wrong clock configuration error flag
    • [3]FREQ (def=0x1) // FIFO request flag
    • [4]CNRDY (def=0x0) // Codec not ready
    • [5]AFSDET (def=0x0) // Anticipated frame synchronization detection
    • [6]LFSDET (def=0x0) // Late frame synchronization detection
    • [16:18]FLVL (def=0x0) // FIFO level threshold
  • 0x40015840SAI_BDATAR// Data register

    • [0:31]DATA (def=0x0) // Data
  interrupts:
  • [123] SAI // SAI global interrupt
• 0x40025400FMC// FMC

  • 0x40025400BCR1// This register contains the control information of each memory bank, used for SRAMs, PSRAM

    • [0]MBKEN (def=0x0) // Memory bank enable
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width Defines the external memory device width, valid for all type of
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable
    • [24:25]BMP (def=0x0) // FMC bank mapping
    • [31]FMC_EN (def=0x0) // FMC controller Enable
  • 0x40025404BTR1// This register contains the control information of each memory bank, used for SRAMs, PSRAM

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory For synchronous access with read write burst mode
    • [28:29]ACCMOD (def=0x0) // Access mode
  • 0x40025408BCR2// This register contains the control information of each memory bank, used for SRAMs, PSRAM

    • [0]MBKEN (def=0x0) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width Defines the external memory device width, valid for all type of
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable For PSRAM (CRAM) operating in Burst mode
    • [24:25]BMP (def=0x0) // FMC bank mapping
    • [31]FMC_EN (def=0x0) // FMC controller Enable
  • 0x4002540CBTR2// This register contains the control information of each memory bank, used for SRAMs, PSRAM

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory For synchronous access with read write burst mode
    • [28:29]ACCMOD (def=0x0) // Access mode
  • 0x40025410BCR3// This register contains the control information of each memory bank, used for SRAMs, PSRAM

    • [0]MBKEN (def=0x0) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width Defines the external memory device width, valid for all type of
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable For PSRAM (CRAM) operating in Burst mode
    • [24:25]BMP (def=0x0) // FMC bank mapping
    • [31]FMC_EN (def=0x0) // FMC controller Enable
  • 0x40025414BTR3// This register contains the control information of each memory bank, used for SRAMs, PSRAM

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory For synchronous access with read write burst mode
    • [28:29]ACCMOD (def=0x0) // Access mode
  • 0x40025418BCR4// This register contains the control information of each memory bank, used for SRAMs, PSRAM

    • [0]MBKEN (def=0x0) // Memory bank enable bit
    • [1]MUXEN (def=0x1) // Address/data multiplexing enable bit
    • [2:3]MTYP (def=0x0) // Memory type
    • [4:5]MWID (def=0x1) // Memory data bus width Defines the external memory device width, valid for all type of
    • [6]FACCEN (def=0x1) // Flash access enable
    • [8]BURSTEN (def=0x0) // Burst enable bit
    • [9]WAITPOL (def=0x0) // Wait signal polarity bit
    • [11]WAITCFG (def=0x0) // Wait timing configuration
    • [12]WREN (def=0x1) // Write enable bit
    • [13]WAITEN (def=0x1) // Wait enable bit
    • [14]EXTMOD (def=0x0) // Extended mode enable
    • [15]ASYNCWAIT (def=0x0) // Wait signal during asynchronous transfers
    • [16:18]CPSIZE (def=0x0) // CRAM Page Size
    • [19]CBURSTRW (def=0x0) // Write burst enable For PSRAM (CRAM) operating in Burst mode
    • [24:25]BMP (def=0x0) // FMC bank mapping
    • [31]FMC_EN (def=0x0) // FMC controller Enable
  • 0x4002541CBTR4// This register contains the control information of each memory bank, used for SRAMs, PSRAM

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [20:23]CLKDIV (def=0xF) // Clock divide ratio (for FMC_CLK signal)
    • [24:27]DATLAT (def=0xF) // Data latency for synchronous memory For synchronous access with read write burst mode
    • [28:29]ACCMOD (def=0x0) // Access mode
  • 0x40025480PCR// NAND Flash control registers

    • [1]PWAITEN (def=0x0) // Wait feature enable bit
    • [2]PBKEN (def=0x0) // NAND Flash memory bank enable bit
    • [3]PTYP (def=0x1) // memory type
    • [4:5]PWID (def=0x1) // Data bus width
    • [6]ECCEN (def=0x0) // ECC computation logic enable bit
    • [9:12]TCLR (def=0x0) // CLE to RE delay
    • [13:16]TAR (def=0x0) // ALE to RE delay
    • [17:19]ECCPS (def=0x0) // ECC page size
  • 0x40025484SR// This register contains information about the FIFO status and interrupt

    • [0]IRS (def=0x0) // Interrupt rising edge status
    • [1]ILS (def=0x0) // Interrupt high-level status
    • [2]IFS (def=0x0) // Interrupt falling edge status
    • [3]IREN (def=0x0) // Interrupt rising edge detection enable bit
    • [4]ILEN (def=0x0) // Interrupt high-level detection enable bit
    • [5]IFEN (def=0x0) // Interrupt falling edge detection enable bit
    • [6]FEMPT (def=0x1) // FIFO empty
  • 0x40025488PMEM// The FMC_PMEM read/write register contains the timing information for NAND Flash memory ba

    • [0:7]MEMSET (def=0xFC) // Common memory x setup time
    • [8:15]MEMWAIT (def=0xFC) // Common memory wait time
    • [16:23]MEMHOLD (def=0xFC) // Common memory hold time
    • [24:31]MEMHIZ (def=0xFC) // Common memory x data bus Hi-Z time
  • 0x4002548CPATT// The FMC_PATT read/write register contains the timing information for NAND Flash memory ba

    • [0:7]ATTSET (def=0xFC) // Attribute memory setup time
    • [8:15]ATTWAIT (def=0xFC) // Attribute memory wait time
    • [16:23]ATTHOLD (def=0xFC) // Attribute memory hold time
    • [24:31]ATTHIZ (def=0xFC) // Attribute memory data bus Hi-Z time
  • 0x40025494ECCR// This register contain the current error correction code value computed by the ECC computa

    • [0:31]ECC (def=0x0) // ECC result This field contains the value computed by the ECC computation logic. Table
  • 0x40025504BWTR1// This register contains the control information of each memory bank. It is used for SRAMs,

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
  • 0x4002550CBWTR2// This register contains the control information of each memory bank. It is used for SRAMs,

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
  • 0x40025514BWTR3// This register contains the control information of each memory bank. It is used for SRAMs,

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
  • 0x4002551CBWTR4// This register contains the control information of each memory bank. It is used for SRAMs,

    • [0:3]ADDSET (def=0xF) // Address setup phase duration
    • [4:7]ADDHLD (def=0xF) // Address-hold phase duration
    • [8:15]DATAST (def=0xFF) // Data-phase duration
    • [16:19]BUSTURN (def=0xF) // Bus turnaround phase duration
    • [28:29]ACCMOD (def=0x0) // Access mode
  • 0x40025540SDCR1// This register contains the control parameters for each SDRAM memory bank

    • [0:1]NC (def=0x0) // Number of column address bits These bits define the number of bits of a column
    • [2:3]NR (def=0x0) // Number of row address bits These bits define the number of bits of a row
    • [4:5]MWID (def=0x1) // Memory data bus width. These bits define the memory device width.
    • [6]NB (def=0x1) // Number of internal banks This bit sets the number of internal banks.
    • [7:8]CAS (def=0x1) // CAS Latency This bits sets the SDRAM CAS latency in number of memory clock
    • [9]WP (def=0x1) // Write protection This bit enables write mode access to the SDRAM bank.
    • [10:11]SDCLK (def=0x0) // SDRAM clock configuration
    • [12]RBURST (def=0x0) // Burst read
    • [13:14]RPIPE (def=0x0) // Read pipe
  • 0x40025544SDCR2// This register contains the control parameters for each SDRAM memory bank

    • [0:1]NC (def=0x0) // Number of column address bits These bits define the number of bits of a column
    • [2:3]NR (def=0x0) // Number of row address bits These bits define the number of bits of a row
    • [4:5]MWID (def=0x1) // Memory data bus width. These bits define the memory device width.
    • [6]NB (def=0x1) // Number of internal banks This bit sets the number of internal banks.
    • [7:8]CAS (def=0x1) // CAS Latency This bits sets the SDRAM CAS latency in number of memory clock
    • [9]WP (def=0x1) // Write protection This bit enables write mode access to the SDRAM bank.
    • [10:11]SDCLK (def=0x0) // SDRAM clock configuration
    • [12]RBURST (def=0x0) // Burst read
    • [13:14]RPIPE (def=0x0) // Read pipe
  • 0x40025548SDTR1// This register contains the timing parameters of each SDRAM bank

    • [0:3]TMRD (def=0xF) // Load Mode Register to Active
    • [4:7]TXSR (def=0xF) // Exit Self-refresh delay
    • [8:11]TRAS (def=0xF) // Self refresh time
    • [12:15]TRC (def=0xF) // Row cycle delay
    • [16:19]TWR (def=0xF) // Recovery delay
    • [20:23]TRP (def=0xF) // Row precharge delay
    • [24:27]TRCD (def=0xF) // Row to column delay
  • 0x4002554CSDTR2// This register contains the timing parameters of each SDRAM bank

    • [0:3]TMRD (def=0xF) // Load Mode Register to Active
    • [4:7]TXSR (def=0xF) // Exit Self-refresh delay
    • [8:11]TRAS (def=0xF) // Self refresh time
    • [12:15]TRC (def=0xF) // Row cycle delay
    • [16:19]TWR (def=0xF) // Recovery delay
    • [20:23]TRP (def=0xF) // Row precharge delay
    • [24:27]TRCD (def=0xF) // Row to column delay
  • 0x40025550SDCMR// This register contains the command issued when the SDRAM device is accessed

    • [0:2]MODE (def=0x0) // Command mode These bits define the command issued to the SDRAM device.
    • [3]CTB2 (def=0x0) // Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM
    • [4]CTB1 (def=0x0) // Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM
    • [5:8]NRFS (def=0x0) // Number of Auto-refresh
    • [9:22]MRD (def=0x0) // Mode Register definition
  • 0x40025554SDRTR// This register sets the refresh rate in number of SDCLK clock cycles between the refresh c

    • [0]CRE (def=0x0) // Clear Refresh error flag
    • [1:13]COUNT (def=0x0) // Refresh Timer Count
    • [14]REIE (def=0x0) // RES Interrupt Enable
  • 0x40025558SDSR// SDRAM Status register

    • [0]RE (def=0x0) // Refresh error flag An interrupt is generated if REIE = 1 and RE = 1
    • [1:2]MODES1 (def=0x0) // Status Mode for Bank 1 These bits define the Status Mode of SDRAM Bank 1.
    • [3:4]MODES2 (def=0x0) // Status Mode for Bank 2 These bits define the Status Mode of SDRAM Bank 2.
    • [5]BUSY (def=0x0) // BUSY
  • 0x40025580MISC// SDRAM custom registers

    • [0:3]NRFS_CNT (def=0x0) // Define the number of times the controller self-refreshes each time
    • [4:7]Phase_Sel (def=0x0) // Phase offset of the output SDR_CLK
    • [15]Enhance_read_mode (def=0x0) // Read enhancement/prefetch mode
    • [16]En_Bank1 (def=0x0) // Enable SDRAM1
    • [17]En_Bank2 (def=0x0) // Enable SDRAM2
  interrupts:
  • [94] FMC // FMC global interrupt
• 0x40028000ETHERNET_MAC// Ethernet: media access control

  • 0x40028000MACCR// Ethernet MAC configuration register (ETH_MACCR)

    • [1]TCF (def=0x0) // Send clock reversal
    • [2]RE (def=0x0) // Receiver enable
    • [3]TE (def=0x0) // Transmitter enable
    • [7]APCS (def=0x0) // Automatic pad/CRC stripping
    • [10]IPCO (def=0x0) // IPv4 checksum offload
    • [11]DM (def=0x0) // Duplex mode
    • [12]LM (def=0x0) // Loopback mode
    • [14:15]FES (def=0x0) // Fast Ethernet speed
    • [17:19]IFG (def=0x0) // Interframe gap
    • [22]JD (def=0x0) // Jabber disable
    • [23]WD (def=0x0) // Watchdog disable
    • [29:31]TCD (def=0x0) // SEND clock delay
  • 0x40028004MACFFR// Ethernet MAC frame filter register (ETH_MACCFFR)

    • [0]PM (def=0x0) // Promiscuous mode
    • [1]HU (def=0x0) // Hash unicast
    • [2]HM (def=0x0) // Hash multicast
    • [3]DAIF (def=0x0) // Destination address inverse filtering
    • [4]PAM (def=0x0) // Pass all multicast
    • [5]BFD (def=0x0) // Broadcast frames disable
    • [6:7]PCF (def=0x0) // Pass control frames
    • [8]SAIF (def=0x0) // Source address inverse filtering
    • [9]SAF (def=0x0) // Source address filter
    • [10]HPF (def=0x0) // Hash or perfect filter
    • [31]RA (def=0x0) // Receive all
  • 0x40028008MACHTHR// Ethernet MAC hash table high register

    • [0:31]HTH (def=0x0) // Hash table high
  • 0x4002800CMACHTLR// Ethernet MAC hash table low register

    • [0:31]HTL (def=0x0) // Hash table low
  • 0x40028010MACMIIAR// Ethernet MAC MII address register (ETH_MACMIIAR)

    • [0]MB (def=0x0) // MII busy
    • [1]MW (def=0x0) // MII write
    • [2:4]CR (def=0x0) // Clock range
    • [6:10]MR (def=0x0) // MII register
    • [11:15]PA (def=0x0) // PHY address
  • 0x40028014MACMIIDR// Ethernet MAC MII data register (ETH_MACMIIDR)

    • [0:15]MD (def=0x0) // MII data
  • 0x40028018MACFCR// Ethernet MAC flow control register (ETH_MACFCR)

    • [0]FCB (def=0x0) // Flow control busy
    • [1]TFCE (def=0x0) // Transmit flow control enable
    • [2]RFCE (def=0x0) // Receive flow control enable
    • [3]UPFD (def=0x0) // Unicast pause frame detect
    • [16:31]PT (def=0x0) // Pass control frames
  • 0x4002801CMACVLAN// Ethernet MAC VLAN tag register (ETH_MACVLAN)

    • [0:15]VLANTI (def=0x0) // VLAN tag identifier (for receive frames)
    • [16]VLANT (def=0x0) // VLAN tag comparison
  • 0x40028028MACRWUFFR// Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)

    • [0:31]RWUFFR (def=0x0) // wakeup frame filter
  • 0x4002802CMACPMTCSR// Ethernet MAC PMT control and status register (ETH_MACPMTCSR)

    • [0]PD (def=0x0) // Power down
    • [1]MPE (def=0x0) // Magic Packet enable
    • [2]WFE (def=0x0) // Wakeup frame enable
    • [3]PHY_PMEB_EN (def=0x0) // PHY_PMEB enable
    • [5]MPR (def=0x0) // Magic packet received
    • [6]WFR (def=0x0) // Wakeup frame received
    • [7]PHY_PMEBR (def=0x0) // PHY_PMEB reset
    • [9]GU (def=0x0) // Global unicast
    • [31]WFFRPR (def=0x0) // Wakeup frame filter register pointer reset
  • 0x40028038MACSR// Ethernet MAC interrupt status register (ETH_MACSR)

    • [3]PMTS (def=0x0) // PMT status
    • [4]MMCS (def=0x0) // MMC status
    • [5]MMCRS (def=0x0) // MMC receive status
    • [6]MMCTS (def=0x0) // MMC transmit status
    • [9]TSTS (def=0x0) // Time stamp trigger status
  • 0x4002803CMACIMR// Ethernet MAC interrupt mask register (ETH_MACIMR)

    • [3]PMTIM (def=0x0) // PMT interrupt mask
    • [9]TSTIM (def=0x0) // Time stamp trigger interrupt mask
  • 0x40028040MACA0HR// Ethernet MAC address 0 high register (ETH_MACA0HR)

    • [0:15]MACA0H (def=0xFFFF) // MAC address0 high
    • [31]MO (def=0x1) // Always 1
  • 0x40028044MACA0LR// Ethernet MAC address 0 low register

    • [0:31]MACA0L (def=0xFFFFFFFF) // MAC address0 low
  • 0x40028048MACA1HR// Ethernet MAC address 1 high register (ETH_MACA1HR)

    • [0:15]MACA1H (def=0xFFFF) // MAC address1 high
    • [24:29]MBC (def=0x0) // Mask byte control
    • [30]SA (def=0x0) // Source address
    • [31]AE (def=0x0) // Address enable
  • 0x4002804CMACA1LR// Ethernet MAC address1 low register

    • [0:31]MACA1L (def=0xFFFFFFFF) // MAC address1 low
  • 0x40028050MACA2HR// Ethernet MAC address 2 high register (ETH_MACA2HR)

    • [0:15]ETH_MACA2HR (def=0xFFFF) // Ethernet MAC address 2 high register
    • [24:29]MBC (def=0x0) // Mask byte control
    • [30]SA (def=0x0) // Source address
    • [31]AE (def=0x0) // Address enable
  • 0x40028054MACA2LR// Ethernet MAC address 2 low register

    • [0:31]MACA2L (def=0xFFFFFFFF) // MAC address2 low
  • 0x40028058MACA3HR// Ethernet MAC address 3 high register (ETH_MACA3HR)

    • [0:15]MACA3H (def=0xFFFF) // MAC address3 high
    • [24:29]MBC (def=0x0) // Mask byte control
    • [30]SA (def=0x0) // Source address
    • [31]AE (def=0x0) // Address enable
  • 0x4002805CMACA3LR// Ethernet MAC address 3 low register

    • [0:31]MBCA3L (def=0xFFFFFFFF) // MAC address3 low
  • 0x40028080ETH_PHY_CFGR// ETH PHY configure register

    • [31]PHY_RSTN (def=0x0) // ETH PHY global reset control
    • [30]PHY_PD (def=0x0) // PHY power-down mode
    • [29]PHY_EEE (def=0x0) // PHY enters power-down mode
    • [10]DUPlEX (def=0x0) // connected mode
    • [9]SPEED (def=0x0) // speed selection
    • [8]LINK_STATUS (def=0x0) // LINK status
    • [7]PHYADDR_EN (def=0x0) // reconfigure the PHY address
    • [0:4]REPHYADDR (def=0x0) // when the bit7 set 1,bit4:0 as PHY address
  interrupts:
  • [110] ETH // Ethernet global interrupt
  • [111] ETHWakeUP // Ethernet Wakeup interrupt
• 0x40028100ETHERNET_MMC// Ethernet: MAC management counters

  • 0x40028100MMCCR// Ethernet MMC control register (ETH_MMCCR)

    • [0]CR (def=0x0) // Counter reset
    • [1]CSR (def=0x0) // Counter stop rollover
    • [2]ROR (def=0x0) // Reset on read
    • [31]MCF (def=0x0) // MMC counter freeze
  • 0x40028104MMCRIR// Ethernet MMC receive interrupt register (ETH_MMCRIR)

    • [5]RFCES (def=0x0) // Received frames CRC error status
    • [17]RGUFS (def=0x0) // Received Good Unicast Frames Status
  • 0x40028108MMCTIR// Ethernet MMC transmit interrupt register (ETH_MMCTIR)

    • [21]TGFS (def=0x0) // Transmitted good frames status
  • 0x4002810CMMCRIMR// Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)

    • [5]RFCEM (def=0x0) // Received frame CRC error mask
    • [17]RGUFM (def=0x0) // Received good unicast frames mask
  • 0x40028110MMCTIMR// Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)

    • [21]TGFM (def=0x0) // Transmitted good frames mask
  • 0x4002814CMMCTGFSCCR// Ethernet MMC transmitted good frames after a single collision counter

    • [0:31]TGFSCC (def=0x0) // Transmitted good frames after a single collision counter
  • 0x40028150MMCTGFMSCCR// Ethernet MMC transmitted good frames after more than a single collision

    • [0:31]TGFMSCC (def=0x0) // Transmitted good frames after more than a single collision counter
  • 0x40028168MMCTGFCR// Ethernet MMC transmitted good frames counter register

    • [0:31]TGFC (def=0x0) // Transmitted good frames counter
  • 0x40028194MMCRFCECR// Ethernet MMC received frames with CRC error counter register

    • [0:31]RFCFC (def=0x0) // Received frames with CRC error counter
  • 0x40028198MMCRFAECR// Ethernet MMC received frames with alignment error counter register

    • [0:31]RFAEC (def=0x0) // Received frames with alignment error counter
  • 0x400281C4MMCRGUFCR// MMC received good unicast frames counter register

    • [0:31]RGUFC (def=0x0) // Received good unicast frames counter
• 0x40028700ETHERNET_PTP// Ethernet: Precision time protocol

  • 0x40028700PTPTSCR// Ethernet PTP time stamp control register (ETH_PTPTSCR)

    • [0]TSE (def=0x0) // Time stamp enable
    • [1]TSFCU (def=0x0) // Time stamp fine or coarse update
    • [2]TSSTI (def=0x0) // Time stamp system time initialize
    • [3]TSSTU (def=0x0) // Time stamp system time update
    • [4]TSITE (def=0x0) // Time stamp interrupt trigger enable
    • [5]TSARU (def=0x0) // Time stamp addend register update
  • 0x40028704PTPSSIR// Ethernet PTP subsecond increment register

    • [0:7]STSSI (def=0x0) // System time subsecond increment
  • 0x40028708PTPTSHR// Ethernet PTP time stamp high register

    • [0:31]STS (def=0x0) // System time second
  • 0x4002870CPTPTSLR// Ethernet PTP time stamp low register (ETH_PTPTSLR)

    • [0:30]STSS (def=0x0) // System time subseconds
    • [31]STPNS (def=0x0) // System time positive or negative sign
  • 0x40028710PTPTSHUR// Ethernet PTP time stamp high update register

    • [0:31]TSUS (def=0x0) // Time stamp update second
  • 0x40028714PTPTSLUR// Ethernet PTP time stamp low update register (ETH_PTPTSLUR)

    • [0:30]TSUSS (def=0x0) // Time stamp update subseconds
    • [31]TSUPNS (def=0x0) // Time stamp update positive or negative sign
  • 0x40028718PTPTSAR// Ethernet PTP time stamp addend register

    • [0:31]TSA (def=0x0) // Time stamp addend
  • 0x4002871CPTPTTHR// Ethernet PTP target time high register

    • [0:31]TTSH (def=0x0) // Target time stamp high
  • 0x40028720PTPTTLR// Ethernet PTP target time low register

    • [0:31]TTSL (def=0x0) // Target time stamp low
• 0x40029000ETHERNET_DMA// Ethernet: DMA controller operation

  • 0x40029000DMABMR// Ethernet DMA bus mode register

    • [0]SR (def=0x1) // Software reset
    • [2:6]DSL (def=0x0) // Descriptor skip length
    • [7]DFM (def=0x0) // Descriptor mode
    • [31]ERX_RST (def=0x0) // MAC receive reset control
    • [30]ETX_RST (def=0x0) // MAC sent reset control
    • [29]DMARX_RST (def=0x0) // DMA receive reset control
    • [28]DMATX_RST (def=0x0) // DMA sent reset control
  • 0x40029004DMATPDR// Ethernet DMA transmit poll demand register

    • [0:31]TPD (def=0x0) // Transmit poll demand
  • 0x40029008DMARPDR// EHERNET DMA receive poll demand register

    • [0:31]RPD (def=0x0) // Receive poll demand
  • 0x4002900CDMARDLAR// Ethernet DMA receive descriptor list address register

    • [0:31]RDLAR (def=0x0) // Start of receive list
  • 0x40029010DMATDLAR// Ethernet DMA transmit descriptor list address register

    • [0:31]TDLAR (def=0x0) // Start of transmit list
  • 0x40029014DMASR// Ethernet DMA status register

    • [0]TS (def=0x0) // Transmit status
    • [1]TPSS (def=0x0) // Transmit process stopped status
    • [2]TBUS (def=0x0) // Transmit buffer unavailable status
    • [3]TJTS (def=0x0) // Transmit jabber timeout status
    • [4]ROS (def=0x0) // Receive overflow status
    • [5]TUS (def=0x0) // Transmit underflow status
    • [6]RS (def=0x0) // Receive status
    • [7]RBUS (def=0x0) // Receive buffer unavailable status
    • [8]RPSS (def=0x0) // Receive process stopped status
    • [9]PWTS (def=0x0) // Receive watchdog timeout status
    • [10]ETS (def=0x0) // Early transmit status
    • [11]PLS (def=0x0) // 10MPHY Physical layer variation
    • [14]ERS (def=0x0) // Early receive status
    • [15]AIS (def=0x0) // Abnormal interrupt summary
    • [16]NIS (def=0x0) // Normal interrupt summary
    • [17:19]RPS (def=0x0) // Receive process state
    • [20:22]TPS (def=0x0) // Transmit process state
    • [23:25]EBS (def=0x0) // Error bits status
    • [27]MMCS (def=0x0) // MMC status
    • [28]PMTS (def=0x0) // PMT status
    • [29]TSTS (def=0x0) // Time stamp trigger status
  • 0x40029018DMAOMR// Ethernet DMA operation mode register

    • [1]SR (def=0x0) // SR
    • [6]FUGF (def=0x0) // FUGF
    • [7]FEF (def=0x0) // FEF
    • [13]ST (def=0x0) // ST
    • [20]FTF (def=0x0) // FTF
    • [21]TSF (def=0x0) // TSF
    • [26]DTCEFD (def=0x0) // DTCEFD
  • 0x4002901CDMAIER// Ethernet DMA interrupt enable register

    • [0]TIE (def=0x0) // Transmit interrupt enable
    • [1]TPSIE (def=0x0) // Transmit process stopped interrupt enable
    • [2]TBUIE (def=0x0) // Transmit buffer unavailable interrupt enable
    • [3]TJTIE (def=0x0) // Transmit jabber timeout interrupt enable
    • [4]ROIE (def=0x0) // Overflow interrupt enable
    • [5]TUIE (def=0x0) // Underflow interrupt enable
    • [6]RIE (def=0x0) // Receive interrupt enable
    • [7]RBUIE (def=0x0) // Receive buffer unavailable interrupt enable
    • [8]RPSIE (def=0x0) // Receive process stopped interrupt enable
    • [9]RWTIE (def=0x0) // receive watchdog timeout interrupt enable
    • [10]ETIE (def=0x0) // Early transmit interrupt enable
    • [11]PLE (def=0x0) // 10M Physical layer connection
    • [14]ERS (def=0x0) // Early receive interrupt enable
    • [15]AISE (def=0x0) // Abnormal interrupt summary enable
    • [16]NISE (def=0x0) // Normal interrupt summary enable
  • 0x40029020DMAMFBOCR// Ethernet DMA missed frame and buffer overflow counter register

    • [0:15]MFC (def=0x0) // Missed frames by the controller
    • [16]OMFC (def=0x0) // Overflow bit for missed frame counter
    • [17:27]MFA (def=0x0) // Missed frames by the application
    • [28]OFOC (def=0x0) // Overflow bit for FIFO overflow counter
  • 0x40029048DMACHTDR// Ethernet DMA current host transmit descriptor register

    • [0:31]HTDAP (def=0x0) // Host transmit descriptor address pointer
  • 0x4002904CDMACHRDR// Ethernet DMA current host receive descriptor register

    • [0:31]HRDAP (def=0x0) // Host receive descriptor address pointer
  • 0x40029050DMACHTBAR// Ethernet DMA current host transmit buffer address register

    • [0:31]HTBAP (def=0x0) // Host transmit buffer address pointer
  • 0x40029054DMACHRBAR// Ethernet DMA current host receive buffer address register

    • [0:31]HRBAP (def=0x0) // Host receive buffer address pointer
• 0x40022000FLASH// FLASH

  • 0x40022000ACTLR// Access control register

    • [0:1]SCK_CFG (def=0x0) // Waiting Status
    • [6]ENHANCE_STATUS (def=0x0) // Enhanced Status
    • [7]EHMOD (def=0x0) // flash enhanced read mode control bit
    • [8]FLASH_LP (def=0x0) // FLASH Low Power Mode Control Bit
    • [14]FLASH_READY (def=0x0) // flash ready indicator
    • [15]FLASH_ST (def=0x0) // FLASH Low Power Status Indicator Bits
  • 0x40022004KEYR// Flash key register

    • [0:31]KEYR (def=0x0) // FPEC key
  • 0x40022008OBKEYR// Flash option key register

    • [0:31]OBTKEY (def=0x0) // Option byte key
  • 0x4002200CSTATR// Status register

    • [15]BOOT_LOCK (def=0x1) // BOOT_LOCK
    • [14]BOOT_MODE (def=0x0) // BOOT_MODE
    • [13]BOOT_STATUS (def=0x0) // BOOT_STATUS
    • [12]BOOT_AVA (def=0x0) // BOOT_AVA
    • [5]EOP (def=0x0) // End of operation
    • [4]WRPRTERR (def=0x0) // Write protection error
    • [1]WRBSY (def=0x0) // Quick page programming
    • [0]BSY (def=0x0) // Busy
  • 0x40022010CTLR// Control register

    • [0]PG (def=0x0) // Programming
    • [1]PER (def=0x0) // Page Erase
    • [4]OBPG (def=0x0) // Option byte programming
    • [5]OBER (def=0x0) // Option byte erase
    • [6]STRT (def=0x0) // Start
    • [7]LOCK (def=0x1) // Lock
    • [9]OBWRE (def=0x0) // Option bytes write enable
    • [10]ERRIE (def=0x0) // Error interrupt enable
    • [12]EOPIE (def=0x0) // End of operation interrupt enable
    • [15]FLOCK (def=0x1) // Fast programmable lock
    • [16]FTPG (def=0x0) // Fast programming
    • [18]BER (def=0x0) // Block Erase
    • [21]PGSTRT (def=0x0) // Page Programming Start
    • [22]RSENACT (def=0x0) // Reset Flash Enhance read mode
  • 0x40022014ADDR// Flash address register

    • [0:31]FAR (def=0x0) // Flash Address
  • 0x4002201COBR// Option byte register

    • [0]OBERR (def=0x0) // Option byte error
    • [1]RDPRT (def=0x0) // Read protection
    • [2]IWDG_SW (def=0x1) // IWDG_SW
    • [8:9]FIX_11 (def=0x3) // Fixed to 11
    • [10:17]DATA0 (def=0xFF) // Data byte 0
    • [18:25]DATA1 (def=0xFF) // Data byte 1
  • 0x40022020WPR// Write protection register

    • [0:31]WRP (def=0x0) // Write protect
  • 0x40022024MODEKEYR// Mode select register

    • [0:31]MODEKEYR (def=0x0) // Mode select
  • 0x4002202CCFGR0// FLASH configuration register

    • [28]DBMODE (def=0x0) // FLASH Mode status
  interrupts:
  • [34] FLASH // Flash global interrupt
• 0xE000D000IPC// Inter-cpre communication

  • 0xE000D000CTLR// IPC control register

    • [0]TX_CID0 (def=0x0) // The ID of the sender kernel to specify the kernel that responds to the sending interrupt
    • [2]RX_CID0 (def=0x0) // The ID of the kernel on the receiver side, which is configured to respond to the receive interrupt
    • [4]TX_IER0 (def=0x0) // Channel 0 transmitter interrupt is enabled, and channel 0 can generate transmit interrupt when set
    • [5]RX_IER0 (def=0x0) // Channel 0 receiver interrupt is enabled, and channel 0 can generate a receive interrupt when 1 is s
    • [6]AUTOEN0 (def=0x0) // The channel 0 status bit enables automatic updates
    • [7]LOCK0 (def=0x0) // Channel 0 is configured locked
    • [8]TX_CID1 (def=0x0) // The ID of the sender kernel to specify the kernel that responds to the sending interrupt
    • [10]RX_CID1 (def=0x0) // The ID of the kernel on the receiver side, which is configured to respond to the receive interrupt
    • [12]TX_IER1 (def=0x0) // Channel 1 transmitter interrupt is enabled, and channel 1 can generate a transmit interrupt when 1
    • [13]RX_IER1 (def=0x0) // Channel 1 receiver interrupt is enabled, and channel 1 can generate receive interrupt when 1 is set
    • [14]AUTOEN1 (def=0x0) // Channel 1 status bits enable automatic updates
    • [15]LOCK1 (def=0x0) // Channel 1 configuration locks
    • [16]TX_CID2 (def=0x0) // The ID of the sender kernel to specify the kernel that responds to the sending interrupt
    • [18]RX_CID2 (def=0x0) // The ID of the kernel on the receiver side, which is configured to respond to the receive interrupt
    • [20]TX_IER2 (def=0x0) // Channel 2 transmitter interrupt is enabled, and channel 2 can generate a transmit interrupt when 1
    • [21]RX_IER2 (def=0x0) // Channel 2 receiver interrupt is enabled, and channel 2 can generate a receive interrupt when 1 is s
    • [22]AUTOEN2 (def=0x0) // Channel 2 status bits are enabled to be updated automatically
    • [23]LOCK2 (def=0x0) // Channel 2 configuration locking
    • [24]TX_CID3 (def=0x0) // The ID of the sender kernel and the kernel that responds to the send interrupt
    • [26]RX_CID3 (def=0x0) // Receiver kernel ID, configure the kernel that responds to receive interrupts
    • [28]TX_IER3 (def=0x0) // Channel 3 transmitter interrupt is enabled, and channel 3 can generate a transmit interrupt when 1
    • [29]RX_IER3 (def=0x0) // Channel 3 receiver interrupt is enabled, and channel 3 can generate receive interrupt when set to 1
    • [30]AUTOEN3 (def=0x0) // The status bit of channel 3 is automatically updated, when the receiver writes IPC _STS when 1,
    • [31]LOCK3 (def=0x0) // Channel 3 is locked, and only reset can be cleared after write 1, and other control registers
  • 0xE000D004ISR// IPC interrupt status register

    • [0:7]IPC_ISR0 (def=0x0) // IPC channel 0 interrupt status register
    • [8:15]IPC_ISR1 (def=0x0) // IPC channel 1 interrupt status register
    • [16:23]IPC_ISR2 (def=0x0) // IPC channel 2 interrupt status register
    • [24:31]IPC_ISR3 (def=0x0) // IPC channel 3 interrupt status register
  • 0xE000D008ISM// IPC ISM channel interrupt mask register

    • [0:7]IPC_ISM0 (def=0x0) // IPC channel 0 interrupts the mask register
    • [8:15]IPC_ISM1 (def=0x0) // IPC channel 1 interrupts the mask register
    • [16:23]IPC_ISM2 (def=0x0) // IPC channel 2 interrupts the mask register
    • [24:31]IPC_ISM3 (def=0x0) // IPC channel 3 interrupts the mask register
  • 0xE000D010ENA// IPC status bit interrupt enable register

    • [0:7]IPC_ENA0 (def=0x0) // IPC channel 0 flag interrupt enable register
    • [8:15]IPC_ENA1 (def=0x0) // IPC channel 1 flag interrupt enable register
    • [16:23]IPC_ENA2 (def=0x0) // IPC channel 2 flag interrupt enable register
    • [24:31]IPC_ENA3 (def=0x0) // IPC channel 3 flag interrupt enable register
  • 0xE000D014STS// IPC channel status registers

    • [0:7]IPC_STS0 (def=0x0) // IPC channel 0 status register
    • [8:15]IPC_STS1 (def=0x0) // IPC channel 1 status register
    • [16:23]IPC_STS2 (def=0x0) // IPC channel 2 status register
    • [24:31]IPC_STS3 (def=0x0) // IPC channel 3 status register
  • 0xE000D018SET// IPC Status Flag Position Bit Register

    • [0:7]IPC_SET0 (def=0x0) // IPC channel 0 status flag position bit register
    • [8:15]IPC_SET1 (def=0x0) // IPC channel 1 status flag position bit register
    • [16:23]IPC_SET2 (def=0x0) // IPC channel 2 status flag position bit register
    • [24:31]IPC_SET3 (def=0x0) // IPC channel 3 status flag position bit register
  • 0xE000D01CCLR// IPC Status Flag Bit Reset Register

    • [0:7]IPC_CLR0 (def=0x0) // The status flag of IPC channel 0 clears the register, and the corresponding bit of the IPC _S
    • [8:15]IPC_CLR1 (def=0x0) // The status flag of IPC channel 1 clears the register, and the corresponding bit of the IPC _S
    • [16:23]IPC_CLR2 (def=0x0) // The status flag of IPC channel 2 clears the register, and the corresponding bit of the IPC _S
    • [24:31]IPC_CLR3 (def=0x0) // The status flag of IPC channel 3 clears the register, and the corresponding bit of the IPC _S
  • 0xE000D020MSG0// IPC information register

    • [0:31]IPC_MSG0 (def=0x0) // IPC information registers are used to store and transmit information that needs to be passed
  • 0xE000D024MSG1// IPC information register

    • [0:31]IPC_MSG1 (def=0x0) // IPC information registers are used to store and transmit information that needs to be passed
  • 0xE000D028MSG2// IPC information register

    • [0:31]IPC_MSG2 (def=0x0) // IPC information registers are used to store and transmit information that needs to be passed
  • 0xE000D02CMSG3// IPC information register

    • [0:31]IPC_MSG3 (def=0x0) // IPC information registers are used to store and transmit information that needs to be passed
  interrupts:
  • [16] IPC_CH0 // IPC global interrupt 0
  • [17] IPC_CH1 // IPC global interrupt 1
  • [18] IPC_CH2 // IPC global interrupt 2
  • [19] IPC_CH3 // IPC global interrupt 3
• 0xE000F000STK// SysTick

  • 0xE000F000STK_CTLR_0// System count control register 0

    • [0]EN_0 (def=0x0) // System counter 0 enable control bit
    • [1]IE_0 (def=0x0) // Counter 0 interrupt enable control bit
    • [2]NO_RTC_0 (def=0x0) // Counter Clock Source Selection Bit
    • [3]AUTO_RELOAD_0 (def=0x0) // Auto Reload Count Enable Bit
    • [4]DOWN_MODE_0 (def=0x0) // Counting Mode
    • [6]CID_0 (def=0x0) // Counter 0 allocates a kernel register
  • 0xE000F004STK_ISR// System counter interrupt status register

    • [0]STK_ISR0 (def=0x0) // Systick0 Interrupt Flag
    • [1]STK_ISR1 (def=0x0) // Systick1 Interrupt Flag
  • 0xE000F008STK_CNT_0// System counter 0 count register

    • [0:31]CNT_0 (def=0x0) // Systick0 counter register, counts are enabled and accumulate/subtract and automatically reloa
  • 0xE000F010STK_CMP_0// System counter 0 comparison register

    • [0:31]CMP_0 (def=0x0) // Systick0 comparison register for automatic reloading when counting up and comparing when count
  • 0xE000F080STK_CTLR_1// System count control register 1

    • [0]EN_1 (def=0x0) // System counter 1 enable control bit
    • [1]IE_1 (def=0x0) // Counter 1 interrupt enable control bit
    • [2]NO_RTC_1 (def=0x0) // Counter Clock Source Selection Bit
    • [3]AUTO_RELOAD_1 (def=0x0) // Auto Reload Count Enable Bit
    • [4]DOWN_MODE_1 (def=0x0) // Counting Mode
    • [6]CID_1 (def=0x0) // Counter 1 allocates a kernel register
  • 0xE000F088STK_CNT_1// System counter 1 count register

    • [0:31]CNT_1 (def=0x0) // Systick1 counter register, counts are enabled and accumulate/subtract and automatically reloa
  • 0xE000F090STK_CMP_1// System counter 1 comparison register

    • [0:31]CMP_1 (def=0x0) // Systick1 comparison register for automatic reloading when counting up and comparing when count
• 0x0E00C000HSEM// HSEM

  • 0x0E00C000HSEM_RX0// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C004HSEM_RX1// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C008HSEM_RX2// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C00CHSEM_RX3// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C010HSEM_RX4// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C014HSEM_RX5// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C018HSEM_RX6// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C01CHSEM_RX7// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C020HSEM_RX8// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C024HSEM_RX9// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C028HSEM_RX10// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C02CHSEM_RX11// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C030HSEM_RX12// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C034HSEM_RX13// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C038HSEM_RX14// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C03CHSEM_RX15// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C040HSEM_RX16// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C044HSEM_RX17// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C048HSEM_RX18// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C04CHSEM_RX19// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C050HSEM_RX20// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C054HSEM_RX21// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C058HSEM_RX22// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C05CHSEM_RX23// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C060HSEM_RX24// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C064HSEM_RX25// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C068HSEM_RX26// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C06CHSEM_RX27// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C070HSEM_RX28// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C074HSEM_RX29// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C078HSEM_RX30// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C07CHSEM_RX31// HSEM register HSEM_RX0 HSEM_RX31

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C100HSEM_RLRX0// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C104HSEM_RLRX1// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C108HSEM_RLRX2// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C10CHSEM_RLRX3// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C110HSEM_RLRX4// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C114HSEM_RLRX5// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C118HSEM_RLRX6// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C11CHSEM_RLRX7// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C120HSEM_RLRX8// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C124HSEM_RLRX9// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C128HSEM_RLRX10// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C12CHSEM_RLRX11// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C130HSEM_RLRX12// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C134HSEM_RLRX13// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C138HSEM_RLRX14// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C13CHSEM_RLRX15// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C140HSEM_RLRX16// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C144HSEM_RLRX17// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C148HSEM_RLRX18// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C14CHSEM_RLRX19// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C150HSEM_RLRX20// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C154HSEM_RLRX21// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C158HSEM_RLRX22// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C15CHSEM_RLRX23// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C160HSEM_RLRX24// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C164HSEM_RLRX25// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C168HSEM_RLRX26// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C16CHSEM_RLRX27// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C170HSEM_RLRX28// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C174HSEM_RLRX29// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C178HSEM_RLRX30// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C17CHSEM_RLRX31// HSEM Read lock register

    • [0:7]PID (def=0x0) // Semaphore ProcessID
    • [8:11]CID (def=0x0) // Semaphore CID
    • [31]LOCK (def=0x0) // Lock indication
  • 0x0E00C300HSEM_IER// HSEM interrupt enable register

    • [0:31]HSEM_IER (def=0x0) // HSEM channel interrupt enable register, kernel private register, set to 1 when the correspond
  • 0x0E00C308HSEM_ISR// HSEM interrupt status register

    • [0:31]HSEM_IER (def=0x0) // HSEM channel interrupt enable register, kernel private register, set to 1 when the correspond
  • 0x0E00C310HSEM_ISM// HSEM interrupt mask register

    • [0:31]HSEM_ISM (def=0x0) // HSEM channel lock status registers to obtain the lock status of 32 channels
  • 0x0E00C200HSEM_LSE// HSEM lock status register

    • [0:31]HSEM_LSE (def=0x0) // HSEM channel lock status registers to obtain the lock status of 32 channels
  • 0x0E00C318HSEM_LSM// HSEM Lock Status Mask Register

    • [0:31]HSEM_LSE (def=0x0) // HSEM channel lock status registers to obtain the lock status of 32 channels
  • 0x0E00C208HSEM_CLR// HSEM Unlock Register

    • [0:7]match_PID (def=0x0) // It is used to match the unlocked PID value and compare it with the PID value of each locked channel
    • [8:9]match_CID (def=0x0) // It is used to match the unlocked CID value and compare it with the CID value of each locked channel
    • [12]PID_MASK (def=0x0) // PID Matching Shielding
    • [13]CID_MASK (def=0x0) // CID Matching Shielding
    • [16:31]CLR_KEY (def=0x0) // Unlock keywords, the operation is valid when the write data is equal to the matching keyword,
  • 0x0E00C20CHSEM_KEY// HSEM unlocks the keyword register

    • [0]auto_1step_clr (def=0x0) // When the channel is locked in 1step mode, the corresponding channel interrupt status bit is a
    • [1]auto_2step_clr (def=0x0) // When the channel is locked in 2step mode, the corresponding channel interrupt status bit is a
    • [16:31]KEY_VALUE (def=0x0) // Unlock keywords, which are used to match unlock method keyword comparisons.
  interrupts:
  • [28] HSEM // HSEM global interrupt
• 0xE000E000PFIC// Programmable Fast Interrupt Controller

  • 0xE000E000ISR1// Interrupt Status Register

    • [2:3]INTENSTA2_3 (def=0x3) // Interrupt ID Status
    • [5]INTENSTA5 (def=0x0) // Interrupt ID Status
    • [8:9]INTENSTA8_9 (def=0x0) // Interrupt ID Status
    • [12:31]INTENSTA12_31 (def=0x0) // Interrupt ID Status
  • 0xE000E004ISR2// Interrupt Status Register

    • [0:31]INTENSTA (def=0x0) // Interrupt ID Status
  • 0xE000E008ISR3// Interrupt Status Register

    • [0:31]INTENSTA (def=0x0) // Interrupt ID Status
  • 0xE000E00CISR4// Interrupt Status Register

    • [0:31]INTENSTA (def=0x0) // Interrupt ID Status
  • 0xE000E010ISR5// Interrupt Status Register

    • [0:19]INTENSTA (def=0x0) // Interrupt ID Status
  • 0xE000E020IPR1// Interrupt Pending Register

    • [2:3]PENDSTA2_3 (def=0x0) // PENDSTA
    • [5]PENDSTA5 (def=0x0) // PENDSTA
    • [8:9]INTENSTA8_9 (def=0x0) // PENDSTA
    • [12:31]INTENSTA12_31 (def=0x0) // PENDSTA
  • 0xE000E024IPR2// Interrupt Pending Register

    • [0:31]PENDSTA (def=0x0) // PENDSTA
  • 0xE000E028IPR3// Interrupt Pending Register

    • [0:31]PENDSTA (def=0x0) // PENDSTA
  • 0xE000E02CIPR4// Interrupt Pending Register

    • [0:31]PENDSTA (def=0x0) // PENDSTA
  • 0xE000E030IPR5// Interrupt Pending Register

    • [0:19]PENDSTA (def=0x0) // PENDSTA
  • 0xE000E040ITHRESDR// Interrupt Priority Register

    • [0:7]THRESHOLD (def=0x0) // THRESHOLD
  • 0xE000E048CFGR// Interrupt configuration register

    • [7]SYSRST (def=0x0) // System reset register
    • [16:31]KEYCODE (def=0x0) // KEYCODE
  • 0xE000E04CGISR// Interrupt Global Register

    • [0:7]NESTSTA (def=0x0) // interrupt nesting
    • [8]GACTSTA (def=0x0) // interrupt execution
    • [9]GPENDSTA (def=0x0) // interrupt pending
    • [11]GLOBL_IE (def=0x0) // global interrupt enable
    • [12]DBG_MODE (def=0x0) // debug mode
    • [13]LOCK_UP (def=0x0) // lock-out state
    • [14:15]EX_STATE (def=0x0) // The kernel status register, which is used to obtain the running state of the kernel
  • 0xE000E050VTFIDR// ID Config Register

    • [0:7]VTFID0 (def=0x0) // VTFID0
    • [8:15]VTFID1 (def=0x0) // VTFID1
    • [16:23]VTFID2 (def=0x0) // VTFID2
    • [24:31]VTFID3 (def=0x0) // VTFID3
  • 0xE000E060VTFADDRR0// Interrupt 0 address Register

    • [0]VTF0EN (def=0x0) // VTF0EN
    • [1:31]ADDR0 (def=0x0) // ADDR0
  • 0xE000E064VTFADDRR1// Interrupt 1 address Register

    • [0]VTF1EN (def=0x0) // VTF1EN
    • [1:31]ADDR1 (def=0x0) // ADDR1
  • 0xE000E068VTFADDRR2// Interrupt 2 address Register

    • [0]VTF2EN (def=0x0) // VTF2EN
    • [1:31]ADDR2 (def=0x0) // ADDR2
  • 0xE000E06CVTFADDRR3// Interrupt 3 address Register

    • [0]VTF3EN (def=0x0) // VTF3EN
    • [1:31]ADDR3 (def=0x0) // ADDR3
  • 0xE000E100IENR1// Interrupt Setting Register

    • [12:31]INTEN12_31 (def=0x0) // INTEN12_31
  • 0xE000E104IENR2// Interrupt Setting Register

    • [0:31]INTEN (def=0x0) // INTEN
  • 0xE000E108IENR3// Interrupt Setting Register

    • [0:31]INTEN (def=0x0) // INTEN
  • 0xE000E10CIENR4// Interrupt Setting Register

    • [0:31]INTEN (def=0x0) // INTEN
  • 0xE000E110IENR5// Interrupt Setting Register

    • [0:19]INTEN (def=0x0) // INTEN
  • 0xE000E180IRER1// Interrupt Clear Register

    • [12:31]INTRSET12_31 (def=0x0) // INTRSET12_31
  • 0xE000E184IRER2// Interrupt Clear Register

    • [0:31]INTRSET (def=0x0) // INTRSET
  • 0xE000E188IRER3// Interrupt Clear Register

    • [0:31]INTRSET (def=0x0) // INTRSET
  • 0xE000E18CIRER4// Interrupt Clear Register

    • [0:31]INTRSET (def=0x0) // INTRSET
  • 0xE000E190IRER5// Interrupt Clear Register

    • [0:19]INTRSET (def=0x0) // INTRSET
  • 0xE000E200IPSR1// Interrupt Pending Register

    • [2:3]PENDSET2_3 (def=0x0) // PENDSET
    • [5]PENDSET5 (def=0x0) // PENDSET
    • [8:9]PENDSET8_9 (def=0x0) // PENDSET
    • [12:31]PENDSET12_31 (def=0x0) // PENDSET
  • 0xE000E204IPSR2// Interrupt Pending Register

    • [0:31]PENDSET (def=0x0) // PENDSET
  • 0xE000E208IPSR3// Interrupt Pending Register

    • [0:31]PENDSET (def=0x0) // PENDSET
  • 0xE000E20CIPSR4// Interrupt Pending Register

    • [0:31]PENDSET (def=0x0) // PENDSET
  • 0xE000E210IPSR5// Interrupt Pending Register

    • [0:19]PENDSET (def=0x0) // PENDSET
  • 0xE000E280IPRR1// Interrupt Pending Clear Register

    • [2:3]PENDRST2_3 (def=0x0) // PENDRESET
    • [5]PENDRST5 (def=0x0) // PENDRESET
    • [8:9]PENDRST8 (def=0x0) // PENDRESET
    • [12:31]PENDRST12_31 (def=0x0) // PENDRESET
  • 0xE000E284IPRR2// Interrupt Pending Clear Register

    • [0:31]PENDRST (def=0x0) // PENDRESET
  • 0xE000E288IPRR3// Interrupt Pending Clear Register

    • [0:31]PENDRST (def=0x0) // PENDRESET
  • 0xE000E28CIPRR4// Interrupt Pending Clear Register

    • [0:31]PENDRST (def=0x0) // PENDRESET
  • 0xE000E290IPRR5// Interrupt Pending Clear Register

    • [0:19]PENDRST (def=0x0) // PENDRESET
  • 0xE000E300IACTR1// Interrupt ACTIVE Register

    • [2:3]IACTS2_3 (def=0x0) // IACTS
    • [5]IACTS5 (def=0x0) // IACTS
    • [8:9]IACTS8_9 (def=0x0) // IACTS
    • [12:31]IACTS12_31 (def=0x0) // IACTS
  • 0xE000E304IACTR2// Interrupt ACTIVE Register

    • [0:31]IACTS (def=0x0) // IACTS
  • 0xE000E308IACTR3// Interrupt ACTIVE Register

    • [0:31]IACTS (def=0x0) // IACTS
  • 0xE000E30CIACTR4// Interrupt ACTIVE Register

    • [0:31]IACTS (def=0x0) // IACTS
  • 0xE000E310IACTR5// Interrupt ACTIVE Register

    • [0:19]IACTS (def=0x0) // IACTS
  • 0xE000E400IPRIOR0// Interrupt Priority Register
  • 0xE000E404IPRIOR1// Interrupt Priority Register
  • 0xE000E408IPRIOR2// Interrupt Priority Register
  • 0xE000E40CIPRIOR3// Interrupt Priority Register
  • 0xE000E410IPRIOR4// Interrupt Priority Register
  • 0xE000E414IPRIOR5// Interrupt Priority Register
  • 0xE000E418IPRIOR6// Interrupt Priority Register
  • 0xE000E41CIPRIOR7// Interrupt Priority Register
  • 0xE000E420IPRIOR8// Interrupt Priority Register
  • 0xE000E424IPRIOR9// Interrupt Priority Register
  • 0xE000E428IPRIOR10// Interrupt Priority Register
  • 0xE000E42CIPRIOR11// Interrupt Priority Register
  • 0xE000E430IPRIOR12// Interrupt Priority Register
  • 0xE000E434IPRIOR13// Interrupt Priority Register
  • 0xE000E438IPRIOR14// Interrupt Priority Register
  • 0xE000E43CIPRIOR15// Interrupt Priority Register
  • 0xE000E440IPRIOR16// Interrupt Priority Register
  • 0xE000E444IPRIOR17// Interrupt Priority Register
  • 0xE000E448IPRIOR18// Interrupt Priority Register
  • 0xE000E44CIPRIOR19// Interrupt Priority Register
  • 0xE000E450IPRIOR20// Interrupt Priority Register
  • 0xE000E454IPRIOR21// Interrupt Priority Register
  • 0xE000E458IPRIOR22// Interrupt Priority Register
  • 0xE000E45CIPRIOR23// Interrupt Priority Register
  • 0xE000E460IPRIOR24// Interrupt Priority Register
  • 0xE000E464IPRIOR25// Interrupt Priority Register
  • 0xE000E468IPRIOR26// Interrupt Priority Register
  • 0xE000E46CIPRIOR27// Interrupt Priority Register
  • 0xE000E470IPRIOR28// Interrupt Priority Register
  • 0xE000E474IPRIOR29// Interrupt Priority Register
  • 0xE000E478IPRIOR30// Interrupt Priority Register
  • 0xE000E47CIPRIOR31// Interrupt Priority Register
  • 0xE000E480IPRIOR32// Interrupt Priority Register
  • 0xE000E484IPRIOR33// Interrupt Priority Register
  • 0xE000E488IPRIOR34// Interrupt Priority Register
  • 0xE000E48CIPRIOR35// Interrupt Priority Register
  • 0xE000E490IPRIOR36// Interrupt Priority Register
  • 0xE000E494IPRIOR37// Interrupt Priority Register
  • 0xE000E498IPRIOR38// Interrupt Priority Register
  • 0xE000E49CIPRIOR39// Interrupt Priority Register
  • 0xE000E4A0IPRIOR40// Interrupt Priority Register
  • 0xE000E4A4IPRIOR41// Interrupt Priority Register
  • 0xE000E4A8IPRIOR42// Interrupt Priority Register
  • 0xE000E4ACIPRIOR43// Interrupt Priority Register
  • 0xE000E4B0IPRIOR44// Interrupt Priority Register
  • 0xE000E4B4IPRIOR45// Interrupt Priority Register
  • 0xE000E4B8IPRIOR46// Interrupt Priority Register
  • 0xE000E4BCIPRIOR47// Interrupt Priority Register
  • 0xE000E4C0IPRIOR48// Interrupt Priority Register
  • 0xE000E4C4IPRIOR49// Interrupt Priority Register
  • 0xE000E4C8IPRIOR50// Interrupt Priority Register
  • 0xE000E4CCIPRIOR51// Interrupt Priority Register
  • 0xE000E4D0IPRIOR52// Interrupt Priority Register
  • 0xE000E4D4IPRIOR53// Interrupt Priority Register
  • 0xE000E4D8IPRIOR54// Interrupt Priority Register
  • 0xE000E4DCIPRIOR55// Interrupt Priority Register
  • 0xE000E4E0IPRIOR56// Interrupt Priority Register
  • 0xE000E4E4IPRIOR57// Interrupt Priority Register
  • 0xE000E4E8IPRIOR58// Interrupt Priority Register
  • 0xE000E4ECIPRIOR59// Interrupt Priority Register
  • 0xE000E4F0IPRIOR60// Interrupt Priority Register
  • 0xE000E4F4IPRIOR61// Interrupt Priority Register
  • 0xE000E4F8IPRIOR62// Interrupt Priority Register
  • 0xE000E4FCIPRIOR63// Interrupt Priority Register
  • 0xE000E600IALLOCR0// Interrupt Allocation Register
  • 0xE000E604IALLOCR1// Interrupt Allocation Register
  • 0xE000E608IALLOCR2// Interrupt Allocation Register
  • 0xE000E60CIALLOCR3// Interrupt Allocation Register
  • 0xE000E610IALLOCR4// Interrupt Allocation Register
  • 0xE000E614IALLOCR5// Interrupt Allocation Register
  • 0xE000E618IALLOCR6// Interrupt Allocation Register
  • 0xE000E61CIALLOCR7// Interrupt Allocation Register
  • 0xE000E620IALLOCR8// Interrupt Allocation Register
  • 0xE000E624IALLOCR9// Interrupt Allocation Register
  • 0xE000E628IALLOCR10// Interrupt Allocation Register
  • 0xE000E62CIALLOCR11// Interrupt Allocation Register
  • 0xE000E630IALLOCR12// Interrupt Allocation Register
  • 0xE000E634IALLOCR13// Interrupt Allocation Register
  • 0xE000E638IALLOCR14// Interrupt Allocation Register
  • 0xE000E63CIALLOCR15// Interrupt Allocation Register
  • 0xE000E640IALLOCR16// Interrupt Allocation Register
  • 0xE000E644IALLOCR17// Interrupt Allocation Register
  • 0xE000E648IALLOCR18// Interrupt Allocation Register
  • 0xE000E64CIALLOCR19// Interrupt Allocation Register
  • 0xE000E650IALLOCR20// Interrupt Allocation Register
  • 0xE000E654IALLOCR21// Interrupt Allocation Register
  • 0xE000E658IALLOCR22// Interrupt Allocation Register
  • 0xE000E65CIALLOCR23// Interrupt Allocation Register
  • 0xE000E660IALLOCR24// Interrupt Allocation Register
  • 0xE000E664IALLOCR25// Interrupt Allocation Register
  • 0xE000E668IALLOCR26// Interrupt Allocation Register
  • 0xE000E66CIALLOCR27// Interrupt Allocation Register
  • 0xE000E670IALLOCR28// Interrupt Allocation Register
  • 0xE000E674IALLOCR29// Interrupt Allocation Register
  • 0xE000E678IALLOCR30// Interrupt Allocation Register
  • 0xE000E67CIALLOCR31// Interrupt Allocation Register
  • 0xE000E680IALLOCR32// Interrupt Allocation Register
  • 0xE000E684IALLOCR33// Interrupt Allocation Register
  • 0xE000E688IALLOCR34// Interrupt Allocation Register
  • 0xE000E68CIALLOCR35// Interrupt Allocation Register
  • 0xE000E690IALLOCR36// Interrupt Allocation Register
  • 0xE000E694IALLOCR37// Interrupt Allocation Register
  • 0xE000E698IALLOCR38// Interrupt Allocation Register
  • 0xE000E69CIALLOCR39// Interrupt Allocation Register
  • 0xE000E6A0IALLOCR40// Interrupt Allocation Register
  • 0xE000E6A4IALLOCR41// Interrupt Allocation Register
  • 0xE000E6A8IALLOCR42// Interrupt Allocation Register
  • 0xE000E6ACIALLOCR43// Interrupt Allocation Register
  • 0xE000E6B0IALLOCR44// Interrupt Allocation Register
  • 0xE000E6B4IALLOCR45// Interrupt Allocation Register
  • 0xE000E6B8IALLOCR46// Interrupt Allocation Register
  • 0xE000E6BCIALLOCR47// Interrupt Allocation Register
  • 0xE000E6C0IALLOCR48// Interrupt Allocation Register
  • 0xE000E6C4IALLOCR49// Interrupt Allocation Register
  • 0xE000E6C8IALLOCR50// Interrupt Allocation Register
  • 0xE000E6CCIALLOCR51// Interrupt Allocation Register
  • 0xE000E6D0IALLOCR52// Interrupt Allocation Register
  • 0xE000E6D4IALLOCR53// Interrupt Allocation Register
  • 0xE000E6D8IALLOCR54// Interrupt Allocation Register
  • 0xE000E6DCIALLOCR55// Interrupt Allocation Register
  • 0xE000E6E0IALLOCR56// Interrupt Allocation Register
  • 0xE000E6E4IALLOCR57// Interrupt Allocation Register
  • 0xE000E6E8IALLOCR58// Interrupt Allocation Register
  • 0xE000E6ECIALLOCR59// Interrupt Allocation Register
  • 0xE000E6F0IALLOCR60// Interrupt Allocation Register
  • 0xE000E6F4IALLOCR61// Interrupt Allocation Register
  • 0xE000E6F8IALLOCR62// Interrupt Allocation Register
  • 0xE000E6FCIALLOCR63// Interrupt Allocation Register
  • 0xE000E700IAUTR1// interrupts authority register 1

    • [0:31]IAUT (def=0x0) // interrupt allocates all registers and is used to query whether the interrupt responds to each
  • 0xE000E704IAUTR2// interrupts authority register 2

    • [0:31]IAUT (def=0x0) // interrupt allocates all registers and is used to query whether the interrupt responds to each
  • 0xE000E708IAUTR3// interrupts authority register 3

    • [0:31]IAUT (def=0x0) // interrupt allocates all registers and is used to query whether the interrupt responds to each
  • 0xE000E70CIAUTR4// interrupts authority register 4

    • [0:31]IAUT (def=0x0) // interrupt allocates all registers and is used to query whether the interrupt responds to each
  • 0xE000E710IAUTR5// interrupts authority register 5

    • [0:31]IAUT (def=0x0) // interrupt allocates all registers and is used to query whether the interrupt responds to each
  • 0xE000E720WAKEIP0// PFIC wake-up instruction pointer register 0

    • [1:31]IP_RELOAD0 (def=0x0) // The PC address register on kernel C0 wake-up, which is used to reload the PC value after powe
    • [0]SHUTDOWN0 (def=0x0) // Kernel C0 Deep Sleep (Locked) Cancellation Register
  • 0xE000E724WAKEIP1// PFIC wake-up instruction pointer register 1

    • [1:31]IP_RELOAD1 (def=0x0) // The PC address register on kernel C1 wake-up, which is used to reload the PC value after powe
    • [0]SHUTDOWN1 (def=0x0) // Kernel C1 Deep Sleep (Locked) Cancellation Register
  • 0xE000E780CSTAR0// PFIC kernel status register 0

    • [0:7]CPU_nest_sta_0 (def=0x0) // The nested status register of kernel C0 interrupts is used to query the nested state of kernel
    • [8]CPU_irq_active_0 (def=0x0) // Kernel C0 interrupt active flag register, which is used to query whether kernel C0 is process
    • [9]CPU_irq_pend_0 (def=0x0) // Kernel C0 interrupt pending flag register, which is used to query kernel C1 for unhandled interrupt
    • [11]CPU_globl_ie_0 (def=0x0) // The kernel C0 global interrupt enable register is used to query whether the kernel C0 global
    • [12]CPU_dbg_mode_0 (def=0x0) // Kernel C0 debug mode register, which is used to query whether kernel C0 is in debug mode
    • [13]CPU_lock_up_0 (def=0x0) // The kernel C0 lock status register is used to query whether kernel C0 is in the locked state
    • [14:15]CPU_ex_state_0 (def=0x0) // The kernel C0 status register is used to obtain the running state of kernel C0
  • 0xE000E784CSTAR1// PFIC kernel status register 1

    • [0:7]CPU_nest_sta_1 (def=0x0) // The nested status register of kernel C1 interrupts is used to query the nested state of kernel
    • [8]CPU_irq_active_1 (def=0x0) // Kernel C1 interrupt active flag register, which is used to query whether kernel C1 is process
    • [9]CPU_irq_pend_1 (def=0x0) // Kernel C1 interrupt pending flag register, which is used to query kernel C1 for unhandled interrupt
    • [11]CPU_globl_ie_1 (def=0x0) // The kernel C1 global interrupt enable register is used to query whether the kernel C1 global
    • [12]CPU_dbg_mode_1 (def=0x0) // Kernel C1 debug mode register, which is used to query whether kernel C1 is in debug mode
    • [13]CPU_lock_up_1 (def=0x0) // The kernel C1 lock status register is used to query whether kernel C1 is in the locked state
    • [14:15]CPU_ex_state_1 (def=0x0) // The kernel C1 status register is used to obtain the running state of kernel C1
  • 0xE000EC80EENR// PFIC Event Enable Register

    • [0:30]EVENTEN (def=0x7FFFFFFF) // 31-0 Event wake-up enabled
  • 0xE000EC84EPR// PFIC Event Suspend Register

    • [8:31]EVENT_PEND31_8 (def=0x0) // 31-8 event is suspended, write 1 to clear zero
    • [0:7]EVENT_PEND7_0 (def=0x0) // 7-0 Event Pending Status, Not Clearable
  • 0xE000EC88EWUPR// PFIC Event Wake Register

    • [0:31]EVENT_WUP (def=0x0) // 31-0 Event Wake Register
  • 0xE000ED10SCTLR// System Control Register

    • [1]SLEEPONEXIT (def=0x0) // system leaves the state after an interruption
    • [2]SLEEPDEEP (def=0x0) // low power mode selection
    • [3]WFITOWFE (def=0x0) // ues WFI as WFE
    • [4]SEVONPEND (def=0x0) // SEVONPEND
    • [5]SETEVENT (def=0x0) // set event
    • [16:23]HART_ID (def=0x0) // Kernel ID register, which is used to obtain the kernel ID of the reader register
    • [31]SYSRST (def=0x0) // System reset