Package

Примечания

2). Both VDD and VBAT can be connected with an internal analog switch to supply power to the backup area and the pins PC13, PC14 and PC15. This analog switch can only pass a limited current (3mA). When powered by VDD, PC14 and PC15 can be used for GPIO or LSE pins, and PC13 can be used as a general-purpose I/O port, TAMPER pin, RTC calibration clock, RTC alarm clock or second output; PC13, PC14 and PC15 can only work in 2MHz mode when they are used as GPIO output pins, and the maximum driving load is 30pF, and they cannot be used as current sources (such as driving LEDs). When the power is supplied by VBAT, PC14 and PC15 can only be used for LSE pin, and PC13 can be used as TAMPER pin, RTC alarm clock or second output.

3). These pins are in the main function state when the backup area is powered on for the first time. Even after reset, the state of these pins is controlled by the backup area registers (these registers will not be reset by the main reset system). For specific information on how to control these I/O ports, please refer to the relevant chapters on the battery backup area and BKP register in the CH32FV2x_V3xRM datasheet.

4). Pin 5 and pin 6 of those in LQFP64M package are configured as OSC_IN and OSC_OUT function pins by default after chip reset. Software can reconfigure these 2 pins as PD0 and PD1. But for those in LQFP100 package, since PD0 and PD1 are inherent functional pins, there is no need to remap settings by software. For more detailed information, please refer to the chapters on Alternate Function I/O and Debug Setting in the CH32FV2x_V3xRM datasheet.

5). For devices without the BOOT0 pinout, they are pulled down to GND internally. For devices with the BOOT0 pinout but no BOOT1/PB2 pinout, BOOT1/PB2 is pulled down to GND internally. In this case, it is recommended that the BOOT1/PB2 pinout is set to input pull-down mode if a device goes into the low-power mode and configures I/O port state, to avoid generating extra current.

6). For CH32V305FBP6 and CH32V305GBU6 chips, the PA8 and PC9 pins are shorted inside the chip, it is prohibited to configure both IOs as output functions, pay attention to the pin state if there are power consumption requirements.

7). SDIO_D0 and SDIO_D1 are mapped to PC8 and PC9 by default. Only for products with the fifth from the bottom of the batch number greater than 1 or the sixth from the bottom of the lot number not equal to 0 (except for the chip CH32V305GBU6), when the bit[14]ETHMACEN=1 and bit[10]SDIOEN=1 in the register RCC_AHBPCENR, the default mapping of SDIO_D0 and SDIO_D1 is automatically changed to PB14 and PB15.

8). DVP_D5 is mapped to PB6 by default. Only for products with the fifth from the bottom of the lot number greater than 1 or the sixth from the bottom of the batch number not equal to 0, when the bit[13]DVPEN=1 and bit[11]USBHSEN=1 in the register RCC_AHBPCENR and the bit[2]RB_UC_RST_SIE=0 in R8_USB_CTRL, the default mapping of DVP_D5 is automatically changed to PB3.

9). FSMC_NADV is mapped to PB7 by default. Only for products with the fifth from the bottom of the lot number greater than 1 or the sixth from the bottom of the lot number not equal to 0, when the bit[8]FSMCEN=1 and bit[11]USBHSEN=1 in the register RCC_AHBPCENR and bit[2]RB_UC_RST_SIE=0 in R8_USB_CTRL, the default mapping of FSMC_NADV will be automatically changed to.

10). I2S3_SD is mapped to PB5 by default. Only for products with the fifth from the bottom of the lot number greater than 2 or the sixth last digit of the lot number not equal to 0, if 10M Ethernet and I2S3 functions are used at the same time, the default mapping of I2S3_SD will be automatically changed to PA9.

11). I2S3_MCK is mapped to PC7 by default. Only for products with the fifth from the bottom of the lot number greater than 2 or the sixth last digit of the lot number not equal to 0, if 10M Ethernet and I2S3 functions are used at the same time, the default mapping of I2S3_MCK will be automatically changed to PA8.

12). SPI3_MOSI is mapped to PB5 by default. Only for products with the fifth from the bottom of the lot number equal to 2 or the sixth last digit of the lot number equal to 0, when using Ethernet, the default pin function of I2S3 is not available, and the chip selection signal of the default pin of SPI3 is not available. At this time, the default mapping of SPI3_MOSI is automatically changed to PA15

13). The value after the underscore of the remap function indicates the configuration value of the corresponding bit in the AFIO register. For example, UART4_RX_3 indicates that the corresponding bit in the AFIO register is configured as 11b.

14). TIM2_CH1 and TIM2_ETR share a common pin, but cannot be used at the same time.

15). For CH32V305FBP6 chip, PA5 and PA1 pins are short-circuited inside the chip, prohibiting both IOs to be configured as output function; PA9 and PA13 pins are short-circuited inside the chip, prohibiting both IOs to be configured as output function; pay attention to the pin status if there is power consumption requirement.