Package

Примечания

2). The PC13, PC14 and PC15 pins are powered by the power's switch, and this power's switch can only absorb a limited current (3mA). Therefore, when these 3 pins are used as output pins, there are the following restrictions: only one pin can be used as an output at the same time. When used as an output pin, it can only work in 2MHz mode. The maximum drive load is 30pF and cannot be used as a current source (Such as driving LED).

3). These pins are in the main function state when the backup area is powered on for the first time. Even after reset, the state of these pins is controlled by the backup area registers (these registers will not be reset by the main reset system). For specific information on how to control these IO ports, please refer to the relevant chapters on the battery backup area and BKP register in the CH32FV2x_V3xRM datasheet.

4). Pin 5 and pin 6 of those in LQFP64M package are configured as OSC_IN and OSC_OUT function pins by default after chip reset. Software can reconfigure these 2 pins as PD0 and PD1. But for those in LQFP100 package, since PD0 and PD1 are inherent functional pins, there is no need to re-image settings by software. For the CH32V203RBT6, the OSC_IN and OSC_OUT function pins have no alternate functions of PD0 and PD1. For more detailed information, please refer to the chapters on Alternate Function I/O and Debug Setting in the CH32FV2x_V3xRM datasheet.

5). For devices without the BOOT0 pinout, they are pulled down to GND internally. For devices with the BOOT0 pinout but no BOOT1/PB2 pinout, BOOT1/PB2 is pulled down to GND internally. In this case, it is recommended that the BOOT1/PB2 pinout is set to input pull-down mode if a device goes into the low-power mode and configures IO port state, to avoid generating extra current.

6). For devices with BOOT0 and PB8 pinouts shorted, it is recommended to be connected to an external 500K pull-down resistor, to ensure that the device is powered on stably and enters the mode of booting from program Flash memory. In this case, the PB8 only supports output drive functions, with all input functions disabled.

7). For devices in 20-pin/28-pin package, several pins are shorted (at least 2 IO function pins are physically shorted as one pin). In this case, the driver should not configure the output function at the same time, otherwise the pins may be damaged. Note pin states when there is a power consumption requirement.

8). The value after the underline of the remapping function indicates the configuration value of the corresponding bit in the AFIO register. For example: UART4_RX_3 indicates that the corresponding bit of AFIO register is configured as 11b.

9). TIM2_CH1 and TIM2_ETR share a common pin, but cannot be used at the same time.