GD32VF103
Search
Reset
0x40012400
ADC0
// Analog to digital converter
0x40012400
STAT
// status register
[4]
STRC
(def=0x0) // Start flag of regular channel group
[3]
STIC
(def=0x0) // Start flag of inserted channel group
[2]
EOIC
(def=0x0) // End of inserted group conversion flag
[1]
EOC
(def=0x0) // End of group conversion flag
[0]
WDE
(def=0x0) // Analog watchdog event flag
0x40012404
CTL0
// control register 0
[23]
RWDEN
(def=0x0) // Regular channel analog watchdog enable
[22]
IWDEN
(def=0x0) // Inserted channel analog watchdog enable
[16:19]
SYNCM
(def=0x0) // sync mode selection
[13:15]
DISNUM
(def=0x0) // Number of conversions in discontinuous mode
[12]
DISIC
(def=0x0) // Discontinuous mode on inserted channels
[11]
DISRC
(def=0x0) // Discontinuous mode on regular channels
[10]
ICA
(def=0x0) // Inserted channel group convert automatically
[9]
WDSC
(def=0x0) // When in scan mode, analog watchdog is effective on a single channel
[8]
SM
(def=0x0) // Scan mode
[7]
EOICIE
(def=0x0) // Interrupt enable for EOIC
[6]
WDEIE
(def=0x0) // Interrupt enable for WDE
[5]
EOCIE
(def=0x0) // Interrupt enable for EOC
[0:4]
WDCHSEL
(def=0x0) // Analog watchdog channel select
0x40012408
CTL1
// control register 1
[23]
TSVREN
(def=0x0) // Channel 16 and 17 enable of ADC0
[22]
SWRCST
(def=0x0) // Start on regular channel
[21]
SWICST
(def=0x0) // Start on inserted channel
[20]
ETERC
(def=0x0) // External trigger enable for regular channel
[17:19]
ETSRC
(def=0x0) // External trigger select for regular channel
[15]
ETEIC
(def=0x0) // External trigger select for inserted channel
[12:14]
ETSIC
(def=0x0) // External trigger select for inserted channel
[11]
DAL
(def=0x0) // Data alignment
[8]
DMA
(def=0x0) // DMA request enable
[3]
RSTCLB
(def=0x0) // Reset calibration
[2]
CLB
(def=0x0) // ADC calibration
[1]
CTN
(def=0x0) // Continuous mode
[0]
ADCON
(def=0x0) // ADC on
0x4001240C
SAMPT0
// Sample time register 0
[0:2]
SPT10
(def=0x0) // Channel 10 sample time selection
[3:5]
SPT11
(def=0x0) // Channel 11 sample time selection
[6:8]
SPT12
(def=0x0) // Channel 12 sample time selection
[9:11]
SPT13
(def=0x0) // Channel 13 sample time selection
[12:14]
SPT14
(def=0x0) // Channel 14 sample time selection
[15:17]
SPT15
(def=0x0) // Channel 15 sample time selection
[18:20]
SPT16
(def=0x0) // Channel 16 sample time selection
[21:23]
SPT17
(def=0x0) // Channel 17 sample time selection
0x40012410
SAMPT1
// Sample time register 1
[0:2]
SPT0
(def=0x0) // Channel 0 sample time selection
[3:5]
SPT1
(def=0x0) // Channel 1 sample time selection
[6:8]
SPT2
(def=0x0) // Channel 2 sample time selection
[9:11]
SPT3
(def=0x0) // Channel 3 sample time selection
[12:14]
SPT4
(def=0x0) // Channel 4 sample time selection
[15:17]
SPT5
(def=0x0) // Channel 5 sample time selection
[18:20]
SPT6
(def=0x0) // Channel 6 sample time selection
[21:23]
SPT7
(def=0x0) // Channel 7 sample time selection
[24:26]
SPT8
(def=0x0) // Channel 8 sample time selection
[27:29]
SPT9
(def=0x0) // Channel 9 sample time selection
0x40012414
IOFF0
// Inserted channel data offset register 0
[0:11]
IOFF
(def=0x0) // Data offset for inserted channel 0
0x40012418
IOFF1
// Inserted channel data offset register 1
[0:11]
IOFF
(def=0x0) // Data offset for inserted channel 1
0x4001241C
IOFF2
// Inserted channel data offset register 2
[0:11]
IOFF
(def=0x0) // Data offset for inserted channel 2
0x40012420
IOFF3
// Inserted channel data offset register 3
[0:11]
IOFF
(def=0x0) // Data offset for inserted channel 3
0x40012424
WDHT
// watchdog higher threshold register
[0:11]
WDHT
(def=0xFFF) // Analog watchdog higher threshold
0x40012428
WDLT
// watchdog lower threshold register
[0:11]
WDLT
(def=0x0) // Analog watchdog lower threshold
0x4001242C
RSQ0
// regular sequence register 0
[20:23]
RL
(def=0x0) // Regular channel group length
[15:19]
RSQ15
(def=0x0) // 16th conversion in regular sequence
[10:14]
RSQ14
(def=0x0) // 15th conversion in regular sequence
[5:9]
RSQ13
(def=0x0) // 14th conversion in regular sequence
[0:4]
RSQ12
(def=0x0) // 13th conversion in regular sequence
0x40012430
RSQ1
// regular sequence register 1
[25:29]
RSQ11
(def=0x0) // 12th conversion in regular sequence
[20:24]
RSQ10
(def=0x0) // 11th conversion in regular sequence
[15:19]
RSQ9
(def=0x0) // 10th conversion in regular sequence
[10:14]
RSQ8
(def=0x0) // 9th conversion in regular sequence
[5:9]
RSQ7
(def=0x0) // 8th conversion in regular sequence
[0:4]
RSQ6
(def=0x0) // 7th conversion in regular sequence
0x40012434
RSQ2
// regular sequence register 2
[25:29]
RSQ5
(def=0x0) // 6th conversion in regular sequence
[20:24]
RSQ4
(def=0x0) // 5th conversion in regular sequence
[15:19]
RSQ3
(def=0x0) // 4th conversion in regular sequence
[10:14]
RSQ2
(def=0x0) // 3rd conversion in regular sequence
[5:9]
RSQ1
(def=0x0) // 2nd conversion in regular sequence
[0:4]
RSQ0
(def=0x0) // 1st conversion in regular sequence
0x40012438
ISQ
// Inserted sequence register
[20:21]
IL
(def=0x0) // Inserted channel group length
[15:19]
ISQ3
(def=0x0) // 4th conversion in inserted sequence
[10:14]
ISQ2
(def=0x0) // 3rd conversion in inserted sequence
[5:9]
ISQ1
(def=0x0) // 2nd conversion in inserted sequence
[0:4]
ISQ0
(def=0x0) // 1st conversion in inserted sequence
0x4001243C
IDATA0
// Inserted data register 0
[0:15]
IDATAn
(def=0x0) // Inserted number n conversion data
0x40012440
IDATA1
// Inserted data register 1
[0:15]
IDATAn
(def=0x0) // Inserted number n conversion data
0x40012444
IDATA2
// Inserted data register 2
[0:15]
IDATAn
(def=0x0) // Inserted number n conversion data
0x40012448
IDATA3
// Inserted data register 3
[0:15]
IDATAn
(def=0x0) // Inserted number n conversion data
0x4001244C
RDATA
// regular data register
[16:31]
ADC1RDTR
(def=0x0) // ADC regular channel data
[0:15]
RDATA
(def=0x0) // Regular channel data
0x40012480
OVSAMPCTL
// Oversample control register
[12:13]
DRES
(def=0x0) // ADC resolution
[9]
TOVS
(def=0x0) // Triggered Oversampling
[5:8]
OVSS
(def=0x0) // Oversampling shift
[2:4]
OVSR
(def=0x0) // Oversampling ratio
[0]
OVSEN
(def=0x0) // Oversampler Enable
interrupts:
[37]
ADC0_1
//
0x40012800
ADC1
// Analog to digital converter
0x40012800
STAT
// status register
[4]
STRC
(def=0x0) // Start flag of regular channel group
[3]
STIC
(def=0x0) // Start flag of inserted channel group
[2]
EOIC
(def=0x0) // End of inserted group conversion flag
[1]
EOC
(def=0x0) // End of group conversion flag
[0]
WDE
(def=0x0) // Analog watchdog event flag
0x40012804
CTL0
// control register 0
[23]
RWDEN
(def=0x0) // Regular channel analog watchdog enable
[22]
IWDEN
(def=0x0) // Inserted channel analog watchdog enable
[13:15]
DISNUM
(def=0x0) // Number of conversions in discontinuous mode
[12]
DISIC
(def=0x0) // Discontinuous mode on inserted channels
[11]
DISRC
(def=0x0) // Discontinuous mode on regular channels
[10]
ICA
(def=0x0) // Inserted channel group convert automatically
[9]
WDSC
(def=0x0) // When in scan mode, analog watchdog is effective on a single channel
[8]
SM
(def=0x0) // Scan mode
[7]
EOICIE
(def=0x0) // Interrupt enable for EOIC
[6]
WDEIE
(def=0x0) // Interrupt enable for WDE
[5]
EOCIE
(def=0x0) // Interrupt enable for EOC
[0:4]
WDCHSEL
(def=0x0) // Analog watchdog channel select
0x40012808
CTL1
// control register 1
[22]
SWRCST
(def=0x0) // Start on regular channel
[21]
SWICST
(def=0x0) // Start on inserted channel
[20]
ETERC
(def=0x0) // External trigger enable for regular channel
[17:19]
ETSRC
(def=0x0) // External trigger select for regular channel
[15]
ETEIC
(def=0x0) // External trigger enable for inserted channel
[12:14]
ETSIC
(def=0x0) // External trigger select for inserted channel
[11]
DAL
(def=0x0) // Data alignment
[8]
DMA
(def=0x0) // DMA request enable
[3]
RSTCLB
(def=0x0) // Reset calibration
[2]
CLB
(def=0x0) // ADC calibration
[1]
CTN
(def=0x0) // Continuous mode
[0]
ADCON
(def=0x0) // ADC on
0x4001280C
SAMPT0
// Sample time register 0
[0:2]
SPT10
(def=0x0) // Channel 10 sample time selection
[3:5]
SPT11
(def=0x0) // Channel 11 sample time selection
[6:8]
SPT12
(def=0x0) // Channel 12 sample time selection
[9:11]
SPT13
(def=0x0) // Channel 13 sample time selection
[12:14]
SPT14
(def=0x0) // Channel 14 sample time selection
[15:17]
SPT15
(def=0x0) // Channel 15 sample time selection
[18:20]
SPT16
(def=0x0) // Channel 16 sample time selection
[21:23]
SPT17
(def=0x0) // Channel 17 sample time selection
0x40012810
SAMPT1
// Sample time register 1
[0:2]
SPT0
(def=0x0) // Channel 0 sample time selection
[3:5]
SPT1
(def=0x0) // Channel 1 sample time selection
[6:8]
SPT2
(def=0x0) // Channel 2 sample time selection
[9:11]
SPT3
(def=0x0) // Channel 3 sample time selection
[12:14]
SPT4
(def=0x0) // Channel 4 sample time selection
[15:17]
SPT5
(def=0x0) // Channel 5 sample time selection
[18:20]
SPT6
(def=0x0) // Channel 6 sample time selection
[21:23]
SPT7
(def=0x0) // Channel 7 sample time selection
[24:26]
SPT8
(def=0x0) // Channel 8 sample time selection
[27:29]
SPT9
(def=0x0) // Channel 9 sample time selection
0x40012814
IOFF0
// Inserted channel data offset register 0
[0:11]
IOFF
(def=0x0) // Data offset for inserted channel 0
0x40012818
IOFF1
// Inserted channel data offset register 1
[0:11]
IOFF
(def=0x0) // Data offset for inserted channel 1
0x4001281C
IOFF2
// Inserted channel data offset register 2
[0:11]
IOFF
(def=0x0) // Data offset for inserted channel 2
0x40012820
IOFF3
// Inserted channel data offset register 3
[0:11]
IOFF
(def=0x0) // Data offset for inserted channel 3
0x40012824
WDHT
// watchdog higher threshold register
[0:11]
WDHT
(def=0xFFF) // Analog watchdog higher threshold
0x40012828
WDLT
// watchdog lower threshold register
[0:11]
WDLT
(def=0x0) // Analog watchdog lower threshold
0x4001282C
RSQ0
// regular sequence register 0
[20:23]
RL
(def=0x0) // Regular channel group length
[15:19]
RSQ15
(def=0x0) // 16th conversion in regular sequence
[10:14]
RSQ14
(def=0x0) // 15th conversion in regular sequence
[5:9]
RSQ13
(def=0x0) // 14th conversion in regular sequence
[0:4]
RSQ12
(def=0x0) // 13th conversion in regular sequence
0x40012830
RSQ1
// regular sequence register 1
[25:29]
RSQ11
(def=0x0) // 12th conversion in regular sequence
[20:24]
RSQ10
(def=0x0) // 11th conversion in regular sequence
[15:19]
RSQ9
(def=0x0) // 10th conversion in regular sequence
[10:14]
RSQ8
(def=0x0) // 9th conversion in regular sequence
[5:9]
RSQ7
(def=0x0) // 8th conversion in regular sequence
[0:4]
RSQ6
(def=0x0) // 7th conversion in regular sequence
0x40012834
RSQ2
// regular sequence register 2
[25:29]
RSQ5
(def=0x0) // 6th conversion in regular sequence
[20:24]
RSQ4
(def=0x0) // 5th conversion in regular sequence
[15:19]
RSQ3
(def=0x0) // 4th conversion in regular sequence
[10:14]
RSQ2
(def=0x0) // 3rd conversion in regular sequence
[5:9]
RSQ1
(def=0x0) // 2nd conversion in regular sequence
[0:4]
RSQ0
(def=0x0) // 1st conversion in regular sequence
0x40012838
ISQ
// Inserted sequence register
[20:21]
IL
(def=0x0) // Inserted channel group length
[15:19]
ISQ3
(def=0x0) // 4th conversion in inserted sequence
[10:14]
ISQ2
(def=0x0) // 3rd conversion in inserted sequence
[5:9]
ISQ1
(def=0x0) // 2nd conversion in inserted sequence
[0:4]
ISQ0
(def=0x0) // 1st conversion in inserted sequence
0x4001283C
IDATA0
// Inserted data register 0
[0:15]
IDATAn
(def=0x0) // Inserted number n conversion data
0x40012840
IDATA1
// Inserted data register 1
[0:15]
IDATAn
(def=0x0) // Inserted number n conversion data
0x40012844
IDATA2
// Inserted data register 2
[0:15]
IDATAn
(def=0x0) // Inserted number n conversion data
0x40012848
IDATA3
// Inserted data register 3
[0:15]
IDATAn
(def=0x0) // Inserted number n conversion data
0x4001284C
RDATA
// regular data register
[0:15]
RDATA
(def=0x0) // Regular channel data
interrupts:
[37]
ADC0_1
//
0x40010000
AFIO
// Alternate-function I/Os
0x40010000
EC
// Event control register
[7]
EOE
(def=0x0) // Event output enable
[4:6]
PORT
(def=0x0) // Event output port selection
[0:3]
PIN
(def=0x0) // Event output pin selection
0x40010004
PCF0
// AFIO port configuration register 0
[29]
TIMER1ITI1_REMAP
(def=0x0) // TIMER1 internal trigger 1 remapping
[28]
SPI2_REMAP
(def=0x0) // SPI2/I2S2 remapping
[24:26]
SWJ_CFG
(def=0x0) // Serial wire JTAG configuration
[22]
CAN1_REMAP
(def=0x0) // CAN1 I/O remapping
[16]
TIMER4CH3_IREMAP
(def=0x0) // TIMER4 channel3 internal remapping
[15]
PD01_REMAP
(def=0x0) // Port D0/Port D1 mapping on OSC_IN/OSC_OUT
[13:14]
CAN0_REMAP
(def=0x0) // CAN0 alternate interface remapping
[12]
TIMER3_REMAP
(def=0x0) // TIMER3 remapping
[10:11]
TIMER2_REMAP
(def=0x0) // TIMER2 remapping
[8:9]
TIMER1_REMAP
(def=0x0) // TIMER1 remapping
[6:7]
TIMER0_REMAP
(def=0x0) // TIMER0 remapping
[4:5]
USART2_REMAP
(def=0x0) // USART2 remapping
[3]
USART1_REMAP
(def=0x0) // USART1 remapping
[2]
USART0_REMAP
(def=0x0) // USART0 remapping
[1]
I2C0_REMAP
(def=0x0) // I2C0 remapping
[0]
SPI0_REMAP
(def=0x0) // SPI0 remapping
0x40010008
EXTISS0
// EXTI sources selection register 0
[12:15]
EXTI3_SS
(def=0x0) // EXTI 3 sources selection
[8:11]
EXTI2_SS
(def=0x0) // EXTI 2 sources selection
[4:7]
EXTI1_SS
(def=0x0) // EXTI 1 sources selection
[0:3]
EXTI0_SS
(def=0x0) // EXTI 0 sources selection
0x4001000C
EXTISS1
// EXTI sources selection register 1
[12:15]
EXTI7_SS
(def=0x0) // EXTI 7 sources selection
[8:11]
EXTI6_SS
(def=0x0) // EXTI 6 sources selection
[4:7]
EXTI5_SS
(def=0x0) // EXTI 5 sources selection
[0:3]
EXTI4_SS
(def=0x0) // EXTI 4 sources selection
0x40010010
EXTISS2
// EXTI sources selection register 2
[12:15]
EXTI11_SS
(def=0x0) // EXTI 11 sources selection
[8:11]
EXTI10_SS
(def=0x0) // EXTI 10 sources selection
[4:7]
EXTI9_SS
(def=0x0) // EXTI 9 sources selection
[0:3]
EXTI8_SS
(def=0x0) // EXTI 8 sources selection
0x40010014
EXTISS3
// EXTI sources selection register 3
[12:15]
EXTI15_SS
(def=0x0) // EXTI 15 sources selection
[8:11]
EXTI14_SS
(def=0x0) // EXTI 14 sources selection
[4:7]
EXTI13_SS
(def=0x0) // EXTI 13 sources selection
[0:3]
EXTI12_SS
(def=0x0) // EXTI 12 sources selection
0x4001001C
PCF1
// AFIO port configuration register 1
[10]
EXMC_NADV
(def=0x0) // EXMC_NADV connect/disconnect
0x40006C00
BKP
// Backup registers
0x40006C04
DATA0
// Backup data register 0
[0:15]
DATA
(def=0x0) // Backup data
0x40006C08
DATA1
// Backup data register 1
[0:15]
DATA
(def=0x0) // Backup data
0x40006C0C
DATA2
// Backup data register 2
[0:15]
DATA
(def=0x0) // Backup data
0x40006C10
DATA3
// Backup data register 3
[0:15]
DATA
(def=0x0) // Backup data
0x40006C14
DATA4
// Backup data register 4
[0:15]
DATA
(def=0x0) // Backup data
0x40006C18
DATA5
// Backup data register 5
[0:15]
DATA
(def=0x0) // Backup data
0x40006C1C
DATA6
// Backup data register 6
[0:15]
DATA
(def=0x0) // Backup data
0x40006C20
DATA7
// Backup data register 7
[0:15]
DATA
(def=0x0) // Backup data
0x40006C24
DATA8
// Backup data register 8
[0:15]
DATA
(def=0x0) // Backup data
0x40006C28
DATA9
// Backup data register 9
[0:15]
DATA
(def=0x0) // Backup data
0x40006C40
DATA10
// Backup data register 10
[0:15]
DATA
(def=0x0) // Backup data
0x40006C44
DATA11
// Backup data register 11
[0:15]
DATA
(def=0x0) // Backup data
0x40006C48
DATA12
// Backup data register 12
[0:15]
DATA
(def=0x0) // Backup data
0x40006C4C
DATA13
// Backup data register 13
[0:15]
DATA
(def=0x0) // Backup data
0x40006C50
DATA14
// Backup data register 14
[0:15]
DATA
(def=0x0) // Backup data
0x40006C54
DATA15
// Backup data register 15
[0:15]
DATA
(def=0x0) // Backup data
0x40006C58
DATA16
// Backup data register 16
[0:15]
DATA
(def=0x0) // Backup data
0x40006C5C
DATA17
// Backup data register 17
[0:15]
DATA
(def=0x0) // Backup data
0x40006C60
DATA18
// Backup data register 18
[0:15]
DATA
(def=0x0) // Backup data
0x40006C64
DATA19
// Backup data register 19
[0:15]
DATA
(def=0x0) // Backup data
0x40006C68
DATA20
// Backup data register 20
[0:15]
DATA
(def=0x0) // Backup data
0x40006C6C
DATA21
// Backup data register 21
[0:15]
DATA
(def=0x0) // Backup data
0x40006C70
DATA22
// Backup data register 22
[0:15]
DATA
(def=0x0) // Backup data
0x40006C74
DATA23
// Backup data register 23
[0:15]
DATA
(def=0x0) // Backup data
0x40006C78
DATA24
// Backup data register 24
[0:15]
DATA
(def=0x0) // Backup data
0x40006C7C
DATA25
// Backup data register 25
[0:15]
DATA
(def=0x0) // Backup data
0x40006C80
DATA26
// Backup data register 26
[0:15]
DATA
(def=0x0) // Backup data
0x40006C84
DATA27
// Backup data register 27
[0:15]
DATA
(def=0x0) // Backup data
0x40006C88
DATA28
// Backup data register 28
[0:15]
DATA
(def=0x0) // Backup data
0x40006C8C
DATA29
// Backup data register 29
[0:15]
DATA
(def=0x0) // Backup data
0x40006C90
DATA30
// Backup data register 30
[0:15]
DATA
(def=0x0) // Backup data
0x40006C94
DATA31
// Backup data register 31
[0:15]
DATA
(def=0x0) // Backup data
0x40006C98
DATA32
// Backup data register 32
[0:15]
DATA
(def=0x0) // Backup data
0x40006C9C
DATA33
// Backup data register 33
[0:15]
DATA
(def=0x0) // Backup data
0x40006CA0
DATA34
// Backup data register 34
[0:15]
DATA
(def=0x0) // Backup data
0x40006CA4
DATA35
// Backup data register 35
[0:15]
DATA
(def=0x0) // Backup data
0x40006CA8
DATA36
// Backup data register 36
[0:15]
DATA
(def=0x0) // Backup data
0x40006CAC
DATA37
// Backup data register 37
[0:15]
DATA
(def=0x0) // Backup data
0x40006CB0
DATA38
// Backup data register 38
[0:15]
DATA
(def=0x0) // Backup data
0x40006CB4
DATA39
// Backup data register 39
[0:15]
DATA
(def=0x0) // Backup data
0x40006CB8
DATA40
// Backup data register 40
[0:15]
DATA
(def=0x0) // Backup data
0x40006CBC
DATA41
// Backup data register 41
[0:15]
DATA
(def=0x0) // Backup data
0x40006C2C
OCTL
// RTC signal output control register
[9]
ROSEL
(def=0x0) // RTC output selection
[8]
ASOEN
(def=0x0) // RTC alarm or second signal output enable
[7]
COEN
(def=0x0) // RTC clock calibration output enable
[0:6]
RCCV
(def=0x0) // RTC clock calibration value
0x40006C30
TPCTL
// Tamper pin control register
[1]
TPAL
(def=0x0) // TAMPER pin active level
[0]
TPEN
(def=0x0) // TAMPER detection enable
0x40006C34
TPCS
// Tamper control and status register
[9]
TIF
(def=0x0) // Tamper interrupt flag
[8]
TEF
(def=0x0) // Tamper event flag
[2]
TPIE
(def=0x0) // Tamper interrupt enable
[1]
TIR
(def=0x0) // Tamper interrupt reset
[0]
TER
(def=0x0) // Tamper event reset
interrupts:
[21]
Tamper
//
0x40006400
CAN0
// Controller area network
0x40006400
CTL
// Control register
[16]
DFZ
(def=0x1) // Debug freeze
[15]
SWRST
(def=0x0) // Software reset
[7]
TTC
(def=0x0) // Time-triggered communication
[6]
ABOR
(def=0x0) // Automatic bus-off recovery
[5]
AWU
(def=0x0) // Automatic wakeup
[4]
ARD
(def=0x0) // Automatic retransmission disable
[3]
RFOD
(def=0x0) // Receive FIFO overwrite disable
[2]
TFO
(def=0x0) // Transmit FIFO order
[1]
SLPWMOD
(def=0x1) // Sleep working mode
[0]
IWMOD
(def=0x0) // Initial working mode
0x40006404
STAT
// Status register
[11]
RXL
(def=0x1) // RX level
[10]
LASTRX
(def=0x1) // Last sample value of RX pin
[9]
RS
(def=0x0) // Receiving state
[8]
TS
(def=0x0) // Transmitting state
[4]
SLPIF
(def=0x0) // Status change interrupt flag of sleep working mode entering
[3]
WUIF
(def=0x0) // Status change interrupt flag of wakeup from sleep working mode
[2]
ERRIF
(def=0x0) // Error interrupt flag
[1]
SLPWS
(def=0x1) // Sleep working state
[0]
IWS
(def=0x0) // Initial working state
0x40006408
TSTAT
// Transmit status register
[31]
TMLS2
(def=0x0) // Transmit mailbox 2 last sending in transmit FIFO
[30]
TMLS1
(def=0x0) // Transmit mailbox 1 last sending in transmit FIFO
[29]
TMLS0
(def=0x0) // Transmit mailbox 0 last sending in transmit FIFO
[28]
TME2
(def=0x1) // Transmit mailbox 2 empty
[27]
TME1
(def=0x1) // Transmit mailbox 1 empty
[26]
TME0
(def=0x1) // Transmit mailbox 0 empty
[24:25]
NUM
(def=0x0) // number of the transmit FIFO mailbox in which the frame will be transmitted if at least one m
[23]
MST2
(def=0x0) // Mailbox 2 stop transmitting
[19]
MTE2
(def=0x0) // Mailbox 2 transmit error
[18]
MAL2
(def=0x0) // Mailbox 2 arbitration lost
[17]
MTFNERR2
(def=0x0) // Mailbox 2 transmit finished and no error
[16]
MTF2
(def=0x0) // Mailbox 2 transmit finished
[15]
MST1
(def=0x0) // Mailbox 1 stop transmitting
[11]
MTE1
(def=0x0) // Mailbox 1 transmit error
[10]
MAL1
(def=0x0) // Mailbox 1 arbitration lost
[9]
MTFNERR1
(def=0x0) // Mailbox 1 transmit finished and no error
[8]
MTF1
(def=0x0) // Mailbox 1 transmit finished
[7]
MST0
(def=0x0) // Mailbox 0 stop transmitting
[3]
MTE0
(def=0x0) // Mailbox 0 transmit error
[2]
MAL0
(def=0x0) // Mailbox 0 arbitration lost
[1]
MTFNERR0
(def=0x0) // Mailbox 0 transmit finished and no error
[0]
MTF0
(def=0x0) // Mailbox 0 transmit finished
0x4000640C
RFIFO0
// Receive message FIFO0 register
[5]
RFD0
(def=0x0) // Receive FIFO0 dequeue
[4]
RFO0
(def=0x0) // Receive FIFO0 overfull
[3]
RFF0
(def=0x0) // Receive FIFO0 full
[0:1]
RFL0
(def=0x0) // Receive FIFO0 length
0x40006410
RFIFO1
// Receive message FIFO1 register
[5]
RFD1
(def=0x0) // Receive FIFO1 dequeue
[4]
RFO1
(def=0x0) // Receive FIFO1 overfull
[3]
RFF1
(def=0x0) // Receive FIFO1 full
[0:1]
RFL1
(def=0x0) // Receive FIFO1 length
0x40006414
INTEN
// Interrupt enable register
[17]
SLPWIE
(def=0x0) // Sleep working interrupt enable
[16]
WIE
(def=0x0) // Wakeup interrupt enable
[15]
ERRIE
(def=0x0) // Error interrupt enable
[11]
ERRNIE
(def=0x0) // Error number interrupt enable
[10]
BOIE
(def=0x0) // Bus-off interrupt enable
[9]
PERRIE
(def=0x0) // Passive error interrupt enable
[8]
WERRIE
(def=0x0) // Warning error interrupt enable
[6]
RFOIE1
(def=0x0) // Receive FIFO1 overfull interrupt enable
[5]
RFFIE1
(def=0x0) // Receive FIFO1 full interrupt enable
[4]
RFNEIE1
(def=0x0) // Receive FIFO1 not empty interrupt enable
[3]
RFOIE0
(def=0x0) // Receive FIFO0 overfull interrupt enable
[2]
RFFIE0
(def=0x0) // Receive FIFO0 full interrupt enable
[1]
RFNEIE0
(def=0x0) // Receive FIFO0 not empty interrupt enable
[0]
TMEIE
(def=0x0) // Transmit mailbox empty interrupt enable
0x40006418
ERR
// Error register
[24:31]
RECNT
(def=0x0) // Receive Error Count defined by the CAN standard
[16:23]
TECNT
(def=0x0) // Transmit Error Count defined by the CAN standard
[4:6]
ERRN
(def=0x0) // Error number
[2]
BOERR
(def=0x0) // Bus-off error
[1]
PERR
(def=0x0) // Passive error
[0]
WERR
(def=0x0) // Warning error
0x4000641C
BT
// Bit timing register
[31]
SCMOD
(def=0x0) // Silent communication mode
[30]
LCMOD
(def=0x0) // Loopback communication mode
[24:25]
SJW
(def=0x1) // Resynchronization jump width
[20:22]
BS2
(def=0x2) // Bit segment 2
[16:19]
BS1
(def=0x3) // Bit segment 1
[0:9]
BAUDPSC
(def=0x0) // Baud rate prescaler
0x40006580
TMI0
// Transmit mailbox identifier register 0
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
[0]
TEN
(def=0x0) // Transmit enable
0x40006584
TMP0
// Transmit mailbox property register 0
[16:31]
TS
(def=0x0) // Time stamp
[8]
TSEN
(def=0x0) // Time stamp enable
[0:3]
DLENC
(def=0x0) // Data length code
0x40006588
TMDATA00
// Transmit mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x4000658C
TMDATA10
// Transmit mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x40006590
TMI1
// Transmit mailbox identifier register 1
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
[0]
TEN
(def=0x0) // Transmit enable
0x40006594
TMP1
// Transmit mailbox property register 1
[16:31]
TS
(def=0x0) // Time stamp
[8]
TSEN
(def=0x0) // Time stamp enable
[0:3]
DLENC
(def=0x0) // Data length code
0x40006598
TMDATA01
// Transmit mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x4000659C
TMDATA11
// Transmit mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x400065A0
TMI2
// Transmit mailbox identifier register 2
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
[0]
TEN
(def=0x0) // Transmit enable
0x400065A4
TMP2
// Transmit mailbox property register 2
[16:31]
TS
(def=0x0) // Time stamp
[8]
TSEN
(def=0x0) // Time stamp enable
[0:3]
DLENC
(def=0x0) // Data length code
0x400065A8
TMDATA02
// Transmit mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x400065AC
TMDATA12
// Transmit mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x400065B0
RFIFOMI0
// Receive FIFO mailbox identifier register
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
0x400065B4
RFIFOMP0
// Receive FIFO0 mailbox property register
[16:31]
TS
(def=0x0) // Time stamp
[8:15]
FI
(def=0x0) // Filtering index
[0:3]
DLENC
(def=0x0) // Data length code
0x400065B8
RFIFOMDATA00
// Receive FIFO0 mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x400065BC
RFIFOMDATA10
// Receive FIFO0 mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x400065C0
RFIFOMI1
// Receive FIFO1 mailbox identifier register
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
0x400065C4
RFIFOMP1
// Receive FIFO1 mailbox property register
[16:31]
TS
(def=0x0) // Time stamp
[8:15]
FI
(def=0x0) // Filtering index
[0:3]
DLENC
(def=0x0) // Data length code
0x400065C8
RFIFOMDATA01
// Receive FIFO1 mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x400065CC
RFIFOMDATA11
// Receive FIFO1 mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x40006600
FCTL
// Filter control register
[8:13]
HBC1F
(def=0xE) // Header bank of CAN1 filter
[0]
FLD
(def=0x1) // Filter lock disable
0x40006604
FMCFG
// Filter mode configuration register
[27]
FMOD27
(def=0x0) // Filter mode
[26]
FMOD26
(def=0x0) // Filter mode
[25]
FMOD25
(def=0x0) // Filter mode
[24]
FMOD24
(def=0x0) // Filter mode
[23]
FMOD23
(def=0x0) // Filter mode
[22]
FMOD22
(def=0x0) // Filter mode
[21]
FMOD21
(def=0x0) // Filter mode
[20]
FMOD20
(def=0x0) // Filter mode
[19]
FMOD19
(def=0x0) // Filter mode
[18]
FMOD18
(def=0x0) // Filter mode
[17]
FMOD17
(def=0x0) // Filter mode
[16]
FMOD16
(def=0x0) // Filter mode
[15]
FMOD15
(def=0x0) // Filter mode
[14]
FMOD14
(def=0x0) // Filter mode
[13]
FMOD13
(def=0x0) // Filter mode
[12]
FMOD12
(def=0x0) // Filter mode
[11]
FMOD11
(def=0x0) // Filter mode
[10]
FMOD10
(def=0x0) // Filter mode
[9]
FMOD9
(def=0x0) // Filter mode
[8]
FMOD8
(def=0x0) // Filter mode
[7]
FMOD7
(def=0x0) // Filter mode
[6]
FMOD6
(def=0x0) // Filter mode
[5]
FMOD5
(def=0x0) // Filter mode
[4]
FMOD4
(def=0x0) // Filter mode
[3]
FMOD3
(def=0x0) // Filter mode
[2]
FMOD2
(def=0x0) // Filter mode
[1]
FMOD1
(def=0x0) // Filter mode
[0]
FMOD0
(def=0x0) // Filter mode
0x4000660C
FSCFG
// Filter scale configuration register
[0]
FS0
(def=0x0) // Filter scale configuration
[1]
FS1
(def=0x0) // Filter scale configuration
[2]
FS2
(def=0x0) // Filter scale configuration
[3]
FS3
(def=0x0) // Filter scale configuration
[4]
FS4
(def=0x0) // Filter scale configuration
[5]
FS5
(def=0x0) // Filter scale configuration
[6]
FS6
(def=0x0) // Filter scale configuration
[7]
FS7
(def=0x0) // Filter scale configuration
[8]
FS8
(def=0x0) // Filter scale configuration
[9]
FS9
(def=0x0) // Filter scale configuration
[10]
FS10
(def=0x0) // Filter scale configuration
[11]
FS11
(def=0x0) // Filter scale configuration
[12]
FS12
(def=0x0) // Filter scale configuration
[13]
FS13
(def=0x0) // Filter scale configuration
[14]
FS14
(def=0x0) // Filter scale configuration
[15]
FS15
(def=0x0) // Filter scale configuration
[16]
FS16
(def=0x0) // Filter scale configuration
[17]
FS17
(def=0x0) // Filter scale configuration
[18]
FS18
(def=0x0) // Filter scale configuration
[19]
FS19
(def=0x0) // Filter scale configuration
[20]
FS20
(def=0x0) // Filter scale configuration
[21]
FS21
(def=0x0) // Filter scale configuration
[22]
FS22
(def=0x0) // Filter scale configuration
[23]
FS23
(def=0x0) // Filter scale configuration
[24]
FS24
(def=0x0) // Filter scale configuration
[25]
FS25
(def=0x0) // Filter scale configuration
[26]
FS26
(def=0x0) // Filter scale configuration
[27]
FS27
(def=0x0) // Filter scale configuration
0x40006614
FAFIFO
// Filter associated FIFO register
[0]
FAF0
(def=0x0) // Filter 0 associated with FIFO
[1]
FAF1
(def=0x0) // Filter 1 associated with FIFO
[2]
FAF2
(def=0x0) // Filter 2 associated with FIFO
[3]
FAF3
(def=0x0) // Filter 3 associated with FIFO
[4]
FAF4
(def=0x0) // Filter 4 associated with FIFO
[5]
FAF5
(def=0x0) // Filter 5 associated with FIFO
[6]
FAF6
(def=0x0) // Filter 6 associated with FIFO
[7]
FAF7
(def=0x0) // Filter 7 associated with FIFO
[8]
FAF8
(def=0x0) // Filter 8 associated with FIFO
[9]
FAF9
(def=0x0) // Filter 9 associated with FIFO
[10]
FAF10
(def=0x0) // Filter 10 associated with FIFO
[11]
FAF11
(def=0x0) // Filter 11 associated with FIFO
[12]
FAF12
(def=0x0) // Filter 12 associated with FIFO
[13]
FAF13
(def=0x0) // Filter 13 associated with FIFO
[14]
FAF14
(def=0x0) // Filter 14 associated with FIFO
[15]
FAF15
(def=0x0) // Filter 15 associated with FIFO
[16]
FAF16
(def=0x0) // Filter 16 associated with FIFO
[17]
FAF17
(def=0x0) // Filter 17 associated with FIFO
[18]
FAF18
(def=0x0) // Filter 18 associated with FIFO
[19]
FAF19
(def=0x0) // Filter 19 associated with FIFO
[20]
FAF20
(def=0x0) // Filter 20 associated with FIFO
[21]
FAF21
(def=0x0) // Filter 21 associated with FIFO
[22]
FAF22
(def=0x0) // Filter 22 associated with FIFO
[23]
FAF23
(def=0x0) // Filter 23 associated with FIFO
[24]
FAF24
(def=0x0) // Filter 24 associated with FIFO
[25]
FAF25
(def=0x0) // Filter 25 associated with FIFO
[26]
FAF26
(def=0x0) // Filter 26 associated with FIFO
[27]
FAF27
(def=0x0) // Filter 27 associated with FIFO
0x4000661C
FW
// Filter working register
[0]
FW0
(def=0x0) // Filter working
[1]
FW1
(def=0x0) // Filter working
[2]
FW2
(def=0x0) // Filter working
[3]
FW3
(def=0x0) // Filter working
[4]
FW4
(def=0x0) // Filter working
[5]
FW5
(def=0x0) // Filter working
[6]
FW6
(def=0x0) // Filter working
[7]
FW7
(def=0x0) // Filter working
[8]
FW8
(def=0x0) // Filter working
[9]
FW9
(def=0x0) // Filter working
[10]
FW10
(def=0x0) // Filter working
[11]
FW11
(def=0x0) // Filter working
[12]
FW12
(def=0x0) // Filter working
[13]
FW13
(def=0x0) // Filter working
[14]
FW14
(def=0x0) // Filter working
[15]
FW15
(def=0x0) // Filter working
[16]
FW16
(def=0x0) // Filter working
[17]
FW17
(def=0x0) // Filter working
[18]
FW18
(def=0x0) // Filter working
[19]
FW19
(def=0x0) // Filter working
[20]
FW20
(def=0x0) // Filter working
[21]
FW21
(def=0x0) // Filter working
[22]
FW22
(def=0x0) // Filter working
[23]
FW23
(def=0x0) // Filter working
[24]
FW24
(def=0x0) // Filter working
[25]
FW25
(def=0x0) // Filter working
[26]
FW26
(def=0x0) // Filter working
[27]
FW27
(def=0x0) // Filter working
0x40006640
F0DATA0
// Filter 0 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006644
F0DATA1
// Filter 0 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006648
F1DATA0
// Filter 1 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x4000664C
F1DATA1
// Filter 1 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006650
F2DATA0
// Filter 2 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006654
F2DATA1
// Filter 2 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006658
F3DATA0
// Filter 3 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x4000665C
F3DATA1
// Filter 3 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006660
F4DATA0
// Filter 4 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006664
F4DATA1
// Filter 4 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006668
F5DATA0
// Filter 5 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x4000666C
F5DATA1
// Filter 5 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006670
F6DATA0
// Filter 6 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006674
F6DATA1
// Filter 6 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006678
F7DATA0
// Filter 7 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x4000667C
F7DATA1
// Filter 7 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006680
F8DATA0
// Filter 8 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006684
F8DATA1
// Filter 8 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006688
F9DATA0
// Filter 9 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x4000668C
F9DATA1
// Filter 9 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006690
F10DATA0
// Filter 10 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006694
F10DATA1
// Filter 10 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006698
F11DATA0
// Filter 11 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x4000669C
F11DATA1
// Filter 11 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066A0
F12DATA0
// Filter 12 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066A4
F12DATA1
// Filter 12 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066A8
F13DATA0
// Filter 13 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066AC
F13DATA1
// Filter 13 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066B0
F14DATA0
// Filter 14 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066B4
F14DATA1
// Filter 14 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066B8
F15DATA0
// Filter 15 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066BC
F15DATA1
// Filter 15 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066C0
F16DATA0
// Filter 16 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066C4
F16DATA1
// Filter 16 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066C8
F17DATA0
// Filter 17 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066CC
F17DATA1
// Filter 17 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066D0
F18DATA0
// Filter 18 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066D4
F18DATA1
// Filter 18 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066D8
F19DATA0
// Filter 19 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066DC
F19DATA1
// Filter 19 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066E0
F20DATA0
// Filter 20 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066E4
F20DATA1
// Filter 20 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066E8
F21DATA0
// Filter 21 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066EC
F21DATA1
// Filter 21 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066F0
F22DATA0
// Filter 22 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066F4
F22DATA1
// Filter 22 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066F8
F23DATA0
// Filter 23 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x400066FC
F23DATA1
// Filter 23 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006700
F24DATA0
// Filter 24 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006704
F24DATA1
// Filter 24 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006708
F25DATA0
// Filter 25 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x4000670C
F25DATA1
// Filter 25 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006710
F26DATA0
// Filter 26 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006714
F26DATA1
// Filter 26 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006718
F27DATA0
// Filter 27 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x4000671C
F27DATA1
// Filter 27 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
interrupts:
[38]
CAN0_TX
//
[39]
CAN0_RX0
//
[40]
CAN0_RX1
//
[41]
CAN0_EWMC
//
0x40006800
CAN1
//
0x40006800
CTL
// Control register
[16]
DFZ
(def=0x1) // Debug freeze
[15]
SWRST
(def=0x0) // Software reset
[7]
TTC
(def=0x0) // Time-triggered communication
[6]
ABOR
(def=0x0) // Automatic bus-off recovery
[5]
AWU
(def=0x0) // Automatic wakeup
[4]
ARD
(def=0x0) // Automatic retransmission disable
[3]
RFOD
(def=0x0) // Receive FIFO overwrite disable
[2]
TFO
(def=0x0) // Transmit FIFO order
[1]
SLPWMOD
(def=0x1) // Sleep working mode
[0]
IWMOD
(def=0x0) // Initial working mode
0x40006804
STAT
// Status register
[11]
RXL
(def=0x1) // RX level
[10]
LASTRX
(def=0x1) // Last sample value of RX pin
[9]
RS
(def=0x0) // Receiving state
[8]
TS
(def=0x0) // Transmitting state
[4]
SLPIF
(def=0x0) // Status change interrupt flag of sleep working mode entering
[3]
WUIF
(def=0x0) // Status change interrupt flag of wakeup from sleep working mode
[2]
ERRIF
(def=0x0) // Error interrupt flag
[1]
SLPWS
(def=0x1) // Sleep working state
[0]
IWS
(def=0x0) // Initial working state
0x40006808
TSTAT
// Transmit status register
[31]
TMLS2
(def=0x0) // Transmit mailbox 2 last sending in transmit FIFO
[30]
TMLS1
(def=0x0) // Transmit mailbox 1 last sending in transmit FIFO
[29]
TMLS0
(def=0x0) // Transmit mailbox 0 last sending in transmit FIFO
[28]
TME2
(def=0x1) // Transmit mailbox 2 empty
[27]
TME1
(def=0x1) // Transmit mailbox 1 empty
[26]
TME0
(def=0x1) // Transmit mailbox 0 empty
[24:25]
NUM
(def=0x0) // number of the transmit FIFO mailbox in which the frame will be transmitted if at least one m
[23]
MST2
(def=0x0) // Mailbox 2 stop transmitting
[19]
MTE2
(def=0x0) // Mailbox 2 transmit error
[18]
MAL2
(def=0x0) // Mailbox 2 arbitration lost
[17]
MTFNERR2
(def=0x0) // Mailbox 2 transmit finished and no error
[16]
MTF2
(def=0x0) // Mailbox 2 transmit finished
[15]
MST1
(def=0x0) // Mailbox 1 stop transmitting
[11]
MTE1
(def=0x0) // Mailbox 1 transmit error
[10]
MAL1
(def=0x0) // Mailbox 1 arbitration lost
[9]
MTFNERR1
(def=0x0) // Mailbox 1 transmit finished and no error
[8]
MTF1
(def=0x0) // Mailbox 1 transmit finished
[7]
MST0
(def=0x0) // Mailbox 0 stop transmitting
[3]
MTE0
(def=0x0) // Mailbox 0 transmit error
[2]
MAL0
(def=0x0) // Mailbox 0 arbitration lost
[1]
MTFNERR0
(def=0x0) // Mailbox 0 transmit finished and no error
[0]
MTF0
(def=0x0) // Mailbox 0 transmit finished
0x4000680C
RFIFO0
// Receive message FIFO0 register
[5]
RFD0
(def=0x0) // Receive FIFO0 dequeue
[4]
RFO0
(def=0x0) // Receive FIFO0 overfull
[3]
RFF0
(def=0x0) // Receive FIFO0 full
[0:1]
RFL0
(def=0x0) // Receive FIFO0 length
0x40006810
RFIFO1
// Receive message FIFO1 register
[5]
RFD1
(def=0x0) // Receive FIFO1 dequeue
[4]
RFO1
(def=0x0) // Receive FIFO1 overfull
[3]
RFF1
(def=0x0) // Receive FIFO1 full
[0:1]
RFL1
(def=0x0) // Receive FIFO1 length
0x40006814
INTEN
// Interrupt enable register
[17]
SLPWIE
(def=0x0) // Sleep working interrupt enable
[16]
WIE
(def=0x0) // Wakeup interrupt enable
[15]
ERRIE
(def=0x0) // Error interrupt enable
[11]
ERRNIE
(def=0x0) // Error number interrupt enable
[10]
BOIE
(def=0x0) // Bus-off interrupt enable
[9]
PERRIE
(def=0x0) // Passive error interrupt enable
[8]
WERRIE
(def=0x0) // Warning error interrupt enable
[6]
RFOIE1
(def=0x0) // Receive FIFO1 overfull interrupt enable
[5]
RFFIE1
(def=0x0) // Receive FIFO1 full interrupt enable
[4]
RFNEIE1
(def=0x0) // Receive FIFO1 not empty interrupt enable
[3]
RFOIE0
(def=0x0) // Receive FIFO0 overfull interrupt enable
[2]
RFFIE0
(def=0x0) // Receive FIFO0 full interrupt enable
[1]
RFNEIE0
(def=0x0) // Receive FIFO0 not empty interrupt enable
[0]
TMEIE
(def=0x0) // Transmit mailbox empty interrupt enable
0x40006818
ERR
// Error register
[24:31]
RECNT
(def=0x0) // Receive Error Count defined by the CAN standard
[16:23]
TECNT
(def=0x0) // Transmit Error Count defined by the CAN standard
[4:6]
ERRN
(def=0x0) // Error number
[2]
BOERR
(def=0x0) // Bus-off error
[1]
PERR
(def=0x0) // Passive error
[0]
WERR
(def=0x0) // Warning error
0x4000681C
BT
// Bit timing register
[31]
SCMOD
(def=0x0) // Silent communication mode
[30]
LCMOD
(def=0x0) // Loopback communication mode
[24:25]
SJW
(def=0x1) // Resynchronization jump width
[20:22]
BS2
(def=0x2) // Bit segment 2
[16:19]
BS1
(def=0x3) // Bit segment 1
[0:9]
BAUDPSC
(def=0x0) // Baud rate prescaler
0x40006980
TMI0
// Transmit mailbox identifier register 0
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
[0]
TEN
(def=0x0) // Transmit enable
0x40006984
TMP0
// Transmit mailbox property register 0
[16:31]
TS
(def=0x0) // Time stamp
[8]
TSEN
(def=0x0) // Time stamp enable
[0:3]
DLENC
(def=0x0) // Data length code
0x40006988
TMDATA00
// Transmit mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x4000698C
TMDATA10
// Transmit mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x40006990
TMI1
// Transmit mailbox identifier register 1
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
[0]
TEN
(def=0x0) // Transmit enable
0x40006994
TMP1
// Transmit mailbox property register 1
[16:31]
TS
(def=0x0) // Time stamp
[8]
TSEN
(def=0x0) // Time stamp enable
[0:3]
DLENC
(def=0x0) // Data length code
0x40006998
TMDATA01
// Transmit mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x4000699C
TMDATA11
// Transmit mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x400069A0
TMI2
// Transmit mailbox identifier register 2
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
[0]
TEN
(def=0x0) // Transmit enable
0x400069A4
TMP2
// Transmit mailbox property register 2
[16:31]
TS
(def=0x0) // Time stamp
[8]
TSEN
(def=0x0) // Time stamp enable
[0:3]
DLENC
(def=0x0) // Data length code
0x400069A8
TMDATA02
// Transmit mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x400069AC
TMDATA12
// Transmit mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x400069B0
RFIFOMI0
// Receive FIFO mailbox identifier register
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
0x400069B4
RFIFOMP0
// Receive FIFO0 mailbox property register
[16:31]
TS
(def=0x0) // Time stamp
[8:15]
FI
(def=0x0) // Filtering index
[0:3]
DLENC
(def=0x0) // Data length code
0x400069B8
RFIFOMDATA00
// Receive FIFO0 mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x400069BC
RFIFOMDATA10
// Receive FIFO0 mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x400069C0
RFIFOMI1
// Receive FIFO1 mailbox identifier register
[21:31]
SFID_EFID
(def=0x0) // The frame identifier
[3:20]
EFID
(def=0x0) // The frame identifier
[2]
FF
(def=0x0) // Frame format
[1]
FT
(def=0x0) // Frame type
0x400069C4
RFIFOMP1
// Receive FIFO1 mailbox property register
[16:31]
TS
(def=0x0) // Time stamp
[8:15]
FI
(def=0x0) // Filtering index
[0:3]
DLENC
(def=0x0) // Data length code
0x400069C8
RFIFOMDATA01
// Receive FIFO1 mailbox data0 register
[24:31]
DB3
(def=0x0) // Data byte 3
[16:23]
DB2
(def=0x0) // Data byte 2
[8:15]
DB1
(def=0x0) // Data byte 1
[0:7]
DB0
(def=0x0) // Data byte 0
0x400069CC
RFIFOMDATA11
// Receive FIFO1 mailbox data1 register
[24:31]
DB7
(def=0x0) // Data byte 7
[16:23]
DB6
(def=0x0) // Data byte 6
[8:15]
DB5
(def=0x0) // Data byte 5
[0:7]
DB4
(def=0x0) // Data byte 4
0x40006A00
FCTL
// Filter control register
[8:13]
HBC1F
(def=0xE) // Header bank of CAN1 filter
[0]
FLD
(def=0x1) // Filter lock disable
0x40006A04
FMCFG
// Filter mode configuration register
[27]
FMOD27
(def=0x0) // Filter mode
[26]
FMOD26
(def=0x0) // Filter mode
[25]
FMOD25
(def=0x0) // Filter mode
[24]
FMOD24
(def=0x0) // Filter mode
[23]
FMOD23
(def=0x0) // Filter mode
[22]
FMOD22
(def=0x0) // Filter mode
[21]
FMOD21
(def=0x0) // Filter mode
[20]
FMOD20
(def=0x0) // Filter mode
[19]
FMOD19
(def=0x0) // Filter mode
[18]
FMOD18
(def=0x0) // Filter mode
[17]
FMOD17
(def=0x0) // Filter mode
[16]
FMOD16
(def=0x0) // Filter mode
[15]
FMOD15
(def=0x0) // Filter mode
[14]
FMOD14
(def=0x0) // Filter mode
[13]
FMOD13
(def=0x0) // Filter mode
[12]
FMOD12
(def=0x0) // Filter mode
[11]
FMOD11
(def=0x0) // Filter mode
[10]
FMOD10
(def=0x0) // Filter mode
[9]
FMOD9
(def=0x0) // Filter mode
[8]
FMOD8
(def=0x0) // Filter mode
[7]
FMOD7
(def=0x0) // Filter mode
[6]
FMOD6
(def=0x0) // Filter mode
[5]
FMOD5
(def=0x0) // Filter mode
[4]
FMOD4
(def=0x0) // Filter mode
[3]
FMOD3
(def=0x0) // Filter mode
[2]
FMOD2
(def=0x0) // Filter mode
[1]
FMOD1
(def=0x0) // Filter mode
[0]
FMOD0
(def=0x0) // Filter mode
0x40006A0C
FSCFG
// Filter scale configuration register
[0]
FS0
(def=0x0) // Filter scale configuration
[1]
FS1
(def=0x0) // Filter scale configuration
[2]
FS2
(def=0x0) // Filter scale configuration
[3]
FS3
(def=0x0) // Filter scale configuration
[4]
FS4
(def=0x0) // Filter scale configuration
[5]
FS5
(def=0x0) // Filter scale configuration
[6]
FS6
(def=0x0) // Filter scale configuration
[7]
FS7
(def=0x0) // Filter scale configuration
[8]
FS8
(def=0x0) // Filter scale configuration
[9]
FS9
(def=0x0) // Filter scale configuration
[10]
FS10
(def=0x0) // Filter scale configuration
[11]
FS11
(def=0x0) // Filter scale configuration
[12]
FS12
(def=0x0) // Filter scale configuration
[13]
FS13
(def=0x0) // Filter scale configuration
[14]
FS14
(def=0x0) // Filter scale configuration
[15]
FS15
(def=0x0) // Filter scale configuration
[16]
FS16
(def=0x0) // Filter scale configuration
[17]
FS17
(def=0x0) // Filter scale configuration
[18]
FS18
(def=0x0) // Filter scale configuration
[19]
FS19
(def=0x0) // Filter scale configuration
[20]
FS20
(def=0x0) // Filter scale configuration
[21]
FS21
(def=0x0) // Filter scale configuration
[22]
FS22
(def=0x0) // Filter scale configuration
[23]
FS23
(def=0x0) // Filter scale configuration
[24]
FS24
(def=0x0) // Filter scale configuration
[25]
FS25
(def=0x0) // Filter scale configuration
[26]
FS26
(def=0x0) // Filter scale configuration
[27]
FS27
(def=0x0) // Filter scale configuration
0x40006A14
FAFIFO
// Filter associated FIFO register
[0]
FAF0
(def=0x0) // Filter 0 associated with FIFO
[1]
FAF1
(def=0x0) // Filter 1 associated with FIFO
[2]
FAF2
(def=0x0) // Filter 2 associated with FIFO
[3]
FAF3
(def=0x0) // Filter 3 associated with FIFO
[4]
FAF4
(def=0x0) // Filter 4 associated with FIFO
[5]
FAF5
(def=0x0) // Filter 5 associated with FIFO
[6]
FAF6
(def=0x0) // Filter 6 associated with FIFO
[7]
FAF7
(def=0x0) // Filter 7 associated with FIFO
[8]
FAF8
(def=0x0) // Filter 8 associated with FIFO
[9]
FAF9
(def=0x0) // Filter 9 associated with FIFO
[10]
FAF10
(def=0x0) // Filter 10 associated with FIFO
[11]
FAF11
(def=0x0) // Filter 11 associated with FIFO
[12]
FAF12
(def=0x0) // Filter 12 associated with FIFO
[13]
FAF13
(def=0x0) // Filter 13 associated with FIFO
[14]
FAF14
(def=0x0) // Filter 14 associated with FIFO
[15]
FAF15
(def=0x0) // Filter 15 associated with FIFO
[16]
FAF16
(def=0x0) // Filter 16 associated with FIFO
[17]
FAF17
(def=0x0) // Filter 17 associated with FIFO
[18]
FAF18
(def=0x0) // Filter 18 associated with FIFO
[19]
FAF19
(def=0x0) // Filter 19 associated with FIFO
[20]
FAF20
(def=0x0) // Filter 20 associated with FIFO
[21]
FAF21
(def=0x0) // Filter 21 associated with FIFO
[22]
FAF22
(def=0x0) // Filter 22 associated with FIFO
[23]
FAF23
(def=0x0) // Filter 23 associated with FIFO
[24]
FAF24
(def=0x0) // Filter 24 associated with FIFO
[25]
FAF25
(def=0x0) // Filter 25 associated with FIFO
[26]
FAF26
(def=0x0) // Filter 26 associated with FIFO
[27]
FAF27
(def=0x0) // Filter 27 associated with FIFO
0x40006A1C
FW
// Filter working register
[0]
FW0
(def=0x0) // Filter working
[1]
FW1
(def=0x0) // Filter working
[2]
FW2
(def=0x0) // Filter working
[3]
FW3
(def=0x0) // Filter working
[4]
FW4
(def=0x0) // Filter working
[5]
FW5
(def=0x0) // Filter working
[6]
FW6
(def=0x0) // Filter working
[7]
FW7
(def=0x0) // Filter working
[8]
FW8
(def=0x0) // Filter working
[9]
FW9
(def=0x0) // Filter working
[10]
FW10
(def=0x0) // Filter working
[11]
FW11
(def=0x0) // Filter working
[12]
FW12
(def=0x0) // Filter working
[13]
FW13
(def=0x0) // Filter working
[14]
FW14
(def=0x0) // Filter working
[15]
FW15
(def=0x0) // Filter working
[16]
FW16
(def=0x0) // Filter working
[17]
FW17
(def=0x0) // Filter working
[18]
FW18
(def=0x0) // Filter working
[19]
FW19
(def=0x0) // Filter working
[20]
FW20
(def=0x0) // Filter working
[21]
FW21
(def=0x0) // Filter working
[22]
FW22
(def=0x0) // Filter working
[23]
FW23
(def=0x0) // Filter working
[24]
FW24
(def=0x0) // Filter working
[25]
FW25
(def=0x0) // Filter working
[26]
FW26
(def=0x0) // Filter working
[27]
FW27
(def=0x0) // Filter working
0x40006A40
F0DATA0
// Filter 0 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A44
F0DATA1
// Filter 0 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A48
F1DATA0
// Filter 1 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A4C
F1DATA1
// Filter 1 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A50
F2DATA0
// Filter 2 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A54
F2DATA1
// Filter 2 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A58
F3DATA0
// Filter 3 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A5C
F3DATA1
// Filter 3 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A60
F4DATA0
// Filter 4 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A64
F4DATA1
// Filter 4 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A68
F5DATA0
// Filter 5 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A6C
F5DATA1
// Filter 5 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A70
F6DATA0
// Filter 6 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A74
F6DATA1
// Filter 6 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A78
F7DATA0
// Filter 7 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A7C
F7DATA1
// Filter 7 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A80
F8DATA0
// Filter 8 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A84
F8DATA1
// Filter 8 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A88
F9DATA0
// Filter 9 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A8C
F9DATA1
// Filter 9 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A90
F10DATA0
// Filter 10 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A94
F10DATA1
// Filter 10 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A98
F11DATA0
// Filter 11 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006A9C
F11DATA1
// Filter 11 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AA0
F12DATA0
// Filter 12 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AA4
F12DATA1
// Filter 12 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AA8
F13DATA0
// Filter 13 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AAC
F13DATA1
// Filter 13 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AB0
F14DATA0
// Filter 14 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AB4
F14DATA1
// Filter 14 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AB8
F15DATA0
// Filter 15 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006ABC
F15DATA1
// Filter 15 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AC0
F16DATA0
// Filter 16 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AC4
F16DATA1
// Filter 16 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AC8
F17DATA0
// Filter 17 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006ACC
F17DATA1
// Filter 17 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AD0
F18DATA0
// Filter 18 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AD4
F18DATA1
// Filter 18 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AD8
F19DATA0
// Filter 19 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006ADC
F19DATA1
// Filter 19 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AE0
F20DATA0
// Filter 20 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AE4
F20DATA1
// Filter 20 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AE8
F21DATA0
// Filter 21 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AEC
F21DATA1
// Filter 21 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AF0
F22DATA0
// Filter 22 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AF4
F22DATA1
// Filter 22 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AF8
F23DATA0
// Filter 23 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006AFC
F23DATA1
// Filter 23 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006B00
F24DATA0
// Filter 24 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006B04
F24DATA1
// Filter 24 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006B08
F25DATA0
// Filter 25 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006B0C
F25DATA1
// Filter 25 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006B10
F26DATA0
// Filter 26 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006B14
F26DATA1
// Filter 26 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006B18
F27DATA0
// Filter 27 data 0 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
0x40006B1C
F27DATA1
// Filter 27 data 1 register
[0]
FD0
(def=0x0) // Filter bits
[1]
FD1
(def=0x0) // Filter bits
[2]
FD2
(def=0x0) // Filter bits
[3]
FD3
(def=0x0) // Filter bits
[4]
FD4
(def=0x0) // Filter bits
[5]
FD5
(def=0x0) // Filter bits
[6]
FD6
(def=0x0) // Filter bits
[7]
FD7
(def=0x0) // Filter bits
[8]
FD8
(def=0x0) // Filter bits
[9]
FD9
(def=0x0) // Filter bits
[10]
FD10
(def=0x0) // Filter bits
[11]
FD11
(def=0x0) // Filter bits
[12]
FD12
(def=0x0) // Filter bits
[13]
FD13
(def=0x0) // Filter bits
[14]
FD14
(def=0x0) // Filter bits
[15]
FD15
(def=0x0) // Filter bits
[16]
FD16
(def=0x0) // Filter bits
[17]
FD17
(def=0x0) // Filter bits
[18]
FD18
(def=0x0) // Filter bits
[19]
FD19
(def=0x0) // Filter bits
[20]
FD20
(def=0x0) // Filter bits
[21]
FD21
(def=0x0) // Filter bits
[22]
FD22
(def=0x0) // Filter bits
[23]
FD23
(def=0x0) // Filter bits
[24]
FD24
(def=0x0) // Filter bits
[25]
FD25
(def=0x0) // Filter bits
[26]
FD26
(def=0x0) // Filter bits
[27]
FD27
(def=0x0) // Filter bits
[28]
FD28
(def=0x0) // Filter bits
[29]
FD29
(def=0x0) // Filter bits
[30]
FD30
(def=0x0) // Filter bits
[31]
FD31
(def=0x0) // Filter bits
interrupts:
[82]
CAN1_TX
//
[83]
CAN1_RX0
//
[84]
CAN1_RX1
//
[85]
CAN1_EWMC
//
0x40023000
CRC
// cyclic redundancy check calculation unit
0x40023000
DATA
// Data register
[0:31]
DATA
(def=0xFFFFFFFF) // CRC calculation result bits
0x40023004
FDATA
// Free data register
[0:7]
FDATA
(def=0x0) // Free Data Register bits
0x40023008
CTL
// Control register
[0]
RST
(def=0x0) // reset bit
0x40007400
DAC
// Digital-to-analog converter
0x40007400
CTL
// control register
[0]
DEN0
(def=0x0) // DAC0 enable
[1]
DBOFF0
(def=0x0) // DAC0 output buffer turn off
[2]
DTEN0
(def=0x0) // DAC0 trigger enable
[3:5]
DTSEL0
(def=0x0) // DAC0 trigger selection
[6:7]
DWM0
(def=0x0) // DAC0 noise wave mode
[8:11]
DWBW0
(def=0x0) // DAC0 noise wave bit width
[12]
DDMAEN0
(def=0x0) // DAC0 DMA enable
[16]
DEN1
(def=0x0) // DAC1 enable
[17]
DBOFF1
(def=0x0) // DAC1 output buffer turn off
[18]
DTEN1
(def=0x0) // DAC1 trigger enable
[19:21]
DTSEL1
(def=0x0) // DAC1 trigger selection
[22:23]
DWM1
(def=0x0) // DAC1 noise wave mode
[24:27]
DWBW1
(def=0x0) // DAC1 noise wave bit width
[28]
DDMAEN1
(def=0x0) // DAC1 DMA enable
0x40007404
SWT
// software trigger register
[0]
SWTR0
(def=0x0) // DAC0 software trigger
[1]
SWTR1
(def=0x0) // DAC1 software trigger
0x40007408
DAC0_R12DH
// DAC0 12-bit right-aligned data holding register
[0:11]
DAC0_DH
(def=0x0) // DAC0 12-bit right-aligned data
0x4000740C
DAC0_L12DH
// DAC0 12-bit left-aligned data holding register
[4:15]
DAC0_DH
(def=0x0) // DAC0 12-bit left-aligned data
0x40007410
DAC0_R8DH
// DAC0 8-bit right aligned data holding register
[0:7]
DAC0_DH
(def=0x0) // DAC0 8-bit right-aligned data
0x40007414
DAC1_R12DH
// DAC1 12-bit right-aligned data holding register
[0:11]
DAC1_DH
(def=0x0) // DAC1 12-bit right-aligned data
0x40007418
DAC1_L12DH
// DAC1 12-bit left aligned data holding register
[4:15]
DAC1_DH
(def=0x0) // DAC1 12-bit left-aligned data
0x4000741C
DAC1_R8DH
// DAC1 8-bit right aligned data holding register
[0:7]
DAC1_DH
(def=0x0) // DAC1 8-bit right-aligned data
0x40007420
DACC_R12DH
// DAC concurrent mode 12-bit right-aligned data holding register
[0:11]
DAC0_DH
(def=0x0) // DAC0 12-bit right-aligned data
[16:27]
DAC1_DH
(def=0x0) // DAC1 12-bit right-aligned data
0x40007424
DACC_L12DH
// DAC concurrent mode 12-bit left aligned data holding register
[4:15]
DAC0_DH
(def=0x0) // DAC0 12-bit left-aligned data
[20:31]
DAC1_DH
(def=0x0) // DAC1 12-bit left-aligned data
0x40007428
DACC_R8DH
// DAC concurrent mode 8-bit right aligned data holding register
[0:7]
DAC0_DH
(def=0x0) // DAC0 8-bit right-aligned data
[8:15]
DAC1_DH
(def=0x0) // DAC1 8-bit right-aligned data
0x4000742C
DAC0_DO
// DAC0 data output register
[0:11]
DAC0_DO
(def=0x0) // DAC0 data output
0x40007430
DAC1_DO
// DAC1 data output register
[0:11]
DAC1_DO
(def=0x0) // DAC1 data output
0xE0042000
DBG
// Debug support
0xE0042000
ID
// ID code register
[0:31]
ID_CODE
(def=0x0) // DBG ID code register
0xE0042004
CTL
// Control register 0
[0]
SLP_HOLD
(def=0x0) // Sleep mode hold register
[1]
DSLP_HOLD
(def=0x0) // Deep-sleep mode hold register
[2]
STB_HOLD
(def=0x0) // Standby mode hold register
[8]
FWDGT_HOLD
(def=0x0) // FWDGT hold bit
[9]
WWDGT_HOLD
(def=0x0) // WWDGT hold bit
[10]
TIMER0_HOLD
(def=0x0) // TIMER 0 hold bit
[11]
TIMER1_HOLD
(def=0x0) // TIMER 1 hold bit
[12]
TIMER2_HOLD
(def=0x0) // TIMER 2 hold bit
[13]
TIMER3_HOLD
(def=0x0) // TIMER 23 hold bit
[14]
CAN0_HOLD
(def=0x0) // CAN0 hold bit
[15]
I2C0_HOLD
(def=0x0) // I2C0 hold bit
[16]
I2C1_HOLD
(def=0x0) // I2C1 hold bit
[18]
TIMER4_HOLD
(def=0x0) // TIMER4_HOLD
[19]
TIMER5_HOLD
(def=0x0) // TIMER 5 hold bit
[20]
TIMER6_HOLD
(def=0x0) // TIMER 6 hold bit
[21]
CAN1_HOLD
(def=0x0) // CAN1 hold bit
0x40020000
DMA0
// DMA controller
0x40020000
INTF
// Interrupt flag register
[0]
GIF0
(def=0x0) // Global interrupt flag of channel 0
[1]
FTFIF0
(def=0x0) // Full Transfer finish flag of channe 0
[2]
HTFIF0
(def=0x0) // Half transfer finish flag of channel 0
[3]
ERRIF0
(def=0x0) // Error flag of channel 0
[4]
GIF1
(def=0x0) // Global interrupt flag of channel 1
[5]
FTFIF1
(def=0x0) // Full Transfer finish flag of channe 1
[6]
HTFIF1
(def=0x0) // Half transfer finish flag of channel 1
[7]
ERRIF1
(def=0x0) // Error flag of channel 1
[8]
GIF2
(def=0x0) // Global interrupt flag of channel 2
[9]
FTFIF2
(def=0x0) // Full Transfer finish flag of channe 2
[10]
HTFIF2
(def=0x0) // Half transfer finish flag of channel 2
[11]
ERRIF2
(def=0x0) // Error flag of channel 2
[12]
GIF3
(def=0x0) // Global interrupt flag of channel 3
[13]
FTFIF3
(def=0x0) // Full Transfer finish flag of channe 3
[14]
HTFIF3
(def=0x0) // Half transfer finish flag of channel 3
[15]
ERRIF3
(def=0x0) // Error flag of channel 3
[16]
GIF4
(def=0x0) // Global interrupt flag of channel 4
[17]
FTFIF4
(def=0x0) // Full Transfer finish flag of channe 4
[18]
HTFIF4
(def=0x0) // Half transfer finish flag of channel 4
[19]
ERRIF4
(def=0x0) // Error flag of channel 4
[20]
GIF5
(def=0x0) // Global interrupt flag of channel 5
[21]
FTFIF5
(def=0x0) // Full Transfer finish flag of channe 5
[22]
HTFIF5
(def=0x0) // Half transfer finish flag of channel 5
[23]
ERRIF5
(def=0x0) // Error flag of channel 5
[24]
GIF6
(def=0x0) // Global interrupt flag of channel 6
[25]
FTFIF6
(def=0x0) // Full Transfer finish flag of channe 6
[26]
HTFIF6
(def=0x0) // Half transfer finish flag of channel 6
[27]
ERRIF6
(def=0x0) // Error flag of channel 6
0x40020004
INTC
// Interrupt flag clear register
[0]
GIFC0
(def=0x0) // Clear global interrupt flag of channel 0
[1]
FTFIFC0
(def=0x0) // Clear bit for full transfer finish flag of channel 0
[2]
HTFIFC0
(def=0x0) // Clear bit for half transfer finish flag of channel 0
[3]
ERRIFC0
(def=0x0) // Clear bit for error flag of channel 0
[4]
GIFC1
(def=0x0) // Clear global interrupt flag of channel 1
[5]
FTFIFC1
(def=0x0) // Clear bit for full transfer finish flag of channel 1
[6]
HTFIFC1
(def=0x0) // Clear bit for half transfer finish flag of channel 1
[7]
ERRIFC1
(def=0x0) // Clear bit for error flag of channel 1
[8]
GIFC2
(def=0x0) // Clear global interrupt flag of channel 2
[9]
FTFIFC2
(def=0x0) // Clear bit for full transfer finish flag of channel 2
[10]
HTFIFC2
(def=0x0) // Clear bit for half transfer finish flag of channel 2
[11]
ERRIFC2
(def=0x0) // Clear bit for error flag of channel 2
[12]
GIFC3
(def=0x0) // Clear global interrupt flag of channel 3
[13]
FTFIFC3
(def=0x0) // Clear bit for full transfer finish flag of channel 3
[14]
HTFIFC3
(def=0x0) // Clear bit for half transfer finish flag of channel 3
[15]
ERRIFC3
(def=0x0) // Clear bit for error flag of channel 3
[16]
GIFC4
(def=0x0) // Clear global interrupt flag of channel 4
[17]
FTFIFC4
(def=0x0) // Clear bit for full transfer finish flag of channel 4
[18]
HTFIFC4
(def=0x0) // Clear bit for half transfer finish flag of channel 4
[19]
ERRIFC4
(def=0x0) // Clear bit for error flag of channel 4
[20]
GIFC5
(def=0x0) // Clear global interrupt flag of channel 5
[21]
FTFIFC5
(def=0x0) // Clear bit for full transfer finish flag of channel 5
[22]
HTFIFC5
(def=0x0) // Clear bit for half transfer finish flag of channel 5
[23]
ERRIFC5
(def=0x0) // Clear bit for error flag of channel 5
[24]
GIFC6
(def=0x0) // Clear global interrupt flag of channel 6
[25]
FTFIFC6
(def=0x0) // Clear bit for full transfer finish flag of channel 6
[26]
HTFIFC6
(def=0x0) // Clear bit for half transfer finish flag of channel 6
[27]
ERRIFC6
(def=0x0) // Clear bit for error flag of channel 6
0x40020008
CH0CTL
// Channel 0 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x4002000C
CH0CNT
// Channel 0 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020010
CH0PADDR
// Channel 0 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x40020014
CH0MADDR
// Channel 0 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x4002001C
CH1CTL
// Channel 1 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x40020020
CH1CNT
// Channel 1 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020024
CH1PADDR
// Channel 1 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x40020028
CH1MADDR
// Channel 1 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x40020030
CH2CTL
// Channel 2 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x40020034
CH2CNT
// Channel 2 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020038
CH2PADDR
// Channel 2 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x4002003C
CH2MADDR
// Channel 2 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x40020044
CH3CTL
// Channel 3 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x40020048
CH3CNT
// Channel 3 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x4002004C
CH3PADDR
// Channel 3 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x40020050
CH3MADDR
// Channel 3 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x40020058
CH4CTL
// Channel 4 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x4002005C
CH4CNT
// Channel 4 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020060
CH4PADDR
// Channel 4 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x40020064
CH4MADDR
// Channel 4 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x4002006C
CH5CTL
// Channel 5 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x40020070
CH5CNT
// Channel 5 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020074
CH5PADDR
// Channel 5 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x40020078
CH5MADDR
// Channel 5 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x40020080
CH6CTL
// Channel 6 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x40020084
CH6CNT
// Channel 6 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020088
CH6PADDR
// Channel 6 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x4002008C
CH6MADDR
// Channel 6 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
interrupts:
[30]
DMA0_Channel0
//
[31]
DMA0_Channel1
//
[32]
DMA0_Channel2
//
[33]
DMA0_Channel3
//
[34]
DMA0_Channel4
//
[35]
DMA0_Channel5
//
[36]
DMA0_Channel6
//
0x40020400
DMA1
// Direct memory access controller
0x40020400
INTF
// Interrupt flag register
[0]
GIF0
(def=0x0) // Global interrupt flag of channel 0
[1]
FTFIF0
(def=0x0) // Full Transfer finish flag of channe 0
[2]
HTFIF0
(def=0x0) // Half transfer finish flag of channel 0
[3]
ERRIF0
(def=0x0) // Error flag of channel 0
[4]
GIF1
(def=0x0) // Global interrupt flag of channel 1
[5]
FTFIF1
(def=0x0) // Full Transfer finish flag of channe 1
[6]
HTFIF1
(def=0x0) // Half transfer finish flag of channel 1
[7]
ERRIF1
(def=0x0) // Error flag of channel 1
[8]
GIF2
(def=0x0) // Global interrupt flag of channel 2
[9]
FTFIF2
(def=0x0) // Full Transfer finish flag of channe 2
[10]
HTFIF2
(def=0x0) // Half transfer finish flag of channel 2
[11]
ERRIF2
(def=0x0) // Error flag of channel 2
[12]
GIF3
(def=0x0) // Global interrupt flag of channel 3
[13]
FTFIF3
(def=0x0) // Full Transfer finish flag of channe 3
[14]
HTFIF3
(def=0x0) // Half transfer finish flag of channel 3
[15]
ERRIF3
(def=0x0) // Error flag of channel 3
[16]
GIF4
(def=0x0) // Global interrupt flag of channel 4
[17]
FTFIF4
(def=0x0) // Full Transfer finish flag of channe 4
[18]
HTFIF4
(def=0x0) // Half transfer finish flag of channel 4
[19]
ERRIF4
(def=0x0) // Error flag of channel 4
0x40020404
INTC
// Interrupt flag clear register
[0]
GIFC0
(def=0x0) // Clear global interrupt flag of channel 0
[1]
FTFIFC0
(def=0x0) // Clear bit for full transfer finish flag of channel 0
[2]
HTFIFC0
(def=0x0) // Clear bit for half transfer finish flag of channel 0
[3]
ERRIFC0
(def=0x0) // Clear bit for error flag of channel 0
[4]
GIFC1
(def=0x0) // Clear global interrupt flag of channel 1
[5]
FTFIFC1
(def=0x0) // Clear bit for full transfer finish flag of channel 1
[6]
HTFIFC1
(def=0x0) // Clear bit for half transfer finish flag of channel 1
[7]
ERRIFC1
(def=0x0) // Clear bit for error flag of channel 1
[8]
GIFC2
(def=0x0) // Clear global interrupt flag of channel 2
[9]
FTFIFC2
(def=0x0) // Clear bit for full transfer finish flag of channel 2
[10]
HTFIFC2
(def=0x0) // Clear bit for half transfer finish flag of channel 2
[11]
ERRIFC2
(def=0x0) // Clear bit for error flag of channel 2
[12]
GIFC3
(def=0x0) // Clear global interrupt flag of channel 3
[13]
FTFIFC3
(def=0x0) // Clear bit for full transfer finish flag of channel 3
[14]
HTFIFC3
(def=0x0) // Clear bit for half transfer finish flag of channel 3
[15]
ERRIFC3
(def=0x0) // Clear bit for error flag of channel 3
[16]
GIFC4
(def=0x0) // Clear global interrupt flag of channel 4
[17]
FTFIFC4
(def=0x0) // Clear bit for full transfer finish flag of channel 4
[18]
HTFIFC4
(def=0x0) // Clear bit for half transfer finish flag of channel 4
[19]
ERRIFC4
(def=0x0) // Clear bit for error flag of channel 4
0x40020408
CH0CTL
// Channel 0 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x4002040C
CH0CNT
// Channel 0 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020410
CH0PADDR
// Channel 0 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x40020414
CH0MADDR
// Channel 0 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x4002041C
CH1CTL
// Channel 1 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x40020420
CH1CNT
// Channel 1 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020424
CH1PADDR
// Channel 1 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x40020428
CH1MADDR
// Channel 1 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x40020430
CH2CTL
// Channel 2 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x40020434
CH2CNT
// Channel 2 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020438
CH2PADDR
// Channel 2 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x4002043C
CH2MADDR
// Channel 2 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x40020444
CH3CTL
// Channel 3 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x40020448
CH3CNT
// Channel 3 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x4002044C
CH3PADDR
// Channel 3 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x40020450
CH3MADDR
// Channel 3 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
0x40020458
CH4CTL
// Channel 4 control register
[0]
CHEN
(def=0x0) // Channel enable
[1]
FTFIE
(def=0x0) // Enable bit for channel full transfer finish interrupt
[2]
HTFIE
(def=0x0) // Enable bit for channel half transfer finish interrupt
[3]
ERRIE
(def=0x0) // Enable bit for channel error interrupt
[4]
DIR
(def=0x0) // Transfer direction
[5]
CMEN
(def=0x0) // Circular mode enable
[6]
PNAGA
(def=0x0) // Next address generation algorithm of peripheral
[7]
MNAGA
(def=0x0) // Next address generation algorithm of memory
[8:9]
PWIDTH
(def=0x0) // Transfer data size of peripheral
[10:11]
MWIDTH
(def=0x0) // Transfer data size of memory
[12:13]
PRIO
(def=0x0) // Priority level
[14]
M2M
(def=0x0) // Memory to Memory Mode
0x4002045C
CH4CNT
// Channel 4 counter register
[0:15]
CNT
(def=0x0) // Transfer counter
0x40020460
CH4PADDR
// Channel 4 peripheral base address register
[0:31]
PADDR
(def=0x0) // Peripheral base address
0x40020464
CH4MADDR
// Channel 4 memory base address register
[0:31]
MADDR
(def=0x0) // Memory base address
interrupts:
[75]
DMA1_Channel0
//
[76]
DMA1_Channel1
//
[77]
DMA1_Channel2
//
[78]
DMA1_Channel3
//
[79]
DMA1_Channel4
//
0xA0000000
EXMC
// External memory controller
0xA0000000
SNCTL0
// SRAM/NOR flash control register 0
[15]
ASYNCWAIT
(def=0x0) // Asynchronous wait
[13]
NRWTEN
(def=0x1) // NWAIT signal enable
[12]
WREN
(def=0x1) // Write enable
[9]
NRWTPOL
(def=0x0) // NWAIT signal polarity
[6]
NREN
(def=0x1) // NOR Flash access enable
[4:5]
NRW
(def=0x1) // NOR bank memory data bus width
[2:3]
NRTP
(def=0x2) // NOR bank memory type
[1]
NRMUX
(def=0x1) // NOR bank memory address/data multiplexing
[0]
NRBKEN
(def=0x0) // NOR bank enable
0xA0000004
SNTCFG0
// SRAM/NOR flash timing configuration register 0
[16:19]
BUSLAT
(def=0xF) // Bus latency
[8:15]
DSET
(def=0xFF) // Data setup time
[4:7]
AHLD
(def=0xF) // Address hold time
[0:3]
ASET
(def=0xF) // Address setup time
0xA0000008
SNCTL1
// SRAM/NOR flash control register 1
[15]
ASYNCWAIT
(def=0x0) // Asynchronous wait
[13]
NRWTEN
(def=0x1) // NWAIT signal enable
[12]
WREN
(def=0x1) // Write enable
[9]
NRWTPOL
(def=0x0) // NWAIT signal polarity
[6]
NREN
(def=0x1) // NOR Flash access enable
[4:5]
NRW
(def=0x1) // NOR bank memory data bus width
[2:3]
NRTP
(def=0x2) // NOR bank memory type
[1]
NRMUX
(def=0x1) // NOR bank memory address/data multiplexing
[0]
NRBKEN
(def=0x0) // NOR bank enable
0x40010400
EXTI
// External interrupt/event controller
0x40010400
INTEN
// Interrupt enable register (EXTI_INTEN)
[0]
INTEN0
(def=0x0) // Enable Interrupt on line 0
[1]
INTEN1
(def=0x0) // Enable Interrupt on line 1
[2]
INTEN2
(def=0x0) // Enable Interrupt on line 2
[3]
INTEN3
(def=0x0) // Enable Interrupt on line 3
[4]
INTEN4
(def=0x0) // Enable Interrupt on line 4
[5]
INTEN5
(def=0x0) // Enable Interrupt on line 5
[6]
INTEN6
(def=0x0) // Enable Interrupt on line 6
[7]
INTEN7
(def=0x0) // Enable Interrupt on line 7
[8]
INTEN8
(def=0x0) // Enable Interrupt on line 8
[9]
INTEN9
(def=0x0) // Enable Interrupt on line 9
[10]
INTEN10
(def=0x0) // Enable Interrupt on line 10
[11]
INTEN11
(def=0x0) // Enable Interrupt on line 11
[12]
INTEN12
(def=0x0) // Enable Interrupt on line 12
[13]
INTEN13
(def=0x0) // Enable Interrupt on line 13
[14]
INTEN14
(def=0x0) // Enable Interrupt on line 14
[15]
INTEN15
(def=0x0) // Enable Interrupt on line 15
[16]
INTEN16
(def=0x0) // Enable Interrupt on line 16
[17]
INTEN17
(def=0x0) // Enable Interrupt on line 17
[18]
INTEN18
(def=0x0) // Enable Interrupt on line 18
0x40010404
EVEN
// Event enable register (EXTI_EVEN)
[0]
EVEN0
(def=0x0) // Enable Event on line 0
[1]
EVEN1
(def=0x0) // Enable Event on line 1
[2]
EVEN2
(def=0x0) // Enable Event on line 2
[3]
EVEN3
(def=0x0) // Enable Event on line 3
[4]
EVEN4
(def=0x0) // Enable Event on line 4
[5]
EVEN5
(def=0x0) // Enable Event on line 5
[6]
EVEN6
(def=0x0) // Enable Event on line 6
[7]
EVEN7
(def=0x0) // Enable Event on line 7
[8]
EVEN8
(def=0x0) // Enable Event on line 8
[9]
EVEN9
(def=0x0) // Enable Event on line 9
[10]
EVEN10
(def=0x0) // Enable Event on line 10
[11]
EVEN11
(def=0x0) // Enable Event on line 11
[12]
EVEN12
(def=0x0) // Enable Event on line 12
[13]
EVEN13
(def=0x0) // Enable Event on line 13
[14]
EVEN14
(def=0x0) // Enable Event on line 14
[15]
EVEN15
(def=0x0) // Enable Event on line 15
[16]
EVEN16
(def=0x0) // Enable Event on line 16
[17]
EVEN17
(def=0x0) // Enable Event on line 17
[18]
EVEN18
(def=0x0) // Enable Event on line 18
0x40010408
RTEN
// Rising Edge Trigger Enable register (EXTI_RTEN)
[0]
RTEN0
(def=0x0) // Rising edge trigger enable of line 0
[1]
RTEN1
(def=0x0) // Rising edge trigger enable of line 1
[2]
RTEN2
(def=0x0) // Rising edge trigger enable of line 2
[3]
RTEN3
(def=0x0) // Rising edge trigger enable of line 3
[4]
RTEN4
(def=0x0) // Rising edge trigger enable of line 4
[5]
RTEN5
(def=0x0) // Rising edge trigger enable of line 5
[6]
RTEN6
(def=0x0) // Rising edge trigger enable of line 6
[7]
RTEN7
(def=0x0) // Rising edge trigger enable of line 7
[8]
RTEN8
(def=0x0) // Rising edge trigger enable of line 8
[9]
RTEN9
(def=0x0) // Rising edge trigger enable of line 9
[10]
RTEN10
(def=0x0) // Rising edge trigger enable of line 10
[11]
RTEN11
(def=0x0) // Rising edge trigger enable of line 11
[12]
RTEN12
(def=0x0) // Rising edge trigger enable of line 12
[13]
RTEN13
(def=0x0) // Rising edge trigger enable of line 13
[14]
RTEN14
(def=0x0) // Rising edge trigger enable of line 14
[15]
RTEN15
(def=0x0) // Rising edge trigger enable of line 15
[16]
RTEN16
(def=0x0) // Rising edge trigger enable of line 16
[17]
RTEN17
(def=0x0) // Rising edge trigger enable of line 17
[18]
RTEN18
(def=0x0) // Rising edge trigger enable of line 18
0x4001040C
FTEN
// Falling Egde Trigger Enable register (EXTI_FTEN)
[0]
FTEN0
(def=0x0) // Falling edge trigger enable of line 0
[1]
FTEN1
(def=0x0) // Falling edge trigger enable of line 1
[2]
FTEN2
(def=0x0) // Falling edge trigger enable of line 2
[3]
FTEN3
(def=0x0) // Falling edge trigger enable of line 3
[4]
FTEN4
(def=0x0) // Falling edge trigger enable of line 4
[5]
FTEN5
(def=0x0) // Falling edge trigger enable of line 5
[6]
FTEN6
(def=0x0) // Falling edge trigger enable of line 6
[7]
FTEN7
(def=0x0) // Falling edge trigger enable of line 7
[8]
FTEN8
(def=0x0) // Falling edge trigger enable of line 8
[9]
FTEN9
(def=0x0) // Falling edge trigger enable of line 9
[10]
FTEN10
(def=0x0) // Falling edge trigger enable of line 10
[11]
FTEN11
(def=0x0) // Falling edge trigger enable of line 11
[12]
FTEN12
(def=0x0) // Falling edge trigger enable of line 12
[13]
FTEN13
(def=0x0) // Falling edge trigger enable of line 13
[14]
FTEN14
(def=0x0) // Falling edge trigger enable of line 14
[15]
FTEN15
(def=0x0) // Falling edge trigger enable of line 15
[16]
FTEN16
(def=0x0) // Falling edge trigger enable of line 16
[17]
FTEN17
(def=0x0) // Falling edge trigger enable of line 17
[18]
FTEN18
(def=0x0) // Falling edge trigger enable of line 18
0x40010410
SWIEV
// Software interrupt event register (EXTI_SWIEV)
[0]
SWIEV0
(def=0x0) // Interrupt/Event software trigger on line 0
[1]
SWIEV1
(def=0x0) // Interrupt/Event software trigger on line 1
[2]
SWIEV2
(def=0x0) // Interrupt/Event software trigger on line 2
[3]
SWIEV3
(def=0x0) // Interrupt/Event software trigger on line 3
[4]
SWIEV4
(def=0x0) // Interrupt/Event software trigger on line 4
[5]
SWIEV5
(def=0x0) // Interrupt/Event software trigger on line 5
[6]
SWIEV6
(def=0x0) // Interrupt/Event software trigger on line 6
[7]
SWIEV7
(def=0x0) // Interrupt/Event software trigger on line 7
[8]
SWIEV8
(def=0x0) // Interrupt/Event software trigger on line 8
[9]
SWIEV9
(def=0x0) // Interrupt/Event software trigger on line 9
[10]
SWIEV10
(def=0x0) // Interrupt/Event software trigger on line 10
[11]
SWIEV11
(def=0x0) // Interrupt/Event software trigger on line 11
[12]
SWIEV12
(def=0x0) // Interrupt/Event software trigger on line 12
[13]
SWIEV13
(def=0x0) // Interrupt/Event software trigger on line 13
[14]
SWIEV14
(def=0x0) // Interrupt/Event software trigger on line 14
[15]
SWIEV15
(def=0x0) // Interrupt/Event software trigger on line 15
[16]
SWIEV16
(def=0x0) // Interrupt/Event software trigger on line 16
[17]
SWIEV17
(def=0x0) // Interrupt/Event software trigger on line 17
[18]
SWIEV18
(def=0x0) // Interrupt/Event software trigger on line 18
0x40010414
PD
// Pending register (EXTI_PD)
[0]
PD0
(def=0x0) // Interrupt pending status of line 0
[1]
PD1
(def=0x0) // Interrupt pending status of line 1
[2]
PD2
(def=0x0) // Interrupt pending status of line 2
[3]
PD3
(def=0x0) // Interrupt pending status of line 3
[4]
PD4
(def=0x0) // Interrupt pending status of line 4
[5]
PD5
(def=0x0) // Interrupt pending status of line 5
[6]
PD6
(def=0x0) // Interrupt pending status of line 6
[7]
PD7
(def=0x0) // Interrupt pending status of line 7
[8]
PD8
(def=0x0) // Interrupt pending status of line 8
[9]
PD9
(def=0x0) // Interrupt pending status of line 9
[10]
PD10
(def=0x0) // Interrupt pending status of line 10
[11]
PD11
(def=0x0) // Interrupt pending status of line 11
[12]
PD12
(def=0x0) // Interrupt pending status of line 12
[13]
PD13
(def=0x0) // Interrupt pending status of line 13
[14]
PD14
(def=0x0) // Interrupt pending status of line 14
[15]
PD15
(def=0x0) // Interrupt pending status of line 15
[16]
PD16
(def=0x0) // Interrupt pending status of line 16
[17]
PD17
(def=0x0) // Interrupt pending status of line 17
[18]
PD18
(def=0x0) // Interrupt pending status of line 18
interrupts:
[25]
EXTI_Line0
//
[26]
EXTI_Line1
//
[27]
EXTI_Line2
//
[28]
EXTI_Line3
//
[29]
EXTI_Line4
//
[42]
EXTI_line9_5
//
[59]
EXTI_line15_10
//
0x40022000
FMC
// FMC
0x40022000
WS
// wait state counter register
[0:2]
WSCNT
(def=0x0) // wait state counter register
0x40022004
KEY0
// Unlock key register 0
[0:31]
KEY
(def=0x0) // FMC_CTL0 unlock key
0x40022008
OBKEY
// Option byte unlock key register
[0:31]
OBKEY
(def=0x0) // FMC_ CTL0 option byte operation unlock register
0x4002200C
STAT0
// Status register 0
[5]
ENDF
(def=0x0) // End of operation flag bit
[4]
WPERR
(def=0x0) // Erase/Program protection error flag bit
[2]
PGERR
(def=0x0) // Program error flag bit
[0]
BUSY
(def=0x0) // The flash is busy bit
0x40022010
CTL0
// Control register 0
[12]
ENDIE
(def=0x0) // End of operation interrupt enable bit
[10]
ERRIE
(def=0x0) // Error interrupt enable bit
[9]
OBWEN
(def=0x0) // Option byte erase/program enable bit
[7]
LK
(def=0x1) // FMC_CTL0 lock bit
[6]
START
(def=0x0) // Send erase command to FMC bit
[5]
OBER
(def=0x0) // Option bytes erase command bit
[4]
OBPG
(def=0x0) // Option bytes program command bit
[2]
MER
(def=0x0) // Main flash mass erase for bank0 command bit
[1]
PER
(def=0x0) // Main flash page erase for bank0 command bit
[0]
PG
(def=0x0) // Main flash program for bank0 command bit
0x40022014
ADDR0
// Address register 0
[0:31]
ADDR
(def=0x0) // Flash erase/program command address bits
0x4002201C
OBSTAT
// Option byte status register
[0]
OBERR
(def=0x0) // Option bytes read error bit
[1]
SPC
(def=0x0) // Option bytes security protection code
[2:9]
USER
(def=0x0) // Store USER of option bytes block after system reset
[10:25]
DATA
(def=0x0) // Store DATA[15:0] of option bytes block after system reset
0x40022020
WP
// Erase/Program Protection register
[0:31]
WP
(def=0x0) // Store WP[31:0] of option bytes block after system reset
0x40022100
PID
// Product ID register
[0:31]
PID
(def=0x0) // Product reserved ID code register
interrupts:
[23]
FMC
//
0x40003000
FWDGT
// free watchdog timer
0x40003000
CTL
// Control register
[0:15]
CMD
(def=0x0) // Key value
0x40003004
PSC
// Prescaler register
[0:2]
PSC
(def=0x0) // Free watchdog timer prescaler selection
0x40003008
RLD
// Reload register
[0:11]
RLD
(def=0xFFF) // Free watchdog timer counter reload value
0x4000300C
STAT
// Status register
[0]
PUD
(def=0x0) // Free watchdog timer prescaler value update
[1]
RUD
(def=0x0) // Free watchdog timer counter reload value update
0x40010800
GPIOA
// General-purpose I/Os
0x40010800
CTL0
// port control register 0
[30:31]
CTL7
(def=0x1) // Port x configuration bits (x = 7)
[28:29]
MD7
(def=0x0) // Port x mode bits (x = 7)
[26:27]
CTL6
(def=0x1) // Port x configuration bits (x = 6)
[24:25]
MD6
(def=0x0) // Port x mode bits (x = 6)
[22:23]
CTL5
(def=0x1) // Port x configuration bits (x = 5)
[20:21]
MD5
(def=0x0) // Port x mode bits (x = 5)
[18:19]
CTL4
(def=0x1) // Port x configuration bits (x = 4)
[16:17]
MD4
(def=0x0) // Port x mode bits (x = 4)
[14:15]
CTL3
(def=0x1) // Port x configuration bits (x = 3)
[12:13]
MD3
(def=0x0) // Port x mode bits (x = 3 )
[10:11]
CTL2
(def=0x1) // Port x configuration bits (x = 2)
[8:9]
MD2
(def=0x0) // Port x mode bits (x = 2 )
[6:7]
CTL1
(def=0x1) // Port x configuration bits (x = 1)
[4:5]
MD1
(def=0x0) // Port x mode bits (x = 1)
[2:3]
CTL0
(def=0x1) // Port x configuration bits (x = 0)
[0:1]
MD0
(def=0x0) // Port x mode bits (x = 0)
0x40010804
CTL1
// port control register 1
[30:31]
CTL15
(def=0x1) // Port x configuration bits (x = 15)
[28:29]
MD15
(def=0x0) // Port x mode bits (x = 15)
[26:27]
CTL14
(def=0x1) // Port x configuration bits (x = 14)
[24:25]
MD14
(def=0x0) // Port x mode bits (x = 14)
[22:23]
CTL13
(def=0x1) // Port x configuration bits (x = 13)
[20:21]
MD13
(def=0x0) // Port x mode bits (x = 13)
[18:19]
CTL12
(def=0x1) // Port x configuration bits (x = 12)
[16:17]
MD12
(def=0x0) // Port x mode bits (x = 12)
[14:15]
CTL11
(def=0x1) // Port x configuration bits (x = 11)
[12:13]
MD11
(def=0x0) // Port x mode bits (x = 11 )
[10:11]
CTL10
(def=0x1) // Port x configuration bits (x = 10)
[8:9]
MD10
(def=0x0) // Port x mode bits (x = 10 )
[6:7]
CTL9
(def=0x1) // Port x configuration bits (x = 9)
[4:5]
MD9
(def=0x0) // Port x mode bits (x = 9)
[2:3]
CTL8
(def=0x1) // Port x configuration bits (x = 8)
[0:1]
MD8
(def=0x0) // Port x mode bits (x = 8)
0x40010808
ISTAT
// Port input status register
[15]
ISTAT15
(def=0x0) // Port input status
[14]
ISTAT14
(def=0x0) // Port input status
[13]
ISTAT13
(def=0x0) // Port input status
[12]
ISTAT12
(def=0x0) // Port input status
[11]
ISTAT11
(def=0x0) // Port input status
[10]
ISTAT10
(def=0x0) // Port input status
[9]
ISTAT9
(def=0x0) // Port input status
[8]
ISTAT8
(def=0x0) // Port input status
[7]
ISTAT7
(def=0x0) // Port input status
[6]
ISTAT6
(def=0x0) // Port input status
[5]
ISTAT5
(def=0x0) // Port input status
[4]
ISTAT4
(def=0x0) // Port input status
[3]
ISTAT3
(def=0x0) // Port input status
[2]
ISTAT2
(def=0x0) // Port input status
[1]
ISTAT1
(def=0x0) // Port input status
[0]
ISTAT0
(def=0x0) // Port input status
0x4001080C
OCTL
// Port output control register
[15]
OCTL15
(def=0x0) // Port output control
[14]
OCTL14
(def=0x0) // Port output control
[13]
OCTL13
(def=0x0) // Port output control
[12]
OCTL12
(def=0x0) // Port output control
[11]
OCTL11
(def=0x0) // Port output control
[10]
OCTL10
(def=0x0) // Port output control
[9]
OCTL9
(def=0x0) // Port output control
[8]
OCTL8
(def=0x0) // Port output control
[7]
OCTL7
(def=0x0) // Port output control
[6]
OCTL6
(def=0x0) // Port output control
[5]
OCTL5
(def=0x0) // Port output control
[4]
OCTL4
(def=0x0) // Port output control
[3]
OCTL3
(def=0x0) // Port output control
[2]
OCTL2
(def=0x0) // Port output control
[1]
OCTL1
(def=0x0) // Port output control
[0]
OCTL0
(def=0x0) // Port output control
0x40010810
BOP
// Port bit operate register
[31]
CR15
(def=0x0) // Port 15 Clear bit
[30]
CR14
(def=0x0) // Port 14 Clear bit
[29]
CR13
(def=0x0) // Port 13 Clear bit
[28]
CR12
(def=0x0) // Port 12 Clear bit
[27]
CR11
(def=0x0) // Port 11 Clear bit
[26]
CR10
(def=0x0) // Port 10 Clear bit
[25]
CR9
(def=0x0) // Port 9 Clear bit
[24]
CR8
(def=0x0) // Port 8 Clear bit
[23]
CR7
(def=0x0) // Port 7 Clear bit
[22]
CR6
(def=0x0) // Port 6 Clear bit
[21]
CR5
(def=0x0) // Port 5 Clear bit
[20]
CR4
(def=0x0) // Port 4 Clear bit
[19]
CR3
(def=0x0) // Port 3 Clear bit
[18]
CR2
(def=0x0) // Port 2 Clear bit
[17]
CR1
(def=0x0) // Port 1 Clear bit
[16]
CR0
(def=0x0) // Port 0 Clear bit
[15]
BOP15
(def=0x0) // Port 15 Set bit
[14]
BOP14
(def=0x0) // Port 14 Set bit
[13]
BOP13
(def=0x0) // Port 13 Set bit
[12]
BOP12
(def=0x0) // Port 12 Set bit
[11]
BOP11
(def=0x0) // Port 11 Set bit
[10]
BOP10
(def=0x0) // Port 10 Set bit
[9]
BOP9
(def=0x0) // Port 9 Set bit
[8]
BOP8
(def=0x0) // Port 8 Set bit
[7]
BOP7
(def=0x0) // Port 7 Set bit
[6]
BOP6
(def=0x0) // Port 6 Set bit
[5]
BOP5
(def=0x0) // Port 5 Set bit
[4]
BOP4
(def=0x0) // Port 4 Set bit
[3]
BOP3
(def=0x0) // Port 3 Set bit
[2]
BOP2
(def=0x0) // Port 2 Set bit
[1]
BOP1
(def=0x0) // Port 1 Set bit
[0]
BOP0
(def=0x0) // Port 0 Set bit
0x40010814
BC
// Port bit clear register
[15]
CR15
(def=0x0) // Port 15 Clear bit
[14]
CR14
(def=0x0) // Port 14 Clear bit
[13]
CR13
(def=0x0) // Port 13 Clear bit
[12]
CR12
(def=0x0) // Port 12 Clear bit
[11]
CR11
(def=0x0) // Port 11 Clear bit
[10]
CR10
(def=0x0) // Port 10 Clear bit
[9]
CR9
(def=0x0) // Port 9 Clear bit
[8]
CR8
(def=0x0) // Port 8 Clear bit
[7]
CR7
(def=0x0) // Port 7 Clear bit
[6]
CR6
(def=0x0) // Port 6 Clear bit
[5]
CR5
(def=0x0) // Port 5 Clear bit
[4]
CR4
(def=0x0) // Port 4 Clear bit
[3]
CR3
(def=0x0) // Port 3 Clear bit
[2]
CR2
(def=0x0) // Port 2 Clear bit
[1]
CR1
(def=0x0) // Port 1 Clear bit
[0]
CR0
(def=0x0) // Port 0 Clear bit
0x40010818
LOCK
// GPIO port configuration lock register
[16]
LKK
(def=0x0) // Lock sequence key
[15]
LK15
(def=0x0) // Port Lock bit 15
[14]
LK14
(def=0x0) // Port Lock bit 14
[13]
LK13
(def=0x0) // Port Lock bit 13
[12]
LK12
(def=0x0) // Port Lock bit 12
[11]
LK11
(def=0x0) // Port Lock bit 11
[10]
LK10
(def=0x0) // Port Lock bit 10
[9]
LK9
(def=0x0) // Port Lock bit 9
[8]
LK8
(def=0x0) // Port Lock bit 8
[7]
LK7
(def=0x0) // Port Lock bit 7
[6]
LK6
(def=0x0) // Port Lock bit 6
[5]
LK5
(def=0x0) // Port Lock bit 5
[4]
LK4
(def=0x0) // Port Lock bit 4
[3]
LK3
(def=0x0) // Port Lock bit 3
[2]
LK2
(def=0x0) // Port Lock bit 2
[1]
LK1
(def=0x0) // Port Lock bit 1
[0]
LK0
(def=0x0) // Port Lock bit 0
0x40010C00
GPIOB
//
0x40010C00
CTL0
// port control register 0
[30:31]
CTL7
(def=0x1) // Port x configuration bits (x = 7)
[28:29]
MD7
(def=0x0) // Port x mode bits (x = 7)
[26:27]
CTL6
(def=0x1) // Port x configuration bits (x = 6)
[24:25]
MD6
(def=0x0) // Port x mode bits (x = 6)
[22:23]
CTL5
(def=0x1) // Port x configuration bits (x = 5)
[20:21]
MD5
(def=0x0) // Port x mode bits (x = 5)
[18:19]
CTL4
(def=0x1) // Port x configuration bits (x = 4)
[16:17]
MD4
(def=0x0) // Port x mode bits (x = 4)
[14:15]
CTL3
(def=0x1) // Port x configuration bits (x = 3)
[12:13]
MD3
(def=0x0) // Port x mode bits (x = 3 )
[10:11]
CTL2
(def=0x1) // Port x configuration bits (x = 2)
[8:9]
MD2
(def=0x0) // Port x mode bits (x = 2 )
[6:7]
CTL1
(def=0x1) // Port x configuration bits (x = 1)
[4:5]
MD1
(def=0x0) // Port x mode bits (x = 1)
[2:3]
CTL0
(def=0x1) // Port x configuration bits (x = 0)
[0:1]
MD0
(def=0x0) // Port x mode bits (x = 0)
0x40010C04
CTL1
// port control register 1
[30:31]
CTL15
(def=0x1) // Port x configuration bits (x = 15)
[28:29]
MD15
(def=0x0) // Port x mode bits (x = 15)
[26:27]
CTL14
(def=0x1) // Port x configuration bits (x = 14)
[24:25]
MD14
(def=0x0) // Port x mode bits (x = 14)
[22:23]
CTL13
(def=0x1) // Port x configuration bits (x = 13)
[20:21]
MD13
(def=0x0) // Port x mode bits (x = 13)
[18:19]
CTL12
(def=0x1) // Port x configuration bits (x = 12)
[16:17]
MD12
(def=0x0) // Port x mode bits (x = 12)
[14:15]
CTL11
(def=0x1) // Port x configuration bits (x = 11)
[12:13]
MD11
(def=0x0) // Port x mode bits (x = 11 )
[10:11]
CTL10
(def=0x1) // Port x configuration bits (x = 10)
[8:9]
MD10
(def=0x0) // Port x mode bits (x = 10 )
[6:7]
CTL9
(def=0x1) // Port x configuration bits (x = 9)
[4:5]
MD9
(def=0x0) // Port x mode bits (x = 9)
[2:3]
CTL8
(def=0x1) // Port x configuration bits (x = 8)
[0:1]
MD8
(def=0x0) // Port x mode bits (x = 8)
0x40010C08
ISTAT
// Port input status register
[15]
ISTAT15
(def=0x0) // Port input status
[14]
ISTAT14
(def=0x0) // Port input status
[13]
ISTAT13
(def=0x0) // Port input status
[12]
ISTAT12
(def=0x0) // Port input status
[11]
ISTAT11
(def=0x0) // Port input status
[10]
ISTAT10
(def=0x0) // Port input status
[9]
ISTAT9
(def=0x0) // Port input status
[8]
ISTAT8
(def=0x0) // Port input status
[7]
ISTAT7
(def=0x0) // Port input status
[6]
ISTAT6
(def=0x0) // Port input status
[5]
ISTAT5
(def=0x0) // Port input status
[4]
ISTAT4
(def=0x0) // Port input status
[3]
ISTAT3
(def=0x0) // Port input status
[2]
ISTAT2
(def=0x0) // Port input status
[1]
ISTAT1
(def=0x0) // Port input status
[0]
ISTAT0
(def=0x0) // Port input status
0x40010C0C
OCTL
// Port output control register
[15]
OCTL15
(def=0x0) // Port output control
[14]
OCTL14
(def=0x0) // Port output control
[13]
OCTL13
(def=0x0) // Port output control
[12]
OCTL12
(def=0x0) // Port output control
[11]
OCTL11
(def=0x0) // Port output control
[10]
OCTL10
(def=0x0) // Port output control
[9]
OCTL9
(def=0x0) // Port output control
[8]
OCTL8
(def=0x0) // Port output control
[7]
OCTL7
(def=0x0) // Port output control
[6]
OCTL6
(def=0x0) // Port output control
[5]
OCTL5
(def=0x0) // Port output control
[4]
OCTL4
(def=0x0) // Port output control
[3]
OCTL3
(def=0x0) // Port output control
[2]
OCTL2
(def=0x0) // Port output control
[1]
OCTL1
(def=0x0) // Port output control
[0]
OCTL0
(def=0x0) // Port output control
0x40010C10
BOP
// Port bit operate register
[31]
CR15
(def=0x0) // Port 15 Clear bit
[30]
CR14
(def=0x0) // Port 14 Clear bit
[29]
CR13
(def=0x0) // Port 13 Clear bit
[28]
CR12
(def=0x0) // Port 12 Clear bit
[27]
CR11
(def=0x0) // Port 11 Clear bit
[26]
CR10
(def=0x0) // Port 10 Clear bit
[25]
CR9
(def=0x0) // Port 9 Clear bit
[24]
CR8
(def=0x0) // Port 8 Clear bit
[23]
CR7
(def=0x0) // Port 7 Clear bit
[22]
CR6
(def=0x0) // Port 6 Clear bit
[21]
CR5
(def=0x0) // Port 5 Clear bit
[20]
CR4
(def=0x0) // Port 4 Clear bit
[19]
CR3
(def=0x0) // Port 3 Clear bit
[18]
CR2
(def=0x0) // Port 2 Clear bit
[17]
CR1
(def=0x0) // Port 1 Clear bit
[16]
CR0
(def=0x0) // Port 0 Clear bit
[15]
BOP15
(def=0x0) // Port 15 Set bit
[14]
BOP14
(def=0x0) // Port 14 Set bit
[13]
BOP13
(def=0x0) // Port 13 Set bit
[12]
BOP12
(def=0x0) // Port 12 Set bit
[11]
BOP11
(def=0x0) // Port 11 Set bit
[10]
BOP10
(def=0x0) // Port 10 Set bit
[9]
BOP9
(def=0x0) // Port 9 Set bit
[8]
BOP8
(def=0x0) // Port 8 Set bit
[7]
BOP7
(def=0x0) // Port 7 Set bit
[6]
BOP6
(def=0x0) // Port 6 Set bit
[5]
BOP5
(def=0x0) // Port 5 Set bit
[4]
BOP4
(def=0x0) // Port 4 Set bit
[3]
BOP3
(def=0x0) // Port 3 Set bit
[2]
BOP2
(def=0x0) // Port 2 Set bit
[1]
BOP1
(def=0x0) // Port 1 Set bit
[0]
BOP0
(def=0x0) // Port 0 Set bit
0x40010C14
BC
// Port bit clear register
[15]
CR15
(def=0x0) // Port 15 Clear bit
[14]
CR14
(def=0x0) // Port 14 Clear bit
[13]
CR13
(def=0x0) // Port 13 Clear bit
[12]
CR12
(def=0x0) // Port 12 Clear bit
[11]
CR11
(def=0x0) // Port 11 Clear bit
[10]
CR10
(def=0x0) // Port 10 Clear bit
[9]
CR9
(def=0x0) // Port 9 Clear bit
[8]
CR8
(def=0x0) // Port 8 Clear bit
[7]
CR7
(def=0x0) // Port 7 Clear bit
[6]
CR6
(def=0x0) // Port 6 Clear bit
[5]
CR5
(def=0x0) // Port 5 Clear bit
[4]
CR4
(def=0x0) // Port 4 Clear bit
[3]
CR3
(def=0x0) // Port 3 Clear bit
[2]
CR2
(def=0x0) // Port 2 Clear bit
[1]
CR1
(def=0x0) // Port 1 Clear bit
[0]
CR0
(def=0x0) // Port 0 Clear bit
0x40010C18
LOCK
// GPIO port configuration lock register
[16]
LKK
(def=0x0) // Lock sequence key
[15]
LK15
(def=0x0) // Port Lock bit 15
[14]
LK14
(def=0x0) // Port Lock bit 14
[13]
LK13
(def=0x0) // Port Lock bit 13
[12]
LK12
(def=0x0) // Port Lock bit 12
[11]
LK11
(def=0x0) // Port Lock bit 11
[10]
LK10
(def=0x0) // Port Lock bit 10
[9]
LK9
(def=0x0) // Port Lock bit 9
[8]
LK8
(def=0x0) // Port Lock bit 8
[7]
LK7
(def=0x0) // Port Lock bit 7
[6]
LK6
(def=0x0) // Port Lock bit 6
[5]
LK5
(def=0x0) // Port Lock bit 5
[4]
LK4
(def=0x0) // Port Lock bit 4
[3]
LK3
(def=0x0) // Port Lock bit 3
[2]
LK2
(def=0x0) // Port Lock bit 2
[1]
LK1
(def=0x0) // Port Lock bit 1
[0]
LK0
(def=0x0) // Port Lock bit 0
0x40011000
GPIOC
//
0x40011000
CTL0
// port control register 0
[30:31]
CTL7
(def=0x1) // Port x configuration bits (x = 7)
[28:29]
MD7
(def=0x0) // Port x mode bits (x = 7)
[26:27]
CTL6
(def=0x1) // Port x configuration bits (x = 6)
[24:25]
MD6
(def=0x0) // Port x mode bits (x = 6)
[22:23]
CTL5
(def=0x1) // Port x configuration bits (x = 5)
[20:21]
MD5
(def=0x0) // Port x mode bits (x = 5)
[18:19]
CTL4
(def=0x1) // Port x configuration bits (x = 4)
[16:17]
MD4
(def=0x0) // Port x mode bits (x = 4)
[14:15]
CTL3
(def=0x1) // Port x configuration bits (x = 3)
[12:13]
MD3
(def=0x0) // Port x mode bits (x = 3 )
[10:11]
CTL2
(def=0x1) // Port x configuration bits (x = 2)
[8:9]
MD2
(def=0x0) // Port x mode bits (x = 2 )
[6:7]
CTL1
(def=0x1) // Port x configuration bits (x = 1)
[4:5]
MD1
(def=0x0) // Port x mode bits (x = 1)
[2:3]
CTL0
(def=0x1) // Port x configuration bits (x = 0)
[0:1]
MD0
(def=0x0) // Port x mode bits (x = 0)
0x40011004
CTL1
// port control register 1
[30:31]
CTL15
(def=0x1) // Port x configuration bits (x = 15)
[28:29]
MD15
(def=0x0) // Port x mode bits (x = 15)
[26:27]
CTL14
(def=0x1) // Port x configuration bits (x = 14)
[24:25]
MD14
(def=0x0) // Port x mode bits (x = 14)
[22:23]
CTL13
(def=0x1) // Port x configuration bits (x = 13)
[20:21]
MD13
(def=0x0) // Port x mode bits (x = 13)
[18:19]
CTL12
(def=0x1) // Port x configuration bits (x = 12)
[16:17]
MD12
(def=0x0) // Port x mode bits (x = 12)
[14:15]
CTL11
(def=0x1) // Port x configuration bits (x = 11)
[12:13]
MD11
(def=0x0) // Port x mode bits (x = 11 )
[10:11]
CTL10
(def=0x1) // Port x configuration bits (x = 10)
[8:9]
MD10
(def=0x0) // Port x mode bits (x = 10 )
[6:7]
CTL9
(def=0x1) // Port x configuration bits (x = 9)
[4:5]
MD9
(def=0x0) // Port x mode bits (x = 9)
[2:3]
CTL8
(def=0x1) // Port x configuration bits (x = 8)
[0:1]
MD8
(def=0x0) // Port x mode bits (x = 8)
0x40011008
ISTAT
// Port input status register
[15]
ISTAT15
(def=0x0) // Port input status
[14]
ISTAT14
(def=0x0) // Port input status
[13]
ISTAT13
(def=0x0) // Port input status
[12]
ISTAT12
(def=0x0) // Port input status
[11]
ISTAT11
(def=0x0) // Port input status
[10]
ISTAT10
(def=0x0) // Port input status
[9]
ISTAT9
(def=0x0) // Port input status
[8]
ISTAT8
(def=0x0) // Port input status
[7]
ISTAT7
(def=0x0) // Port input status
[6]
ISTAT6
(def=0x0) // Port input status
[5]
ISTAT5
(def=0x0) // Port input status
[4]
ISTAT4
(def=0x0) // Port input status
[3]
ISTAT3
(def=0x0) // Port input status
[2]
ISTAT2
(def=0x0) // Port input status
[1]
ISTAT1
(def=0x0) // Port input status
[0]
ISTAT0
(def=0x0) // Port input status
0x4001100C
OCTL
// Port output control register
[15]
OCTL15
(def=0x0) // Port output control
[14]
OCTL14
(def=0x0) // Port output control
[13]
OCTL13
(def=0x0) // Port output control
[12]
OCTL12
(def=0x0) // Port output control
[11]
OCTL11
(def=0x0) // Port output control
[10]
OCTL10
(def=0x0) // Port output control
[9]
OCTL9
(def=0x0) // Port output control
[8]
OCTL8
(def=0x0) // Port output control
[7]
OCTL7
(def=0x0) // Port output control
[6]
OCTL6
(def=0x0) // Port output control
[5]
OCTL5
(def=0x0) // Port output control
[4]
OCTL4
(def=0x0) // Port output control
[3]
OCTL3
(def=0x0) // Port output control
[2]
OCTL2
(def=0x0) // Port output control
[1]
OCTL1
(def=0x0) // Port output control
[0]
OCTL0
(def=0x0) // Port output control
0x40011010
BOP
// Port bit operate register
[31]
CR15
(def=0x0) // Port 15 Clear bit
[30]
CR14
(def=0x0) // Port 14 Clear bit
[29]
CR13
(def=0x0) // Port 13 Clear bit
[28]
CR12
(def=0x0) // Port 12 Clear bit
[27]
CR11
(def=0x0) // Port 11 Clear bit
[26]
CR10
(def=0x0) // Port 10 Clear bit
[25]
CR9
(def=0x0) // Port 9 Clear bit
[24]
CR8
(def=0x0) // Port 8 Clear bit
[23]
CR7
(def=0x0) // Port 7 Clear bit
[22]
CR6
(def=0x0) // Port 6 Clear bit
[21]
CR5
(def=0x0) // Port 5 Clear bit
[20]
CR4
(def=0x0) // Port 4 Clear bit
[19]
CR3
(def=0x0) // Port 3 Clear bit
[18]
CR2
(def=0x0) // Port 2 Clear bit
[17]
CR1
(def=0x0) // Port 1 Clear bit
[16]
CR0
(def=0x0) // Port 0 Clear bit
[15]
BOP15
(def=0x0) // Port 15 Set bit
[14]
BOP14
(def=0x0) // Port 14 Set bit
[13]
BOP13
(def=0x0) // Port 13 Set bit
[12]
BOP12
(def=0x0) // Port 12 Set bit
[11]
BOP11
(def=0x0) // Port 11 Set bit
[10]
BOP10
(def=0x0) // Port 10 Set bit
[9]
BOP9
(def=0x0) // Port 9 Set bit
[8]
BOP8
(def=0x0) // Port 8 Set bit
[7]
BOP7
(def=0x0) // Port 7 Set bit
[6]
BOP6
(def=0x0) // Port 6 Set bit
[5]
BOP5
(def=0x0) // Port 5 Set bit
[4]
BOP4
(def=0x0) // Port 4 Set bit
[3]
BOP3
(def=0x0) // Port 3 Set bit
[2]
BOP2
(def=0x0) // Port 2 Set bit
[1]
BOP1
(def=0x0) // Port 1 Set bit
[0]
BOP0
(def=0x0) // Port 0 Set bit
0x40011014
BC
// Port bit clear register
[15]
CR15
(def=0x0) // Port 15 Clear bit
[14]
CR14
(def=0x0) // Port 14 Clear bit
[13]
CR13
(def=0x0) // Port 13 Clear bit
[12]
CR12
(def=0x0) // Port 12 Clear bit
[11]
CR11
(def=0x0) // Port 11 Clear bit
[10]
CR10
(def=0x0) // Port 10 Clear bit
[9]
CR9
(def=0x0) // Port 9 Clear bit
[8]
CR8
(def=0x0) // Port 8 Clear bit
[7]
CR7
(def=0x0) // Port 7 Clear bit
[6]
CR6
(def=0x0) // Port 6 Clear bit
[5]
CR5
(def=0x0) // Port 5 Clear bit
[4]
CR4
(def=0x0) // Port 4 Clear bit
[3]
CR3
(def=0x0) // Port 3 Clear bit
[2]
CR2
(def=0x0) // Port 2 Clear bit
[1]
CR1
(def=0x0) // Port 1 Clear bit
[0]
CR0
(def=0x0) // Port 0 Clear bit
0x40011018
LOCK
// GPIO port configuration lock register
[16]
LKK
(def=0x0) // Lock sequence key
[15]
LK15
(def=0x0) // Port Lock bit 15
[14]
LK14
(def=0x0) // Port Lock bit 14
[13]
LK13
(def=0x0) // Port Lock bit 13
[12]
LK12
(def=0x0) // Port Lock bit 12
[11]
LK11
(def=0x0) // Port Lock bit 11
[10]
LK10
(def=0x0) // Port Lock bit 10
[9]
LK9
(def=0x0) // Port Lock bit 9
[8]
LK8
(def=0x0) // Port Lock bit 8
[7]
LK7
(def=0x0) // Port Lock bit 7
[6]
LK6
(def=0x0) // Port Lock bit 6
[5]
LK5
(def=0x0) // Port Lock bit 5
[4]
LK4
(def=0x0) // Port Lock bit 4
[3]
LK3
(def=0x0) // Port Lock bit 3
[2]
LK2
(def=0x0) // Port Lock bit 2
[1]
LK1
(def=0x0) // Port Lock bit 1
[0]
LK0
(def=0x0) // Port Lock bit 0
0x40011400
GPIOD
//
0x40011400
CTL0
// port control register 0
[30:31]
CTL7
(def=0x1) // Port x configuration bits (x = 7)
[28:29]
MD7
(def=0x0) // Port x mode bits (x = 7)
[26:27]
CTL6
(def=0x1) // Port x configuration bits (x = 6)
[24:25]
MD6
(def=0x0) // Port x mode bits (x = 6)
[22:23]
CTL5
(def=0x1) // Port x configuration bits (x = 5)
[20:21]
MD5
(def=0x0) // Port x mode bits (x = 5)
[18:19]
CTL4
(def=0x1) // Port x configuration bits (x = 4)
[16:17]
MD4
(def=0x0) // Port x mode bits (x = 4)
[14:15]
CTL3
(def=0x1) // Port x configuration bits (x = 3)
[12:13]
MD3
(def=0x0) // Port x mode bits (x = 3 )
[10:11]
CTL2
(def=0x1) // Port x configuration bits (x = 2)
[8:9]
MD2
(def=0x0) // Port x mode bits (x = 2 )
[6:7]
CTL1
(def=0x1) // Port x configuration bits (x = 1)
[4:5]
MD1
(def=0x0) // Port x mode bits (x = 1)
[2:3]
CTL0
(def=0x1) // Port x configuration bits (x = 0)
[0:1]
MD0
(def=0x0) // Port x mode bits (x = 0)
0x40011404
CTL1
// port control register 1
[30:31]
CTL15
(def=0x1) // Port x configuration bits (x = 15)
[28:29]
MD15
(def=0x0) // Port x mode bits (x = 15)
[26:27]
CTL14
(def=0x1) // Port x configuration bits (x = 14)
[24:25]
MD14
(def=0x0) // Port x mode bits (x = 14)
[22:23]
CTL13
(def=0x1) // Port x configuration bits (x = 13)
[20:21]
MD13
(def=0x0) // Port x mode bits (x = 13)
[18:19]
CTL12
(def=0x1) // Port x configuration bits (x = 12)
[16:17]
MD12
(def=0x0) // Port x mode bits (x = 12)
[14:15]
CTL11
(def=0x1) // Port x configuration bits (x = 11)
[12:13]
MD11
(def=0x0) // Port x mode bits (x = 11 )
[10:11]
CTL10
(def=0x1) // Port x configuration bits (x = 10)
[8:9]
MD10
(def=0x0) // Port x mode bits (x = 10 )
[6:7]
CTL9
(def=0x1) // Port x configuration bits (x = 9)
[4:5]
MD9
(def=0x0) // Port x mode bits (x = 9)
[2:3]
CTL8
(def=0x1) // Port x configuration bits (x = 8)
[0:1]
MD8
(def=0x0) // Port x mode bits (x = 8)
0x40011408
ISTAT
// Port input status register
[15]
ISTAT15
(def=0x0) // Port input status
[14]
ISTAT14
(def=0x0) // Port input status
[13]
ISTAT13
(def=0x0) // Port input status
[12]
ISTAT12
(def=0x0) // Port input status
[11]
ISTAT11
(def=0x0) // Port input status
[10]
ISTAT10
(def=0x0) // Port input status
[9]
ISTAT9
(def=0x0) // Port input status
[8]
ISTAT8
(def=0x0) // Port input status
[7]
ISTAT7
(def=0x0) // Port input status
[6]
ISTAT6
(def=0x0) // Port input status
[5]
ISTAT5
(def=0x0) // Port input status
[4]
ISTAT4
(def=0x0) // Port input status
[3]
ISTAT3
(def=0x0) // Port input status
[2]
ISTAT2
(def=0x0) // Port input status
[1]
ISTAT1
(def=0x0) // Port input status
[0]
ISTAT0
(def=0x0) // Port input status
0x4001140C
OCTL
// Port output control register
[15]
OCTL15
(def=0x0) // Port output control
[14]
OCTL14
(def=0x0) // Port output control
[13]
OCTL13
(def=0x0) // Port output control
[12]
OCTL12
(def=0x0) // Port output control
[11]
OCTL11
(def=0x0) // Port output control
[10]
OCTL10
(def=0x0) // Port output control
[9]
OCTL9
(def=0x0) // Port output control
[8]
OCTL8
(def=0x0) // Port output control
[7]
OCTL7
(def=0x0) // Port output control
[6]
OCTL6
(def=0x0) // Port output control
[5]
OCTL5
(def=0x0) // Port output control
[4]
OCTL4
(def=0x0) // Port output control
[3]
OCTL3
(def=0x0) // Port output control
[2]
OCTL2
(def=0x0) // Port output control
[1]
OCTL1
(def=0x0) // Port output control
[0]
OCTL0
(def=0x0) // Port output control
0x40011410
BOP
// Port bit operate register
[31]
CR15
(def=0x0) // Port 15 Clear bit
[30]
CR14
(def=0x0) // Port 14 Clear bit
[29]
CR13
(def=0x0) // Port 13 Clear bit
[28]
CR12
(def=0x0) // Port 12 Clear bit
[27]
CR11
(def=0x0) // Port 11 Clear bit
[26]
CR10
(def=0x0) // Port 10 Clear bit
[25]
CR9
(def=0x0) // Port 9 Clear bit
[24]
CR8
(def=0x0) // Port 8 Clear bit
[23]
CR7
(def=0x0) // Port 7 Clear bit
[22]
CR6
(def=0x0) // Port 6 Clear bit
[21]
CR5
(def=0x0) // Port 5 Clear bit
[20]
CR4
(def=0x0) // Port 4 Clear bit
[19]
CR3
(def=0x0) // Port 3 Clear bit
[18]
CR2
(def=0x0) // Port 2 Clear bit
[17]
CR1
(def=0x0) // Port 1 Clear bit
[16]
CR0
(def=0x0) // Port 0 Clear bit
[15]
BOP15
(def=0x0) // Port 15 Set bit
[14]
BOP14
(def=0x0) // Port 14 Set bit
[13]
BOP13
(def=0x0) // Port 13 Set bit
[12]
BOP12
(def=0x0) // Port 12 Set bit
[11]
BOP11
(def=0x0) // Port 11 Set bit
[10]
BOP10
(def=0x0) // Port 10 Set bit
[9]
BOP9
(def=0x0) // Port 9 Set bit
[8]
BOP8
(def=0x0) // Port 8 Set bit
[7]
BOP7
(def=0x0) // Port 7 Set bit
[6]
BOP6
(def=0x0) // Port 6 Set bit
[5]
BOP5
(def=0x0) // Port 5 Set bit
[4]
BOP4
(def=0x0) // Port 4 Set bit
[3]
BOP3
(def=0x0) // Port 3 Set bit
[2]
BOP2
(def=0x0) // Port 2 Set bit
[1]
BOP1
(def=0x0) // Port 1 Set bit
[0]
BOP0
(def=0x0) // Port 0 Set bit
0x40011414
BC
// Port bit clear register
[15]
CR15
(def=0x0) // Port 15 Clear bit
[14]
CR14
(def=0x0) // Port 14 Clear bit
[13]
CR13
(def=0x0) // Port 13 Clear bit
[12]
CR12
(def=0x0) // Port 12 Clear bit
[11]
CR11
(def=0x0) // Port 11 Clear bit
[10]
CR10
(def=0x0) // Port 10 Clear bit
[9]
CR9
(def=0x0) // Port 9 Clear bit
[8]
CR8
(def=0x0) // Port 8 Clear bit
[7]
CR7
(def=0x0) // Port 7 Clear bit
[6]
CR6
(def=0x0) // Port 6 Clear bit
[5]
CR5
(def=0x0) // Port 5 Clear bit
[4]
CR4
(def=0x0) // Port 4 Clear bit
[3]
CR3
(def=0x0) // Port 3 Clear bit
[2]
CR2
(def=0x0) // Port 2 Clear bit
[1]
CR1
(def=0x0) // Port 1 Clear bit
[0]
CR0
(def=0x0) // Port 0 Clear bit
0x40011418
LOCK
// GPIO port configuration lock register
[16]
LKK
(def=0x0) // Lock sequence key
[15]
LK15
(def=0x0) // Port Lock bit 15
[14]
LK14
(def=0x0) // Port Lock bit 14
[13]
LK13
(def=0x0) // Port Lock bit 13
[12]
LK12
(def=0x0) // Port Lock bit 12
[11]
LK11
(def=0x0) // Port Lock bit 11
[10]
LK10
(def=0x0) // Port Lock bit 10
[9]
LK9
(def=0x0) // Port Lock bit 9
[8]
LK8
(def=0x0) // Port Lock bit 8
[7]
LK7
(def=0x0) // Port Lock bit 7
[6]
LK6
(def=0x0) // Port Lock bit 6
[5]
LK5
(def=0x0) // Port Lock bit 5
[4]
LK4
(def=0x0) // Port Lock bit 4
[3]
LK3
(def=0x0) // Port Lock bit 3
[2]
LK2
(def=0x0) // Port Lock bit 2
[1]
LK1
(def=0x0) // Port Lock bit 1
[0]
LK0
(def=0x0) // Port Lock bit 0
0x40011800
GPIOE
//
0x40011800
CTL0
// port control register 0
[30:31]
CTL7
(def=0x1) // Port x configuration bits (x = 7)
[28:29]
MD7
(def=0x0) // Port x mode bits (x = 7)
[26:27]
CTL6
(def=0x1) // Port x configuration bits (x = 6)
[24:25]
MD6
(def=0x0) // Port x mode bits (x = 6)
[22:23]
CTL5
(def=0x1) // Port x configuration bits (x = 5)
[20:21]
MD5
(def=0x0) // Port x mode bits (x = 5)
[18:19]
CTL4
(def=0x1) // Port x configuration bits (x = 4)
[16:17]
MD4
(def=0x0) // Port x mode bits (x = 4)
[14:15]
CTL3
(def=0x1) // Port x configuration bits (x = 3)
[12:13]
MD3
(def=0x0) // Port x mode bits (x = 3 )
[10:11]
CTL2
(def=0x1) // Port x configuration bits (x = 2)
[8:9]
MD2
(def=0x0) // Port x mode bits (x = 2 )
[6:7]
CTL1
(def=0x1) // Port x configuration bits (x = 1)
[4:5]
MD1
(def=0x0) // Port x mode bits (x = 1)
[2:3]
CTL0
(def=0x1) // Port x configuration bits (x = 0)
[0:1]
MD0
(def=0x0) // Port x mode bits (x = 0)
0x40011804
CTL1
// port control register 1
[30:31]
CTL15
(def=0x1) // Port x configuration bits (x = 15)
[28:29]
MD15
(def=0x0) // Port x mode bits (x = 15)
[26:27]
CTL14
(def=0x1) // Port x configuration bits (x = 14)
[24:25]
MD14
(def=0x0) // Port x mode bits (x = 14)
[22:23]
CTL13
(def=0x1) // Port x configuration bits (x = 13)
[20:21]
MD13
(def=0x0) // Port x mode bits (x = 13)
[18:19]
CTL12
(def=0x1) // Port x configuration bits (x = 12)
[16:17]
MD12
(def=0x0) // Port x mode bits (x = 12)
[14:15]
CTL11
(def=0x1) // Port x configuration bits (x = 11)
[12:13]
MD11
(def=0x0) // Port x mode bits (x = 11 )
[10:11]
CTL10
(def=0x1) // Port x configuration bits (x = 10)
[8:9]
MD10
(def=0x0) // Port x mode bits (x = 10 )
[6:7]
CTL9
(def=0x1) // Port x configuration bits (x = 9)
[4:5]
MD9
(def=0x0) // Port x mode bits (x = 9)
[2:3]
CTL8
(def=0x1) // Port x configuration bits (x = 8)
[0:1]
MD8
(def=0x0) // Port x mode bits (x = 8)
0x40011808
ISTAT
// Port input status register
[15]
ISTAT15
(def=0x0) // Port input status
[14]
ISTAT14
(def=0x0) // Port input status
[13]
ISTAT13
(def=0x0) // Port input status
[12]
ISTAT12
(def=0x0) // Port input status
[11]
ISTAT11
(def=0x0) // Port input status
[10]
ISTAT10
(def=0x0) // Port input status
[9]
ISTAT9
(def=0x0) // Port input status
[8]
ISTAT8
(def=0x0) // Port input status
[7]
ISTAT7
(def=0x0) // Port input status
[6]
ISTAT6
(def=0x0) // Port input status
[5]
ISTAT5
(def=0x0) // Port input status
[4]
ISTAT4
(def=0x0) // Port input status
[3]
ISTAT3
(def=0x0) // Port input status
[2]
ISTAT2
(def=0x0) // Port input status
[1]
ISTAT1
(def=0x0) // Port input status
[0]
ISTAT0
(def=0x0) // Port input status
0x4001180C
OCTL
// Port output control register
[15]
OCTL15
(def=0x0) // Port output control
[14]
OCTL14
(def=0x0) // Port output control
[13]
OCTL13
(def=0x0) // Port output control
[12]
OCTL12
(def=0x0) // Port output control
[11]
OCTL11
(def=0x0) // Port output control
[10]
OCTL10
(def=0x0) // Port output control
[9]
OCTL9
(def=0x0) // Port output control
[8]
OCTL8
(def=0x0) // Port output control
[7]
OCTL7
(def=0x0) // Port output control
[6]
OCTL6
(def=0x0) // Port output control
[5]
OCTL5
(def=0x0) // Port output control
[4]
OCTL4
(def=0x0) // Port output control
[3]
OCTL3
(def=0x0) // Port output control
[2]
OCTL2
(def=0x0) // Port output control
[1]
OCTL1
(def=0x0) // Port output control
[0]
OCTL0
(def=0x0) // Port output control
0x40011810
BOP
// Port bit operate register
[31]
CR15
(def=0x0) // Port 15 Clear bit
[30]
CR14
(def=0x0) // Port 14 Clear bit
[29]
CR13
(def=0x0) // Port 13 Clear bit
[28]
CR12
(def=0x0) // Port 12 Clear bit
[27]
CR11
(def=0x0) // Port 11 Clear bit
[26]
CR10
(def=0x0) // Port 10 Clear bit
[25]
CR9
(def=0x0) // Port 9 Clear bit
[24]
CR8
(def=0x0) // Port 8 Clear bit
[23]
CR7
(def=0x0) // Port 7 Clear bit
[22]
CR6
(def=0x0) // Port 6 Clear bit
[21]
CR5
(def=0x0) // Port 5 Clear bit
[20]
CR4
(def=0x0) // Port 4 Clear bit
[19]
CR3
(def=0x0) // Port 3 Clear bit
[18]
CR2
(def=0x0) // Port 2 Clear bit
[17]
CR1
(def=0x0) // Port 1 Clear bit
[16]
CR0
(def=0x0) // Port 0 Clear bit
[15]
BOP15
(def=0x0) // Port 15 Set bit
[14]
BOP14
(def=0x0) // Port 14 Set bit
[13]
BOP13
(def=0x0) // Port 13 Set bit
[12]
BOP12
(def=0x0) // Port 12 Set bit
[11]
BOP11
(def=0x0) // Port 11 Set bit
[10]
BOP10
(def=0x0) // Port 10 Set bit
[9]
BOP9
(def=0x0) // Port 9 Set bit
[8]
BOP8
(def=0x0) // Port 8 Set bit
[7]
BOP7
(def=0x0) // Port 7 Set bit
[6]
BOP6
(def=0x0) // Port 6 Set bit
[5]
BOP5
(def=0x0) // Port 5 Set bit
[4]
BOP4
(def=0x0) // Port 4 Set bit
[3]
BOP3
(def=0x0) // Port 3 Set bit
[2]
BOP2
(def=0x0) // Port 2 Set bit
[1]
BOP1
(def=0x0) // Port 1 Set bit
[0]
BOP0
(def=0x0) // Port 0 Set bit
0x40011814
BC
// Port bit clear register
[15]
CR15
(def=0x0) // Port 15 Clear bit
[14]
CR14
(def=0x0) // Port 14 Clear bit
[13]
CR13
(def=0x0) // Port 13 Clear bit
[12]
CR12
(def=0x0) // Port 12 Clear bit
[11]
CR11
(def=0x0) // Port 11 Clear bit
[10]
CR10
(def=0x0) // Port 10 Clear bit
[9]
CR9
(def=0x0) // Port 9 Clear bit
[8]
CR8
(def=0x0) // Port 8 Clear bit
[7]
CR7
(def=0x0) // Port 7 Clear bit
[6]
CR6
(def=0x0) // Port 6 Clear bit
[5]
CR5
(def=0x0) // Port 5 Clear bit
[4]
CR4
(def=0x0) // Port 4 Clear bit
[3]
CR3
(def=0x0) // Port 3 Clear bit
[2]
CR2
(def=0x0) // Port 2 Clear bit
[1]
CR1
(def=0x0) // Port 1 Clear bit
[0]
CR0
(def=0x0) // Port 0 Clear bit
0x40011818
LOCK
// GPIO port configuration lock register
[16]
LKK
(def=0x0) // Lock sequence key
[15]
LK15
(def=0x0) // Port Lock bit 15
[14]
LK14
(def=0x0) // Port Lock bit 14
[13]
LK13
(def=0x0) // Port Lock bit 13
[12]
LK12
(def=0x0) // Port Lock bit 12
[11]
LK11
(def=0x0) // Port Lock bit 11
[10]
LK10
(def=0x0) // Port Lock bit 10
[9]
LK9
(def=0x0) // Port Lock bit 9
[8]
LK8
(def=0x0) // Port Lock bit 8
[7]
LK7
(def=0x0) // Port Lock bit 7
[6]
LK6
(def=0x0) // Port Lock bit 6
[5]
LK5
(def=0x0) // Port Lock bit 5
[4]
LK4
(def=0x0) // Port Lock bit 4
[3]
LK3
(def=0x0) // Port Lock bit 3
[2]
LK2
(def=0x0) // Port Lock bit 2
[1]
LK1
(def=0x0) // Port Lock bit 1
[0]
LK0
(def=0x0) // Port Lock bit 0
0x40005400
I2C0
// Inter integrated circuit
0x40005400
CTL0
// Control register 0
[15]
SRESET
(def=0x0) // Software reset
[13]
SALT
(def=0x0) // SMBus alert
[12]
PECTRANS
(def=0x0) // PEC Transfer
[11]
POAP
(def=0x0) // Position of ACK and PEC when receiving
[10]
ACKEN
(def=0x0) // Whether or not to send an ACK
[9]
STOP
(def=0x0) // Generate a STOP condition on I2C bus
[8]
START
(def=0x0) // Generate a START condition on I2C bus
[7]
SS
(def=0x0) // Whether to stretch SCL low when data is not ready in slave mode
[6]
GCEN
(def=0x0) // Whether or not to response to a General Call (0x00)
[5]
PECEN
(def=0x0) // PEC Calculation Switch
[4]
ARPEN
(def=0x0) // ARP protocol in SMBus switch
[3]
SMBSEL
(def=0x0) // SMBusType Selection
[1]
SMBEN
(def=0x0) // SMBus/I2C mode switch
[0]
I2CEN
(def=0x0) // I2C peripheral enable
0x40005404
CTL1
// Control register 1
[12]
DMALST
(def=0x0) // Flag indicating DMA last transfer
[11]
DMAON
(def=0x0) // DMA mode switch
[10]
BUFIE
(def=0x0) // Buffer interrupt enable
[9]
EVIE
(def=0x0) // Event interrupt enable
[8]
ERRIE
(def=0x0) // Error interrupt enable
[0:5]
I2CCLK
(def=0x0) // I2C Peripheral clock frequency
0x40005408
SADDR0
// Slave address register 0
[15]
ADDFORMAT
(def=0x0) // Address mode for the I2C slave
[8:9]
ADDRESS9_8
(def=0x0) // Highest two bits of a 10-bit address
[1:7]
ADDRESS7_1
(def=0x0) // 7-bit address or bits 7:1 of a 10-bit address
[0]
ADDRESS0
(def=0x0) // Bit 0 of a 10-bit address
0x4000540C
SADDR1
// Slave address register 1
[1:7]
ADDRESS2
(def=0x0) // Second I2C address for the slave in Dual-Address mode
[0]
DUADEN
(def=0x0) // Dual-Address mode switch
0x40005410
DATA
// Transfer buffer register
[0:7]
TRB
(def=0x0) // Transmission or reception data buffer register
0x40005414
STAT0
// Transfer status register 0
[15]
SMBALT
(def=0x0) // SMBus Alert status
[14]
SMBTO
(def=0x0) // Timeout signal in SMBus mode
[12]
PECERR
(def=0x0) // PEC error when receiving data
[11]
OUERR
(def=0x0) // Over-run or under-run situation occurs in slave mode
[10]
AERR
(def=0x0) // Acknowledge error
[9]
LOSTARB
(def=0x0) // Arbitration Lost in master mode
[8]
BERR
(def=0x0) // A bus error occurs indication a unexpected START or STOP condition on I2C bus
[7]
TBE
(def=0x0) // I2C_DATA is Empty during transmitting
[6]
RBNE
(def=0x0) // I2C_DATA is not Empty during receiving
[4]
STPDET
(def=0x0) // STOP condition detected in slave mode
[3]
ADD10SEND
(def=0x0) // Header of 10-bit address is sent in master mode
[2]
BTC
(def=0x0) // Byte transmission completed
[1]
ADDSEND
(def=0x0) // Address is sent in master mode or received and matches in slave mode
[0]
SBSEND
(def=0x0) // START condition sent out in master mode
0x40005418
STAT1
// Transfer status register 1
[8:15]
PECV
(def=0x0) // Packet Error Checking Value that calculated by hardware when PEC is enabled
[7]
DUMODF
(def=0x0) // Dual Flag in slave mode
[6]
HSTSMB
(def=0x0) // SMBus Host Header detected in slave mode
[5]
DEFSMB
(def=0x0) // Default address of SMBusDevice
[4]
RXGC
(def=0x0) // General call address (00h) received
[2]
TR
(def=0x0) // Whether the I2C is a transmitter or a receiver
[1]
I2CBSY
(def=0x0) // Busy flag
[0]
MASTER
(def=0x0) // A flag indicating whether I2C block is in master or slave mode
0x4000541C
CKCFG
// Clock configure register
[15]
FAST
(def=0x0) // I2C speed selection in master mode
[14]
DTCY
(def=0x0) // Duty cycle in fast mode
[0:11]
CLKC
(def=0x0) // I2C Clock control in master mode
0x40005420
RT
// Rise time register
[0:5]
RISETIME
(def=0x2) // Maximum rise time in master mode
interrupts:
[50]
I2C0_EV
//
[51]
I2C0_ER
//
0x40005800
I2C1
//
0x40005800
CTL0
// Control register 0
[15]
SRESET
(def=0x0) // Software reset
[13]
SALT
(def=0x0) // SMBus alert
[12]
PECTRANS
(def=0x0) // PEC Transfer
[11]
POAP
(def=0x0) // Position of ACK and PEC when receiving
[10]
ACKEN
(def=0x0) // Whether or not to send an ACK
[9]
STOP
(def=0x0) // Generate a STOP condition on I2C bus
[8]
START
(def=0x0) // Generate a START condition on I2C bus
[7]
SS
(def=0x0) // Whether to stretch SCL low when data is not ready in slave mode
[6]
GCEN
(def=0x0) // Whether or not to response to a General Call (0x00)
[5]
PECEN
(def=0x0) // PEC Calculation Switch
[4]
ARPEN
(def=0x0) // ARP protocol in SMBus switch
[3]
SMBSEL
(def=0x0) // SMBusType Selection
[1]
SMBEN
(def=0x0) // SMBus/I2C mode switch
[0]
I2CEN
(def=0x0) // I2C peripheral enable
0x40005804
CTL1
// Control register 1
[12]
DMALST
(def=0x0) // Flag indicating DMA last transfer
[11]
DMAON
(def=0x0) // DMA mode switch
[10]
BUFIE
(def=0x0) // Buffer interrupt enable
[9]
EVIE
(def=0x0) // Event interrupt enable
[8]
ERRIE
(def=0x0) // Error interrupt enable
[0:5]
I2CCLK
(def=0x0) // I2C Peripheral clock frequency
0x40005808
SADDR0
// Slave address register 0
[15]
ADDFORMAT
(def=0x0) // Address mode for the I2C slave
[8:9]
ADDRESS9_8
(def=0x0) // Highest two bits of a 10-bit address
[1:7]
ADDRESS7_1
(def=0x0) // 7-bit address or bits 7:1 of a 10-bit address
[0]
ADDRESS0
(def=0x0) // Bit 0 of a 10-bit address
0x4000580C
SADDR1
// Slave address register 1
[1:7]
ADDRESS2
(def=0x0) // Second I2C address for the slave in Dual-Address mode
[0]
DUADEN
(def=0x0) // Dual-Address mode switch
0x40005810
DATA
// Transfer buffer register
[0:7]
TRB
(def=0x0) // Transmission or reception data buffer register
0x40005814
STAT0
// Transfer status register 0
[15]
SMBALT
(def=0x0) // SMBus Alert status
[14]
SMBTO
(def=0x0) // Timeout signal in SMBus mode
[12]
PECERR
(def=0x0) // PEC error when receiving data
[11]
OUERR
(def=0x0) // Over-run or under-run situation occurs in slave mode
[10]
AERR
(def=0x0) // Acknowledge error
[9]
LOSTARB
(def=0x0) // Arbitration Lost in master mode
[8]
BERR
(def=0x0) // A bus error occurs indication a unexpected START or STOP condition on I2C bus
[7]
TBE
(def=0x0) // I2C_DATA is Empty during transmitting
[6]
RBNE
(def=0x0) // I2C_DATA is not Empty during receiving
[4]
STPDET
(def=0x0) // STOP condition detected in slave mode
[3]
ADD10SEND
(def=0x0) // Header of 10-bit address is sent in master mode
[2]
BTC
(def=0x0) // Byte transmission completed
[1]
ADDSEND
(def=0x0) // Address is sent in master mode or received and matches in slave mode
[0]
SBSEND
(def=0x0) // START condition sent out in master mode
0x40005818
STAT1
// Transfer status register 1
[8:15]
PECV
(def=0x0) // Packet Error Checking Value that calculated by hardware when PEC is enabled
[7]
DUMODF
(def=0x0) // Dual Flag in slave mode
[6]
HSTSMB
(def=0x0) // SMBus Host Header detected in slave mode
[5]
DEFSMB
(def=0x0) // Default address of SMBusDevice
[4]
RXGC
(def=0x0) // General call address (00h) received
[2]
TR
(def=0x0) // Whether the I2C is a transmitter or a receiver
[1]
I2CBSY
(def=0x0) // Busy flag
[0]
MASTER
(def=0x0) // A flag indicating whether I2C block is in master or slave mode
0x4000581C
CKCFG
// Clock configure register
[15]
FAST
(def=0x0) // I2C speed selection in master mode
[14]
DTCY
(def=0x0) // Duty cycle in fast mode
[0:11]
CLKC
(def=0x0) // I2C Clock control in master mode
0x40005820
RT
// Rise time register
[0:5]
RISETIME
(def=0x2) // Maximum rise time in master mode
interrupts:
[52]
I2C1_EV
//
[53]
I2C1_ER
//
0xD2000000
ECLIC
// Enhanced Core Local Interrupt Controller
0xD2000000
CLICCFG
// cliccfg Register
[1:4]
NLBITS
(def=0x0) // NLBITS
0xD2000004
CLICINFO
// clicinfo Register
[0:12]
NUM_INTERRUPT
(def=0x0) // NUM_INTERRUPT
[13:20]
VERSION
(def=0x0) // VERSION
[21:24]
CLICINTCTLBITS
(def=0x0) // CLICINTCTLBITS
0xD200000B
MTH
// MTH Register
[0:7]
MTH
(def=0x0) // MTH
0xD2001000
CLICINTIP_0
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001004
CLICINTIP_1
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001008
CLICINTIP_2
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200100C
CLICINTIP_3
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001010
CLICINTIP_4
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001014
CLICINTIP_5
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001018
CLICINTIP_6
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200101C
CLICINTIP_7
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001020
CLICINTIP_8
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001024
CLICINTIP_9
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001028
CLICINTIP_10
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200102C
CLICINTIP_11
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001030
CLICINTIP_12
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001034
CLICINTIP_13
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001038
CLICINTIP_14
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200103C
CLICINTIP_15
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001040
CLICINTIP_16
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001044
CLICINTIP_17
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001048
CLICINTIP_18
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200104C
CLICINTIP_19
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001050
CLICINTIP_20
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001054
CLICINTIP_21
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001058
CLICINTIP_22
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200105C
CLICINTIP_23
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001060
CLICINTIP_24
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001064
CLICINTIP_25
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001068
CLICINTIP_26
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200106C
CLICINTIP_27
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001070
CLICINTIP_28
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001074
CLICINTIP_29
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001078
CLICINTIP_30
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200107C
CLICINTIP_31
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001080
CLICINTIP_32
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001084
CLICINTIP_33
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001088
CLICINTIP_34
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200108C
CLICINTIP_35
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001090
CLICINTIP_36
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001094
CLICINTIP_37
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001098
CLICINTIP_38
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200109C
CLICINTIP_39
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010A0
CLICINTIP_40
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010A4
CLICINTIP_41
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010A8
CLICINTIP_42
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010AC
CLICINTIP_43
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010B0
CLICINTIP_44
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010B4
CLICINTIP_45
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010B8
CLICINTIP_46
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010BC
CLICINTIP_47
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010C0
CLICINTIP_48
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010C4
CLICINTIP_49
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010C8
CLICINTIP_50
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010CC
CLICINTIP_51
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010D0
CLICINTIP_52
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010D4
CLICINTIP_53
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010D8
CLICINTIP_54
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010DC
CLICINTIP_55
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010E0
CLICINTIP_56
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010E4
CLICINTIP_57
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010E8
CLICINTIP_58
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010EC
CLICINTIP_59
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010F0
CLICINTIP_60
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010F4
CLICINTIP_61
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010F8
CLICINTIP_62
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD20010FC
CLICINTIP_63
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001100
CLICINTIP_64
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001104
CLICINTIP_65
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001108
CLICINTIP_66
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200110C
CLICINTIP_67
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001110
CLICINTIP_68
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001114
CLICINTIP_69
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001118
CLICINTIP_70
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200111C
CLICINTIP_71
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001120
CLICINTIP_72
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001124
CLICINTIP_73
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001128
CLICINTIP_74
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200112C
CLICINTIP_75
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001130
CLICINTIP_76
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001134
CLICINTIP_77
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001138
CLICINTIP_78
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200113C
CLICINTIP_79
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001140
CLICINTIP_80
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001144
CLICINTIP_81
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001148
CLICINTIP_82
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200114C
CLICINTIP_83
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001150
CLICINTIP_84
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001158
CLICINTIP_85
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD200115C
CLICINTIP_86
// clicintip Register
[0]
IP
(def=0x0) // IP
0xD2001001
CLICINTIE_0
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001005
CLICINTIE_1
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001009
CLICINTIE_2
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200100D
CLICINTIE_3
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001011
CLICINTIE_4
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001015
CLICINTIE_5
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001019
CLICINTIE_6
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200101D
CLICINTIE_7
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001021
CLICINTIE_8
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001025
CLICINTIE_9
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001029
CLICINTIE_10
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200102D
CLICINTIE_11
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001031
CLICINTIE_12
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001035
CLICINTIE_13
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001039
CLICINTIE_14
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200103D
CLICINTIE_15
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001041
CLICINTIE_16
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001045
CLICINTIE_17
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001049
CLICINTIE_18
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200104D
CLICINTIE_19
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001051
CLICINTIE_20
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001055
CLICINTIE_21
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001059
CLICINTIE_22
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200105D
CLICINTIE_23
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001061
CLICINTIE_24
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001065
CLICINTIE_25
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001069
CLICINTIE_26
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200106D
CLICINTIE_27
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001071
CLICINTIE_28
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001075
CLICINTIE_29
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001079
CLICINTIE_30
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200107D
CLICINTIE_31
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001081
CLICINTIE_32
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001085
CLICINTIE_33
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001089
CLICINTIE_34
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200108D
CLICINTIE_35
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001091
CLICINTIE_36
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001095
CLICINTIE_37
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001099
CLICINTIE_38
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200109D
CLICINTIE_39
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010A1
CLICINTIE_40
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010A5
CLICINTIE_41
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010A9
CLICINTIE_42
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010AD
CLICINTIE_43
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010B1
CLICINTIE_44
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010B5
CLICINTIE_45
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010B9
CLICINTIE_46
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010BD
CLICINTIE_47
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010C1
CLICINTIE_48
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010C5
CLICINTIE_49
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010C9
CLICINTIE_50
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010CD
CLICINTIE_51
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010D1
CLICINTIE_52
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010D5
CLICINTIE_53
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010D9
CLICINTIE_54
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010DD
CLICINTIE_55
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010E1
CLICINTIE_56
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010E5
CLICINTIE_57
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010E9
CLICINTIE_58
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010ED
CLICINTIE_59
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010F1
CLICINTIE_60
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010F5
CLICINTIE_61
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010F9
CLICINTIE_62
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD20010FD
CLICINTIE_63
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001101
CLICINTIE_64
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001105
CLICINTIE_65
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001109
CLICINTIE_66
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200110D
CLICINTIE_67
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001111
CLICINTIE_68
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001115
CLICINTIE_69
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001119
CLICINTIE_70
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200111D
CLICINTIE_71
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001121
CLICINTIE_72
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001125
CLICINTIE_73
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001129
CLICINTIE_74
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200112D
CLICINTIE_75
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001131
CLICINTIE_76
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001135
CLICINTIE_77
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001139
CLICINTIE_78
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200113D
CLICINTIE_79
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001141
CLICINTIE_80
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001145
CLICINTIE_81
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001149
CLICINTIE_82
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD200114D
CLICINTIE_83
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001151
CLICINTIE_84
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001155
CLICINTIE_85
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001159
CLICINTIE_86
// clicintie Register
[0]
IE
(def=0x0) // IE
0xD2001002
CLICINTATTR_0
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001006
CLICINTATTR_1
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200100A
CLICINTATTR_2
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200100E
CLICINTATTR_3
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001012
CLICINTATTR_4
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001016
CLICINTATTR_5
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200101A
CLICINTATTR_6
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200101E
CLICINTATTR_7
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001022
CLICINTATTR_8
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001026
CLICINTATTR_9
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200102A
CLICINTATTR_10
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200102E
CLICINTATTR_11
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001032
CLICINTATTR_12
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001036
CLICINTATTR_13
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200103A
CLICINTATTR_14
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200103E
CLICINTATTR_15
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001042
CLICINTATTR_16
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001046
CLICINTATTR_17
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200104A
CLICINTATTR_18
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200104E
CLICINTATTR_19
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001052
CLICINTATTR_20
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001056
CLICINTATTR_21
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200105A
CLICINTATTR_22
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200105E
CLICINTATTR_23
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001062
CLICINTATTR_24
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001066
CLICINTATTR_25
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200106A
CLICINTATTR_26
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200106E
CLICINTATTR_27
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001072
CLICINTATTR_28
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001076
CLICINTATTR_29
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200107A
CLICINTATTR_30
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200107E
CLICINTATTR_31
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001082
CLICINTATTR_32
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001086
CLICINTATTR_33
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200108A
CLICINTATTR_34
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200108E
CLICINTATTR_35
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001092
CLICINTATTR_36
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001096
CLICINTATTR_37
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200109A
CLICINTATTR_38
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200109E
CLICINTATTR_39
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010A2
CLICINTATTR_40
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010A6
CLICINTATTR_41
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010AA
CLICINTATTR_42
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010AE
CLICINTATTR_43
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010B2
CLICINTATTR_44
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010B6
CLICINTATTR_45
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010BA
CLICINTATTR_46
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010BE
CLICINTATTR_47
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010C2
CLICINTATTR_48
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010C6
CLICINTATTR_49
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010CA
CLICINTATTR_50
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010CE
CLICINTATTR_51
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010D2
CLICINTATTR_52
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010D6
CLICINTATTR_53
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010DA
CLICINTATTR_54
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010DE
CLICINTATTR_55
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010E2
CLICINTATTR_56
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010E6
CLICINTATTR_57
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010EA
CLICINTATTR_58
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010EE
CLICINTATTR_59
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010F2
CLICINTATTR_60
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010F6
CLICINTATTR_61
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010FA
CLICINTATTR_62
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD20010FE
CLICINTATTR_63
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001102
CLICINTATTR_64
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001106
CLICINTATTR_65
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200110A
CLICINTATTR_66
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200110E
CLICINTATTR_67
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001112
CLICINTATTR_68
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001116
CLICINTATTR_69
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200111A
CLICINTATTR_70
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200111E
CLICINTATTR_71
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001122
CLICINTATTR_72
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001126
CLICINTATTR_73
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200112A
CLICINTATTR_74
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200112E
CLICINTATTR_75
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001132
CLICINTATTR_76
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001136
CLICINTATTR_77
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200113A
CLICINTATTR_78
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200113E
CLICINTATTR_79
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001142
CLICINTATTR_80
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001146
CLICINTATTR_81
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200114A
CLICINTATTR_82
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200114E
CLICINTATTR_83
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001152
CLICINTATTR_84
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001156
CLICINTATTR_85
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD200115A
CLICINTATTR_86
// clicintattr Register
[0]
SHV
(def=0x0) // SHV
[1:2]
TRIG
(def=0x0) // TRIG
0xD2001003
CLICINTCTL_0
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001007
CLICINTCTL_1
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200100B
CLICINTCTL_2
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200100F
CLICINTCTL_3
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001013
CLICINTCTL_4
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001017
CLICINTCTL_5
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200101B
CLICINTCTL_6
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200101F
CLICINTCTL_7
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001023
CLICINTCTL_8
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001027
CLICINTCTL_9
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200102B
CLICINTCTL_10
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200102F
CLICINTCTL_11
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001033
CLICINTCTL_12
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001037
CLICINTCTL_13
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200103B
CLICINTCTL_14
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200103F
CLICINTCTL_15
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001043
CLICINTCTL_16
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001047
CLICINTCTL_17
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200104B
CLICINTCTL_18
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200104F
CLICINTCTL_19
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001053
CLICINTCTL_20
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001057
CLICINTCTL_21
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200105B
CLICINTCTL_22
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200105F
CLICINTCTL_23
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001063
CLICINTCTL_24
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001067
CLICINTCTL_25
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200106B
CLICINTCTL_26
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200106F
CLICINTCTL_27
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001073
CLICINTCTL_28
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001077
CLICINTCTL_29
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200107B
CLICINTCTL_30
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200107F
CLICINTCTL_31
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001083
CLICINTCTL_32
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001087
CLICINTCTL_33
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200108B
CLICINTCTL_34
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200108F
CLICINTCTL_35
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001093
CLICINTCTL_36
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001097
CLICINTCTL_37
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200109B
CLICINTCTL_38
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200109F
CLICINTCTL_39
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010A3
CLICINTCTL_40
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010A7
CLICINTCTL_41
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010AB
CLICINTCTL_42
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010AF
CLICINTCTL_43
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010B3
CLICINTCTL_44
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010B7
CLICINTCTL_45
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010BB
CLICINTCTL_46
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010BF
CLICINTCTL_47
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010C3
CLICINTCTL_48
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010C7
CLICINTCTL_49
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010CB
CLICINTCTL_50
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010CF
CLICINTCTL_51
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010D3
CLICINTCTL_52
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010D7
CLICINTCTL_53
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010DB
CLICINTCTL_54
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010DF
CLICINTCTL_55
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010E3
CLICINTCTL_56
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010E7
CLICINTCTL_57
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010EB
CLICINTCTL_58
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010EF
CLICINTCTL_59
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010F3
CLICINTCTL_60
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010F7
CLICINTCTL_61
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010FB
CLICINTCTL_62
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD20010FF
CLICINTCTL_63
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001103
CLICINTCTL_64
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001107
CLICINTCTL_65
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200110B
CLICINTCTL_66
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200110F
CLICINTCTL_67
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001113
CLICINTCTL_68
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001117
CLICINTCTL_69
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200111B
CLICINTCTL_70
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200111F
CLICINTCTL_71
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001123
CLICINTCTL_72
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001127
CLICINTCTL_73
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200112B
CLICINTCTL_74
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200112F
CLICINTCTL_75
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001133
CLICINTCTL_76
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001137
CLICINTCTL_77
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200113B
CLICINTCTL_78
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200113F
CLICINTCTL_79
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001143
CLICINTCTL_80
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001147
CLICINTCTL_81
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200114B
CLICINTCTL_82
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200114F
CLICINTCTL_83
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001153
CLICINTCTL_84
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD2001157
CLICINTCTL_85
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0xD200115B
CLICINTCTL_86
// clicintctl Register
[0:7]
LEVEL_PRIORITY
(def=0x0) // LEVEL_PRIORITY
0x40007000
PMU
// Power management unit
0x40007000
CTL
// power control register
[8]
BKPWEN
(def=0x0) // Backup Domain Write Enable
[5:7]
LVDT
(def=0x0) // Low Voltage Detector Threshold
[4]
LVDEN
(def=0x0) // Low Voltage Detector Enable
[3]
STBRST
(def=0x0) // Standby Flag Reset
[2]
WURST
(def=0x0) // Wakeup Flag Reset
[1]
STBMOD
(def=0x0) // Standby Mode
[0]
LDOLP
(def=0x0) // LDO Low Power Mode
0x40007004
CS
// power control/status register
[8]
WUPEN
(def=0x0) // Enable WKUP pin
[2]
LVDF
(def=0x0) // Low Voltage Detector Status Flag
[1]
STBF
(def=0x0) // Standby flag
[0]
WUF
(def=0x0) // Wakeup flag
0x40021000
RCU
// Reset and clock unit
0x40021000
CTL
// Control register
[0]
IRC8MEN
(def=0x1) // Internal 8MHz RC oscillator Enable
[1]
IRC8MSTB
(def=0x1) // IRC8M Internal 8MHz RC Oscillator stabilization Flag
[3:7]
IRC8MADJ
(def=0x10) // Internal 8MHz RC Oscillator clock trim adjust value
[8:15]
IRC8MCALIB
(def=0x0) // Internal 8MHz RC Oscillator calibration value register
[16]
HXTALEN
(def=0x0) // External High Speed oscillator Enable
[17]
HXTALSTB
(def=0x0) // External crystal oscillator (HXTAL) clock stabilization flag
[18]
HXTALBPS
(def=0x0) // External crystal oscillator (HXTAL) clock bypass mode enable
[19]
CKMEN
(def=0x0) // HXTAL Clock Monitor Enable
[24]
PLLEN
(def=0x0) // PLL enable
[25]
PLLSTB
(def=0x0) // PLL Clock Stabilization Flag
[26]
PLL1EN
(def=0x0) // PLL1 enable
[27]
PLL1STB
(def=0x0) // PLL1 Clock Stabilization Flag
[28]
PLL2EN
(def=0x0) // PLL2 enable
[29]
PLL2STB
(def=0x0) // PLL2 Clock Stabilization Flag
0x40021004
CFG0
// Clock configuration register 0 (RCU_CFG0)
[0:1]
SCS
(def=0x0) // System clock switch
[2:3]
SCSS
(def=0x0) // System clock switch status
[4:7]
AHBPSC
(def=0x0) // AHB prescaler selection
[8:10]
APB1PSC
(def=0x0) // APB1 prescaler selection
[11:13]
APB2PSC
(def=0x0) // APB2 prescaler selection
[14:15]
ADCPSC_1_0
(def=0x0) // ADC clock prescaler selection
[16]
PLLSEL
(def=0x0) // PLL Clock Source Selection
[17]
PREDV0_LSB
(def=0x0) // The LSB of PREDV0 division factor
[18:21]
PLLMF_3_0
(def=0x0) // The PLL clock multiplication factor
[22:23]
USBFSPSC
(def=0x0) // USBFS clock prescaler selection
[24:27]
CKOUT0SEL
(def=0x0) // CKOUT0 Clock Source Selection
[28]
ADCPSC_2
(def=0x0) // Bit 2 of ADCPSC
[29]
PLLMF_4
(def=0x0) // Bit 4 of PLLMF
0x40021008
INT
// Clock interrupt register (RCU_INT)
[0]
IRC40KSTBIF
(def=0x0) // IRC40K stabilization interrupt flag
[1]
LXTALSTBIF
(def=0x0) // LXTAL stabilization interrupt flag
[2]
IRC8MSTBIF
(def=0x0) // IRC8M stabilization interrupt flag
[3]
HXTALSTBIF
(def=0x0) // HXTAL stabilization interrupt flag
[4]
PLLSTBIF
(def=0x0) // PLL stabilization interrupt flag
[5]
PLL1STBIF
(def=0x0) // PLL1 stabilization interrupt flag
[6]
PLL2STBIF
(def=0x0) // PLL2 stabilization interrupt flag
[7]
CKMIF
(def=0x0) // HXTAL Clock Stuck Interrupt Flag
[8]
IRC40KSTBIE
(def=0x0) // IRC40K Stabilization interrupt enable
[9]
LXTALSTBIE
(def=0x0) // LXTAL Stabilization Interrupt Enable
[10]
IRC8MSTBIE
(def=0x0) // IRC8M Stabilization Interrupt Enable
[11]
HXTALSTBIE
(def=0x0) // HXTAL Stabilization Interrupt Enable
[12]
PLLSTBIE
(def=0x0) // PLL Stabilization Interrupt Enable
[13]
PLL1STBIE
(def=0x0) // PLL1 Stabilization Interrupt Enable
[14]
PLL2STBIE
(def=0x0) // PLL2 Stabilization Interrupt Enable
[16]
IRC40KSTBIC
(def=0x0) // IRC40K Stabilization Interrupt Clear
[17]
LXTALSTBIC
(def=0x0) // LXTAL Stabilization Interrupt Clear
[18]
IRC8MSTBIC
(def=0x0) // IRC8M Stabilization Interrupt Clear
[19]
HXTALSTBIC
(def=0x0) // HXTAL Stabilization Interrupt Clear
[20]
PLLSTBIC
(def=0x0) // PLL stabilization Interrupt Clear
[21]
PLL1STBIC
(def=0x0) // PLL1 stabilization Interrupt Clear
[22]
PLL2STBIC
(def=0x0) // PLL2 stabilization Interrupt Clear
[23]
CKMIC
(def=0x0) // HXTAL Clock Stuck Interrupt Clear
0x4002100C
APB2RST
// APB2 reset register (RCU_APB2RST)
[0]
AFRST
(def=0x0) // Alternate function I/O reset
[2]
PARST
(def=0x0) // GPIO port A reset
[3]
PBRST
(def=0x0) // GPIO port B reset
[4]
PCRST
(def=0x0) // GPIO port C reset
[5]
PDRST
(def=0x0) // GPIO port D reset
[6]
PERST
(def=0x0) // GPIO port E reset
[9]
ADC0RST
(def=0x0) // ADC0 reset
[10]
ADC1RST
(def=0x0) // ADC1 reset
[11]
TIMER0RST
(def=0x0) // Timer 0 reset
[12]
SPI0RST
(def=0x0) // SPI0 reset
[14]
USART0RST
(def=0x0) // USART0 Reset
0x40021010
APB1RST
// APB1 reset register (RCU_APB1RST)
[0]
TIMER1RST
(def=0x0) // TIMER1 timer reset
[1]
TIMER2RST
(def=0x0) // TIMER2 timer reset
[2]
TIMER3RST
(def=0x0) // TIMER3 timer reset
[3]
TIMER4RST
(def=0x0) // TIMER4 timer reset
[4]
TIMER5RST
(def=0x0) // TIMER5 timer reset
[5]
TIMER6RST
(def=0x0) // TIMER6 timer reset
[11]
WWDGTRST
(def=0x0) // Window watchdog timer reset
[14]
SPI1RST
(def=0x0) // SPI1 reset
[15]
SPI2RST
(def=0x0) // SPI2 reset
[17]
USART1RST
(def=0x0) // USART1 reset
[18]
USART2RST
(def=0x0) // USART2 reset
[19]
UART3RST
(def=0x0) // UART3 reset
[20]
UART4RST
(def=0x0) // UART4 reset
[21]
I2C0RST
(def=0x0) // I2C0 reset
[22]
I2C1RST
(def=0x0) // I2C1 reset
[25]
CAN0RST
(def=0x0) // CAN0 reset
[26]
CAN1RST
(def=0x0) // CAN1 reset
[27]
BKPIRST
(def=0x0) // Backup interface reset
[28]
PMURST
(def=0x0) // Power control reset
[29]
DACRST
(def=0x0) // DAC reset
0x40021014
AHBEN
// AHB enable register
[0]
DMA0EN
(def=0x0) // DMA0 clock enable
[1]
DMA1EN
(def=0x0) // DMA1 clock enable
[2]
SRAMSPEN
(def=0x1) // SRAM interface clock enable when sleep mode
[4]
FMCSPEN
(def=0x1) // FMC clock enable when sleep mode
[6]
CRCEN
(def=0x0) // CRC clock enable
[8]
EXMCEN
(def=0x0) // EXMC clock enable
[12]
USBFSEN
(def=0x0) // USBFS clock enable
0x40021018
APB2EN
// APB2 clock enable register (RCU_APB2EN)
[0]
AFEN
(def=0x0) // Alternate function IO clock enable
[2]
PAEN
(def=0x0) // GPIO port A clock enable
[3]
PBEN
(def=0x0) // GPIO port B clock enable
[4]
PCEN
(def=0x0) // GPIO port C clock enable
[5]
PDEN
(def=0x0) // GPIO port D clock enable
[6]
PEEN
(def=0x0) // GPIO port E clock enable
[9]
ADC0EN
(def=0x0) // ADC0 clock enable
[10]
ADC1EN
(def=0x0) // ADC1 clock enable
[11]
TIMER0EN
(def=0x0) // TIMER0 clock enable
[12]
SPI0EN
(def=0x0) // SPI0 clock enable
[14]
USART0EN
(def=0x0) // USART0 clock enable
0x4002101C
APB1EN
// APB1 clock enable register (RCU_APB1EN)
[0]
TIMER1EN
(def=0x0) // TIMER1 timer clock enable
[1]
TIMER2EN
(def=0x0) // TIMER2 timer clock enable
[2]
TIMER3EN
(def=0x0) // TIMER3 timer clock enable
[3]
TIMER4EN
(def=0x0) // TIMER4 timer clock enable
[4]
TIMER5EN
(def=0x0) // TIMER5 timer clock enable
[5]
TIMER6EN
(def=0x0) // TIMER6 timer clock enable
[11]
WWDGTEN
(def=0x0) // Window watchdog timer clock enable
[14]
SPI1EN
(def=0x0) // SPI1 clock enable
[15]
SPI2EN
(def=0x0) // SPI2 clock enable
[17]
USART1EN
(def=0x0) // USART1 clock enable
[18]
USART2EN
(def=0x0) // USART2 clock enable
[19]
UART3EN
(def=0x0) // UART3 clock enable
[20]
UART4EN
(def=0x0) // UART4 clock enable
[21]
I2C0EN
(def=0x0) // I2C0 clock enable
[22]
I2C1EN
(def=0x0) // I2C1 clock enable
[25]
CAN0EN
(def=0x0) // CAN0 clock enable
[26]
CAN1EN
(def=0x0) // CAN1 clock enable
[27]
BKPIEN
(def=0x0) // Backup interface clock enable
[28]
PMUEN
(def=0x0) // Power control clock enable
[29]
DACEN
(def=0x0) // DAC clock enable
0x40021020
BDCTL
// Backup domain control register (RCU_BDCTL)
[0]
LXTALEN
(def=0x0) // LXTAL enable
[1]
LXTALSTB
(def=0x0) // External low-speed oscillator stabilization
[2]
LXTALBPS
(def=0x0) // LXTAL bypass mode enable
[8:9]
RTCSRC
(def=0x0) // RTC clock entry selection
[15]
RTCEN
(def=0x0) // RTC clock enable
[16]
BKPRST
(def=0x0) // Backup domain reset
0x40021024
RSTSCK
// Reset source /clock register (RCU_RSTSCK)
[0]
IRC40KEN
(def=0x0) // IRC40K enable
[1]
IRC40KSTB
(def=0x0) // IRC40K stabilization
[24]
RSTFC
(def=0x0) // Reset flag clear
[26]
EPRSTF
(def=0x1) // External PIN reset flag
[27]
PORRSTF
(def=0x1) // Power reset flag
[28]
SWRSTF
(def=0x0) // Software reset flag
[29]
FWDGTRSTF
(def=0x0) // Free Watchdog timer reset flag
[30]
WWDGTRSTF
(def=0x0) // Window watchdog timer reset flag
[31]
LPRSTF
(def=0x0) // Low-power reset flag
0x40021028
AHBRST
// AHB reset register
[12]
USBFSRST
(def=0x0) // USBFS reset
0x4002102C
CFG1
// Clock Configuration register 1
[0:3]
PREDV0
(def=0x0) // PREDV0 division factor
[4:7]
PREDV1
(def=0x0) // PREDV1 division factor
[8:11]
PLL1MF
(def=0x0) // The PLL1 clock multiplication factor
[12:15]
PLL2MF
(def=0x0) // The PLL2 clock multiplication factor
[16]
PREDV0SEL
(def=0x0) // PREDV0 input Clock Source Selection
[17]
I2S1SEL
(def=0x0) // I2S1 Clock Source Selection
[18]
I2S2SEL
(def=0x0) // I2S2 Clock Source Selection
0x40021034
DSV
// Deep sleep mode Voltage register
[0:1]
DSLPVS
(def=0x0) // Deep-sleep mode voltage select
interrupts:
[24]
RCU
//
0x40002800
RTC
// Real-time clock
0x40002800
INTEN
// RTC interrupt enable register
[2]
OVIE
(def=0x0) // Overflow interrupt enable
[1]
ALRMIE
(def=0x0) // Alarm interrupt enable
[0]
SCIE
(def=0x0) // Second interrupt
0x40002804
CTL
// control register
[5]
LWOFF
(def=0x1) // Last write operation finished flag
[4]
CMF
(def=0x0) // Configuration mode flag
[3]
RSYNF
(def=0x0) // Registers synchronized flag
[2]
OVIF
(def=0x0) // Overflow interrupt flag
[1]
ALRMIF
(def=0x0) // Alarm interrupt flag
[0]
SCIF
(def=0x0) // Sencond interrupt flag
0x40002808
PSCH
// RTC prescaler high register
[0:3]
PSC
(def=0x0) // RTC prescaler value high
0x4000280C
PSCL
// RTC prescaler low register
[0:15]
PSC
(def=0x8000) // RTC prescaler value low
0x40002810
DIVH
// RTC divider high register
[0:3]
DIV
(def=0x0) // RTC divider value high
0x40002814
DIVL
// RTC divider low register
[0:15]
DIV
(def=0x8000) // RTC divider value low
0x40002818
CNTH
// RTC counter high register
[0:15]
CNT
(def=0x0) // RTC counter value high
0x4000281C
CNTL
// RTC counter low register
[0:15]
CNT
(def=0x0) // RTC counter value low
0x40002820
ALRMH
// Alarm high register
[0:15]
ALRM
(def=0xFFFF) // Alarm value high
0x40002824
ALRML
// RTC alarm low register
[0:15]
ALRM
(def=0xFFFF) // alarm value low
interrupts:
[22]
RTC
//
[60]
RTC_Alarm
//
0x40013000
SPI0
// Serial peripheral interface
0x40013000
CTL0
// control register 0
[15]
BDEN
(def=0x0) // Bidirectional enable
[14]
BDOEN
(def=0x0) // Bidirectional Transmit output enable
[13]
CRCEN
(def=0x0) // CRC Calculation Enable
[12]
CRCNT
(def=0x0) // CRC Next Transfer
[11]
FF16
(def=0x0) // Data frame format
[10]
RO
(def=0x0) // Receive only
[9]
SWNSSEN
(def=0x0) // NSS Software Mode Selection
[8]
SWNSS
(def=0x0) // NSS Pin Selection In NSS Software Mode
[7]
LF
(def=0x0) // LSB First Mode
[6]
SPIEN
(def=0x0) // SPI enable
[3:5]
PSC
(def=0x0) // Master Clock Prescaler Selection
[2]
MSTMOD
(def=0x0) // Master Mode Enable
[1]
CKPL
(def=0x0) // Clock polarity Selection
[0]
CKPH
(def=0x0) // Clock Phase Selection
0x40013004
CTL1
// control register 1
[7]
TBEIE
(def=0x0) // Tx buffer empty interrupt enable
[6]
RBNEIE
(def=0x0) // RX buffer not empty interrupt enable
[5]
ERRIE
(def=0x0) // Error interrupt enable
[4]
TMOD
(def=0x0) // SPI TI mode enable
[3]
NSSP
(def=0x0) // SPI NSS pulse mode enable
[2]
NSSDRV
(def=0x0) // Drive NSS Output
[1]
DMATEN
(def=0x0) // Transmit Buffer DMA Enable
[0]
DMAREN
(def=0x0) // Rx buffer DMA enable
0x40013008
STAT
// status register
[8]
FERR
(def=0x0) // Format error
[7]
TRANS
(def=0x0) // Transmitting On-going Bit
[6]
RXORERR
(def=0x0) // Reception Overrun Error Bit
[5]
CONFERR
(def=0x0) // SPI Configuration error
[4]
CRCERR
(def=0x0) // SPI CRC Error Bit
[3]
TXURERR
(def=0x0) // Transmission underrun error bit
[2]
I2SCH
(def=0x0) // I2S channel side
[1]
TBE
(def=0x1) // Transmit Buffer Empty
[0]
RBNE
(def=0x0) // Receive Buffer Not Empty
0x4001300C
DATA
// data register
[0:15]
SPI_DATA
(def=0x0) // Data transfer register
0x40013010
CRCPOLY
// CRC polynomial register
[0:15]
CRCPOLY
(def=0x7) // CRC polynomial value
0x40013014
RCRC
// RX CRC register
[0:15]
RCRC
(def=0x0) // RX CRC value
0x40013018
TCRC
// TX CRC register
[0:15]
TCRC
(def=0x0) // Tx CRC value
0x4001301C
I2SCTL
// I2S control register
[11]
I2SSEL
(def=0x0) // I2S mode selection
[10]
I2SEN
(def=0x0) // I2S Enable
[8:9]
I2SOPMOD
(def=0x0) // I2S operation mode
[7]
PCMSMOD
(def=0x0) // PCM frame synchronization mode
[4:5]
I2SSTD
(def=0x0) // I2S standard selection
[3]
CKPL
(def=0x0) // Idle state clock polarity
[1:2]
DTLEN
(def=0x0) // Data length
[0]
CHLEN
(def=0x0) // Channel length (number of bits per audio channel)
0x40013020
I2SPSC
// I2S prescaler register
[9]
MCKOEN
(def=0x0) // I2S_MCK output enable
[8]
OF
(def=0x0) // Odd factor for the prescaler
[0:7]
DIV
(def=0x2) // Dividing factor for the prescaler
interrupts:
[54]
SPI0
//
0x40003800
SPI1
//
0x40003800
CTL0
// control register 0
[15]
BDEN
(def=0x0) // Bidirectional enable
[14]
BDOEN
(def=0x0) // Bidirectional Transmit output enable
[13]
CRCEN
(def=0x0) // CRC Calculation Enable
[12]
CRCNT
(def=0x0) // CRC Next Transfer
[11]
FF16
(def=0x0) // Data frame format
[10]
RO
(def=0x0) // Receive only
[9]
SWNSSEN
(def=0x0) // NSS Software Mode Selection
[8]
SWNSS
(def=0x0) // NSS Pin Selection In NSS Software Mode
[7]
LF
(def=0x0) // LSB First Mode
[6]
SPIEN
(def=0x0) // SPI enable
[3:5]
PSC
(def=0x0) // Master Clock Prescaler Selection
[2]
MSTMOD
(def=0x0) // Master Mode Enable
[1]
CKPL
(def=0x0) // Clock polarity Selection
[0]
CKPH
(def=0x0) // Clock Phase Selection
0x40003804
CTL1
// control register 1
[7]
TBEIE
(def=0x0) // Tx buffer empty interrupt enable
[6]
RBNEIE
(def=0x0) // RX buffer not empty interrupt enable
[5]
ERRIE
(def=0x0) // Error interrupt enable
[4]
TMOD
(def=0x0) // SPI TI mode enable
[3]
NSSP
(def=0x0) // SPI NSS pulse mode enable
[2]
NSSDRV
(def=0x0) // Drive NSS Output
[1]
DMATEN
(def=0x0) // Transmit Buffer DMA Enable
[0]
DMAREN
(def=0x0) // Rx buffer DMA enable
0x40003808
STAT
// status register
[8]
FERR
(def=0x0) // Format error
[7]
TRANS
(def=0x0) // Transmitting On-going Bit
[6]
RXORERR
(def=0x0) // Reception Overrun Error Bit
[5]
CONFERR
(def=0x0) // SPI Configuration error
[4]
CRCERR
(def=0x0) // SPI CRC Error Bit
[3]
TXURERR
(def=0x0) // Transmission underrun error bit
[2]
I2SCH
(def=0x0) // I2S channel side
[1]
TBE
(def=0x1) // Transmit Buffer Empty
[0]
RBNE
(def=0x0) // Receive Buffer Not Empty
0x4000380C
DATA
// data register
[0:15]
SPI_DATA
(def=0x0) // Data transfer register
0x40003810
CRCPOLY
// CRC polynomial register
[0:15]
CRCPOLY
(def=0x7) // CRC polynomial value
0x40003814
RCRC
// RX CRC register
[0:15]
RCRC
(def=0x0) // RX CRC value
0x40003818
TCRC
// TX CRC register
[0:15]
TCRC
(def=0x0) // Tx CRC value
0x4000381C
I2SCTL
// I2S control register
[11]
I2SSEL
(def=0x0) // I2S mode selection
[10]
I2SEN
(def=0x0) // I2S Enable
[8:9]
I2SOPMOD
(def=0x0) // I2S operation mode
[7]
PCMSMOD
(def=0x0) // PCM frame synchronization mode
[4:5]
I2SSTD
(def=0x0) // I2S standard selection
[3]
CKPL
(def=0x0) // Idle state clock polarity
[1:2]
DTLEN
(def=0x0) // Data length
[0]
CHLEN
(def=0x0) // Channel length (number of bits per audio channel)
0x40003820
I2SPSC
// I2S prescaler register
[9]
MCKOEN
(def=0x0) // I2S_MCK output enable
[8]
OF
(def=0x0) // Odd factor for the prescaler
[0:7]
DIV
(def=0x2) // Dividing factor for the prescaler
interrupts:
[55]
SPI1
//
0x40003C00
SPI2
//
0x40003C00
CTL0
// control register 0
[15]
BDEN
(def=0x0) // Bidirectional enable
[14]
BDOEN
(def=0x0) // Bidirectional Transmit output enable
[13]
CRCEN
(def=0x0) // CRC Calculation Enable
[12]
CRCNT
(def=0x0) // CRC Next Transfer
[11]
FF16
(def=0x0) // Data frame format
[10]
RO
(def=0x0) // Receive only
[9]
SWNSSEN
(def=0x0) // NSS Software Mode Selection
[8]
SWNSS
(def=0x0) // NSS Pin Selection In NSS Software Mode
[7]
LF
(def=0x0) // LSB First Mode
[6]
SPIEN
(def=0x0) // SPI enable
[3:5]
PSC
(def=0x0) // Master Clock Prescaler Selection
[2]
MSTMOD
(def=0x0) // Master Mode Enable
[1]
CKPL
(def=0x0) // Clock polarity Selection
[0]
CKPH
(def=0x0) // Clock Phase Selection
0x40003C04
CTL1
// control register 1
[7]
TBEIE
(def=0x0) // Tx buffer empty interrupt enable
[6]
RBNEIE
(def=0x0) // RX buffer not empty interrupt enable
[5]
ERRIE
(def=0x0) // Error interrupt enable
[4]
TMOD
(def=0x0) // SPI TI mode enable
[3]
NSSP
(def=0x0) // SPI NSS pulse mode enable
[2]
NSSDRV
(def=0x0) // Drive NSS Output
[1]
DMATEN
(def=0x0) // Transmit Buffer DMA Enable
[0]
DMAREN
(def=0x0) // Rx buffer DMA enable
0x40003C08
STAT
// status register
[8]
FERR
(def=0x0) // Format error
[7]
TRANS
(def=0x0) // Transmitting On-going Bit
[6]
RXORERR
(def=0x0) // Reception Overrun Error Bit
[5]
CONFERR
(def=0x0) // SPI Configuration error
[4]
CRCERR
(def=0x0) // SPI CRC Error Bit
[3]
TXURERR
(def=0x0) // Transmission underrun error bit
[2]
I2SCH
(def=0x0) // I2S channel side
[1]
TBE
(def=0x1) // Transmit Buffer Empty
[0]
RBNE
(def=0x0) // Receive Buffer Not Empty
0x40003C0C
DATA
// data register
[0:15]
SPI_DATA
(def=0x0) // Data transfer register
0x40003C10
CRCPOLY
// CRC polynomial register
[0:15]
CRCPOLY
(def=0x7) // CRC polynomial value
0x40003C14
RCRC
// RX CRC register
[0:15]
RCRC
(def=0x0) // RX CRC value
0x40003C18
TCRC
// TX CRC register
[0:15]
TCRC
(def=0x0) // Tx CRC value
0x40003C1C
I2SCTL
// I2S control register
[11]
I2SSEL
(def=0x0) // I2S mode selection
[10]
I2SEN
(def=0x0) // I2S Enable
[8:9]
I2SOPMOD
(def=0x0) // I2S operation mode
[7]
PCMSMOD
(def=0x0) // PCM frame synchronization mode
[4:5]
I2SSTD
(def=0x0) // I2S standard selection
[3]
CKPL
(def=0x0) // Idle state clock polarity
[1:2]
DTLEN
(def=0x0) // Data length
[0]
CHLEN
(def=0x0) // Channel length (number of bits per audio channel)
0x40003C20
I2SPSC
// I2S prescaler register
[9]
MCKOEN
(def=0x0) // I2S_MCK output enable
[8]
OF
(def=0x0) // Odd factor for the prescaler
[0:7]
DIV
(def=0x2) // Dividing factor for the prescaler
interrupts:
[70]
SPI2
//
0x40012C00
TIMER0
// Advanced-timers
0x40012C00
CTL0
// control register 0
[8:9]
CKDIV
(def=0x0) // Clock division
[7]
ARSE
(def=0x0) // Auto-reload shadow enable
[5:6]
CAM
(def=0x0) // Counter aligns mode selection
[4]
DIR
(def=0x0) // Direction
[3]
SPM
(def=0x0) // Single pulse mode
[2]
UPS
(def=0x0) // Update source
[1]
UPDIS
(def=0x0) // Update disable
[0]
CEN
(def=0x0) // Counter enable
0x40012C04
CTL1
// control register 1
[14]
ISO3
(def=0x0) // Idle state of channel 3 output
[13]
ISO2N
(def=0x0) // Idle state of channel 2 complementary output
[12]
ISO2
(def=0x0) // Idle state of channel 2 output
[11]
ISO1N
(def=0x0) // Idle state of channel 1 complementary output
[10]
ISO1
(def=0x0) // Idle state of channel 1 output
[9]
ISO0N
(def=0x0) // Idle state of channel 0 complementary output
[8]
ISO0
(def=0x0) // Idle state of channel 0 output
[7]
TI0S
(def=0x0) // Channel 0 trigger input selection
[4:6]
MMC
(def=0x0) // Master mode control
[3]
DMAS
(def=0x0) // DMA request source selection
[2]
CCUC
(def=0x0) // Commutation control shadow register update control
[0]
CCSE
(def=0x0) // Commutation control shadow enable
0x40012C08
SMCFG
// slave mode configuration register
[15]
ETP
(def=0x0) // External trigger polarity
[14]
SMC1
(def=0x0) // Part of SMC for enable External clock mode1
[12:13]
ETPSC
(def=0x0) // External trigger prescaler
[8:11]
ETFC
(def=0x0) // External trigger filter control
[7]
MSM
(def=0x0) // Master/Slave mode
[4:6]
TRGS
(def=0x0) // Trigger selection
[0:2]
SMC
(def=0x0) // Slave mode selection
0x40012C0C
DMAINTEN
// DMA/Interrupt enable register
[14]
TRGDEN
(def=0x0) // Trigger DMA request enable
[13]
CMTDEN
(def=0x0) // Commutation DMA request enable
[12]
CH3DEN
(def=0x0) // Channel 3 capture/compare DMA request enable
[11]
CH2DEN
(def=0x0) // Channel 2 capture/compare DMA request enable
[10]
CH1DEN
(def=0x0) // Channel 1 capture/compare DMA request enable
[9]
CH0DEN
(def=0x0) // Channel 0 capture/compare DMA request enable
[8]
UPDEN
(def=0x0) // Update DMA request enable
[7]
BRKIE
(def=0x0) // Break interrupt enable
[6]
TRGIE
(def=0x0) // Trigger interrupt enable
[5]
CMTIE
(def=0x0) // commutation interrupt enable
[4]
CH3IE
(def=0x0) // Channel 3 capture/compare interrupt enable
[3]
CH2IE
(def=0x0) // Channel 2 capture/compare interrupt enable
[2]
CH1IE
(def=0x0) // Channel 1 capture/compare interrupt enable
[1]
CH0IE
(def=0x0) // Channel 0 capture/compare interrupt enable
[0]
UPIE
(def=0x0) // Update interrupt enable
0x40012C10
INTF
// Interrupt flag register
[12]
CH3OF
(def=0x0) // Channel 3 over capture flag
[11]
CH2OF
(def=0x0) // Channel 2 over capture flag
[10]
CH1OF
(def=0x0) // Channel 1 over capture flag
[9]
CH0OF
(def=0x0) // Channel 0 over capture flag
[7]
BRKIF
(def=0x0) // Break interrupt flag
[6]
TRGIF
(def=0x0) // Trigger interrupt flag
[5]
CMTIF
(def=0x0) // Channel commutation interrupt flag
[4]
CH3IF
(def=0x0) // Channel 3 capture/compare interrupt flag
[3]
CH2IF
(def=0x0) // Channel 2 capture/compare interrupt flag
[2]
CH1IF
(def=0x0) // Channel 1 capture/compare interrupt flag
[1]
CH0IF
(def=0x0) // Channel 0 capture/compare interrupt flag
[0]
UPIF
(def=0x0) // Update interrupt flag
0x40012C14
SWEVG
// Software event generation register
[7]
BRKG
(def=0x0) // Break event generation
[6]
TRGG
(def=0x0) // Trigger event generation
[5]
CMTG
(def=0x0) // Channel commutation event generation
[4]
CH3G
(def=0x0) // Channel 3 capture or compare event generation
[3]
CH2G
(def=0x0) // Channel 2 capture or compare event generation
[2]
CH1G
(def=0x0) // Channel 1 capture or compare event generation
[1]
CH0G
(def=0x0) // Channel 0 capture or compare event generation
[0]
UPG
(def=0x0) // Update event generation
0x40012C18
CHCTL0_Output
// Channel control register 0 (output mode)
[15]
CH1COMCEN
(def=0x0) // Channel 1 output compare clear enable
[12:14]
CH1COMCTL
(def=0x0) // Channel 1 compare output control
[11]
CH1COMSEN
(def=0x0) // Channel 1 output compare shadow enable
[10]
CH1COMFEN
(def=0x0) // Channel 1 output compare fast enable
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[7]
CH0COMCEN
(def=0x0) // Channel 0 output compare clear enable
[4:6]
CH0COMCTL
(def=0x0) // Channel 0 compare output control
[3]
CH0COMSEN
(def=0x0) // Channel 0 compare output shadow enable
[2]
CH0COMFEN
(def=0x0) // Channel 0 output compare fast enable
[0:1]
CH0MS
(def=0x0) // Channel 0 I/O mode selection
0x40012C18
CHCTL0_Input
// Channel control register 0 (input mode)
[12:15]
CH1CAPFLT
(def=0x0) // Channel 1 input capture filter control
[10:11]
CH1CAPPSC
(def=0x0) // Channel 1 input capture prescaler
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[4:7]
CH0CAPFLT
(def=0x0) // Channel 0 input capture filter control
[2:3]
CH0CAPPSC
(def=0x0) // Channel 0 input capture prescaler
[0:1]
CH0MS
(def=0x0) // Channel 0 mode selection
0x40012C1C
CHCTL1_Output
// Channel control register 1 (output mode)
[15]
CH3COMCEN
(def=0x0) // Channel 3 output compare clear enable
[12:14]
CH3COMCTL
(def=0x0) // Channel 3 compare output control
[11]
CH3COMSEN
(def=0x0) // Channel 3 output compare shadow enable
[10]
CH3COMFEN
(def=0x0) // Channel 3 output compare fast enable
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[7]
CH2COMCEN
(def=0x0) // Channel 2 output compare clear enable
[4:6]
CH2COMCTL
(def=0x0) // Channel 2 compare output control
[3]
CH2COMSEN
(def=0x0) // Channel 2 compare output shadow enable
[2]
CH2COMFEN
(def=0x0) // Channel 2 output compare fast enable
[0:1]
CH2MS
(def=0x0) // Channel 2 I/O mode selection
0x40012C1C
CHCTL1_Input
// Channel control register 1 (input mode)
[12:15]
CH3CAPFLT
(def=0x0) // Channel 3 input capture filter control
[10:11]
CH3CAPPSC
(def=0x0) // Channel 3 input capture prescaler
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[4:7]
CH2CAPFLT
(def=0x0) // Channel 2 input capture filter control
[2:3]
CH2CAPPSC
(def=0x0) // Channel 2 input capture prescaler
[0:1]
CH2MS
(def=0x0) // Channel 2 mode selection
0x40012C20
CHCTL2
// Channel control register 2
[13]
CH3P
(def=0x0) // Channel 3 capture/compare function polarity
[12]
CH3EN
(def=0x0) // Channel 3 capture/compare function enable
[11]
CH2NP
(def=0x0) // Channel 2 complementary output polarity
[10]
CH2NEN
(def=0x0) // Channel 2 complementary output enable
[9]
CH2P
(def=0x0) // Channel 2 capture/compare function polarity
[8]
CH2EN
(def=0x0) // Channel 2 capture/compare function enable
[7]
CH1NP
(def=0x0) // Channel 1 complementary output polarity
[6]
CH1NEN
(def=0x0) // Channel 1 complementary output enable
[5]
CH1P
(def=0x0) // Channel 1 capture/compare function polarity
[4]
CH1EN
(def=0x0) // Channel 1 capture/compare function enable
[3]
CH0NP
(def=0x0) // Channel 0 complementary output polarity
[2]
CH0NEN
(def=0x0) // Channel 0 complementary output enable
[1]
CH0P
(def=0x0) // Channel 0 capture/compare function polarity
[0]
CH0EN
(def=0x0) // Channel 0 capture/compare function enable
0x40012C24
CNT
// counter
[0:15]
CNT
(def=0x0) // current counter value
0x40012C28
PSC
// prescaler
[0:15]
PSC
(def=0x0) // Prescaler value of the counter clock
0x40012C2C
CAR
// Counter auto reload register
[0:15]
CARL
(def=0x0) // Counter auto reload value
0x40012C30
CREP
// Counter repetition register
[0:7]
CREP
(def=0x0) // Counter repetition value
0x40012C34
CH0CV
// Channel 0 capture/compare value register
[0:15]
CH0VAL
(def=0x0) // Capture or compare value of channel0
0x40012C38
CH1CV
// Channel 1 capture/compare value register
[0:15]
CH1VAL
(def=0x0) // Capture or compare value of channel1
0x40012C3C
CH2CV
// Channel 2 capture/compare value register
[0:15]
CH2VAL
(def=0x0) // Capture or compare value of channel 2
0x40012C40
CH3CV
// Channel 3 capture/compare value register
[0:15]
CH3VAL
(def=0x0) // Capture or compare value of channel 3
0x40012C44
CCHP
// channel complementary protection register
[15]
POEN
(def=0x0) // Primary output enable
[14]
OAEN
(def=0x0) // Output automatic enable
[13]
BRKP
(def=0x0) // Break polarity
[12]
BRKEN
(def=0x0) // Break enable
[11]
ROS
(def=0x0) // Run mode off-state configure
[10]
IOS
(def=0x0) // Idle mode off-state configure
[8:9]
PROT
(def=0x0) // Complementary register protect control
[0:7]
DTCFG
(def=0x0) // Dead time configure
0x40012C48
DMACFG
// DMA configuration register
[8:12]
DMATC
(def=0x0) // DMA transfer count
[0:4]
DMATA
(def=0x0) // DMA transfer access start address
0x40012C4C
DMATB
// DMA transfer buffer register
[0:15]
DMATB
(def=0x0) // DMA transfer buffer
interrupts:
[43]
TIMER0_BRK
//
[44]
TIMER0_UP
//
[45]
TIMER0_TRG_CMT
//
[46]
TIMER0_Channel
//
0x40000000
TIMER1
// General-purpose-timers
0x40000000
CTL0
// control register 0
[8:9]
CKDIV
(def=0x0) // Clock division
[7]
ARSE
(def=0x0) // Auto-reload shadow enable
[5:6]
CAM
(def=0x0) // Counter aligns mode selection
[4]
DIR
(def=0x0) // Direction
[3]
SPM
(def=0x0) // Single pulse mode
[2]
UPS
(def=0x0) // Update source
[1]
UPDIS
(def=0x0) // Update disable
[0]
CEN
(def=0x0) // Counter enable
0x40000004
CTL1
// control register 1
[7]
TI0S
(def=0x0) // Channel 0 trigger input selection
[4:6]
MMC
(def=0x0) // Master mode control
[3]
DMAS
(def=0x0) // DMA request source selection
0x40000008
SMCFG
// slave mode control register
[15]
ETP
(def=0x0) // External trigger polarity
[14]
SMC1
(def=0x0) // Part of SMC for enable External clock mode1
[12:13]
ETPSC
(def=0x0) // External trigger prescaler
[8:11]
ETFC
(def=0x0) // External trigger filter control
[7]
MSM
(def=0x0) // Master-slave mode
[4:6]
TRGS
(def=0x0) // Trigger selection
[0:2]
SMC
(def=0x0) // Slave mode control
0x4000000C
DMAINTEN
// DMA/Interrupt enable register
[14]
TRGDEN
(def=0x0) // Trigger DMA request enable
[12]
CH3DEN
(def=0x0) // Channel 3 capture/compare DMA request enable
[11]
CH2DEN
(def=0x0) // Channel 2 capture/compare DMA request enable
[10]
CH1DEN
(def=0x0) // Channel 1 capture/compare DMA request enable
[9]
CH0DEN
(def=0x0) // Channel 0 capture/compare DMA request enable
[8]
UPDEN
(def=0x0) // Update DMA request enable
[6]
TRGIE
(def=0x0) // Trigger interrupt enable
[4]
CH3IE
(def=0x0) // Channel 3 capture/compare interrupt enable
[3]
CH2IE
(def=0x0) // Channel 2 capture/compare interrupt enable
[2]
CH1IE
(def=0x0) // Channel 1 capture/compare interrupt enable
[1]
CH0IE
(def=0x0) // Channel 0 capture/compare interrupt enable
[0]
UPIE
(def=0x0) // Update interrupt enable
0x40000010
INTF
// interrupt flag register
[12]
CH3OF
(def=0x0) // Channel 3 over capture flag
[11]
CH2OF
(def=0x0) // Channel 2 over capture flag
[10]
CH1OF
(def=0x0) // Channel 1 over capture flag
[9]
CH0OF
(def=0x0) // Channel 0 over capture flag
[6]
TRGIF
(def=0x0) // Trigger interrupt flag
[4]
CH3IF
(def=0x0) // Channel 3 capture/compare interrupt enable
[3]
CH2IF
(def=0x0) // Channel 2 capture/compare interrupt enable
[2]
CH1IF
(def=0x0) // Channel 1 capture/compare interrupt flag
[1]
CH0IF
(def=0x0) // Channel 0 capture/compare interrupt flag
[0]
UPIF
(def=0x0) // Update interrupt flag
0x40000014
SWEVG
// event generation register
[6]
TRGG
(def=0x0) // Trigger event generation
[4]
CH3G
(def=0x0) // Channel 3 capture or compare event generation
[3]
CH2G
(def=0x0) // Channel 2 capture or compare event generation
[2]
CH1G
(def=0x0) // Channel 1 capture or compare event generation
[1]
CH0G
(def=0x0) // Channel 0 capture or compare event generation
[0]
UPG
(def=0x0) // Update generation
0x40000018
CHCTL0_Output
// Channel control register 0 (output mode)
[15]
CH1COMCEN
(def=0x0) // Channel 1 output compare clear enable
[12:14]
CH1COMCTL
(def=0x0) // Channel 1 compare output control
[11]
CH1COMSEN
(def=0x0) // Channel 1 output compare shadow enable
[10]
CH1COMFEN
(def=0x0) // Channel 1 output compare fast enable
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[7]
CH0COMCEN
(def=0x0) // Channel 0 output compare clear enable
[4:6]
CH0COMCTL
(def=0x0) // Channel 0 compare output control
[3]
CH0COMSEN
(def=0x0) // Channel 0 compare output shadow enable
[2]
CH0COMFEN
(def=0x0) // Channel 0 output compare fast enable
[0:1]
CH0MS
(def=0x0) // Channel 0 I/O mode selection
0x40000018
CHCTL0_Input
// Channel control register 0 (input mode)
[12:15]
CH1CAPFLT
(def=0x0) // Channel 1 input capture filter control
[10:11]
CH1CAPPSC
(def=0x0) // Channel 1 input capture prescaler
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[4:7]
CH0CAPFLT
(def=0x0) // Channel 0 input capture filter control
[2:3]
CH0CAPPSC
(def=0x0) // Channel 0 input capture prescaler
[0:1]
CH0MS
(def=0x0) // Channel 0 mode selection
0x4000001C
CHCTL1_Output
// Channel control register 1 (output mode)
[15]
CH3COMCEN
(def=0x0) // Channel 3 output compare clear enable
[12:14]
CH3COMCTL
(def=0x0) // Channel 3 compare output control
[11]
CH3COMSEN
(def=0x0) // Channel 3 output compare shadow enable
[10]
CH3COMFEN
(def=0x0) // Channel 3 output compare fast enable
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[7]
CH2COMCEN
(def=0x0) // Channel 2 output compare clear enable
[4:6]
CH2COMCTL
(def=0x0) // Channel 2 compare output control
[3]
CH2COMSEN
(def=0x0) // Channel 2 compare output shadow enable
[2]
CH2COMFEN
(def=0x0) // Channel 2 output compare fast enable
[0:1]
CH2MS
(def=0x0) // Channel 2 I/O mode selection
0x4000001C
CHCTL1_Input
// Channel control register 1 (input mode)
[12:15]
CH3CAPFLT
(def=0x0) // Channel 3 input capture filter control
[10:11]
CH3CAPPSC
(def=0x0) // Channel 3 input capture prescaler
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[4:7]
CH2CAPFLT
(def=0x0) // Channel 2 input capture filter control
[2:3]
CH2CAPPSC
(def=0x0) // Channel 2 input capture prescaler
[0:1]
CH2MS
(def=0x0) // Channel 2 mode selection
0x40000020
CHCTL2
// Channel control register 2
[13]
CH3P
(def=0x0) // Channel 3 capture/compare function polarity
[12]
CH3EN
(def=0x0) // Channel 3 capture/compare function enable
[9]
CH2P
(def=0x0) // Channel 2 capture/compare function polarity
[8]
CH2EN
(def=0x0) // Channel 2 capture/compare function enable
[5]
CH1P
(def=0x0) // Channel 1 capture/compare function polarity
[4]
CH1EN
(def=0x0) // Channel 1 capture/compare function enable
[1]
CH0P
(def=0x0) // Channel 0 capture/compare function polarity
[0]
CH0EN
(def=0x0) // Channel 0 capture/compare function enable
0x40000024
CNT
// Counter register
[0:15]
CNT
(def=0x0) // counter value
0x40000028
PSC
// Prescaler register
[0:15]
PSC
(def=0x0) // Prescaler value of the counter clock
0x4000002C
CAR
// Counter auto reload register
[0:15]
CARL
(def=0x0) // Counter auto reload value
0x40000034
CH0CV
// Channel 0 capture/compare value register
[0:15]
CH0VAL
(def=0x0) // Capture or compare value of channel 0
0x40000038
CH1CV
// Channel 1 capture/compare value register
[0:15]
CH1VAL
(def=0x0) // Capture or compare value of channel1
0x4000003C
CH2CV
// Channel 2 capture/compare value register
[0:15]
CH2VAL
(def=0x0) // Capture or compare value of channel 2
0x40000040
CH3CV
// Channel 3 capture/compare value register
[0:15]
CH3VAL
(def=0x0) // Capture or compare value of channel 3
0x40000048
DMACFG
// DMA configuration register
[8:12]
DMATC
(def=0x0) // DMA transfer count
[0:4]
DMATA
(def=0x0) // DMA transfer access start address
0x4000004C
DMATB
// DMA transfer buffer register
[0:15]
DMATB
(def=0x0) // DMA transfer buffer
interrupts:
[47]
TIMER1
//
0x40000400
TIMER2
//
0x40000400
CTL0
// control register 0
[8:9]
CKDIV
(def=0x0) // Clock division
[7]
ARSE
(def=0x0) // Auto-reload shadow enable
[5:6]
CAM
(def=0x0) // Counter aligns mode selection
[4]
DIR
(def=0x0) // Direction
[3]
SPM
(def=0x0) // Single pulse mode
[2]
UPS
(def=0x0) // Update source
[1]
UPDIS
(def=0x0) // Update disable
[0]
CEN
(def=0x0) // Counter enable
0x40000404
CTL1
// control register 1
[7]
TI0S
(def=0x0) // Channel 0 trigger input selection
[4:6]
MMC
(def=0x0) // Master mode control
[3]
DMAS
(def=0x0) // DMA request source selection
0x40000408
SMCFG
// slave mode control register
[15]
ETP
(def=0x0) // External trigger polarity
[14]
SMC1
(def=0x0) // Part of SMC for enable External clock mode1
[12:13]
ETPSC
(def=0x0) // External trigger prescaler
[8:11]
ETFC
(def=0x0) // External trigger filter control
[7]
MSM
(def=0x0) // Master-slave mode
[4:6]
TRGS
(def=0x0) // Trigger selection
[0:2]
SMC
(def=0x0) // Slave mode control
0x4000040C
DMAINTEN
// DMA/Interrupt enable register
[14]
TRGDEN
(def=0x0) // Trigger DMA request enable
[12]
CH3DEN
(def=0x0) // Channel 3 capture/compare DMA request enable
[11]
CH2DEN
(def=0x0) // Channel 2 capture/compare DMA request enable
[10]
CH1DEN
(def=0x0) // Channel 1 capture/compare DMA request enable
[9]
CH0DEN
(def=0x0) // Channel 0 capture/compare DMA request enable
[8]
UPDEN
(def=0x0) // Update DMA request enable
[6]
TRGIE
(def=0x0) // Trigger interrupt enable
[4]
CH3IE
(def=0x0) // Channel 3 capture/compare interrupt enable
[3]
CH2IE
(def=0x0) // Channel 2 capture/compare interrupt enable
[2]
CH1IE
(def=0x0) // Channel 1 capture/compare interrupt enable
[1]
CH0IE
(def=0x0) // Channel 0 capture/compare interrupt enable
[0]
UPIE
(def=0x0) // Update interrupt enable
0x40000410
INTF
// interrupt flag register
[12]
CH3OF
(def=0x0) // Channel 3 over capture flag
[11]
CH2OF
(def=0x0) // Channel 2 over capture flag
[10]
CH1OF
(def=0x0) // Channel 1 over capture flag
[9]
CH0OF
(def=0x0) // Channel 0 over capture flag
[6]
TRGIF
(def=0x0) // Trigger interrupt flag
[4]
CH3IF
(def=0x0) // Channel 3 capture/compare interrupt enable
[3]
CH2IF
(def=0x0) // Channel 2 capture/compare interrupt enable
[2]
CH1IF
(def=0x0) // Channel 1 capture/compare interrupt flag
[1]
CH0IF
(def=0x0) // Channel 0 capture/compare interrupt flag
[0]
UPIF
(def=0x0) // Update interrupt flag
0x40000414
SWEVG
// event generation register
[6]
TRGG
(def=0x0) // Trigger event generation
[4]
CH3G
(def=0x0) // Channel 3 capture or compare event generation
[3]
CH2G
(def=0x0) // Channel 2 capture or compare event generation
[2]
CH1G
(def=0x0) // Channel 1 capture or compare event generation
[1]
CH0G
(def=0x0) // Channel 0 capture or compare event generation
[0]
UPG
(def=0x0) // Update generation
0x40000418
CHCTL0_Output
// Channel control register 0 (output mode)
[15]
CH1COMCEN
(def=0x0) // Channel 1 output compare clear enable
[12:14]
CH1COMCTL
(def=0x0) // Channel 1 compare output control
[11]
CH1COMSEN
(def=0x0) // Channel 1 output compare shadow enable
[10]
CH1COMFEN
(def=0x0) // Channel 1 output compare fast enable
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[7]
CH0COMCEN
(def=0x0) // Channel 0 output compare clear enable
[4:6]
CH0COMCTL
(def=0x0) // Channel 0 compare output control
[3]
CH0COMSEN
(def=0x0) // Channel 0 compare output shadow enable
[2]
CH0COMFEN
(def=0x0) // Channel 0 output compare fast enable
[0:1]
CH0MS
(def=0x0) // Channel 0 I/O mode selection
0x40000418
CHCTL0_Input
// Channel control register 0 (input mode)
[12:15]
CH1CAPFLT
(def=0x0) // Channel 1 input capture filter control
[10:11]
CH1CAPPSC
(def=0x0) // Channel 1 input capture prescaler
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[4:7]
CH0CAPFLT
(def=0x0) // Channel 0 input capture filter control
[2:3]
CH0CAPPSC
(def=0x0) // Channel 0 input capture prescaler
[0:1]
CH0MS
(def=0x0) // Channel 0 mode selection
0x4000041C
CHCTL1_Output
// Channel control register 1 (output mode)
[15]
CH3COMCEN
(def=0x0) // Channel 3 output compare clear enable
[12:14]
CH3COMCTL
(def=0x0) // Channel 3 compare output control
[11]
CH3COMSEN
(def=0x0) // Channel 3 output compare shadow enable
[10]
CH3COMFEN
(def=0x0) // Channel 3 output compare fast enable
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[7]
CH2COMCEN
(def=0x0) // Channel 2 output compare clear enable
[4:6]
CH2COMCTL
(def=0x0) // Channel 2 compare output control
[3]
CH2COMSEN
(def=0x0) // Channel 2 compare output shadow enable
[2]
CH2COMFEN
(def=0x0) // Channel 2 output compare fast enable
[0:1]
CH2MS
(def=0x0) // Channel 2 I/O mode selection
0x4000041C
CHCTL1_Input
// Channel control register 1 (input mode)
[12:15]
CH3CAPFLT
(def=0x0) // Channel 3 input capture filter control
[10:11]
CH3CAPPSC
(def=0x0) // Channel 3 input capture prescaler
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[4:7]
CH2CAPFLT
(def=0x0) // Channel 2 input capture filter control
[2:3]
CH2CAPPSC
(def=0x0) // Channel 2 input capture prescaler
[0:1]
CH2MS
(def=0x0) // Channel 2 mode selection
0x40000420
CHCTL2
// Channel control register 2
[13]
CH3P
(def=0x0) // Channel 3 capture/compare function polarity
[12]
CH3EN
(def=0x0) // Channel 3 capture/compare function enable
[9]
CH2P
(def=0x0) // Channel 2 capture/compare function polarity
[8]
CH2EN
(def=0x0) // Channel 2 capture/compare function enable
[5]
CH1P
(def=0x0) // Channel 1 capture/compare function polarity
[4]
CH1EN
(def=0x0) // Channel 1 capture/compare function enable
[1]
CH0P
(def=0x0) // Channel 0 capture/compare function polarity
[0]
CH0EN
(def=0x0) // Channel 0 capture/compare function enable
0x40000424
CNT
// Counter register
[0:15]
CNT
(def=0x0) // counter value
0x40000428
PSC
// Prescaler register
[0:15]
PSC
(def=0x0) // Prescaler value of the counter clock
0x4000042C
CAR
// Counter auto reload register
[0:15]
CARL
(def=0x0) // Counter auto reload value
0x40000434
CH0CV
// Channel 0 capture/compare value register
[0:15]
CH0VAL
(def=0x0) // Capture or compare value of channel 0
0x40000438
CH1CV
// Channel 1 capture/compare value register
[0:15]
CH1VAL
(def=0x0) // Capture or compare value of channel1
0x4000043C
CH2CV
// Channel 2 capture/compare value register
[0:15]
CH2VAL
(def=0x0) // Capture or compare value of channel 2
0x40000440
CH3CV
// Channel 3 capture/compare value register
[0:15]
CH3VAL
(def=0x0) // Capture or compare value of channel 3
0x40000448
DMACFG
// DMA configuration register
[8:12]
DMATC
(def=0x0) // DMA transfer count
[0:4]
DMATA
(def=0x0) // DMA transfer access start address
0x4000044C
DMATB
// DMA transfer buffer register
[0:15]
DMATB
(def=0x0) // DMA transfer buffer
interrupts:
[48]
TIMER2
//
0x40000800
TIMER3
//
0x40000800
CTL0
// control register 0
[8:9]
CKDIV
(def=0x0) // Clock division
[7]
ARSE
(def=0x0) // Auto-reload shadow enable
[5:6]
CAM
(def=0x0) // Counter aligns mode selection
[4]
DIR
(def=0x0) // Direction
[3]
SPM
(def=0x0) // Single pulse mode
[2]
UPS
(def=0x0) // Update source
[1]
UPDIS
(def=0x0) // Update disable
[0]
CEN
(def=0x0) // Counter enable
0x40000804
CTL1
// control register 1
[7]
TI0S
(def=0x0) // Channel 0 trigger input selection
[4:6]
MMC
(def=0x0) // Master mode control
[3]
DMAS
(def=0x0) // DMA request source selection
0x40000808
SMCFG
// slave mode control register
[15]
ETP
(def=0x0) // External trigger polarity
[14]
SMC1
(def=0x0) // Part of SMC for enable External clock mode1
[12:13]
ETPSC
(def=0x0) // External trigger prescaler
[8:11]
ETFC
(def=0x0) // External trigger filter control
[7]
MSM
(def=0x0) // Master-slave mode
[4:6]
TRGS
(def=0x0) // Trigger selection
[0:2]
SMC
(def=0x0) // Slave mode control
0x4000080C
DMAINTEN
// DMA/Interrupt enable register
[14]
TRGDEN
(def=0x0) // Trigger DMA request enable
[12]
CH3DEN
(def=0x0) // Channel 3 capture/compare DMA request enable
[11]
CH2DEN
(def=0x0) // Channel 2 capture/compare DMA request enable
[10]
CH1DEN
(def=0x0) // Channel 1 capture/compare DMA request enable
[9]
CH0DEN
(def=0x0) // Channel 0 capture/compare DMA request enable
[8]
UPDEN
(def=0x0) // Update DMA request enable
[6]
TRGIE
(def=0x0) // Trigger interrupt enable
[4]
CH3IE
(def=0x0) // Channel 3 capture/compare interrupt enable
[3]
CH2IE
(def=0x0) // Channel 2 capture/compare interrupt enable
[2]
CH1IE
(def=0x0) // Channel 1 capture/compare interrupt enable
[1]
CH0IE
(def=0x0) // Channel 0 capture/compare interrupt enable
[0]
UPIE
(def=0x0) // Update interrupt enable
0x40000810
INTF
// interrupt flag register
[12]
CH3OF
(def=0x0) // Channel 3 over capture flag
[11]
CH2OF
(def=0x0) // Channel 2 over capture flag
[10]
CH1OF
(def=0x0) // Channel 1 over capture flag
[9]
CH0OF
(def=0x0) // Channel 0 over capture flag
[6]
TRGIF
(def=0x0) // Trigger interrupt flag
[4]
CH3IF
(def=0x0) // Channel 3 capture/compare interrupt enable
[3]
CH2IF
(def=0x0) // Channel 2 capture/compare interrupt enable
[2]
CH1IF
(def=0x0) // Channel 1 capture/compare interrupt flag
[1]
CH0IF
(def=0x0) // Channel 0 capture/compare interrupt flag
[0]
UPIF
(def=0x0) // Update interrupt flag
0x40000814
SWEVG
// event generation register
[6]
TRGG
(def=0x0) // Trigger event generation
[4]
CH3G
(def=0x0) // Channel 3 capture or compare event generation
[3]
CH2G
(def=0x0) // Channel 2 capture or compare event generation
[2]
CH1G
(def=0x0) // Channel 1 capture or compare event generation
[1]
CH0G
(def=0x0) // Channel 0 capture or compare event generation
[0]
UPG
(def=0x0) // Update generation
0x40000818
CHCTL0_Output
// Channel control register 0 (output mode)
[15]
CH1COMCEN
(def=0x0) // Channel 1 output compare clear enable
[12:14]
CH1COMCTL
(def=0x0) // Channel 1 compare output control
[11]
CH1COMSEN
(def=0x0) // Channel 1 output compare shadow enable
[10]
CH1COMFEN
(def=0x0) // Channel 1 output compare fast enable
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[7]
CH0COMCEN
(def=0x0) // Channel 0 output compare clear enable
[4:6]
CH0COMCTL
(def=0x0) // Channel 0 compare output control
[3]
CH0COMSEN
(def=0x0) // Channel 0 compare output shadow enable
[2]
CH0COMFEN
(def=0x0) // Channel 0 output compare fast enable
[0:1]
CH0MS
(def=0x0) // Channel 0 I/O mode selection
0x40000818
CHCTL0_Input
// Channel control register 0 (input mode)
[12:15]
CH1CAPFLT
(def=0x0) // Channel 1 input capture filter control
[10:11]
CH1CAPPSC
(def=0x0) // Channel 1 input capture prescaler
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[4:7]
CH0CAPFLT
(def=0x0) // Channel 0 input capture filter control
[2:3]
CH0CAPPSC
(def=0x0) // Channel 0 input capture prescaler
[0:1]
CH0MS
(def=0x0) // Channel 0 mode selection
0x4000081C
CHCTL1_Output
// Channel control register 1 (output mode)
[15]
CH3COMCEN
(def=0x0) // Channel 3 output compare clear enable
[12:14]
CH3COMCTL
(def=0x0) // Channel 3 compare output control
[11]
CH3COMSEN
(def=0x0) // Channel 3 output compare shadow enable
[10]
CH3COMFEN
(def=0x0) // Channel 3 output compare fast enable
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[7]
CH2COMCEN
(def=0x0) // Channel 2 output compare clear enable
[4:6]
CH2COMCTL
(def=0x0) // Channel 2 compare output control
[3]
CH2COMSEN
(def=0x0) // Channel 2 compare output shadow enable
[2]
CH2COMFEN
(def=0x0) // Channel 2 output compare fast enable
[0:1]
CH2MS
(def=0x0) // Channel 2 I/O mode selection
0x4000081C
CHCTL1_Input
// Channel control register 1 (input mode)
[12:15]
CH3CAPFLT
(def=0x0) // Channel 3 input capture filter control
[10:11]
CH3CAPPSC
(def=0x0) // Channel 3 input capture prescaler
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[4:7]
CH2CAPFLT
(def=0x0) // Channel 2 input capture filter control
[2:3]
CH2CAPPSC
(def=0x0) // Channel 2 input capture prescaler
[0:1]
CH2MS
(def=0x0) // Channel 2 mode selection
0x40000820
CHCTL2
// Channel control register 2
[13]
CH3P
(def=0x0) // Channel 3 capture/compare function polarity
[12]
CH3EN
(def=0x0) // Channel 3 capture/compare function enable
[9]
CH2P
(def=0x0) // Channel 2 capture/compare function polarity
[8]
CH2EN
(def=0x0) // Channel 2 capture/compare function enable
[5]
CH1P
(def=0x0) // Channel 1 capture/compare function polarity
[4]
CH1EN
(def=0x0) // Channel 1 capture/compare function enable
[1]
CH0P
(def=0x0) // Channel 0 capture/compare function polarity
[0]
CH0EN
(def=0x0) // Channel 0 capture/compare function enable
0x40000824
CNT
// Counter register
[0:15]
CNT
(def=0x0) // counter value
0x40000828
PSC
// Prescaler register
[0:15]
PSC
(def=0x0) // Prescaler value of the counter clock
0x4000082C
CAR
// Counter auto reload register
[0:15]
CARL
(def=0x0) // Counter auto reload value
0x40000834
CH0CV
// Channel 0 capture/compare value register
[0:15]
CH0VAL
(def=0x0) // Capture or compare value of channel 0
0x40000838
CH1CV
// Channel 1 capture/compare value register
[0:15]
CH1VAL
(def=0x0) // Capture or compare value of channel1
0x4000083C
CH2CV
// Channel 2 capture/compare value register
[0:15]
CH2VAL
(def=0x0) // Capture or compare value of channel 2
0x40000840
CH3CV
// Channel 3 capture/compare value register
[0:15]
CH3VAL
(def=0x0) // Capture or compare value of channel 3
0x40000848
DMACFG
// DMA configuration register
[8:12]
DMATC
(def=0x0) // DMA transfer count
[0:4]
DMATA
(def=0x0) // DMA transfer access start address
0x4000084C
DMATB
// DMA transfer buffer register
[0:15]
DMATB
(def=0x0) // DMA transfer buffer
interrupts:
[49]
TIMER3
//
0x40000C00
TIMER4
//
0x40000C00
CTL0
// control register 0
[8:9]
CKDIV
(def=0x0) // Clock division
[7]
ARSE
(def=0x0) // Auto-reload shadow enable
[5:6]
CAM
(def=0x0) // Counter aligns mode selection
[4]
DIR
(def=0x0) // Direction
[3]
SPM
(def=0x0) // Single pulse mode
[2]
UPS
(def=0x0) // Update source
[1]
UPDIS
(def=0x0) // Update disable
[0]
CEN
(def=0x0) // Counter enable
0x40000C04
CTL1
// control register 1
[7]
TI0S
(def=0x0) // Channel 0 trigger input selection
[4:6]
MMC
(def=0x0) // Master mode control
[3]
DMAS
(def=0x0) // DMA request source selection
0x40000C08
SMCFG
// slave mode control register
[15]
ETP
(def=0x0) // External trigger polarity
[14]
SMC1
(def=0x0) // Part of SMC for enable External clock mode1
[12:13]
ETPSC
(def=0x0) // External trigger prescaler
[8:11]
ETFC
(def=0x0) // External trigger filter control
[7]
MSM
(def=0x0) // Master-slave mode
[4:6]
TRGS
(def=0x0) // Trigger selection
[0:2]
SMC
(def=0x0) // Slave mode control
0x40000C0C
DMAINTEN
// DMA/Interrupt enable register
[14]
TRGDEN
(def=0x0) // Trigger DMA request enable
[12]
CH3DEN
(def=0x0) // Channel 3 capture/compare DMA request enable
[11]
CH2DEN
(def=0x0) // Channel 2 capture/compare DMA request enable
[10]
CH1DEN
(def=0x0) // Channel 1 capture/compare DMA request enable
[9]
CH0DEN
(def=0x0) // Channel 0 capture/compare DMA request enable
[8]
UPDEN
(def=0x0) // Update DMA request enable
[6]
TRGIE
(def=0x0) // Trigger interrupt enable
[4]
CH3IE
(def=0x0) // Channel 3 capture/compare interrupt enable
[3]
CH2IE
(def=0x0) // Channel 2 capture/compare interrupt enable
[2]
CH1IE
(def=0x0) // Channel 1 capture/compare interrupt enable
[1]
CH0IE
(def=0x0) // Channel 0 capture/compare interrupt enable
[0]
UPIE
(def=0x0) // Update interrupt enable
0x40000C10
INTF
// interrupt flag register
[12]
CH3OF
(def=0x0) // Channel 3 over capture flag
[11]
CH2OF
(def=0x0) // Channel 2 over capture flag
[10]
CH1OF
(def=0x0) // Channel 1 over capture flag
[9]
CH0OF
(def=0x0) // Channel 0 over capture flag
[6]
TRGIF
(def=0x0) // Trigger interrupt flag
[4]
CH3IF
(def=0x0) // Channel 3 capture/compare interrupt enable
[3]
CH2IF
(def=0x0) // Channel 2 capture/compare interrupt enable
[2]
CH1IF
(def=0x0) // Channel 1 capture/compare interrupt flag
[1]
CH0IF
(def=0x0) // Channel 0 capture/compare interrupt flag
[0]
UPIF
(def=0x0) // Update interrupt flag
0x40000C14
SWEVG
// event generation register
[6]
TRGG
(def=0x0) // Trigger event generation
[4]
CH3G
(def=0x0) // Channel 3 capture or compare event generation
[3]
CH2G
(def=0x0) // Channel 2 capture or compare event generation
[2]
CH1G
(def=0x0) // Channel 1 capture or compare event generation
[1]
CH0G
(def=0x0) // Channel 0 capture or compare event generation
[0]
UPG
(def=0x0) // Update generation
0x40000C18
CHCTL0_Output
// Channel control register 0 (output mode)
[15]
CH1COMCEN
(def=0x0) // Channel 1 output compare clear enable
[12:14]
CH1COMCTL
(def=0x0) // Channel 1 compare output control
[11]
CH1COMSEN
(def=0x0) // Channel 1 output compare shadow enable
[10]
CH1COMFEN
(def=0x0) // Channel 1 output compare fast enable
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[7]
CH0COMCEN
(def=0x0) // Channel 0 output compare clear enable
[4:6]
CH0COMCTL
(def=0x0) // Channel 0 compare output control
[3]
CH0COMSEN
(def=0x0) // Channel 0 compare output shadow enable
[2]
CH0COMFEN
(def=0x0) // Channel 0 output compare fast enable
[0:1]
CH0MS
(def=0x0) // Channel 0 I/O mode selection
0x40000C18
CHCTL0_Input
// Channel control register 0 (input mode)
[12:15]
CH1CAPFLT
(def=0x0) // Channel 1 input capture filter control
[10:11]
CH1CAPPSC
(def=0x0) // Channel 1 input capture prescaler
[8:9]
CH1MS
(def=0x0) // Channel 1 mode selection
[4:7]
CH0CAPFLT
(def=0x0) // Channel 0 input capture filter control
[2:3]
CH0CAPPSC
(def=0x0) // Channel 0 input capture prescaler
[0:1]
CH0MS
(def=0x0) // Channel 0 mode selection
0x40000C1C
CHCTL1_Output
// Channel control register 1 (output mode)
[15]
CH3COMCEN
(def=0x0) // Channel 3 output compare clear enable
[12:14]
CH3COMCTL
(def=0x0) // Channel 3 compare output control
[11]
CH3COMSEN
(def=0x0) // Channel 3 output compare shadow enable
[10]
CH3COMFEN
(def=0x0) // Channel 3 output compare fast enable
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[7]
CH2COMCEN
(def=0x0) // Channel 2 output compare clear enable
[4:6]
CH2COMCTL
(def=0x0) // Channel 2 compare output control
[3]
CH2COMSEN
(def=0x0) // Channel 2 compare output shadow enable
[2]
CH2COMFEN
(def=0x0) // Channel 2 output compare fast enable
[0:1]
CH2MS
(def=0x0) // Channel 2 I/O mode selection
0x40000C1C
CHCTL1_Input
// Channel control register 1 (input mode)
[12:15]
CH3CAPFLT
(def=0x0) // Channel 3 input capture filter control
[10:11]
CH3CAPPSC
(def=0x0) // Channel 3 input capture prescaler
[8:9]
CH3MS
(def=0x0) // Channel 3 mode selection
[4:7]
CH2CAPFLT
(def=0x0) // Channel 2 input capture filter control
[2:3]
CH2CAPPSC
(def=0x0) // Channel 2 input capture prescaler
[0:1]
CH2MS
(def=0x0) // Channel 2 mode selection
0x40000C20
CHCTL2
// Channel control register 2
[13]
CH3P
(def=0x0) // Channel 3 capture/compare function polarity
[12]
CH3EN
(def=0x0) // Channel 3 capture/compare function enable
[9]
CH2P
(def=0x0) // Channel 2 capture/compare function polarity
[8]
CH2EN
(def=0x0) // Channel 2 capture/compare function enable
[5]
CH1P
(def=0x0) // Channel 1 capture/compare function polarity
[4]
CH1EN
(def=0x0) // Channel 1 capture/compare function enable
[1]
CH0P
(def=0x0) // Channel 0 capture/compare function polarity
[0]
CH0EN
(def=0x0) // Channel 0 capture/compare function enable
0x40000C24
CNT
// Counter register
[0:15]
CNT
(def=0x0) // counter value
0x40000C28
PSC
// Prescaler register
[0:15]
PSC
(def=0x0) // Prescaler value of the counter clock
0x40000C2C
CAR
// Counter auto reload register
[0:15]
CARL
(def=0x0) // Counter auto reload value
0x40000C34
CH0CV
// Channel 0 capture/compare value register
[0:15]
CH0VAL
(def=0x0) // Capture or compare value of channel 0
0x40000C38
CH1CV
// Channel 1 capture/compare value register
[0:15]
CH1VAL
(def=0x0) // Capture or compare value of channel1
0x40000C3C
CH2CV
// Channel 2 capture/compare value register
[0:15]
CH2VAL
(def=0x0) // Capture or compare value of channel 2
0x40000C40
CH3CV
// Channel 3 capture/compare value register
[0:15]
CH3VAL
(def=0x0) // Capture or compare value of channel 3
0x40000C48
DMACFG
// DMA configuration register
[8:12]
DMATC
(def=0x0) // DMA transfer count
[0:4]
DMATA
(def=0x0) // DMA transfer access start address
0x40000C4C
DMATB
// DMA transfer buffer register
[0:15]
DMATB
(def=0x0) // DMA transfer buffer
interrupts:
[69]
TIMER4
//
0x40001000
TIMER5
// Basic-timers
0x40001000
CTL0
// control register 0
[7]
ARSE
(def=0x0) // Auto-reload shadow enable
[3]
SPM
(def=0x0) // Single pulse mode
[2]
UPS
(def=0x0) // Update source
[1]
UPDIS
(def=0x0) // Update disable
[0]
CEN
(def=0x0) // Counter enable
0x40001004
CTL1
// control register 1
[4:6]
MMC
(def=0x0) // Master mode control
0x4000100C
DMAINTEN
// DMA/Interrupt enable register
[8]
UPDEN
(def=0x0) // Update DMA request enable
[0]
UPIE
(def=0x0) // Update interrupt enable
0x40001010
INTF
// Interrupt flag register
[0]
UPIF
(def=0x0) // Update interrupt flag
0x40001014
SWEVG
// event generation register
[0]
UPG
(def=0x0) // Update generation
0x40001024
CNT
// Counter register
[0:15]
CNT
(def=0x0) // Low counter value
0x40001028
PSC
// Prescaler register
[0:15]
PSC
(def=0x0) // Prescaler value of the counter clock
0x4000102C
CAR
// Counter auto reload register
[0:15]
CARL
(def=0x0) // Counter auto reload value
interrupts:
[73]
TIMER5
//
0x40001400
TIMER6
//
0x40001400
CTL0
// control register 0
[7]
ARSE
(def=0x0) // Auto-reload shadow enable
[3]
SPM
(def=0x0) // Single pulse mode
[2]
UPS
(def=0x0) // Update source
[1]
UPDIS
(def=0x0) // Update disable
[0]
CEN
(def=0x0) // Counter enable
0x40001404
CTL1
// control register 1
[4:6]
MMC
(def=0x0) // Master mode control
0x4000140C
DMAINTEN
// DMA/Interrupt enable register
[8]
UPDEN
(def=0x0) // Update DMA request enable
[0]
UPIE
(def=0x0) // Update interrupt enable
0x40001410
INTF
// Interrupt flag register
[0]
UPIF
(def=0x0) // Update interrupt flag
0x40001414
SWEVG
// event generation register
[0]
UPG
(def=0x0) // Update generation
0x40001424
CNT
// Counter register
[0:15]
CNT
(def=0x0) // Low counter value
0x40001428
PSC
// Prescaler register
[0:15]
PSC
(def=0x0) // Prescaler value of the counter clock
0x4000142C
CAR
// Counter auto reload register
[0:15]
CARL
(def=0x0) // Counter auto reload value
interrupts:
[74]
TIMER6
//
0x40013800
USART0
// Universal synchronous asynchronous receiver transmitter
0x40013800
STAT
// Status register
[9]
CTSF
(def=0x0) // CTS change flag
[8]
LBDF
(def=0x0) // LIN break detection flag
[7]
TBE
(def=0x1) // Transmit data buffer empty
[6]
TC
(def=0x1) // Transmission complete
[5]
RBNE
(def=0x0) // Read data buffer not empty
[4]
IDLEF
(def=0x0) // IDLE frame detected flag
[3]
ORERR
(def=0x0) // Overrun error
[2]
NERR
(def=0x0) // Noise error flag
[1]
FERR
(def=0x0) // Frame error flag
[0]
PERR
(def=0x0) // Parity error flag
0x40013804
DATA
// Data register
[0:8]
DATA
(def=0x0) // Transmit or read data value
0x40013808
BAUD
// Baud rate register
[4:15]
INTDIV
(def=0x0) // Integer part of baud-rate divider
[0:3]
FRADIV
(def=0x0) // Fraction part of baud-rate divider
0x4001380C
CTL0
// Control register 0
[13]
UEN
(def=0x0) // USART enable
[12]
WL
(def=0x0) // Word length
[11]
WM
(def=0x0) // Wakeup method in mute mode
[10]
PCEN
(def=0x0) // Parity check function enable
[9]
PM
(def=0x0) // Parity mode
[8]
PERRIE
(def=0x0) // Parity error interrupt enable
[7]
TBEIE
(def=0x0) // Transmitter buffer empty interrupt enable
[6]
TCIE
(def=0x0) // Transmission complete interrupt enable
[5]
RBNEIE
(def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
[4]
IDLEIE
(def=0x0) // IDLE line detected interrupt enable
[3]
TEN
(def=0x0) // Transmitter enable
[2]
REN
(def=0x0) // Receiver enable
[1]
RWU
(def=0x0) // Receiver wakeup from mute mode
[0]
SBKCMD
(def=0x0) // Send break command
0x40013810
CTL1
// Control register 1
[14]
LMEN
(def=0x0) // LIN mode enable
[12:13]
STB
(def=0x0) // STOP bits length
[11]
CKEN
(def=0x0) // CK pin enable
[10]
CPL
(def=0x0) // Clock polarity
[9]
CPH
(def=0x0) // Clock phase
[8]
CLEN
(def=0x0) // CK Length
[6]
LBDIE
(def=0x0) // LIN break detection interrupt enable
[5]
LBLEN
(def=0x0) // LIN break frame length
[0:3]
ADDR
(def=0x0) // Address of the USART
0x40013814
CTL2
// Control register 2
[10]
CTSIE
(def=0x0) // CTS interrupt enable
[9]
CTSEN
(def=0x0) // CTS enable
[8]
RTSEN
(def=0x0) // RTS enable
[7]
DENT
(def=0x0) // DMA request enable for transmission
[6]
DENR
(def=0x0) // DMA request enable for reception
[5]
SCEN
(def=0x0) // Smartcard mode enable
[4]
NKEN
(def=0x0) // Smartcard NACK enable
[3]
HDEN
(def=0x0) // Half-duplex selection
[2]
IRLP
(def=0x0) // IrDA low-power
[1]
IREN
(def=0x0) // IrDA mode enable
[0]
ERRIE
(def=0x0) // Error interrupt enable
0x40013818
GP
// Guard time and prescaler register
[8:15]
GUAT
(def=0x0) // Guard time value in Smartcard mode
[0:7]
PSC
(def=0x0) // Prescaler value
interrupts:
[56]
USART0
//
0x40004400
USART1
//
0x40004400
STAT
// Status register
[9]
CTSF
(def=0x0) // CTS change flag
[8]
LBDF
(def=0x0) // LIN break detection flag
[7]
TBE
(def=0x1) // Transmit data buffer empty
[6]
TC
(def=0x1) // Transmission complete
[5]
RBNE
(def=0x0) // Read data buffer not empty
[4]
IDLEF
(def=0x0) // IDLE frame detected flag
[3]
ORERR
(def=0x0) // Overrun error
[2]
NERR
(def=0x0) // Noise error flag
[1]
FERR
(def=0x0) // Frame error flag
[0]
PERR
(def=0x0) // Parity error flag
0x40004404
DATA
// Data register
[0:8]
DATA
(def=0x0) // Transmit or read data value
0x40004408
BAUD
// Baud rate register
[4:15]
INTDIV
(def=0x0) // Integer part of baud-rate divider
[0:3]
FRADIV
(def=0x0) // Fraction part of baud-rate divider
0x4000440C
CTL0
// Control register 0
[13]
UEN
(def=0x0) // USART enable
[12]
WL
(def=0x0) // Word length
[11]
WM
(def=0x0) // Wakeup method in mute mode
[10]
PCEN
(def=0x0) // Parity check function enable
[9]
PM
(def=0x0) // Parity mode
[8]
PERRIE
(def=0x0) // Parity error interrupt enable
[7]
TBEIE
(def=0x0) // Transmitter buffer empty interrupt enable
[6]
TCIE
(def=0x0) // Transmission complete interrupt enable
[5]
RBNEIE
(def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
[4]
IDLEIE
(def=0x0) // IDLE line detected interrupt enable
[3]
TEN
(def=0x0) // Transmitter enable
[2]
REN
(def=0x0) // Receiver enable
[1]
RWU
(def=0x0) // Receiver wakeup from mute mode
[0]
SBKCMD
(def=0x0) // Send break command
0x40004410
CTL1
// Control register 1
[14]
LMEN
(def=0x0) // LIN mode enable
[12:13]
STB
(def=0x0) // STOP bits length
[11]
CKEN
(def=0x0) // CK pin enable
[10]
CPL
(def=0x0) // Clock polarity
[9]
CPH
(def=0x0) // Clock phase
[8]
CLEN
(def=0x0) // CK Length
[6]
LBDIE
(def=0x0) // LIN break detection interrupt enable
[5]
LBLEN
(def=0x0) // LIN break frame length
[0:3]
ADDR
(def=0x0) // Address of the USART
0x40004414
CTL2
// Control register 2
[10]
CTSIE
(def=0x0) // CTS interrupt enable
[9]
CTSEN
(def=0x0) // CTS enable
[8]
RTSEN
(def=0x0) // RTS enable
[7]
DENT
(def=0x0) // DMA request enable for transmission
[6]
DENR
(def=0x0) // DMA request enable for reception
[5]
SCEN
(def=0x0) // Smartcard mode enable
[4]
NKEN
(def=0x0) // Smartcard NACK enable
[3]
HDEN
(def=0x0) // Half-duplex selection
[2]
IRLP
(def=0x0) // IrDA low-power
[1]
IREN
(def=0x0) // IrDA mode enable
[0]
ERRIE
(def=0x0) // Error interrupt enable
0x40004418
GP
// Guard time and prescaler register
[8:15]
GUAT
(def=0x0) // Guard time value in Smartcard mode
[0:7]
PSC
(def=0x0) // Prescaler value
interrupts:
[57]
USART1
//
0x40004800
USART2
//
0x40004800
STAT
// Status register
[9]
CTSF
(def=0x0) // CTS change flag
[8]
LBDF
(def=0x0) // LIN break detection flag
[7]
TBE
(def=0x1) // Transmit data buffer empty
[6]
TC
(def=0x1) // Transmission complete
[5]
RBNE
(def=0x0) // Read data buffer not empty
[4]
IDLEF
(def=0x0) // IDLE frame detected flag
[3]
ORERR
(def=0x0) // Overrun error
[2]
NERR
(def=0x0) // Noise error flag
[1]
FERR
(def=0x0) // Frame error flag
[0]
PERR
(def=0x0) // Parity error flag
0x40004804
DATA
// Data register
[0:8]
DATA
(def=0x0) // Transmit or read data value
0x40004808
BAUD
// Baud rate register
[4:15]
INTDIV
(def=0x0) // Integer part of baud-rate divider
[0:3]
FRADIV
(def=0x0) // Fraction part of baud-rate divider
0x4000480C
CTL0
// Control register 0
[13]
UEN
(def=0x0) // USART enable
[12]
WL
(def=0x0) // Word length
[11]
WM
(def=0x0) // Wakeup method in mute mode
[10]
PCEN
(def=0x0) // Parity check function enable
[9]
PM
(def=0x0) // Parity mode
[8]
PERRIE
(def=0x0) // Parity error interrupt enable
[7]
TBEIE
(def=0x0) // Transmitter buffer empty interrupt enable
[6]
TCIE
(def=0x0) // Transmission complete interrupt enable
[5]
RBNEIE
(def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
[4]
IDLEIE
(def=0x0) // IDLE line detected interrupt enable
[3]
TEN
(def=0x0) // Transmitter enable
[2]
REN
(def=0x0) // Receiver enable
[1]
RWU
(def=0x0) // Receiver wakeup from mute mode
[0]
SBKCMD
(def=0x0) // Send break command
0x40004810
CTL1
// Control register 1
[14]
LMEN
(def=0x0) // LIN mode enable
[12:13]
STB
(def=0x0) // STOP bits length
[11]
CKEN
(def=0x0) // CK pin enable
[10]
CPL
(def=0x0) // Clock polarity
[9]
CPH
(def=0x0) // Clock phase
[8]
CLEN
(def=0x0) // CK Length
[6]
LBDIE
(def=0x0) // LIN break detection interrupt enable
[5]
LBLEN
(def=0x0) // LIN break frame length
[0:3]
ADDR
(def=0x0) // Address of the USART
0x40004814
CTL2
// Control register 2
[10]
CTSIE
(def=0x0) // CTS interrupt enable
[9]
CTSEN
(def=0x0) // CTS enable
[8]
RTSEN
(def=0x0) // RTS enable
[7]
DENT
(def=0x0) // DMA request enable for transmission
[6]
DENR
(def=0x0) // DMA request enable for reception
[5]
SCEN
(def=0x0) // Smartcard mode enable
[4]
NKEN
(def=0x0) // Smartcard NACK enable
[3]
HDEN
(def=0x0) // Half-duplex selection
[2]
IRLP
(def=0x0) // IrDA low-power
[1]
IREN
(def=0x0) // IrDA mode enable
[0]
ERRIE
(def=0x0) // Error interrupt enable
0x40004818
GP
// Guard time and prescaler register
[8:15]
GUAT
(def=0x0) // Guard time value in Smartcard mode
[0:7]
PSC
(def=0x0) // Prescaler value
interrupts:
[58]
USART2
//
0x40004C00
UART3
// Universal asynchronous receiver transmitter
0x40004C00
STAT
// Status register
[8]
LBDF
(def=0x0) // LIN break detection flag
[7]
TBE
(def=0x1) // Transmit data buffer empty
[6]
TC
(def=0x1) // Transmission complete
[5]
RBNE
(def=0x0) // Read data buffer not empty
[4]
IDLEF
(def=0x0) // IDLE frame detected flag
[3]
ORERR
(def=0x0) // Overrun error
[2]
NERR
(def=0x0) // Noise error flag
[1]
FERR
(def=0x0) // Frame error flag
[0]
PERR
(def=0x0) // Parity error flag
0x40004C04
DATA
// Data register
[0:8]
DATA
(def=0x0) // Transmit or read data value
0x40004C08
BAUD
// Baud rate register
[4:15]
INTDIV
(def=0x0) // Integer part of baud-rate divider
[0:3]
FRADIV
(def=0x0) // Fraction part of baud-rate divider
0x40004C0C
CTL0
// Control register 0
[13]
UEN
(def=0x0) // USART enable
[12]
WL
(def=0x0) // Word length
[11]
WM
(def=0x0) // Wakeup method in mute mode
[10]
PCEN
(def=0x0) // Parity check function enable
[9]
PM
(def=0x0) // Parity mode
[8]
PERRIE
(def=0x0) // Parity error interrupt enable
[7]
TBEIE
(def=0x0) // Transmitter buffer empty interrupt enable
[6]
TCIE
(def=0x0) // Transmission complete interrupt enable
[5]
RBNEIE
(def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
[4]
IDLEIE
(def=0x0) // IDLE line detected interrupt enable
[3]
TEN
(def=0x0) // Transmitter enable
[2]
REN
(def=0x0) // Receiver enable
[1]
RWU
(def=0x0) // Receiver wakeup from mute mode
[0]
SBKCMD
(def=0x0) // Send break command
0x40004C10
CTL1
// Control register 1
[14]
LMEN
(def=0x0) // LIN mode enable
[12:13]
STB
(def=0x0) // STOP bits length
[6]
LBDIE
(def=0x0) // LIN break detection interrupt enable
[5]
LBLEN
(def=0x0) // LIN break frame length
[0:3]
ADDR
(def=0x0) // Address of the USART
0x40004C14
CTL2
// Control register 2
[7]
DENT
(def=0x0) // DMA request enable for transmission
[6]
DENR
(def=0x0) // DMA request enable for reception
[3]
HDEN
(def=0x0) // Half-duplex selection
[2]
IRLP
(def=0x0) // IrDA low-power
[1]
IREN
(def=0x0) // IrDA mode enable
[0]
ERRIE
(def=0x0) // Error interrupt enable
0x40004C18
GP
// Guard time and prescaler register
[0:7]
PSC
(def=0x0) // Prescaler value
interrupts:
[71]
UART3
//
0x40005000
UART4
//
0x40005000
STAT
// Status register
[8]
LBDF
(def=0x0) // LIN break detection flag
[7]
TBE
(def=0x1) // Transmit data buffer empty
[6]
TC
(def=0x1) // Transmission complete
[5]
RBNE
(def=0x0) // Read data buffer not empty
[4]
IDLEF
(def=0x0) // IDLE frame detected flag
[3]
ORERR
(def=0x0) // Overrun error
[2]
NERR
(def=0x0) // Noise error flag
[1]
FERR
(def=0x0) // Frame error flag
[0]
PERR
(def=0x0) // Parity error flag
0x40005004
DATA
// Data register
[0:8]
DATA
(def=0x0) // Transmit or read data value
0x40005008
BAUD
// Baud rate register
[4:15]
INTDIV
(def=0x0) // Integer part of baud-rate divider
[0:3]
FRADIV
(def=0x0) // Fraction part of baud-rate divider
0x4000500C
CTL0
// Control register 0
[13]
UEN
(def=0x0) // USART enable
[12]
WL
(def=0x0) // Word length
[11]
WM
(def=0x0) // Wakeup method in mute mode
[10]
PCEN
(def=0x0) // Parity check function enable
[9]
PM
(def=0x0) // Parity mode
[8]
PERRIE
(def=0x0) // Parity error interrupt enable
[7]
TBEIE
(def=0x0) // Transmitter buffer empty interrupt enable
[6]
TCIE
(def=0x0) // Transmission complete interrupt enable
[5]
RBNEIE
(def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
[4]
IDLEIE
(def=0x0) // IDLE line detected interrupt enable
[3]
TEN
(def=0x0) // Transmitter enable
[2]
REN
(def=0x0) // Receiver enable
[1]
RWU
(def=0x0) // Receiver wakeup from mute mode
[0]
SBKCMD
(def=0x0) // Send break command
0x40005010
CTL1
// Control register 1
[14]
LMEN
(def=0x0) // LIN mode enable
[12:13]
STB
(def=0x0) // STOP bits length
[6]
LBDIE
(def=0x0) // LIN break detection interrupt enable
[5]
LBLEN
(def=0x0) // LIN break frame length
[0:3]
ADDR
(def=0x0) // Address of the USART
0x40005014
CTL2
// Control register 2
[7]
DENT
(def=0x0) // DMA request enable for transmission
[6]
DENR
(def=0x0) // DMA request enable for reception
[3]
HDEN
(def=0x0) // Half-duplex selection
[2]
IRLP
(def=0x0) // IrDA low-power
[1]
IREN
(def=0x0) // IrDA mode enable
[0]
ERRIE
(def=0x0) // Error interrupt enable
0x40005018
GP
// Guard time and prescaler register
[0:7]
PSC
(def=0x0) // Prescaler value
interrupts:
[72]
UART4
//
0x50000000
USBFS_GLOBAL
// USB full speed global registers
0x50000000
GOTGCS
// Global OTG control and status register (USBFS_GOTGCS)
[0]
SRPS
(def=0x0) // SRP success
[1]
SRPREQ
(def=0x0) // SRP request
[8]
HNPS
(def=0x0) // Host success
[9]
HNPREQ
(def=0x0) // HNP request
[10]
HHNPEN
(def=0x0) // Host HNP enable
[11]
DHNPEN
(def=0x1) // Device HNP enabled
[16]
IDPS
(def=0x0) // ID pin status
[17]
DI
(def=0x0) // Debounce interval
[18]
ASV
(def=0x0) // A-session valid
[19]
BSV
(def=0x0) // B-session valid
0x50000004
GOTGINTF
// Global OTG interrupt flag register (USBFS_GOTGINTF)
[2]
SESEND
(def=0x0) // Session end
[8]
SRPEND
(def=0x0) // Session request success status change
[9]
HNPEND
(def=0x0) // HNP end
[17]
HNPDET
(def=0x0) // Host negotiation request detected
[18]
ADTO
(def=0x0) // A-device timeout
[19]
DF
(def=0x0) // Debounce finish
0x50000008
GAHBCS
// Global AHB control and status register (USBFS_GAHBCS)
[0]
GINTEN
(def=0x0) // Global interrupt enable
[7]
TXFTH
(def=0x0) // Tx FIFO threshold
[8]
PTXFTH
(def=0x0) // Periodic Tx FIFO threshold
0x5000000C
GUSBCS
// Global USB control and status register (USBFS_GUSBCSR)
[0:2]
TOC
(def=0x0) // Timeout calibration
[8]
SRPCEN
(def=0x0) // SRP capability enable
[9]
HNPCEN
(def=0x1) // HNP capability enable
[10:13]
UTT
(def=0x2) // USB turnaround time
[29]
FHM
(def=0x0) // Force host mode
[30]
FDM
(def=0x0) // Force device mode
0x50000010
GRSTCTL
// Global reset control register (USBFS_GRSTCTL)
[0]
CSRST
(def=0x0) // Core soft reset
[1]
HCSRST
(def=0x0) // HCLK soft reset
[2]
HFCRST
(def=0x0) // Host frame counter reset
[4]
RXFF
(def=0x0) // RxFIFO flush
[5]
TXFF
(def=0x0) // TxFIFO flush
[6:10]
TXFNUM
(def=0x0) // TxFIFO number
0x50000014
GINTF
// Global interrupt flag register (USBFS_GINTF)
[0]
COPM
(def=0x1) // Current operation mode
[1]
MFIF
(def=0x0) // Mode fault interrupt flag
[2]
OTGIF
(def=0x0) // OTG interrupt flag
[3]
SOF
(def=0x0) // Start of frame
[4]
RXFNEIF
(def=0x0) // RxFIFO non-empty interrupt flag
[5]
NPTXFEIF
(def=0x1) // Non-periodic TxFIFO empty interrupt flag
[6]
GNPINAK
(def=0x0) // Global Non-Periodic IN NAK effective
[7]
GONAK
(def=0x0) // Global OUT NAK effective
[10]
ESP
(def=0x0) // Early suspend
[11]
SP
(def=0x0) // USB suspend
[12]
RST
(def=0x0) // USB reset
[13]
ENUMF
(def=0x0) // Enumeration finished
[14]
ISOOPDIF
(def=0x0) // Isochronous OUT packet dropped interrupt
[15]
EOPFIF
(def=0x0) // End of periodic frame interrupt flag
[18]
IEPIF
(def=0x0) // IN endpoint interrupt flag
[19]
OEPIF
(def=0x0) // OUT endpoint interrupt flag
[20]
ISOINCIF
(def=0x0) // Isochronous IN transfer Not Complete Interrupt Flag
[21]
PXNCIF_ISOONCIF
(def=0x0) // periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not
[24]
HPIF
(def=0x0) // Host port interrupt flag
[25]
HCIF
(def=0x0) // Host channels interrupt flag
[26]
PTXFEIF
(def=0x1) // Periodic TxFIFO empty interrupt flag
[28]
IDPSC
(def=0x0) // ID pin status change
[29]
DISCIF
(def=0x0) // Disconnect interrupt flag
[30]
SESIF
(def=0x0) // Session interrupt flag
[31]
WKUPIF
(def=0x0) // Wakeup interrupt flag
0x50000018
GINTEN
// Global interrupt enable register (USBFS_GINTEN)
[1]
MFIE
(def=0x0) // Mode fault interrupt enable
[2]
OTGIE
(def=0x0) // OTG interrupt enable
[3]
SOFIE
(def=0x0) // Start of frame interrupt enable
[4]
RXFNEIE
(def=0x0) // Receive FIFO non-empty interrupt enable
[5]
NPTXFEIE
(def=0x0) // Non-periodic TxFIFO empty interrupt enable
[6]
GNPINAKIE
(def=0x0) // Global non-periodic IN NAK effective interrupt enable
[7]
GONAKIE
(def=0x0) // Global OUT NAK effective interrupt enable
[10]
ESPIE
(def=0x0) // Early suspend interrupt enable
[11]
SPIE
(def=0x0) // USB suspend interrupt enable
[12]
RSTIE
(def=0x0) // USB reset interrupt enable
[13]
ENUMFIE
(def=0x0) // Enumeration finish interrupt enable
[14]
ISOOPDIE
(def=0x0) // Isochronous OUT packet dropped interrupt enable
[15]
EOPFIE
(def=0x0) // End of periodic frame interrupt enable
[18]
IEPIE
(def=0x0) // IN endpoints interrupt enable
[19]
OEPIE
(def=0x0) // OUT endpoints interrupt enable
[20]
ISOINCIE
(def=0x0) // isochronous IN transfer not complete interrupt enable
[21]
PXNCIE_ISOONCIE
(def=0x0) // periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer
[24]
HPIE
(def=0x0) // Host port interrupt enable
[25]
HCIE
(def=0x0) // Host channels interrupt enable
[26]
PTXFEIE
(def=0x0) // Periodic TxFIFO empty interrupt enable
[28]
IDPSCIE
(def=0x0) // ID pin status change interrupt enable
[29]
DISCIE
(def=0x0) // Disconnect interrupt enable
[30]
SESIE
(def=0x0) // Session interrupt enable
[31]
WKUPIE
(def=0x0) // Wakeup interrupt enable
0x5000001C
GRSTATR_Device
// Global Receive status read(Device mode)
[0:3]
EPNUM
(def=0x0) // Endpoint number
[4:14]
BCOUNT
(def=0x0) // Byte count
[15:16]
DPID
(def=0x0) // Data PID
[17:20]
RPCKST
(def=0x0) // Recieve packet status
0x5000001C
GRSTATR_Host
// Global Receive status read(Host mode)
[0:3]
CNUM
(def=0x0) // Channel number
[4:14]
BCOUNT
(def=0x0) // Byte count
[15:16]
DPID
(def=0x0) // Data PID
[17:20]
RPCKST
(def=0x0) // Reivece packet status
0x50000020
GRSTATP_Device
// Global Receive status pop(Device mode)
[0:3]
EPNUM
(def=0x0) // Endpoint number
[4:14]
BCOUNT
(def=0x0) // Byte count
[15:16]
DPID
(def=0x0) // Data PID
[17:20]
RPCKST
(def=0x0) // Recieve packet status
0x50000020
GRSTATP_Host
// Global Receive status pop(Host mode)
[0:3]
CNUM
(def=0x0) // Channel number
[4:14]
BCOUNT
(def=0x0) // Byte count
[15:16]
DPID
(def=0x0) // Data PID
[17:20]
RPCKST
(def=0x0) // Reivece packet status
0x50000024
GRFLEN
// Global Receive FIFO size register (USBFS_GRFLEN)
[0:15]
RXFD
(def=0x200) // Rx FIFO depth
0x50000028
HNPTFLEN
// Host non-periodic transmit FIFO length register (Host mode)
[0:15]
HNPTXRSAR
(def=0x200) // host non-periodic transmit Tx RAM start address
[16:31]
HNPTXFD
(def=0x200) // host non-periodic TxFIFO depth
0x50000028
DIEP0TFLEN
// Device IN endpoint 0 transmit FIFO length (Device mode)
[16:31]
IEP0TXFD
(def=0x200) // in endpoint 0 Tx FIFO depth
[0:15]
IEP0TXRSAR
(def=0x200) // in endpoint 0 Tx RAM start address
0x5000002C
HNPTFQSTAT
// Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)
[0:15]
NPTXFS
(def=0x200) // Non-periodic TxFIFO space
[16:23]
NPTXRQS
(def=0x8) // Non-periodic transmit request queue space
[24:30]
NPTXRQTOP
(def=0x0) // Top of the non-periodic transmit request queue
0x50000038
GCCFG
// Global core configuration register (USBFS_GCCFG)
[16]
PWRON
(def=0x0) // Power on
[18]
VBUSACEN
(def=0x0) // The VBUS A-device Comparer enable
[19]
VBUSBCEN
(def=0x0) // The VBUS B-device Comparer enable
[20]
SOFOEN
(def=0x0) // SOF output enable
[21]
VBUSIG
(def=0x0) // VBUS ignored
0x5000003C
CID
// core ID register
[0:31]
CID
(def=0x1000) // Core ID
0x50000100
HPTFLEN
// Host periodic transmit FIFO length register (HPTFLEN)
[0:15]
HPTXFSAR
(def=0x600) // Host periodic TxFIFO start address
[16:31]
HPTXFD
(def=0x200) // Host periodic TxFIFO depth
0x50000104
DIEP1TFLEN
// device IN endpoint transmit FIFO size register (DIEP1TFLEN)
[0:15]
IEPTXRSAR
(def=0x400) // IN endpoint FIFO transmit RAM start address
[16:31]
IEPTXFD
(def=0x200) // IN endpoint TxFIFO depth
0x50000108
DIEP2TFLEN
// device IN endpoint transmit FIFO size register (DIEP2TFLEN)
[0:15]
IEPTXRSAR
(def=0x400) // IN endpoint FIFO transmit RAM start address
[16:31]
IEPTXFD
(def=0x200) // IN endpoint TxFIFO depth
0x5000010C
DIEP3TFLEN
// device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN)
[0:15]
IEPTXRSAR
(def=0x400) // IN endpoint FIFO4 transmit RAM start address
[16:31]
IEPTXFD
(def=0x200) // IN endpoint TxFIFO depth
interrupts:
[61]
USBFS_WKUP
//
[86]
USBFS
//
0x50000400
USBFS_HOST
// USB on the go full speed host
0x50000400
HCTL
// host configuration register (HCTL)
[0:1]
CLKSEL
(def=0x0) // clock select for USB clock
0x50000404
HFT
// Host frame interval register
[0:15]
FRI
(def=0xBB80) // Frame interval
0x50000408
HFINFR
// FS host frame number/frame time remaining register (HFINFR)
[0:15]
FRNUM
(def=0x0) // Frame number
[16:31]
FRT
(def=0xBB80) // Frame remaining time
0x50000410
HPTFQSTAT
// Host periodic transmit FIFO/queue status register (HPTFQSTAT)
[0:15]
PTXFS
(def=0x200) // Periodic transmit data FIFO space available
[16:23]
PTXREQS
(def=0x8) // Periodic transmit request queue space available
[24:31]
PTXREQT
(def=0x0) // Top of the periodic transmit request queue
0x50000414
HACHINT
// Host all channels interrupt register
[0:7]
HACHINT
(def=0x0) // Host all channel interrupts
0x50000418
HACHINTEN
// host all channels interrupt mask register
[0:7]
CINTEN
(def=0x0) // Channel interrupt enable
0x50000440
HPCS
// Host port control and status register (USBFS_HPCS)
[0]
PCST
(def=0x0) // Port connect status
[1]
PCD
(def=0x0) // Port connect detected
[2]
PE
(def=0x0) // Port enable
[3]
PEDC
(def=0x0) // Port enable/disable change
[6]
PREM
(def=0x0) // Port resume
[7]
PSP
(def=0x0) // Port suspend
[8]
PRST
(def=0x0) // Port reset
[10:11]
PLST
(def=0x0) // Port line status
[12]
PP
(def=0x0) // Port power
[17:18]
PS
(def=0x0) // Port speed
0x50000500
HCH0CTL
// host channel-0 characteristics register (HCH0CTL)
[0:10]
MPL
(def=0x0) // Maximum packet size
[11:14]
EPNUM
(def=0x0) // Endpoint number
[15]
EPDIR
(def=0x0) // Endpoint direction
[17]
LSD
(def=0x0) // Low-speed device
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[22:28]
DAR
(def=0x0) // Device address
[29]
ODDFRM
(def=0x0) // Odd frame
[30]
CDIS
(def=0x0) // Channel disable
[31]
CEN
(def=0x0) // Channel enable
0x50000520
HCH1CTL
// host channel-1 characteristics register (HCH1CTL)
[0:10]
MPL
(def=0x0) // Maximum packet size
[11:14]
EPNUM
(def=0x0) // Endpoint number
[15]
EPDIR
(def=0x0) // Endpoint direction
[17]
LSD
(def=0x0) // Low-speed device
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[22:28]
DAR
(def=0x0) // Device address
[29]
ODDFRM
(def=0x0) // Odd frame
[30]
CDIS
(def=0x0) // Channel disable
[31]
CEN
(def=0x0) // Channel enable
0x50000540
HCH2CTL
// host channel-2 characteristics register (HCH2CTL)
[0:10]
MPL
(def=0x0) // Maximum packet size
[11:14]
EPNUM
(def=0x0) // Endpoint number
[15]
EPDIR
(def=0x0) // Endpoint direction
[17]
LSD
(def=0x0) // Low-speed device
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[22:28]
DAR
(def=0x0) // Device address
[29]
ODDFRM
(def=0x0) // Odd frame
[30]
CDIS
(def=0x0) // Channel disable
[31]
CEN
(def=0x0) // Channel enable
0x50000560
HCH3CTL
// host channel-3 characteristics register (HCH3CTL)
[0:10]
MPL
(def=0x0) // Maximum packet size
[11:14]
EPNUM
(def=0x0) // Endpoint number
[15]
EPDIR
(def=0x0) // Endpoint direction
[17]
LSD
(def=0x0) // Low-speed device
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[22:28]
DAR
(def=0x0) // Device address
[29]
ODDFRM
(def=0x0) // Odd frame
[30]
CDIS
(def=0x0) // Channel disable
[31]
CEN
(def=0x0) // Channel enable
0x50000580
HCH4CTL
// host channel-4 characteristics register (HCH4CTL)
[0:10]
MPL
(def=0x0) // Maximum packet size
[11:14]
EPNUM
(def=0x0) // Endpoint number
[15]
EPDIR
(def=0x0) // Endpoint direction
[17]
LSD
(def=0x0) // Low-speed device
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[22:28]
DAR
(def=0x0) // Device address
[29]
ODDFRM
(def=0x0) // Odd frame
[30]
CDIS
(def=0x0) // Channel disable
[31]
CEN
(def=0x0) // Channel enable
0x500005A0
HCH5CTL
// host channel-5 characteristics register (HCH5CTL)
[0:10]
MPL
(def=0x0) // Maximum packet size
[11:14]
EPNUM
(def=0x0) // Endpoint number
[15]
EPDIR
(def=0x0) // Endpoint direction
[17]
LSD
(def=0x0) // Low-speed device
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[22:28]
DAR
(def=0x0) // Device address
[29]
ODDFRM
(def=0x0) // Odd frame
[30]
CDIS
(def=0x0) // Channel disable
[31]
CEN
(def=0x0) // Channel enable
0x500005C0
HCH6CTL
// host channel-6 characteristics register (HCH6CTL)
[0:10]
MPL
(def=0x0) // Maximum packet size
[11:14]
EPNUM
(def=0x0) // Endpoint number
[15]
EPDIR
(def=0x0) // Endpoint direction
[17]
LSD
(def=0x0) // Low-speed device
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[22:28]
DAR
(def=0x0) // Device address
[29]
ODDFRM
(def=0x0) // Odd frame
[30]
CDIS
(def=0x0) // Channel disable
[31]
CEN
(def=0x0) // Channel enable
0x500005E0
HCH7CTL
// host channel-7 characteristics register (HCH7CTL)
[0:10]
MPL
(def=0x0) // Maximum packet size
[11:14]
EPNUM
(def=0x0) // Endpoint number
[15]
EPDIR
(def=0x0) // Endpoint direction
[17]
LSD
(def=0x0) // Low-speed device
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[22:28]
DAR
(def=0x0) // Device address
[29]
ODDFRM
(def=0x0) // Odd frame
[30]
CDIS
(def=0x0) // Channel disable
[31]
CEN
(def=0x0) // Channel enable
0x50000508
HCH0INTF
// host channel-0 interrupt register (USBFS_HCHxINTF)
[0]
TF
(def=0x0) // Transfer finished
[1]
CH
(def=0x0) // Channel halted
[3]
STALL
(def=0x0) // STALL response received interrupt
[4]
NAK
(def=0x0) // NAK response received interrupt
[5]
ACK
(def=0x0) // ACK response received/transmitted interrupt
[7]
USBER
(def=0x0) // USB bus error
[8]
BBER
(def=0x0) // Babble error
[9]
REQOVR
(def=0x0) // Request queue overrun
[10]
DTER
(def=0x0) // Data toggle error
0x50000528
HCH1INTF
// host channel-1 interrupt register (HCH1INTF)
[0]
TF
(def=0x0) // Transfer finished
[1]
CH
(def=0x0) // Channel halted
[3]
STALL
(def=0x0) // STALL response received interrupt
[4]
NAK
(def=0x0) // NAK response received interrupt
[5]
ACK
(def=0x0) // ACK response received/transmitted interrupt
[7]
USBER
(def=0x0) // USB bus error
[8]
BBER
(def=0x0) // Babble error
[9]
REQOVR
(def=0x0) // Request queue overrun
[10]
DTER
(def=0x0) // Data toggle error
0x50000548
HCH2INTF
// host channel-2 interrupt register (HCH2INTF)
[0]
TF
(def=0x0) // Transfer finished
[1]
CH
(def=0x0) // Channel halted
[3]
STALL
(def=0x0) // STALL response received interrupt
[4]
NAK
(def=0x0) // NAK response received interrupt
[5]
ACK
(def=0x0) // ACK response received/transmitted interrupt
[7]
USBER
(def=0x0) // USB bus error
[8]
BBER
(def=0x0) // Babble error
[9]
REQOVR
(def=0x0) // Request queue overrun
[10]
DTER
(def=0x0) // Data toggle error
0x50000568
HCH3INTF
// host channel-3 interrupt register (HCH3INTF)
[0]
TF
(def=0x0) // Transfer finished
[1]
CH
(def=0x0) // Channel halted
[3]
STALL
(def=0x0) // STALL response received interrupt
[4]
NAK
(def=0x0) // NAK response received interrupt
[5]
ACK
(def=0x0) // ACK response received/transmitted interrupt
[7]
USBER
(def=0x0) // USB bus error
[8]
BBER
(def=0x0) // Babble error
[9]
REQOVR
(def=0x0) // Request queue overrun
[10]
DTER
(def=0x0) // Data toggle error
0x50000588
HCH4INTF
// host channel-4 interrupt register (HCH4INTF)
[0]
TF
(def=0x0) // Transfer finished
[1]
CH
(def=0x0) // Channel halted
[3]
STALL
(def=0x0) // STALL response received interrupt
[4]
NAK
(def=0x0) // NAK response received interrupt
[5]
ACK
(def=0x0) // ACK response received/transmitted interrupt
[7]
USBER
(def=0x0) // USB bus error
[8]
BBER
(def=0x0) // Babble error
[9]
REQOVR
(def=0x0) // Request queue overrun
[10]
DTER
(def=0x0) // Data toggle error
0x500005A8
HCH5INTF
// host channel-5 interrupt register (HCH5INTF)
[0]
TF
(def=0x0) // Transfer finished
[1]
CH
(def=0x0) // Channel halted
[3]
STALL
(def=0x0) // STALL response received interrupt
[4]
NAK
(def=0x0) // NAK response received interrupt
[5]
ACK
(def=0x0) // ACK response received/transmitted interrupt
[7]
USBER
(def=0x0) // USB bus error
[8]
BBER
(def=0x0) // Babble error
[9]
REQOVR
(def=0x0) // Request queue overrun
[10]
DTER
(def=0x0) // Data toggle error
0x500005C8
HCH6INTF
// host channel-6 interrupt register (HCH6INTF)
[0]
TF
(def=0x0) // Transfer finished
[1]
CH
(def=0x0) // Channel halted
[3]
STALL
(def=0x0) // STALL response received interrupt
[4]
NAK
(def=0x0) // NAK response received interrupt
[5]
ACK
(def=0x0) // ACK response received/transmitted interrupt
[7]
USBER
(def=0x0) // USB bus error
[8]
BBER
(def=0x0) // Babble error
[9]
REQOVR
(def=0x0) // Request queue overrun
[10]
DTER
(def=0x0) // Data toggle error
0x500005E8
HCH7INTF
// host channel-7 interrupt register (HCH7INTF)
[0]
TF
(def=0x0) // Transfer finished
[1]
CH
(def=0x0) // Channel halted
[3]
STALL
(def=0x0) // STALL response received interrupt
[4]
NAK
(def=0x0) // NAK response received interrupt
[5]
ACK
(def=0x0) // ACK response received/transmitted interrupt
[7]
USBER
(def=0x0) // USB bus error
[8]
BBER
(def=0x0) // Babble error
[9]
REQOVR
(def=0x0) // Request queue overrun
[10]
DTER
(def=0x0) // Data toggle error
0x5000050C
HCH0INTEN
// host channel-0 interrupt enable register (HCH0INTEN)
[0]
TFIE
(def=0x0) // Transfer completed interrupt enable
[1]
CHIE
(def=0x0) // Channel halted interrupt enable
[3]
STALLIE
(def=0x0) // STALL interrupt enable
[4]
NAKIE
(def=0x0) // NAK interrupt enable
[5]
ACKIE
(def=0x0) // ACK interrupt enable
[7]
USBERIE
(def=0x0) // USB bus error interrupt enable
[8]
BBERIE
(def=0x0) // Babble error interrupt enable
[9]
REQOVRIE
(def=0x0) // request queue overrun interrupt enable
[10]
DTERIE
(def=0x0) // Data toggle error interrupt enable
0x5000052C
HCH1INTEN
// host channel-1 interrupt enable register (HCH1INTEN)
[0]
TFIE
(def=0x0) // Transfer completed interrupt enable
[1]
CHIE
(def=0x0) // Channel halted interrupt enable
[3]
STALLIE
(def=0x0) // STALL interrupt enable
[4]
NAKIE
(def=0x0) // NAK interrupt enable
[5]
ACKIE
(def=0x0) // ACK interrupt enable
[7]
USBERIE
(def=0x0) // USB bus error interrupt enable
[8]
BBERIE
(def=0x0) // Babble error interrupt enable
[9]
REQOVRIE
(def=0x0) // request queue overrun interrupt enable
[10]
DTERIE
(def=0x0) // Data toggle error interrupt enable
0x5000054C
HCH2INTEN
// host channel-2 interrupt enable register (HCH2INTEN)
[0]
TFIE
(def=0x0) // Transfer completed interrupt enable
[1]
CHIE
(def=0x0) // Channel halted interrupt enable
[3]
STALLIE
(def=0x0) // STALL interrupt enable
[4]
NAKIE
(def=0x0) // NAK interrupt enable
[5]
ACKIE
(def=0x0) // ACK interrupt enable
[7]
USBERIE
(def=0x0) // USB bus error interrupt enable
[8]
BBERIE
(def=0x0) // Babble error interrupt enable
[9]
REQOVRIE
(def=0x0) // request queue overrun interrupt enable
[10]
DTERIE
(def=0x0) // Data toggle error interrupt enable
0x5000056C
HCH3INTEN
// host channel-3 interrupt enable register (HCH3INTEN)
[0]
TFIE
(def=0x0) // Transfer completed interrupt enable
[1]
CHIE
(def=0x0) // Channel halted interrupt enable
[3]
STALLIE
(def=0x0) // STALL interrupt enable
[4]
NAKIE
(def=0x0) // NAK interrupt enable
[5]
ACKIE
(def=0x0) // ACK interrupt enable
[7]
USBERIE
(def=0x0) // USB bus error interrupt enable
[8]
BBERIE
(def=0x0) // Babble error interrupt enable
[9]
REQOVRIE
(def=0x0) // request queue overrun interrupt enable
[10]
DTERIE
(def=0x0) // Data toggle error interrupt enable
0x5000058C
HCH4INTEN
// host channel-4 interrupt enable register (HCH4INTEN)
[0]
TFIE
(def=0x0) // Transfer completed interrupt enable
[1]
CHIE
(def=0x0) // Channel halted interrupt enable
[3]
STALLIE
(def=0x0) // STALL interrupt enable
[4]
NAKIE
(def=0x0) // NAK interrupt enable
[5]
ACKIE
(def=0x0) // ACK interrupt enable
[7]
USBERIE
(def=0x0) // USB bus error interrupt enable
[8]
BBERIE
(def=0x0) // Babble error interrupt enable
[9]
REQOVRIE
(def=0x0) // request queue overrun interrupt enable
[10]
DTERIE
(def=0x0) // Data toggle error interrupt enable
0x500005AC
HCH5INTEN
// host channel-5 interrupt enable register (HCH5INTEN)
[0]
TFIE
(def=0x0) // Transfer completed interrupt enable
[1]
CHIE
(def=0x0) // Channel halted interrupt enable
[3]
STALLIE
(def=0x0) // STALL interrupt enable
[4]
NAKIE
(def=0x0) // NAK interrupt enable
[5]
ACKIE
(def=0x0) // ACK interrupt enable
[7]
USBERIE
(def=0x0) // USB bus error interrupt enable
[8]
BBERIE
(def=0x0) // Babble error interrupt enable
[9]
REQOVRIE
(def=0x0) // request queue overrun interrupt enable
[10]
DTERIE
(def=0x0) // Data toggle error interrupt enable
0x500005CC
HCH6INTEN
// host channel-6 interrupt enable register (HCH6INTEN)
[0]
TFIE
(def=0x0) // Transfer completed interrupt enable
[1]
CHIE
(def=0x0) // Channel halted interrupt enable
[3]
STALLIE
(def=0x0) // STALL interrupt enable
[4]
NAKIE
(def=0x0) // NAK interrupt enable
[5]
ACKIE
(def=0x0) // ACK interrupt enable
[7]
USBERIE
(def=0x0) // USB bus error interrupt enable
[8]
BBERIE
(def=0x0) // Babble error interrupt enable
[9]
REQOVRIE
(def=0x0) // request queue overrun interrupt enable
[10]
DTERIE
(def=0x0) // Data toggle error interrupt enable
0x500005EC
HCH7INTEN
// host channel-7 interrupt enable register (HCH7INTEN)
[0]
TFIE
(def=0x0) // Transfer completed interrupt enable
[1]
CHIE
(def=0x0) // Channel halted interrupt enable
[3]
STALLIE
(def=0x0) // STALL interrupt enable
[4]
NAKIE
(def=0x0) // NAK interrupt enable
[5]
ACKIE
(def=0x0) // ACK interrupt enable
[7]
USBERIE
(def=0x0) // USB bus error interrupt enable
[8]
BBERIE
(def=0x0) // Babble error interrupt enable
[9]
REQOVRIE
(def=0x0) // request queue overrun interrupt enable
[10]
DTERIE
(def=0x0) // Data toggle error interrupt enable
0x50000510
HCH0LEN
// host channel-0 transfer length register
[0:18]
TLEN
(def=0x0) // Transfer length
[19:28]
PCNT
(def=0x0) // Packet count
[29:30]
DPID
(def=0x0) // Data PID
0x50000530
HCH1LEN
// host channel-1 transfer length register
[0:18]
TLEN
(def=0x0) // Transfer length
[19:28]
PCNT
(def=0x0) // Packet count
[29:30]
DPID
(def=0x0) // Data PID
0x50000550
HCH2LEN
// host channel-2 transfer length register
[0:18]
TLEN
(def=0x0) // Transfer length
[19:28]
PCNT
(def=0x0) // Packet count
[29:30]
DPID
(def=0x0) // Data PID
0x50000570
HCH3LEN
// host channel-3 transfer length register
[0:18]
TLEN
(def=0x0) // Transfer length
[19:28]
PCNT
(def=0x0) // Packet count
[29:30]
DPID
(def=0x0) // Data PID
0x50000590
HCH4LEN
// host channel-4 transfer length register
[0:18]
TLEN
(def=0x0) // Transfer length
[19:28]
PCNT
(def=0x0) // Packet count
[29:30]
DPID
(def=0x0) // Data PID
0x500005B0
HCH5LEN
// host channel-5 transfer length register
[0:18]
TLEN
(def=0x0) // Transfer length
[19:28]
PCNT
(def=0x0) // Packet count
[29:30]
DPID
(def=0x0) // Data PID
0x500005D0
HCH6LEN
// host channel-6 transfer length register
[0:18]
TLEN
(def=0x0) // Transfer length
[19:28]
PCNT
(def=0x0) // Packet count
[29:30]
DPID
(def=0x0) // Data PID
0x500005F0
HCH7LEN
// host channel-7 transfer length register
[0:18]
TLEN
(def=0x0) // Transfer length
[19:28]
PCNT
(def=0x0) // Packet count
[29:30]
DPID
(def=0x0) // Data PID
0x50000800
USBFS_DEVICE
// USB on the go full speed device
0x50000800
DCFG
// device configuration register (DCFG)
[0:1]
DS
(def=0x0) // Device speed
[2]
NZLSOH
(def=0x0) // Non-zero-length status OUT handshake
[4:10]
DAR
(def=0x0) // Device address
[11:12]
EOPFT
(def=0x0) // end of periodic frame time
0x50000804
DCTL
// device control register (DCTL)
[0]
RWKUP
(def=0x0) // Remote wakeup
[1]
SD
(def=0x0) // Soft disconnect
[2]
GINS
(def=0x0) // Global IN NAK status
[3]
GONS
(def=0x0) // Global OUT NAK status
[7]
SGINAK
(def=0x0) // Set global IN NAK
[8]
CGINAK
(def=0x0) // Clear global IN NAK
[9]
SGONAK
(def=0x0) // Set global OUT NAK
[10]
CGONAK
(def=0x0) // Clear global OUT NAK
[11]
POIF
(def=0x0) // Power-on initialization flag
0x50000808
DSTAT
// device status register (DSTAT)
[0]
SPST
(def=0x0) // Suspend status
[1:2]
ES
(def=0x0) // Enumerated speed
[8:21]
FNRSOF
(def=0x0) // Frame number of the received SOF
0x50000810
DIEPINTEN
// device IN endpoint common interrupt mask register (DIEPINTEN)
[0]
TFEN
(def=0x0) // Transfer finished interrupt enable
[1]
EPDISEN
(def=0x0) // Endpoint disabled interrupt enable
[3]
CITOEN
(def=0x0) // Control IN timeout condition interrupt enable (Non-isochronous endpoints)
[4]
EPTXFUDEN
(def=0x0) // Endpoint Tx FIFO underrun interrupt enable bit
[6]
IEPNEEN
(def=0x0) // IN endpoint NAK effective interrupt enable
0x50000814
DOEPINTEN
// device OUT endpoint common interrupt enable register (DOEPINTEN)
[0]
TFEN
(def=0x0) // Transfer finished interrupt enable
[1]
EPDISEN
(def=0x0) // Endpoint disabled interrupt enable
[3]
STPFEN
(def=0x0) // SETUP phase finished interrupt enable
[4]
EPRXFOVREN
(def=0x0) // Endpoint Rx FIFO overrun interrupt enable
[6]
BTBSTPEN
(def=0x0) // Back-to-back SETUP packets interrupt enable
0x50000818
DAEPINT
// device all endpoints interrupt register (DAEPINT)
[0:3]
IEPITB
(def=0x0) // Device all IN endpoint interrupt bits
[16:19]
OEPITB
(def=0x0) // Device all OUT endpoint interrupt bits
0x5000081C
DAEPINTEN
// Device all endpoints interrupt enable register (DAEPINTEN)
[0:3]
IEPIE
(def=0x0) // IN EP interrupt interrupt enable bits
[16:19]
OEPIE
(def=0x0) // OUT endpoint interrupt enable bits
0x50000828
DVBUSDT
// device VBUS discharge time register
[0:15]
DVBUSDT
(def=0x17D7) // Device VBUS discharge time
0x5000082C
DVBUSPT
// device VBUS pulsing time register
[0:11]
DVBUSPT
(def=0x5B8) // Device VBUS pulsing time
0x50000834
DIEPFEINTEN
// device IN endpoint FIFO empty interrupt enable register
[0:3]
IEPTXFEIE
(def=0x0) // IN EP Tx FIFO empty interrupt enable bits
0x50000900
DIEP0CTL
// device IN endpoint 0 control register (DIEP0CTL)
[0:1]
MPL
(def=0x0) // Maximum packet length
[15]
EPACT
(def=0x1) // endpoint active
[17]
NAKS
(def=0x0) // NAK status
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[21]
STALL
(def=0x0) // STALL handshake
[22:25]
TXFNUM
(def=0x0) // TxFIFO number
[26]
CNAK
(def=0x0) // Clear NAK
[27]
SNAK
(def=0x0) // Set NAK
[30]
EPD
(def=0x0) // Endpoint disable
[31]
EPEN
(def=0x0) // Endpoint enable
0x50000920
DIEP1CTL
// device in endpoint-1 control register
[31]
EPEN
(def=0x0) // Endpoint enable
[30]
EPD
(def=0x0) // Endpoint disable
[29]
SD1PID_SODDFRM
(def=0x0) // Set DATA1 PID/Set odd frame
[28]
SD0PID_SEVENFRM
(def=0x0) // SD0PID/SEVNFRM
[27]
SNAK
(def=0x0) // Set NAK
[26]
CNAK
(def=0x0) // Clear NAK
[22:25]
TXFNUM
(def=0x0) // Tx FIFO number
[21]
STALL
(def=0x0) // STALL handshake
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[17]
NAKS
(def=0x0) // NAK status
[16]
EOFRM_DPID
(def=0x0) // EOFRM/DPID
[15]
EPACT
(def=0x0) // Endpoint active
[0:10]
MPL
(def=0x0) // maximum packet length
0x50000940
DIEP2CTL
// device endpoint-2 control register
[31]
EPEN
(def=0x0) // Endpoint enable
[30]
EPD
(def=0x0) // Endpoint disable
[29]
SD1PID_SODDFRM
(def=0x0) // Set DATA1 PID/Set odd frame
[28]
SD0PID_SEVENFRM
(def=0x0) // SD0PID/SEVNFRM
[27]
SNAK
(def=0x0) // Set NAK
[26]
CNAK
(def=0x0) // Clear NAK
[22:25]
TXFNUM
(def=0x0) // Tx FIFO number
[21]
STALL
(def=0x0) // STALL handshake
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[17]
NAKS
(def=0x0) // NAK status
[16]
EOFRM_DPID
(def=0x0) // EOFRM/DPID
[15]
EPACT
(def=0x0) // Endpoint active
[0:10]
MPL
(def=0x0) // maximum packet length
0x50000960
DIEP3CTL
// device endpoint-3 control register
[31]
EPEN
(def=0x0) // Endpoint enable
[30]
EPD
(def=0x0) // Endpoint disable
[29]
SD1PID_SODDFRM
(def=0x0) // Set DATA1 PID/Set odd frame
[28]
SD0PID_SEVENFRM
(def=0x0) // SD0PID/SEVNFRM
[27]
SNAK
(def=0x0) // Set NAK
[26]
CNAK
(def=0x0) // Clear NAK
[22:25]
TXFNUM
(def=0x0) // Tx FIFO number
[21]
STALL
(def=0x0) // STALL handshake
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[17]
NAKS
(def=0x0) // NAK status
[16]
EOFRM_DPID
(def=0x0) // EOFRM/DPID
[15]
EPACT
(def=0x0) // Endpoint active
[0:10]
MPL
(def=0x0) // maximum packet length
0x50000B00
DOEP0CTL
// device endpoint-0 control register
[31]
EPEN
(def=0x0) // Endpoint enable
[30]
EPD
(def=0x0) // Endpoint disable
[27]
SNAK
(def=0x0) // Set NAK
[26]
CNAK
(def=0x0) // Clear NAK
[21]
STALL
(def=0x0) // STALL handshake
[20]
SNOOP
(def=0x0) // Snoop mode
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[17]
NAKS
(def=0x0) // NAK status
[15]
EPACT
(def=0x1) // Endpoint active
[0:1]
MPL
(def=0x0) // Maximum packet length
0x50000B20
DOEP1CTL
// device endpoint-1 control register
[31]
EPEN
(def=0x0) // Endpoint enable
[30]
EPD
(def=0x0) // Endpoint disable
[29]
SD1PID_SODDFRM
(def=0x0) // SD1PID/SODDFRM
[28]
SD0PID_SEVENFRM
(def=0x0) // SD0PID/SEVENFRM
[27]
SNAK
(def=0x0) // Set NAK
[26]
CNAK
(def=0x0) // Clear NAK
[21]
STALL
(def=0x0) // STALL handshake
[20]
SNOOP
(def=0x0) // Snoop mode
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[17]
NAKS
(def=0x0) // NAK status
[16]
EOFRM_DPID
(def=0x0) // EOFRM/DPID
[15]
EPACT
(def=0x0) // Endpoint active
[0:10]
MPL
(def=0x0) // maximum packet length
0x50000B40
DOEP2CTL
// device endpoint-2 control register
[31]
EPEN
(def=0x0) // Endpoint enable
[30]
EPD
(def=0x0) // Endpoint disable
[29]
SD1PID_SODDFRM
(def=0x0) // SD1PID/SODDFRM
[28]
SD0PID_SEVENFRM
(def=0x0) // SD0PID/SEVENFRM
[27]
SNAK
(def=0x0) // Set NAK
[26]
CNAK
(def=0x0) // Clear NAK
[21]
STALL
(def=0x0) // STALL handshake
[20]
SNOOP
(def=0x0) // Snoop mode
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[17]
NAKS
(def=0x0) // NAK status
[16]
EOFRM_DPID
(def=0x0) // EOFRM/DPID
[15]
EPACT
(def=0x0) // Endpoint active
[0:10]
MPL
(def=0x0) // maximum packet length
0x50000B60
DOEP3CTL
// device endpoint-3 control register
[31]
EPEN
(def=0x0) // Endpoint enable
[30]
EPD
(def=0x0) // Endpoint disable
[29]
SD1PID_SODDFRM
(def=0x0) // SD1PID/SODDFRM
[28]
SD0PID_SEVENFRM
(def=0x0) // SD0PID/SEVENFRM
[27]
SNAK
(def=0x0) // Set NAK
[26]
CNAK
(def=0x0) // Clear NAK
[21]
STALL
(def=0x0) // STALL handshake
[20]
SNOOP
(def=0x0) // Snoop mode
[18:19]
EPTYPE
(def=0x0) // Endpoint type
[17]
NAKS
(def=0x0) // NAK status
[16]
EOFRM_DPID
(def=0x0) // EOFRM/DPID
[15]
EPACT
(def=0x0) // Endpoint active
[0:10]
MPL
(def=0x0) // maximum packet length
0x50000908
DIEP0INTF
// device endpoint-0 interrupt register
[7]
TXFE
(def=0x1) // Transmit FIFO empty
[6]
IEPNE
(def=0x0) // IN endpoint NAK effective
[4]
EPTXFUD
(def=0x0) // Endpoint Tx FIFO underrun
[3]
CITO
(def=0x0) // Control in timeout interrupt
[1]
EPDIS
(def=0x0) // Endpoint finished
[0]
TF
(def=0x0) // Transfer finished
0x50000928
DIEP1INTF
// device endpoint-1 interrupt register
[7]
TXFE
(def=0x1) // Transmit FIFO empty
[6]
IEPNE
(def=0x0) // IN endpoint NAK effective
[4]
EPTXFUD
(def=0x0) // Endpoint Tx FIFO underrun
[3]
CITO
(def=0x0) // Control in timeout interrupt
[1]
EPDIS
(def=0x0) // Endpoint finished
[0]
TF
(def=0x0) // Transfer finished
0x50000948
DIEP2INTF
// device endpoint-2 interrupt register
[7]
TXFE
(def=0x1) // Transmit FIFO empty
[6]
IEPNE
(def=0x0) // IN endpoint NAK effective
[4]
EPTXFUD
(def=0x0) // Endpoint Tx FIFO underrun
[3]
CITO
(def=0x0) // Control in timeout interrupt
[1]
EPDIS
(def=0x0) // Endpoint finished
[0]
TF
(def=0x0) // Transfer finished
0x50000968
DIEP3INTF
// device endpoint-3 interrupt register
[7]
TXFE
(def=0x1) // Transmit FIFO empty
[6]
IEPNE
(def=0x0) // IN endpoint NAK effective
[4]
EPTXFUD
(def=0x0) // Endpoint Tx FIFO underrun
[3]
CITO
(def=0x0) // Control in timeout interrupt
[1]
EPDIS
(def=0x0) // Endpoint finished
[0]
TF
(def=0x0) // Transfer finished
0x50000B08
DOEP0INTF
// device out endpoint-0 interrupt flag register
[6]
BTBSTP
(def=0x0) // Back-to-back SETUP packets
[4]
EPRXFOVR
(def=0x0) // Endpoint Rx FIFO overrun
[3]
STPF
(def=0x0) // Setup phase finished
[1]
EPDIS
(def=0x0) // Endpoint disabled
[0]
TF
(def=0x0) // Transfer finished
0x50000B28
DOEP1INTF
// device out endpoint-1 interrupt flag register
[6]
BTBSTP
(def=0x0) // Back-to-back SETUP packets
[4]
EPRXFOVR
(def=0x0) // Endpoint Rx FIFO overrun
[3]
STPF
(def=0x0) // Setup phase finished
[1]
EPDIS
(def=0x0) // Endpoint disabled
[0]
TF
(def=0x0) // Transfer finished
0x50000B48
DOEP2INTF
// device out endpoint-2 interrupt flag register
[6]
BTBSTP
(def=0x0) // Back-to-back SETUP packets
[4]
EPRXFOVR
(def=0x0) // Endpoint Rx FIFO overrun
[3]
STPF
(def=0x0) // Setup phase finished
[1]
EPDIS
(def=0x0) // Endpoint disabled
[0]
TF
(def=0x0) // Transfer finished
0x50000B68
DOEP3INTF
// device out endpoint-3 interrupt flag register
[6]
BTBSTP
(def=0x0) // Back-to-back SETUP packets
[4]
EPRXFOVR
(def=0x0) // Endpoint Rx FIFO overrun
[3]
STPF
(def=0x0) // Setup phase finished
[1]
EPDIS
(def=0x0) // Endpoint disabled
[0]
TF
(def=0x0) // Transfer finished
0x50000910
DIEP0LEN
// device IN endpoint-0 transfer length register
[19:20]
PCNT
(def=0x0) // Packet count
[0:6]
TLEN
(def=0x0) // Transfer length
0x50000B10
DOEP0LEN
// device OUT endpoint-0 transfer length register
[29:30]
STPCNT
(def=0x0) // SETUP packet count
[19]
PCNT
(def=0x0) // Packet count
[0:6]
TLEN
(def=0x0) // Transfer length
0x50000930
DIEP1LEN
// device IN endpoint-1 transfer length register
[29:30]
MCPF
(def=0x0) // Multi packet count per frame
[19:28]
PCNT
(def=0x0) // Packet count
[0:18]
TLEN
(def=0x0) // Transfer length
0x50000950
DIEP2LEN
// device IN endpoint-2 transfer length register
[29:30]
MCPF
(def=0x0) // Multi packet count per frame
[19:28]
PCNT
(def=0x0) // Packet count
[0:18]
TLEN
(def=0x0) // Transfer length
0x50000970
DIEP3LEN
// device IN endpoint-3 transfer length register
[29:30]
MCPF
(def=0x0) // Multi packet count per frame
[19:28]
PCNT
(def=0x0) // Packet count
[0:18]
TLEN
(def=0x0) // Transfer length
0x50000B30
DOEP1LEN
// device OUT endpoint-1 transfer length register
[29:30]
STPCNT_RXDPID
(def=0x0) // SETUP packet count/Received data PID
[19:28]
PCNT
(def=0x0) // Packet count
[0:18]
TLEN
(def=0x0) // Transfer length
0x50000B50
DOEP2LEN
// device OUT endpoint-2 transfer length register
[29:30]
STPCNT_RXDPID
(def=0x0) // SETUP packet count/Received data PID
[19:28]
PCNT
(def=0x0) // Packet count
[0:18]
TLEN
(def=0x0) // Transfer length
0x50000B70
DOEP3LEN
// device OUT endpoint-3 transfer length register
[29:30]
STPCNT_RXDPID
(def=0x0) // SETUP packet count/Received data PID
[19:28]
PCNT
(def=0x0) // Packet count
[0:18]
TLEN
(def=0x0) // Transfer length
0x50000918
DIEP0TFSTAT
// device IN endpoint 0 transmit FIFO status register
[0:15]
IEPTFS
(def=0x200) // IN endpoint TxFIFO space remaining
0x50000938
DIEP1TFSTAT
// device IN endpoint 1 transmit FIFO status register
[0:15]
IEPTFS
(def=0x200) // IN endpoint TxFIFO space remaining
0x50000958
DIEP2TFSTAT
// device IN endpoint 2 transmit FIFO status register
[0:15]
IEPTFS
(def=0x200) // IN endpoint TxFIFO space remaining
0x50000978
DIEP3TFSTAT
// device IN endpoint 3 transmit FIFO status register
[0:15]
IEPTFS
(def=0x200) // IN endpoint TxFIFO space remaining
0x50000E00
USBFS_PWRCLK
// USB on the go full speed
0x50000E00
PWRCLKCTL
// power and clock gating control register (PWRCLKCTL)
[0]
SUCLK
(def=0x0) // Stop the USB clock
[1]
SHCLK
(def=0x0) // Stop HCLK
0x40002C00
WWDGT
// Window watchdog timer
0x40002C00
CTL
// Control register
[7]
WDGTEN
(def=0x0) // Activation bit
[0:6]
CNT
(def=0x7F) // 7-bit counter
0x40002C04
CFG
// Configuration register
[9]
EWIE
(def=0x0) // Early wakeup interrupt
[7:8]
PSC
(def=0x0) // Prescaler
[0:6]
WIN
(def=0x7F) // 7-bit window value
0x40002C08
STAT
// Status register
[0]
EWIF
(def=0x0) // Early wakeup interrupt flag
interrupts:
[0]
WWDGT
//
Load
CMP