GD32VF103
0x40012400ADC0// Analog to digital converter
0x40012400STAT// status register
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[4]STRC (def=0x0) // Start flag of regular channel group
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[3]STIC (def=0x0) // Start flag of inserted channel group
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[2]EOIC (def=0x0) // End of inserted group conversion flag
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[1]EOC (def=0x0) // End of group conversion flag
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[0]WDE (def=0x0) // Analog watchdog event flag
0x40012404CTL0// control register 0
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[23]RWDEN (def=0x0) // Regular channel analog watchdog enable
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[22]IWDEN (def=0x0) // Inserted channel analog watchdog enable
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[16:19]SYNCM (def=0x0) // sync mode selection
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[13:15]DISNUM (def=0x0) // Number of conversions in discontinuous mode
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[12]DISIC (def=0x0) // Discontinuous mode on inserted channels
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[11]DISRC (def=0x0) // Discontinuous mode on regular channels
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[10]ICA (def=0x0) // Inserted channel group convert automatically
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[9]WDSC (def=0x0) // When in scan mode, analog watchdog is effective on a single channel
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[8]SM (def=0x0) // Scan mode
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[7]EOICIE (def=0x0) // Interrupt enable for EOIC
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[6]WDEIE (def=0x0) // Interrupt enable for WDE
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[5]EOCIE (def=0x0) // Interrupt enable for EOC
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[0:4]WDCHSEL (def=0x0) // Analog watchdog channel select
0x40012408CTL1// control register 1
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[23]TSVREN (def=0x0) // Channel 16 and 17 enable of ADC0
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[22]SWRCST (def=0x0) // Start on regular channel
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[21]SWICST (def=0x0) // Start on inserted channel
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[20]ETERC (def=0x0) // External trigger enable for regular channel
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[17:19]ETSRC (def=0x0) // External trigger select for regular channel
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[15]ETEIC (def=0x0) // External trigger select for inserted channel
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[12:14]ETSIC (def=0x0) // External trigger select for inserted channel
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[11]DAL (def=0x0) // Data alignment
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[8]DMA (def=0x0) // DMA request enable
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[3]RSTCLB (def=0x0) // Reset calibration
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[2]CLB (def=0x0) // ADC calibration
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[1]CTN (def=0x0) // Continuous mode
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[0]ADCON (def=0x0) // ADC on
0x4001240CSAMPT0// Sample time register 0
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[0:2]SPT10 (def=0x0) // Channel 10 sample time selection
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[3:5]SPT11 (def=0x0) // Channel 11 sample time selection
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[6:8]SPT12 (def=0x0) // Channel 12 sample time selection
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[9:11]SPT13 (def=0x0) // Channel 13 sample time selection
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[12:14]SPT14 (def=0x0) // Channel 14 sample time selection
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[15:17]SPT15 (def=0x0) // Channel 15 sample time selection
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[18:20]SPT16 (def=0x0) // Channel 16 sample time selection
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[21:23]SPT17 (def=0x0) // Channel 17 sample time selection
0x40012410SAMPT1// Sample time register 1
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[0:2]SPT0 (def=0x0) // Channel 0 sample time selection
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[3:5]SPT1 (def=0x0) // Channel 1 sample time selection
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[6:8]SPT2 (def=0x0) // Channel 2 sample time selection
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[9:11]SPT3 (def=0x0) // Channel 3 sample time selection
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[12:14]SPT4 (def=0x0) // Channel 4 sample time selection
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[15:17]SPT5 (def=0x0) // Channel 5 sample time selection
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[18:20]SPT6 (def=0x0) // Channel 6 sample time selection
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[21:23]SPT7 (def=0x0) // Channel 7 sample time selection
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[24:26]SPT8 (def=0x0) // Channel 8 sample time selection
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[27:29]SPT9 (def=0x0) // Channel 9 sample time selection
0x40012414IOFF0// Inserted channel data offset register 0
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[0:11]IOFF (def=0x0) // Data offset for inserted channel 0
0x40012418IOFF1// Inserted channel data offset register 1
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[0:11]IOFF (def=0x0) // Data offset for inserted channel 1
0x4001241CIOFF2// Inserted channel data offset register 2
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[0:11]IOFF (def=0x0) // Data offset for inserted channel 2
0x40012420IOFF3// Inserted channel data offset register 3
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[0:11]IOFF (def=0x0) // Data offset for inserted channel 3
0x40012424WDHT// watchdog higher threshold register
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[0:11]WDHT (def=0xFFF) // Analog watchdog higher threshold
0x40012428WDLT// watchdog lower threshold register
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[0:11]WDLT (def=0x0) // Analog watchdog lower threshold
0x4001242CRSQ0// regular sequence register 0
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[20:23]RL (def=0x0) // Regular channel group length
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[15:19]RSQ15 (def=0x0) // 16th conversion in regular sequence
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[10:14]RSQ14 (def=0x0) // 15th conversion in regular sequence
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[5:9]RSQ13 (def=0x0) // 14th conversion in regular sequence
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[0:4]RSQ12 (def=0x0) // 13th conversion in regular sequence
0x40012430RSQ1// regular sequence register 1
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[25:29]RSQ11 (def=0x0) // 12th conversion in regular sequence
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[20:24]RSQ10 (def=0x0) // 11th conversion in regular sequence
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[15:19]RSQ9 (def=0x0) // 10th conversion in regular sequence
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[10:14]RSQ8 (def=0x0) // 9th conversion in regular sequence
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[5:9]RSQ7 (def=0x0) // 8th conversion in regular sequence
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[0:4]RSQ6 (def=0x0) // 7th conversion in regular sequence
0x40012434RSQ2// regular sequence register 2
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[25:29]RSQ5 (def=0x0) // 6th conversion in regular sequence
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[20:24]RSQ4 (def=0x0) // 5th conversion in regular sequence
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[15:19]RSQ3 (def=0x0) // 4th conversion in regular sequence
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[10:14]RSQ2 (def=0x0) // 3rd conversion in regular sequence
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[5:9]RSQ1 (def=0x0) // 2nd conversion in regular sequence
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[0:4]RSQ0 (def=0x0) // 1st conversion in regular sequence
0x40012438ISQ// Inserted sequence register
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[20:21]IL (def=0x0) // Inserted channel group length
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[15:19]ISQ3 (def=0x0) // 4th conversion in inserted sequence
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[10:14]ISQ2 (def=0x0) // 3rd conversion in inserted sequence
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[5:9]ISQ1 (def=0x0) // 2nd conversion in inserted sequence
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[0:4]ISQ0 (def=0x0) // 1st conversion in inserted sequence
0x4001243CIDATA0// Inserted data register 0
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x40012440IDATA1// Inserted data register 1
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x40012444IDATA2// Inserted data register 2
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x40012448IDATA3// Inserted data register 3
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x4001244CRDATA// regular data register
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[16:31]ADC1RDTR (def=0x0) // ADC regular channel data
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[0:15]RDATA (def=0x0) // Regular channel data
0x40012480OVSAMPCTL// Oversample control register
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[12:13]DRES (def=0x0) // ADC resolution
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[9]TOVS (def=0x0) // Triggered Oversampling
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[5:8]OVSS (def=0x0) // Oversampling shift
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[2:4]OVSR (def=0x0) // Oversampling ratio
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[0]OVSEN (def=0x0) // Oversampler Enable
0x40012800ADC1// Analog to digital converter
0x40012800STAT// status register
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[4]STRC (def=0x0) // Start flag of regular channel group
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[3]STIC (def=0x0) // Start flag of inserted channel group
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[2]EOIC (def=0x0) // End of inserted group conversion flag
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[1]EOC (def=0x0) // End of group conversion flag
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[0]WDE (def=0x0) // Analog watchdog event flag
0x40012804CTL0// control register 0
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[23]RWDEN (def=0x0) // Regular channel analog watchdog enable
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[22]IWDEN (def=0x0) // Inserted channel analog watchdog enable
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[13:15]DISNUM (def=0x0) // Number of conversions in discontinuous mode
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[12]DISIC (def=0x0) // Discontinuous mode on inserted channels
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[11]DISRC (def=0x0) // Discontinuous mode on regular channels
-
[10]ICA (def=0x0) // Inserted channel group convert automatically
-
[9]WDSC (def=0x0) // When in scan mode, analog watchdog is effective on a single channel
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[8]SM (def=0x0) // Scan mode
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[7]EOICIE (def=0x0) // Interrupt enable for EOIC
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[6]WDEIE (def=0x0) // Interrupt enable for WDE
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[5]EOCIE (def=0x0) // Interrupt enable for EOC
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[0:4]WDCHSEL (def=0x0) // Analog watchdog channel select
0x40012808CTL1// control register 1
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[22]SWRCST (def=0x0) // Start on regular channel
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[21]SWICST (def=0x0) // Start on inserted channel
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[20]ETERC (def=0x0) // External trigger enable for regular channel
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[17:19]ETSRC (def=0x0) // External trigger select for regular channel
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[15]ETEIC (def=0x0) // External trigger enable for inserted channel
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[12:14]ETSIC (def=0x0) // External trigger select for inserted channel
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[11]DAL (def=0x0) // Data alignment
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[8]DMA (def=0x0) // DMA request enable
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[3]RSTCLB (def=0x0) // Reset calibration
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[2]CLB (def=0x0) // ADC calibration
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[1]CTN (def=0x0) // Continuous mode
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[0]ADCON (def=0x0) // ADC on
0x4001280CSAMPT0// Sample time register 0
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[0:2]SPT10 (def=0x0) // Channel 10 sample time selection
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[3:5]SPT11 (def=0x0) // Channel 11 sample time selection
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[6:8]SPT12 (def=0x0) // Channel 12 sample time selection
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[9:11]SPT13 (def=0x0) // Channel 13 sample time selection
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[12:14]SPT14 (def=0x0) // Channel 14 sample time selection
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[15:17]SPT15 (def=0x0) // Channel 15 sample time selection
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[18:20]SPT16 (def=0x0) // Channel 16 sample time selection
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[21:23]SPT17 (def=0x0) // Channel 17 sample time selection
0x40012810SAMPT1// Sample time register 1
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[0:2]SPT0 (def=0x0) // Channel 0 sample time selection
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[3:5]SPT1 (def=0x0) // Channel 1 sample time selection
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[6:8]SPT2 (def=0x0) // Channel 2 sample time selection
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[9:11]SPT3 (def=0x0) // Channel 3 sample time selection
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[12:14]SPT4 (def=0x0) // Channel 4 sample time selection
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[15:17]SPT5 (def=0x0) // Channel 5 sample time selection
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[18:20]SPT6 (def=0x0) // Channel 6 sample time selection
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[21:23]SPT7 (def=0x0) // Channel 7 sample time selection
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[24:26]SPT8 (def=0x0) // Channel 8 sample time selection
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[27:29]SPT9 (def=0x0) // Channel 9 sample time selection
0x40012814IOFF0// Inserted channel data offset register 0
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[0:11]IOFF (def=0x0) // Data offset for inserted channel 0
0x40012818IOFF1// Inserted channel data offset register 1
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[0:11]IOFF (def=0x0) // Data offset for inserted channel 1
0x4001281CIOFF2// Inserted channel data offset register 2
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[0:11]IOFF (def=0x0) // Data offset for inserted channel 2
0x40012820IOFF3// Inserted channel data offset register 3
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[0:11]IOFF (def=0x0) // Data offset for inserted channel 3
0x40012824WDHT// watchdog higher threshold register
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[0:11]WDHT (def=0xFFF) // Analog watchdog higher threshold
0x40012828WDLT// watchdog lower threshold register
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[0:11]WDLT (def=0x0) // Analog watchdog lower threshold
0x4001282CRSQ0// regular sequence register 0
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[20:23]RL (def=0x0) // Regular channel group length
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[15:19]RSQ15 (def=0x0) // 16th conversion in regular sequence
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[10:14]RSQ14 (def=0x0) // 15th conversion in regular sequence
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[5:9]RSQ13 (def=0x0) // 14th conversion in regular sequence
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[0:4]RSQ12 (def=0x0) // 13th conversion in regular sequence
0x40012830RSQ1// regular sequence register 1
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[25:29]RSQ11 (def=0x0) // 12th conversion in regular sequence
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[20:24]RSQ10 (def=0x0) // 11th conversion in regular sequence
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[15:19]RSQ9 (def=0x0) // 10th conversion in regular sequence
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[10:14]RSQ8 (def=0x0) // 9th conversion in regular sequence
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[5:9]RSQ7 (def=0x0) // 8th conversion in regular sequence
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[0:4]RSQ6 (def=0x0) // 7th conversion in regular sequence
0x40012834RSQ2// regular sequence register 2
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[25:29]RSQ5 (def=0x0) // 6th conversion in regular sequence
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[20:24]RSQ4 (def=0x0) // 5th conversion in regular sequence
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[15:19]RSQ3 (def=0x0) // 4th conversion in regular sequence
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[10:14]RSQ2 (def=0x0) // 3rd conversion in regular sequence
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[5:9]RSQ1 (def=0x0) // 2nd conversion in regular sequence
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[0:4]RSQ0 (def=0x0) // 1st conversion in regular sequence
0x40012838ISQ// Inserted sequence register
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[20:21]IL (def=0x0) // Inserted channel group length
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[15:19]ISQ3 (def=0x0) // 4th conversion in inserted sequence
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[10:14]ISQ2 (def=0x0) // 3rd conversion in inserted sequence
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[5:9]ISQ1 (def=0x0) // 2nd conversion in inserted sequence
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[0:4]ISQ0 (def=0x0) // 1st conversion in inserted sequence
0x4001283CIDATA0// Inserted data register 0
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x40012840IDATA1// Inserted data register 1
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x40012844IDATA2// Inserted data register 2
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x40012848IDATA3// Inserted data register 3
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[0:15]IDATAn (def=0x0) // Inserted number n conversion data
0x4001284CRDATA// regular data register
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[0:15]RDATA (def=0x0) // Regular channel data
0x40010000AFIO// Alternate-function I/Os
0x40010000EC// Event control register
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[7]EOE (def=0x0) // Event output enable
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[4:6]PORT (def=0x0) // Event output port selection
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[0:3]PIN (def=0x0) // Event output pin selection
0x40010004PCF0// AFIO port configuration register 0
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[29]TIMER1ITI1_REMAP (def=0x0) // TIMER1 internal trigger 1 remapping
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[28]SPI2_REMAP (def=0x0) // SPI2/I2S2 remapping
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[24:26]SWJ_CFG (def=0x0) // Serial wire JTAG configuration
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[22]CAN1_REMAP (def=0x0) // CAN1 I/O remapping
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[16]TIMER4CH3_IREMAP (def=0x0) // TIMER4 channel3 internal remapping
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[15]PD01_REMAP (def=0x0) // Port D0/Port D1 mapping on OSC_IN/OSC_OUT
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[13:14]CAN0_REMAP (def=0x0) // CAN0 alternate interface remapping
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[12]TIMER3_REMAP (def=0x0) // TIMER3 remapping
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[10:11]TIMER2_REMAP (def=0x0) // TIMER2 remapping
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[8:9]TIMER1_REMAP (def=0x0) // TIMER1 remapping
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[6:7]TIMER0_REMAP (def=0x0) // TIMER0 remapping
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[4:5]USART2_REMAP (def=0x0) // USART2 remapping
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[3]USART1_REMAP (def=0x0) // USART1 remapping
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[2]USART0_REMAP (def=0x0) // USART0 remapping
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[1]I2C0_REMAP (def=0x0) // I2C0 remapping
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[0]SPI0_REMAP (def=0x0) // SPI0 remapping
0x40010008EXTISS0// EXTI sources selection register 0
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[12:15]EXTI3_SS (def=0x0) // EXTI 3 sources selection
-
[8:11]EXTI2_SS (def=0x0) // EXTI 2 sources selection
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[4:7]EXTI1_SS (def=0x0) // EXTI 1 sources selection
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[0:3]EXTI0_SS (def=0x0) // EXTI 0 sources selection
0x4001000CEXTISS1// EXTI sources selection register 1
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[12:15]EXTI7_SS (def=0x0) // EXTI 7 sources selection
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[8:11]EXTI6_SS (def=0x0) // EXTI 6 sources selection
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[4:7]EXTI5_SS (def=0x0) // EXTI 5 sources selection
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[0:3]EXTI4_SS (def=0x0) // EXTI 4 sources selection
0x40010010EXTISS2// EXTI sources selection register 2
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[12:15]EXTI11_SS (def=0x0) // EXTI 11 sources selection
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[8:11]EXTI10_SS (def=0x0) // EXTI 10 sources selection
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[4:7]EXTI9_SS (def=0x0) // EXTI 9 sources selection
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[0:3]EXTI8_SS (def=0x0) // EXTI 8 sources selection
0x40010014EXTISS3// EXTI sources selection register 3
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[12:15]EXTI15_SS (def=0x0) // EXTI 15 sources selection
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[8:11]EXTI14_SS (def=0x0) // EXTI 14 sources selection
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[4:7]EXTI13_SS (def=0x0) // EXTI 13 sources selection
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[0:3]EXTI12_SS (def=0x0) // EXTI 12 sources selection
0x4001001CPCF1// AFIO port configuration register 1
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[10]EXMC_NADV (def=0x0) // EXMC_NADV connect/disconnect
0x40006C00BKP// Backup registers
0x40006C04DATA0// Backup data register 0
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[0:15]DATA (def=0x0) // Backup data
0x40006C08DATA1// Backup data register 1
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[0:15]DATA (def=0x0) // Backup data
0x40006C0CDATA2// Backup data register 2
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[0:15]DATA (def=0x0) // Backup data
0x40006C10DATA3// Backup data register 3
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[0:15]DATA (def=0x0) // Backup data
0x40006C14DATA4// Backup data register 4
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[0:15]DATA (def=0x0) // Backup data
0x40006C18DATA5// Backup data register 5
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[0:15]DATA (def=0x0) // Backup data
0x40006C1CDATA6// Backup data register 6
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[0:15]DATA (def=0x0) // Backup data
0x40006C20DATA7// Backup data register 7
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[0:15]DATA (def=0x0) // Backup data
0x40006C24DATA8// Backup data register 8
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[0:15]DATA (def=0x0) // Backup data
0x40006C28DATA9// Backup data register 9
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[0:15]DATA (def=0x0) // Backup data
0x40006C40DATA10// Backup data register 10
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[0:15]DATA (def=0x0) // Backup data
0x40006C44DATA11// Backup data register 11
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[0:15]DATA (def=0x0) // Backup data
0x40006C48DATA12// Backup data register 12
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[0:15]DATA (def=0x0) // Backup data
0x40006C4CDATA13// Backup data register 13
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[0:15]DATA (def=0x0) // Backup data
0x40006C50DATA14// Backup data register 14
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[0:15]DATA (def=0x0) // Backup data
0x40006C54DATA15// Backup data register 15
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[0:15]DATA (def=0x0) // Backup data
0x40006C58DATA16// Backup data register 16
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[0:15]DATA (def=0x0) // Backup data
0x40006C5CDATA17// Backup data register 17
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[0:15]DATA (def=0x0) // Backup data
0x40006C60DATA18// Backup data register 18
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[0:15]DATA (def=0x0) // Backup data
0x40006C64DATA19// Backup data register 19
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[0:15]DATA (def=0x0) // Backup data
0x40006C68DATA20// Backup data register 20
-
[0:15]DATA (def=0x0) // Backup data
0x40006C6CDATA21// Backup data register 21
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[0:15]DATA (def=0x0) // Backup data
0x40006C70DATA22// Backup data register 22
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[0:15]DATA (def=0x0) // Backup data
0x40006C74DATA23// Backup data register 23
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[0:15]DATA (def=0x0) // Backup data
0x40006C78DATA24// Backup data register 24
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[0:15]DATA (def=0x0) // Backup data
0x40006C7CDATA25// Backup data register 25
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[0:15]DATA (def=0x0) // Backup data
0x40006C80DATA26// Backup data register 26
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[0:15]DATA (def=0x0) // Backup data
0x40006C84DATA27// Backup data register 27
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[0:15]DATA (def=0x0) // Backup data
0x40006C88DATA28// Backup data register 28
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[0:15]DATA (def=0x0) // Backup data
0x40006C8CDATA29// Backup data register 29
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[0:15]DATA (def=0x0) // Backup data
0x40006C90DATA30// Backup data register 30
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[0:15]DATA (def=0x0) // Backup data
0x40006C94DATA31// Backup data register 31
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[0:15]DATA (def=0x0) // Backup data
0x40006C98DATA32// Backup data register 32
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[0:15]DATA (def=0x0) // Backup data
0x40006C9CDATA33// Backup data register 33
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[0:15]DATA (def=0x0) // Backup data
0x40006CA0DATA34// Backup data register 34
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[0:15]DATA (def=0x0) // Backup data
0x40006CA4DATA35// Backup data register 35
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[0:15]DATA (def=0x0) // Backup data
0x40006CA8DATA36// Backup data register 36
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[0:15]DATA (def=0x0) // Backup data
0x40006CACDATA37// Backup data register 37
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[0:15]DATA (def=0x0) // Backup data
0x40006CB0DATA38// Backup data register 38
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[0:15]DATA (def=0x0) // Backup data
0x40006CB4DATA39// Backup data register 39
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[0:15]DATA (def=0x0) // Backup data
0x40006CB8DATA40// Backup data register 40
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[0:15]DATA (def=0x0) // Backup data
0x40006CBCDATA41// Backup data register 41
-
[0:15]DATA (def=0x0) // Backup data
0x40006C2COCTL// RTC signal output control register
-
[9]ROSEL (def=0x0) // RTC output selection
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[8]ASOEN (def=0x0) // RTC alarm or second signal output enable
-
[7]COEN (def=0x0) // RTC clock calibration output enable
-
[0:6]RCCV (def=0x0) // RTC clock calibration value
0x40006C30TPCTL// Tamper pin control register
-
[1]TPAL (def=0x0) // TAMPER pin active level
-
[0]TPEN (def=0x0) // TAMPER detection enable
0x40006C34TPCS// Tamper control and status register
-
[9]TIF (def=0x0) // Tamper interrupt flag
-
[8]TEF (def=0x0) // Tamper event flag
-
[2]TPIE (def=0x0) // Tamper interrupt enable
-
[1]TIR (def=0x0) // Tamper interrupt reset
-
[0]TER (def=0x0) // Tamper event reset
0x40006400CAN0// Controller area network
0x40006400CTL// Control register
-
[16]DFZ (def=0x1) // Debug freeze
-
[15]SWRST (def=0x0) // Software reset
-
[7]TTC (def=0x0) // Time-triggered communication
-
[6]ABOR (def=0x0) // Automatic bus-off recovery
-
[5]AWU (def=0x0) // Automatic wakeup
-
[4]ARD (def=0x0) // Automatic retransmission disable
-
[3]RFOD (def=0x0) // Receive FIFO overwrite disable
-
[2]TFO (def=0x0) // Transmit FIFO order
-
[1]SLPWMOD (def=0x1) // Sleep working mode
-
[0]IWMOD (def=0x0) // Initial working mode
0x40006404STAT// Status register
-
[11]RXL (def=0x1) // RX level
-
[10]LASTRX (def=0x1) // Last sample value of RX pin
-
[9]RS (def=0x0) // Receiving state
-
[8]TS (def=0x0) // Transmitting state
-
[4]SLPIF (def=0x0) // Status change interrupt flag of sleep working mode entering
-
[3]WUIF (def=0x0) // Status change interrupt flag of wakeup from sleep working mode
-
[2]ERRIF (def=0x0) // Error interrupt flag
-
[1]SLPWS (def=0x1) // Sleep working state
-
[0]IWS (def=0x0) // Initial working state
0x40006408TSTAT// Transmit status register
-
[31]TMLS2 (def=0x0) // Transmit mailbox 2 last sending in transmit FIFO
-
[30]TMLS1 (def=0x0) // Transmit mailbox 1 last sending in transmit FIFO
-
[29]TMLS0 (def=0x0) // Transmit mailbox 0 last sending in transmit FIFO
-
[28]TME2 (def=0x1) // Transmit mailbox 2 empty
-
[27]TME1 (def=0x1) // Transmit mailbox 1 empty
-
[26]TME0 (def=0x1) // Transmit mailbox 0 empty
-
[24:25]NUM (def=0x0) // number of the transmit FIFO mailbox in which the frame will be transmitted if at least one m
-
[23]MST2 (def=0x0) // Mailbox 2 stop transmitting
-
[19]MTE2 (def=0x0) // Mailbox 2 transmit error
-
[18]MAL2 (def=0x0) // Mailbox 2 arbitration lost
-
[17]MTFNERR2 (def=0x0) // Mailbox 2 transmit finished and no error
-
[16]MTF2 (def=0x0) // Mailbox 2 transmit finished
-
[15]MST1 (def=0x0) // Mailbox 1 stop transmitting
-
[11]MTE1 (def=0x0) // Mailbox 1 transmit error
-
[10]MAL1 (def=0x0) // Mailbox 1 arbitration lost
-
[9]MTFNERR1 (def=0x0) // Mailbox 1 transmit finished and no error
-
[8]MTF1 (def=0x0) // Mailbox 1 transmit finished
-
[7]MST0 (def=0x0) // Mailbox 0 stop transmitting
-
[3]MTE0 (def=0x0) // Mailbox 0 transmit error
-
[2]MAL0 (def=0x0) // Mailbox 0 arbitration lost
-
[1]MTFNERR0 (def=0x0) // Mailbox 0 transmit finished and no error
-
[0]MTF0 (def=0x0) // Mailbox 0 transmit finished
0x4000640CRFIFO0// Receive message FIFO0 register
-
[5]RFD0 (def=0x0) // Receive FIFO0 dequeue
-
[4]RFO0 (def=0x0) // Receive FIFO0 overfull
-
[3]RFF0 (def=0x0) // Receive FIFO0 full
-
[0:1]RFL0 (def=0x0) // Receive FIFO0 length
0x40006410RFIFO1// Receive message FIFO1 register
-
[5]RFD1 (def=0x0) // Receive FIFO1 dequeue
-
[4]RFO1 (def=0x0) // Receive FIFO1 overfull
-
[3]RFF1 (def=0x0) // Receive FIFO1 full
-
[0:1]RFL1 (def=0x0) // Receive FIFO1 length
0x40006414INTEN// Interrupt enable register
-
[17]SLPWIE (def=0x0) // Sleep working interrupt enable
-
[16]WIE (def=0x0) // Wakeup interrupt enable
-
[15]ERRIE (def=0x0) // Error interrupt enable
-
[11]ERRNIE (def=0x0) // Error number interrupt enable
-
[10]BOIE (def=0x0) // Bus-off interrupt enable
-
[9]PERRIE (def=0x0) // Passive error interrupt enable
-
[8]WERRIE (def=0x0) // Warning error interrupt enable
-
[6]RFOIE1 (def=0x0) // Receive FIFO1 overfull interrupt enable
-
[5]RFFIE1 (def=0x0) // Receive FIFO1 full interrupt enable
-
[4]RFNEIE1 (def=0x0) // Receive FIFO1 not empty interrupt enable
-
[3]RFOIE0 (def=0x0) // Receive FIFO0 overfull interrupt enable
-
[2]RFFIE0 (def=0x0) // Receive FIFO0 full interrupt enable
-
[1]RFNEIE0 (def=0x0) // Receive FIFO0 not empty interrupt enable
-
[0]TMEIE (def=0x0) // Transmit mailbox empty interrupt enable
0x40006418ERR// Error register
-
[24:31]RECNT (def=0x0) // Receive Error Count defined by the CAN standard
-
[16:23]TECNT (def=0x0) // Transmit Error Count defined by the CAN standard
-
[4:6]ERRN (def=0x0) // Error number
-
[2]BOERR (def=0x0) // Bus-off error
-
[1]PERR (def=0x0) // Passive error
-
[0]WERR (def=0x0) // Warning error
0x4000641CBT// Bit timing register
-
[31]SCMOD (def=0x0) // Silent communication mode
-
[30]LCMOD (def=0x0) // Loopback communication mode
-
[24:25]SJW (def=0x1) // Resynchronization jump width
-
[20:22]BS2 (def=0x2) // Bit segment 2
-
[16:19]BS1 (def=0x3) // Bit segment 1
-
[0:9]BAUDPSC (def=0x0) // Baud rate prescaler
0x40006580TMI0// Transmit mailbox identifier register 0
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
-
[0]TEN (def=0x0) // Transmit enable
0x40006584TMP0// Transmit mailbox property register 0
-
[16:31]TS (def=0x0) // Time stamp
-
[8]TSEN (def=0x0) // Time stamp enable
-
[0:3]DLENC (def=0x0) // Data length code
0x40006588TMDATA00// Transmit mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x4000658CTMDATA10// Transmit mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x40006590TMI1// Transmit mailbox identifier register 1
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
-
[0]TEN (def=0x0) // Transmit enable
0x40006594TMP1// Transmit mailbox property register 1
-
[16:31]TS (def=0x0) // Time stamp
-
[8]TSEN (def=0x0) // Time stamp enable
-
[0:3]DLENC (def=0x0) // Data length code
0x40006598TMDATA01// Transmit mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x4000659CTMDATA11// Transmit mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x400065A0TMI2// Transmit mailbox identifier register 2
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
-
[0]TEN (def=0x0) // Transmit enable
0x400065A4TMP2// Transmit mailbox property register 2
-
[16:31]TS (def=0x0) // Time stamp
-
[8]TSEN (def=0x0) // Time stamp enable
-
[0:3]DLENC (def=0x0) // Data length code
0x400065A8TMDATA02// Transmit mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x400065ACTMDATA12// Transmit mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x400065B0RFIFOMI0// Receive FIFO mailbox identifier register
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
0x400065B4RFIFOMP0// Receive FIFO0 mailbox property register
-
[16:31]TS (def=0x0) // Time stamp
-
[8:15]FI (def=0x0) // Filtering index
-
[0:3]DLENC (def=0x0) // Data length code
0x400065B8RFIFOMDATA00// Receive FIFO0 mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x400065BCRFIFOMDATA10// Receive FIFO0 mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x400065C0RFIFOMI1// Receive FIFO1 mailbox identifier register
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
0x400065C4RFIFOMP1// Receive FIFO1 mailbox property register
-
[16:31]TS (def=0x0) // Time stamp
-
[8:15]FI (def=0x0) // Filtering index
-
[0:3]DLENC (def=0x0) // Data length code
0x400065C8RFIFOMDATA01// Receive FIFO1 mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x400065CCRFIFOMDATA11// Receive FIFO1 mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x40006600FCTL// Filter control register
-
[8:13]HBC1F (def=0xE) // Header bank of CAN1 filter
-
[0]FLD (def=0x1) // Filter lock disable
0x40006604FMCFG// Filter mode configuration register
-
[27]FMOD27 (def=0x0) // Filter mode
-
[26]FMOD26 (def=0x0) // Filter mode
-
[25]FMOD25 (def=0x0) // Filter mode
-
[24]FMOD24 (def=0x0) // Filter mode
-
[23]FMOD23 (def=0x0) // Filter mode
-
[22]FMOD22 (def=0x0) // Filter mode
-
[21]FMOD21 (def=0x0) // Filter mode
-
[20]FMOD20 (def=0x0) // Filter mode
-
[19]FMOD19 (def=0x0) // Filter mode
-
[18]FMOD18 (def=0x0) // Filter mode
-
[17]FMOD17 (def=0x0) // Filter mode
-
[16]FMOD16 (def=0x0) // Filter mode
-
[15]FMOD15 (def=0x0) // Filter mode
-
[14]FMOD14 (def=0x0) // Filter mode
-
[13]FMOD13 (def=0x0) // Filter mode
-
[12]FMOD12 (def=0x0) // Filter mode
-
[11]FMOD11 (def=0x0) // Filter mode
-
[10]FMOD10 (def=0x0) // Filter mode
-
[9]FMOD9 (def=0x0) // Filter mode
-
[8]FMOD8 (def=0x0) // Filter mode
-
[7]FMOD7 (def=0x0) // Filter mode
-
[6]FMOD6 (def=0x0) // Filter mode
-
[5]FMOD5 (def=0x0) // Filter mode
-
[4]FMOD4 (def=0x0) // Filter mode
-
[3]FMOD3 (def=0x0) // Filter mode
-
[2]FMOD2 (def=0x0) // Filter mode
-
[1]FMOD1 (def=0x0) // Filter mode
-
[0]FMOD0 (def=0x0) // Filter mode
0x4000660CFSCFG// Filter scale configuration register
-
[0]FS0 (def=0x0) // Filter scale configuration
-
[1]FS1 (def=0x0) // Filter scale configuration
-
[2]FS2 (def=0x0) // Filter scale configuration
-
[3]FS3 (def=0x0) // Filter scale configuration
-
[4]FS4 (def=0x0) // Filter scale configuration
-
[5]FS5 (def=0x0) // Filter scale configuration
-
[6]FS6 (def=0x0) // Filter scale configuration
-
[7]FS7 (def=0x0) // Filter scale configuration
-
[8]FS8 (def=0x0) // Filter scale configuration
-
[9]FS9 (def=0x0) // Filter scale configuration
-
[10]FS10 (def=0x0) // Filter scale configuration
-
[11]FS11 (def=0x0) // Filter scale configuration
-
[12]FS12 (def=0x0) // Filter scale configuration
-
[13]FS13 (def=0x0) // Filter scale configuration
-
[14]FS14 (def=0x0) // Filter scale configuration
-
[15]FS15 (def=0x0) // Filter scale configuration
-
[16]FS16 (def=0x0) // Filter scale configuration
-
[17]FS17 (def=0x0) // Filter scale configuration
-
[18]FS18 (def=0x0) // Filter scale configuration
-
[19]FS19 (def=0x0) // Filter scale configuration
-
[20]FS20 (def=0x0) // Filter scale configuration
-
[21]FS21 (def=0x0) // Filter scale configuration
-
[22]FS22 (def=0x0) // Filter scale configuration
-
[23]FS23 (def=0x0) // Filter scale configuration
-
[24]FS24 (def=0x0) // Filter scale configuration
-
[25]FS25 (def=0x0) // Filter scale configuration
-
[26]FS26 (def=0x0) // Filter scale configuration
-
[27]FS27 (def=0x0) // Filter scale configuration
0x40006614FAFIFO// Filter associated FIFO register
-
[0]FAF0 (def=0x0) // Filter 0 associated with FIFO
-
[1]FAF1 (def=0x0) // Filter 1 associated with FIFO
-
[2]FAF2 (def=0x0) // Filter 2 associated with FIFO
-
[3]FAF3 (def=0x0) // Filter 3 associated with FIFO
-
[4]FAF4 (def=0x0) // Filter 4 associated with FIFO
-
[5]FAF5 (def=0x0) // Filter 5 associated with FIFO
-
[6]FAF6 (def=0x0) // Filter 6 associated with FIFO
-
[7]FAF7 (def=0x0) // Filter 7 associated with FIFO
-
[8]FAF8 (def=0x0) // Filter 8 associated with FIFO
-
[9]FAF9 (def=0x0) // Filter 9 associated with FIFO
-
[10]FAF10 (def=0x0) // Filter 10 associated with FIFO
-
[11]FAF11 (def=0x0) // Filter 11 associated with FIFO
-
[12]FAF12 (def=0x0) // Filter 12 associated with FIFO
-
[13]FAF13 (def=0x0) // Filter 13 associated with FIFO
-
[14]FAF14 (def=0x0) // Filter 14 associated with FIFO
-
[15]FAF15 (def=0x0) // Filter 15 associated with FIFO
-
[16]FAF16 (def=0x0) // Filter 16 associated with FIFO
-
[17]FAF17 (def=0x0) // Filter 17 associated with FIFO
-
[18]FAF18 (def=0x0) // Filter 18 associated with FIFO
-
[19]FAF19 (def=0x0) // Filter 19 associated with FIFO
-
[20]FAF20 (def=0x0) // Filter 20 associated with FIFO
-
[21]FAF21 (def=0x0) // Filter 21 associated with FIFO
-
[22]FAF22 (def=0x0) // Filter 22 associated with FIFO
-
[23]FAF23 (def=0x0) // Filter 23 associated with FIFO
-
[24]FAF24 (def=0x0) // Filter 24 associated with FIFO
-
[25]FAF25 (def=0x0) // Filter 25 associated with FIFO
-
[26]FAF26 (def=0x0) // Filter 26 associated with FIFO
-
[27]FAF27 (def=0x0) // Filter 27 associated with FIFO
0x4000661CFW// Filter working register
-
[0]FW0 (def=0x0) // Filter working
-
[1]FW1 (def=0x0) // Filter working
-
[2]FW2 (def=0x0) // Filter working
-
[3]FW3 (def=0x0) // Filter working
-
[4]FW4 (def=0x0) // Filter working
-
[5]FW5 (def=0x0) // Filter working
-
[6]FW6 (def=0x0) // Filter working
-
[7]FW7 (def=0x0) // Filter working
-
[8]FW8 (def=0x0) // Filter working
-
[9]FW9 (def=0x0) // Filter working
-
[10]FW10 (def=0x0) // Filter working
-
[11]FW11 (def=0x0) // Filter working
-
[12]FW12 (def=0x0) // Filter working
-
[13]FW13 (def=0x0) // Filter working
-
[14]FW14 (def=0x0) // Filter working
-
[15]FW15 (def=0x0) // Filter working
-
[16]FW16 (def=0x0) // Filter working
-
[17]FW17 (def=0x0) // Filter working
-
[18]FW18 (def=0x0) // Filter working
-
[19]FW19 (def=0x0) // Filter working
-
[20]FW20 (def=0x0) // Filter working
-
[21]FW21 (def=0x0) // Filter working
-
[22]FW22 (def=0x0) // Filter working
-
[23]FW23 (def=0x0) // Filter working
-
[24]FW24 (def=0x0) // Filter working
-
[25]FW25 (def=0x0) // Filter working
-
[26]FW26 (def=0x0) // Filter working
-
[27]FW27 (def=0x0) // Filter working
0x40006640F0DATA0// Filter 0 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006644F0DATA1// Filter 0 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006648F1DATA0// Filter 1 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x4000664CF1DATA1// Filter 1 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006650F2DATA0// Filter 2 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006654F2DATA1// Filter 2 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006658F3DATA0// Filter 3 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x4000665CF3DATA1// Filter 3 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006660F4DATA0// Filter 4 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006664F4DATA1// Filter 4 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006668F5DATA0// Filter 5 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x4000666CF5DATA1// Filter 5 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006670F6DATA0// Filter 6 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006674F6DATA1// Filter 6 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006678F7DATA0// Filter 7 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x4000667CF7DATA1// Filter 7 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006680F8DATA0// Filter 8 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006684F8DATA1// Filter 8 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006688F9DATA0// Filter 9 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x4000668CF9DATA1// Filter 9 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006690F10DATA0// Filter 10 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006694F10DATA1// Filter 10 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006698F11DATA0// Filter 11 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x4000669CF11DATA1// Filter 11 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066A0F12DATA0// Filter 12 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066A4F12DATA1// Filter 12 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066A8F13DATA0// Filter 13 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066ACF13DATA1// Filter 13 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066B0F14DATA0// Filter 14 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066B4F14DATA1// Filter 14 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066B8F15DATA0// Filter 15 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066BCF15DATA1// Filter 15 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066C0F16DATA0// Filter 16 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066C4F16DATA1// Filter 16 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066C8F17DATA0// Filter 17 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066CCF17DATA1// Filter 17 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066D0F18DATA0// Filter 18 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066D4F18DATA1// Filter 18 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066D8F19DATA0// Filter 19 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066DCF19DATA1// Filter 19 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066E0F20DATA0// Filter 20 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066E4F20DATA1// Filter 20 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066E8F21DATA0// Filter 21 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066ECF21DATA1// Filter 21 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066F0F22DATA0// Filter 22 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066F4F22DATA1// Filter 22 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066F8F23DATA0// Filter 23 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x400066FCF23DATA1// Filter 23 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006700F24DATA0// Filter 24 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006704F24DATA1// Filter 24 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006708F25DATA0// Filter 25 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x4000670CF25DATA1// Filter 25 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006710F26DATA0// Filter 26 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006714F26DATA1// Filter 26 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006718F27DATA0// Filter 27 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x4000671CF27DATA1// Filter 27 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
- [38] CAN0_TX //
- [39] CAN0_RX0 //
- [40] CAN0_RX1 //
- [41] CAN0_EWMC //
0x40006800CAN1//
0x40006800CTL// Control register
-
[16]DFZ (def=0x1) // Debug freeze
-
[15]SWRST (def=0x0) // Software reset
-
[7]TTC (def=0x0) // Time-triggered communication
-
[6]ABOR (def=0x0) // Automatic bus-off recovery
-
[5]AWU (def=0x0) // Automatic wakeup
-
[4]ARD (def=0x0) // Automatic retransmission disable
-
[3]RFOD (def=0x0) // Receive FIFO overwrite disable
-
[2]TFO (def=0x0) // Transmit FIFO order
-
[1]SLPWMOD (def=0x1) // Sleep working mode
-
[0]IWMOD (def=0x0) // Initial working mode
0x40006804STAT// Status register
-
[11]RXL (def=0x1) // RX level
-
[10]LASTRX (def=0x1) // Last sample value of RX pin
-
[9]RS (def=0x0) // Receiving state
-
[8]TS (def=0x0) // Transmitting state
-
[4]SLPIF (def=0x0) // Status change interrupt flag of sleep working mode entering
-
[3]WUIF (def=0x0) // Status change interrupt flag of wakeup from sleep working mode
-
[2]ERRIF (def=0x0) // Error interrupt flag
-
[1]SLPWS (def=0x1) // Sleep working state
-
[0]IWS (def=0x0) // Initial working state
0x40006808TSTAT// Transmit status register
-
[31]TMLS2 (def=0x0) // Transmit mailbox 2 last sending in transmit FIFO
-
[30]TMLS1 (def=0x0) // Transmit mailbox 1 last sending in transmit FIFO
-
[29]TMLS0 (def=0x0) // Transmit mailbox 0 last sending in transmit FIFO
-
[28]TME2 (def=0x1) // Transmit mailbox 2 empty
-
[27]TME1 (def=0x1) // Transmit mailbox 1 empty
-
[26]TME0 (def=0x1) // Transmit mailbox 0 empty
-
[24:25]NUM (def=0x0) // number of the transmit FIFO mailbox in which the frame will be transmitted if at least one m
-
[23]MST2 (def=0x0) // Mailbox 2 stop transmitting
-
[19]MTE2 (def=0x0) // Mailbox 2 transmit error
-
[18]MAL2 (def=0x0) // Mailbox 2 arbitration lost
-
[17]MTFNERR2 (def=0x0) // Mailbox 2 transmit finished and no error
-
[16]MTF2 (def=0x0) // Mailbox 2 transmit finished
-
[15]MST1 (def=0x0) // Mailbox 1 stop transmitting
-
[11]MTE1 (def=0x0) // Mailbox 1 transmit error
-
[10]MAL1 (def=0x0) // Mailbox 1 arbitration lost
-
[9]MTFNERR1 (def=0x0) // Mailbox 1 transmit finished and no error
-
[8]MTF1 (def=0x0) // Mailbox 1 transmit finished
-
[7]MST0 (def=0x0) // Mailbox 0 stop transmitting
-
[3]MTE0 (def=0x0) // Mailbox 0 transmit error
-
[2]MAL0 (def=0x0) // Mailbox 0 arbitration lost
-
[1]MTFNERR0 (def=0x0) // Mailbox 0 transmit finished and no error
-
[0]MTF0 (def=0x0) // Mailbox 0 transmit finished
0x4000680CRFIFO0// Receive message FIFO0 register
-
[5]RFD0 (def=0x0) // Receive FIFO0 dequeue
-
[4]RFO0 (def=0x0) // Receive FIFO0 overfull
-
[3]RFF0 (def=0x0) // Receive FIFO0 full
-
[0:1]RFL0 (def=0x0) // Receive FIFO0 length
0x40006810RFIFO1// Receive message FIFO1 register
-
[5]RFD1 (def=0x0) // Receive FIFO1 dequeue
-
[4]RFO1 (def=0x0) // Receive FIFO1 overfull
-
[3]RFF1 (def=0x0) // Receive FIFO1 full
-
[0:1]RFL1 (def=0x0) // Receive FIFO1 length
0x40006814INTEN// Interrupt enable register
-
[17]SLPWIE (def=0x0) // Sleep working interrupt enable
-
[16]WIE (def=0x0) // Wakeup interrupt enable
-
[15]ERRIE (def=0x0) // Error interrupt enable
-
[11]ERRNIE (def=0x0) // Error number interrupt enable
-
[10]BOIE (def=0x0) // Bus-off interrupt enable
-
[9]PERRIE (def=0x0) // Passive error interrupt enable
-
[8]WERRIE (def=0x0) // Warning error interrupt enable
-
[6]RFOIE1 (def=0x0) // Receive FIFO1 overfull interrupt enable
-
[5]RFFIE1 (def=0x0) // Receive FIFO1 full interrupt enable
-
[4]RFNEIE1 (def=0x0) // Receive FIFO1 not empty interrupt enable
-
[3]RFOIE0 (def=0x0) // Receive FIFO0 overfull interrupt enable
-
[2]RFFIE0 (def=0x0) // Receive FIFO0 full interrupt enable
-
[1]RFNEIE0 (def=0x0) // Receive FIFO0 not empty interrupt enable
-
[0]TMEIE (def=0x0) // Transmit mailbox empty interrupt enable
0x40006818ERR// Error register
-
[24:31]RECNT (def=0x0) // Receive Error Count defined by the CAN standard
-
[16:23]TECNT (def=0x0) // Transmit Error Count defined by the CAN standard
-
[4:6]ERRN (def=0x0) // Error number
-
[2]BOERR (def=0x0) // Bus-off error
-
[1]PERR (def=0x0) // Passive error
-
[0]WERR (def=0x0) // Warning error
0x4000681CBT// Bit timing register
-
[31]SCMOD (def=0x0) // Silent communication mode
-
[30]LCMOD (def=0x0) // Loopback communication mode
-
[24:25]SJW (def=0x1) // Resynchronization jump width
-
[20:22]BS2 (def=0x2) // Bit segment 2
-
[16:19]BS1 (def=0x3) // Bit segment 1
-
[0:9]BAUDPSC (def=0x0) // Baud rate prescaler
0x40006980TMI0// Transmit mailbox identifier register 0
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
-
[0]TEN (def=0x0) // Transmit enable
0x40006984TMP0// Transmit mailbox property register 0
-
[16:31]TS (def=0x0) // Time stamp
-
[8]TSEN (def=0x0) // Time stamp enable
-
[0:3]DLENC (def=0x0) // Data length code
0x40006988TMDATA00// Transmit mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x4000698CTMDATA10// Transmit mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x40006990TMI1// Transmit mailbox identifier register 1
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
-
[0]TEN (def=0x0) // Transmit enable
0x40006994TMP1// Transmit mailbox property register 1
-
[16:31]TS (def=0x0) // Time stamp
-
[8]TSEN (def=0x0) // Time stamp enable
-
[0:3]DLENC (def=0x0) // Data length code
0x40006998TMDATA01// Transmit mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x4000699CTMDATA11// Transmit mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x400069A0TMI2// Transmit mailbox identifier register 2
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
-
[0]TEN (def=0x0) // Transmit enable
0x400069A4TMP2// Transmit mailbox property register 2
-
[16:31]TS (def=0x0) // Time stamp
-
[8]TSEN (def=0x0) // Time stamp enable
-
[0:3]DLENC (def=0x0) // Data length code
0x400069A8TMDATA02// Transmit mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x400069ACTMDATA12// Transmit mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x400069B0RFIFOMI0// Receive FIFO mailbox identifier register
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
0x400069B4RFIFOMP0// Receive FIFO0 mailbox property register
-
[16:31]TS (def=0x0) // Time stamp
-
[8:15]FI (def=0x0) // Filtering index
-
[0:3]DLENC (def=0x0) // Data length code
0x400069B8RFIFOMDATA00// Receive FIFO0 mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x400069BCRFIFOMDATA10// Receive FIFO0 mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x400069C0RFIFOMI1// Receive FIFO1 mailbox identifier register
-
[21:31]SFID_EFID (def=0x0) // The frame identifier
-
[3:20]EFID (def=0x0) // The frame identifier
-
[2]FF (def=0x0) // Frame format
-
[1]FT (def=0x0) // Frame type
0x400069C4RFIFOMP1// Receive FIFO1 mailbox property register
-
[16:31]TS (def=0x0) // Time stamp
-
[8:15]FI (def=0x0) // Filtering index
-
[0:3]DLENC (def=0x0) // Data length code
0x400069C8RFIFOMDATA01// Receive FIFO1 mailbox data0 register
-
[24:31]DB3 (def=0x0) // Data byte 3
-
[16:23]DB2 (def=0x0) // Data byte 2
-
[8:15]DB1 (def=0x0) // Data byte 1
-
[0:7]DB0 (def=0x0) // Data byte 0
0x400069CCRFIFOMDATA11// Receive FIFO1 mailbox data1 register
-
[24:31]DB7 (def=0x0) // Data byte 7
-
[16:23]DB6 (def=0x0) // Data byte 6
-
[8:15]DB5 (def=0x0) // Data byte 5
-
[0:7]DB4 (def=0x0) // Data byte 4
0x40006A00FCTL// Filter control register
-
[8:13]HBC1F (def=0xE) // Header bank of CAN1 filter
-
[0]FLD (def=0x1) // Filter lock disable
0x40006A04FMCFG// Filter mode configuration register
-
[27]FMOD27 (def=0x0) // Filter mode
-
[26]FMOD26 (def=0x0) // Filter mode
-
[25]FMOD25 (def=0x0) // Filter mode
-
[24]FMOD24 (def=0x0) // Filter mode
-
[23]FMOD23 (def=0x0) // Filter mode
-
[22]FMOD22 (def=0x0) // Filter mode
-
[21]FMOD21 (def=0x0) // Filter mode
-
[20]FMOD20 (def=0x0) // Filter mode
-
[19]FMOD19 (def=0x0) // Filter mode
-
[18]FMOD18 (def=0x0) // Filter mode
-
[17]FMOD17 (def=0x0) // Filter mode
-
[16]FMOD16 (def=0x0) // Filter mode
-
[15]FMOD15 (def=0x0) // Filter mode
-
[14]FMOD14 (def=0x0) // Filter mode
-
[13]FMOD13 (def=0x0) // Filter mode
-
[12]FMOD12 (def=0x0) // Filter mode
-
[11]FMOD11 (def=0x0) // Filter mode
-
[10]FMOD10 (def=0x0) // Filter mode
-
[9]FMOD9 (def=0x0) // Filter mode
-
[8]FMOD8 (def=0x0) // Filter mode
-
[7]FMOD7 (def=0x0) // Filter mode
-
[6]FMOD6 (def=0x0) // Filter mode
-
[5]FMOD5 (def=0x0) // Filter mode
-
[4]FMOD4 (def=0x0) // Filter mode
-
[3]FMOD3 (def=0x0) // Filter mode
-
[2]FMOD2 (def=0x0) // Filter mode
-
[1]FMOD1 (def=0x0) // Filter mode
-
[0]FMOD0 (def=0x0) // Filter mode
0x40006A0CFSCFG// Filter scale configuration register
-
[0]FS0 (def=0x0) // Filter scale configuration
-
[1]FS1 (def=0x0) // Filter scale configuration
-
[2]FS2 (def=0x0) // Filter scale configuration
-
[3]FS3 (def=0x0) // Filter scale configuration
-
[4]FS4 (def=0x0) // Filter scale configuration
-
[5]FS5 (def=0x0) // Filter scale configuration
-
[6]FS6 (def=0x0) // Filter scale configuration
-
[7]FS7 (def=0x0) // Filter scale configuration
-
[8]FS8 (def=0x0) // Filter scale configuration
-
[9]FS9 (def=0x0) // Filter scale configuration
-
[10]FS10 (def=0x0) // Filter scale configuration
-
[11]FS11 (def=0x0) // Filter scale configuration
-
[12]FS12 (def=0x0) // Filter scale configuration
-
[13]FS13 (def=0x0) // Filter scale configuration
-
[14]FS14 (def=0x0) // Filter scale configuration
-
[15]FS15 (def=0x0) // Filter scale configuration
-
[16]FS16 (def=0x0) // Filter scale configuration
-
[17]FS17 (def=0x0) // Filter scale configuration
-
[18]FS18 (def=0x0) // Filter scale configuration
-
[19]FS19 (def=0x0) // Filter scale configuration
-
[20]FS20 (def=0x0) // Filter scale configuration
-
[21]FS21 (def=0x0) // Filter scale configuration
-
[22]FS22 (def=0x0) // Filter scale configuration
-
[23]FS23 (def=0x0) // Filter scale configuration
-
[24]FS24 (def=0x0) // Filter scale configuration
-
[25]FS25 (def=0x0) // Filter scale configuration
-
[26]FS26 (def=0x0) // Filter scale configuration
-
[27]FS27 (def=0x0) // Filter scale configuration
0x40006A14FAFIFO// Filter associated FIFO register
-
[0]FAF0 (def=0x0) // Filter 0 associated with FIFO
-
[1]FAF1 (def=0x0) // Filter 1 associated with FIFO
-
[2]FAF2 (def=0x0) // Filter 2 associated with FIFO
-
[3]FAF3 (def=0x0) // Filter 3 associated with FIFO
-
[4]FAF4 (def=0x0) // Filter 4 associated with FIFO
-
[5]FAF5 (def=0x0) // Filter 5 associated with FIFO
-
[6]FAF6 (def=0x0) // Filter 6 associated with FIFO
-
[7]FAF7 (def=0x0) // Filter 7 associated with FIFO
-
[8]FAF8 (def=0x0) // Filter 8 associated with FIFO
-
[9]FAF9 (def=0x0) // Filter 9 associated with FIFO
-
[10]FAF10 (def=0x0) // Filter 10 associated with FIFO
-
[11]FAF11 (def=0x0) // Filter 11 associated with FIFO
-
[12]FAF12 (def=0x0) // Filter 12 associated with FIFO
-
[13]FAF13 (def=0x0) // Filter 13 associated with FIFO
-
[14]FAF14 (def=0x0) // Filter 14 associated with FIFO
-
[15]FAF15 (def=0x0) // Filter 15 associated with FIFO
-
[16]FAF16 (def=0x0) // Filter 16 associated with FIFO
-
[17]FAF17 (def=0x0) // Filter 17 associated with FIFO
-
[18]FAF18 (def=0x0) // Filter 18 associated with FIFO
-
[19]FAF19 (def=0x0) // Filter 19 associated with FIFO
-
[20]FAF20 (def=0x0) // Filter 20 associated with FIFO
-
[21]FAF21 (def=0x0) // Filter 21 associated with FIFO
-
[22]FAF22 (def=0x0) // Filter 22 associated with FIFO
-
[23]FAF23 (def=0x0) // Filter 23 associated with FIFO
-
[24]FAF24 (def=0x0) // Filter 24 associated with FIFO
-
[25]FAF25 (def=0x0) // Filter 25 associated with FIFO
-
[26]FAF26 (def=0x0) // Filter 26 associated with FIFO
-
[27]FAF27 (def=0x0) // Filter 27 associated with FIFO
0x40006A1CFW// Filter working register
-
[0]FW0 (def=0x0) // Filter working
-
[1]FW1 (def=0x0) // Filter working
-
[2]FW2 (def=0x0) // Filter working
-
[3]FW3 (def=0x0) // Filter working
-
[4]FW4 (def=0x0) // Filter working
-
[5]FW5 (def=0x0) // Filter working
-
[6]FW6 (def=0x0) // Filter working
-
[7]FW7 (def=0x0) // Filter working
-
[8]FW8 (def=0x0) // Filter working
-
[9]FW9 (def=0x0) // Filter working
-
[10]FW10 (def=0x0) // Filter working
-
[11]FW11 (def=0x0) // Filter working
-
[12]FW12 (def=0x0) // Filter working
-
[13]FW13 (def=0x0) // Filter working
-
[14]FW14 (def=0x0) // Filter working
-
[15]FW15 (def=0x0) // Filter working
-
[16]FW16 (def=0x0) // Filter working
-
[17]FW17 (def=0x0) // Filter working
-
[18]FW18 (def=0x0) // Filter working
-
[19]FW19 (def=0x0) // Filter working
-
[20]FW20 (def=0x0) // Filter working
-
[21]FW21 (def=0x0) // Filter working
-
[22]FW22 (def=0x0) // Filter working
-
[23]FW23 (def=0x0) // Filter working
-
[24]FW24 (def=0x0) // Filter working
-
[25]FW25 (def=0x0) // Filter working
-
[26]FW26 (def=0x0) // Filter working
-
[27]FW27 (def=0x0) // Filter working
0x40006A40F0DATA0// Filter 0 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A44F0DATA1// Filter 0 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A48F1DATA0// Filter 1 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A4CF1DATA1// Filter 1 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A50F2DATA0// Filter 2 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A54F2DATA1// Filter 2 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A58F3DATA0// Filter 3 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A5CF3DATA1// Filter 3 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A60F4DATA0// Filter 4 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A64F4DATA1// Filter 4 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A68F5DATA0// Filter 5 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A6CF5DATA1// Filter 5 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A70F6DATA0// Filter 6 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A74F6DATA1// Filter 6 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A78F7DATA0// Filter 7 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A7CF7DATA1// Filter 7 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A80F8DATA0// Filter 8 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A84F8DATA1// Filter 8 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A88F9DATA0// Filter 9 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A8CF9DATA1// Filter 9 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A90F10DATA0// Filter 10 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A94F10DATA1// Filter 10 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A98F11DATA0// Filter 11 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006A9CF11DATA1// Filter 11 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AA0F12DATA0// Filter 12 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AA4F12DATA1// Filter 12 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AA8F13DATA0// Filter 13 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AACF13DATA1// Filter 13 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AB0F14DATA0// Filter 14 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AB4F14DATA1// Filter 14 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AB8F15DATA0// Filter 15 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006ABCF15DATA1// Filter 15 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AC0F16DATA0// Filter 16 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AC4F16DATA1// Filter 16 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AC8F17DATA0// Filter 17 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006ACCF17DATA1// Filter 17 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AD0F18DATA0// Filter 18 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AD4F18DATA1// Filter 18 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AD8F19DATA0// Filter 19 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006ADCF19DATA1// Filter 19 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AE0F20DATA0// Filter 20 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AE4F20DATA1// Filter 20 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AE8F21DATA0// Filter 21 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AECF21DATA1// Filter 21 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AF0F22DATA0// Filter 22 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AF4F22DATA1// Filter 22 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AF8F23DATA0// Filter 23 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006AFCF23DATA1// Filter 23 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006B00F24DATA0// Filter 24 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006B04F24DATA1// Filter 24 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006B08F25DATA0// Filter 25 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006B0CF25DATA1// Filter 25 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006B10F26DATA0// Filter 26 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006B14F26DATA1// Filter 26 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006B18F27DATA0// Filter 27 data 0 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
0x40006B1CF27DATA1// Filter 27 data 1 register
-
[0]FD0 (def=0x0) // Filter bits
-
[1]FD1 (def=0x0) // Filter bits
-
[2]FD2 (def=0x0) // Filter bits
-
[3]FD3 (def=0x0) // Filter bits
-
[4]FD4 (def=0x0) // Filter bits
-
[5]FD5 (def=0x0) // Filter bits
-
[6]FD6 (def=0x0) // Filter bits
-
[7]FD7 (def=0x0) // Filter bits
-
[8]FD8 (def=0x0) // Filter bits
-
[9]FD9 (def=0x0) // Filter bits
-
[10]FD10 (def=0x0) // Filter bits
-
[11]FD11 (def=0x0) // Filter bits
-
[12]FD12 (def=0x0) // Filter bits
-
[13]FD13 (def=0x0) // Filter bits
-
[14]FD14 (def=0x0) // Filter bits
-
[15]FD15 (def=0x0) // Filter bits
-
[16]FD16 (def=0x0) // Filter bits
-
[17]FD17 (def=0x0) // Filter bits
-
[18]FD18 (def=0x0) // Filter bits
-
[19]FD19 (def=0x0) // Filter bits
-
[20]FD20 (def=0x0) // Filter bits
-
[21]FD21 (def=0x0) // Filter bits
-
[22]FD22 (def=0x0) // Filter bits
-
[23]FD23 (def=0x0) // Filter bits
-
[24]FD24 (def=0x0) // Filter bits
-
[25]FD25 (def=0x0) // Filter bits
-
[26]FD26 (def=0x0) // Filter bits
-
[27]FD27 (def=0x0) // Filter bits
-
[28]FD28 (def=0x0) // Filter bits
-
[29]FD29 (def=0x0) // Filter bits
-
[30]FD30 (def=0x0) // Filter bits
-
[31]FD31 (def=0x0) // Filter bits
- [82] CAN1_TX //
- [83] CAN1_RX0 //
- [84] CAN1_RX1 //
- [85] CAN1_EWMC //
0x40023000CRC// cyclic redundancy check calculation unit
0x40023000DATA// Data register
-
[0:31]DATA (def=0xFFFFFFFF) // CRC calculation result bits
0x40023004FDATA// Free data register
-
[0:7]FDATA (def=0x0) // Free Data Register bits
0x40023008CTL// Control register
-
[0]RST (def=0x0) // reset bit
0x40007400DAC// Digital-to-analog converter
0x40007400CTL// control register
-
[0]DEN0 (def=0x0) // DAC0 enable
-
[1]DBOFF0 (def=0x0) // DAC0 output buffer turn off
-
[2]DTEN0 (def=0x0) // DAC0 trigger enable
-
[3:5]DTSEL0 (def=0x0) // DAC0 trigger selection
-
[6:7]DWM0 (def=0x0) // DAC0 noise wave mode
-
[8:11]DWBW0 (def=0x0) // DAC0 noise wave bit width
-
[12]DDMAEN0 (def=0x0) // DAC0 DMA enable
-
[16]DEN1 (def=0x0) // DAC1 enable
-
[17]DBOFF1 (def=0x0) // DAC1 output buffer turn off
-
[18]DTEN1 (def=0x0) // DAC1 trigger enable
-
[19:21]DTSEL1 (def=0x0) // DAC1 trigger selection
-
[22:23]DWM1 (def=0x0) // DAC1 noise wave mode
-
[24:27]DWBW1 (def=0x0) // DAC1 noise wave bit width
-
[28]DDMAEN1 (def=0x0) // DAC1 DMA enable
0x40007404SWT// software trigger register
-
[0]SWTR0 (def=0x0) // DAC0 software trigger
-
[1]SWTR1 (def=0x0) // DAC1 software trigger
0x40007408DAC0_R12DH// DAC0 12-bit right-aligned data holding register
-
[0:11]DAC0_DH (def=0x0) // DAC0 12-bit right-aligned data
0x4000740CDAC0_L12DH// DAC0 12-bit left-aligned data holding register
-
[4:15]DAC0_DH (def=0x0) // DAC0 12-bit left-aligned data
0x40007410DAC0_R8DH// DAC0 8-bit right aligned data holding register
-
[0:7]DAC0_DH (def=0x0) // DAC0 8-bit right-aligned data
0x40007414DAC1_R12DH// DAC1 12-bit right-aligned data holding register
-
[0:11]DAC1_DH (def=0x0) // DAC1 12-bit right-aligned data
0x40007418DAC1_L12DH// DAC1 12-bit left aligned data holding register
-
[4:15]DAC1_DH (def=0x0) // DAC1 12-bit left-aligned data
0x4000741CDAC1_R8DH// DAC1 8-bit right aligned data holding register
-
[0:7]DAC1_DH (def=0x0) // DAC1 8-bit right-aligned data
0x40007420DACC_R12DH// DAC concurrent mode 12-bit right-aligned data holding register
-
[0:11]DAC0_DH (def=0x0) // DAC0 12-bit right-aligned data
-
[16:27]DAC1_DH (def=0x0) // DAC1 12-bit right-aligned data
0x40007424DACC_L12DH// DAC concurrent mode 12-bit left aligned data holding register
-
[4:15]DAC0_DH (def=0x0) // DAC0 12-bit left-aligned data
-
[20:31]DAC1_DH (def=0x0) // DAC1 12-bit left-aligned data
0x40007428DACC_R8DH// DAC concurrent mode 8-bit right aligned data holding register
-
[0:7]DAC0_DH (def=0x0) // DAC0 8-bit right-aligned data
-
[8:15]DAC1_DH (def=0x0) // DAC1 8-bit right-aligned data
0x4000742CDAC0_DO// DAC0 data output register
-
[0:11]DAC0_DO (def=0x0) // DAC0 data output
0x40007430DAC1_DO// DAC1 data output register
-
[0:11]DAC1_DO (def=0x0) // DAC1 data output
0xE0042000DBG// Debug support
0xE0042000ID// ID code register
-
[0:31]ID_CODE (def=0x0) // DBG ID code register
0xE0042004CTL// Control register 0
-
[0]SLP_HOLD (def=0x0) // Sleep mode hold register
-
[1]DSLP_HOLD (def=0x0) // Deep-sleep mode hold register
-
[2]STB_HOLD (def=0x0) // Standby mode hold register
-
[8]FWDGT_HOLD (def=0x0) // FWDGT hold bit
-
[9]WWDGT_HOLD (def=0x0) // WWDGT hold bit
-
[10]TIMER0_HOLD (def=0x0) // TIMER 0 hold bit
-
[11]TIMER1_HOLD (def=0x0) // TIMER 1 hold bit
-
[12]TIMER2_HOLD (def=0x0) // TIMER 2 hold bit
-
[13]TIMER3_HOLD (def=0x0) // TIMER 23 hold bit
-
[14]CAN0_HOLD (def=0x0) // CAN0 hold bit
-
[15]I2C0_HOLD (def=0x0) // I2C0 hold bit
-
[16]I2C1_HOLD (def=0x0) // I2C1 hold bit
-
[18]TIMER4_HOLD (def=0x0) // TIMER4_HOLD
-
[19]TIMER5_HOLD (def=0x0) // TIMER 5 hold bit
-
[20]TIMER6_HOLD (def=0x0) // TIMER 6 hold bit
-
[21]CAN1_HOLD (def=0x0) // CAN1 hold bit
0x40020000DMA0// DMA controller
0x40020000INTF// Interrupt flag register
-
[0]GIF0 (def=0x0) // Global interrupt flag of channel 0
-
[1]FTFIF0 (def=0x0) // Full Transfer finish flag of channe 0
-
[2]HTFIF0 (def=0x0) // Half transfer finish flag of channel 0
-
[3]ERRIF0 (def=0x0) // Error flag of channel 0
-
[4]GIF1 (def=0x0) // Global interrupt flag of channel 1
-
[5]FTFIF1 (def=0x0) // Full Transfer finish flag of channe 1
-
[6]HTFIF1 (def=0x0) // Half transfer finish flag of channel 1
-
[7]ERRIF1 (def=0x0) // Error flag of channel 1
-
[8]GIF2 (def=0x0) // Global interrupt flag of channel 2
-
[9]FTFIF2 (def=0x0) // Full Transfer finish flag of channe 2
-
[10]HTFIF2 (def=0x0) // Half transfer finish flag of channel 2
-
[11]ERRIF2 (def=0x0) // Error flag of channel 2
-
[12]GIF3 (def=0x0) // Global interrupt flag of channel 3
-
[13]FTFIF3 (def=0x0) // Full Transfer finish flag of channe 3
-
[14]HTFIF3 (def=0x0) // Half transfer finish flag of channel 3
-
[15]ERRIF3 (def=0x0) // Error flag of channel 3
-
[16]GIF4 (def=0x0) // Global interrupt flag of channel 4
-
[17]FTFIF4 (def=0x0) // Full Transfer finish flag of channe 4
-
[18]HTFIF4 (def=0x0) // Half transfer finish flag of channel 4
-
[19]ERRIF4 (def=0x0) // Error flag of channel 4
-
[20]GIF5 (def=0x0) // Global interrupt flag of channel 5
-
[21]FTFIF5 (def=0x0) // Full Transfer finish flag of channe 5
-
[22]HTFIF5 (def=0x0) // Half transfer finish flag of channel 5
-
[23]ERRIF5 (def=0x0) // Error flag of channel 5
-
[24]GIF6 (def=0x0) // Global interrupt flag of channel 6
-
[25]FTFIF6 (def=0x0) // Full Transfer finish flag of channe 6
-
[26]HTFIF6 (def=0x0) // Half transfer finish flag of channel 6
-
[27]ERRIF6 (def=0x0) // Error flag of channel 6
0x40020004INTC// Interrupt flag clear register
-
[0]GIFC0 (def=0x0) // Clear global interrupt flag of channel 0
-
[1]FTFIFC0 (def=0x0) // Clear bit for full transfer finish flag of channel 0
-
[2]HTFIFC0 (def=0x0) // Clear bit for half transfer finish flag of channel 0
-
[3]ERRIFC0 (def=0x0) // Clear bit for error flag of channel 0
-
[4]GIFC1 (def=0x0) // Clear global interrupt flag of channel 1
-
[5]FTFIFC1 (def=0x0) // Clear bit for full transfer finish flag of channel 1
-
[6]HTFIFC1 (def=0x0) // Clear bit for half transfer finish flag of channel 1
-
[7]ERRIFC1 (def=0x0) // Clear bit for error flag of channel 1
-
[8]GIFC2 (def=0x0) // Clear global interrupt flag of channel 2
-
[9]FTFIFC2 (def=0x0) // Clear bit for full transfer finish flag of channel 2
-
[10]HTFIFC2 (def=0x0) // Clear bit for half transfer finish flag of channel 2
-
[11]ERRIFC2 (def=0x0) // Clear bit for error flag of channel 2
-
[12]GIFC3 (def=0x0) // Clear global interrupt flag of channel 3
-
[13]FTFIFC3 (def=0x0) // Clear bit for full transfer finish flag of channel 3
-
[14]HTFIFC3 (def=0x0) // Clear bit for half transfer finish flag of channel 3
-
[15]ERRIFC3 (def=0x0) // Clear bit for error flag of channel 3
-
[16]GIFC4 (def=0x0) // Clear global interrupt flag of channel 4
-
[17]FTFIFC4 (def=0x0) // Clear bit for full transfer finish flag of channel 4
-
[18]HTFIFC4 (def=0x0) // Clear bit for half transfer finish flag of channel 4
-
[19]ERRIFC4 (def=0x0) // Clear bit for error flag of channel 4
-
[20]GIFC5 (def=0x0) // Clear global interrupt flag of channel 5
-
[21]FTFIFC5 (def=0x0) // Clear bit for full transfer finish flag of channel 5
-
[22]HTFIFC5 (def=0x0) // Clear bit for half transfer finish flag of channel 5
-
[23]ERRIFC5 (def=0x0) // Clear bit for error flag of channel 5
-
[24]GIFC6 (def=0x0) // Clear global interrupt flag of channel 6
-
[25]FTFIFC6 (def=0x0) // Clear bit for full transfer finish flag of channel 6
-
[26]HTFIFC6 (def=0x0) // Clear bit for half transfer finish flag of channel 6
-
[27]ERRIFC6 (def=0x0) // Clear bit for error flag of channel 6
0x40020008CH0CTL// Channel 0 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x4002000CCH0CNT// Channel 0 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020010CH0PADDR// Channel 0 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40020014CH0MADDR// Channel 0 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x4002001CCH1CTL// Channel 1 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x40020020CH1CNT// Channel 1 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020024CH1PADDR// Channel 1 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40020028CH1MADDR// Channel 1 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x40020030CH2CTL// Channel 2 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x40020034CH2CNT// Channel 2 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020038CH2PADDR// Channel 2 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x4002003CCH2MADDR// Channel 2 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x40020044CH3CTL// Channel 3 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x40020048CH3CNT// Channel 3 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x4002004CCH3PADDR// Channel 3 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40020050CH3MADDR// Channel 3 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x40020058CH4CTL// Channel 4 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x4002005CCH4CNT// Channel 4 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020060CH4PADDR// Channel 4 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40020064CH4MADDR// Channel 4 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x4002006CCH5CTL// Channel 5 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x40020070CH5CNT// Channel 5 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020074CH5PADDR// Channel 5 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40020078CH5MADDR// Channel 5 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x40020080CH6CTL// Channel 6 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x40020084CH6CNT// Channel 6 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020088CH6PADDR// Channel 6 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x4002008CCH6MADDR// Channel 6 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
- [30] DMA0_Channel0 //
- [31] DMA0_Channel1 //
- [32] DMA0_Channel2 //
- [33] DMA0_Channel3 //
- [34] DMA0_Channel4 //
- [35] DMA0_Channel5 //
- [36] DMA0_Channel6 //
0x40020400DMA1// Direct memory access controller
0x40020400INTF// Interrupt flag register
-
[0]GIF0 (def=0x0) // Global interrupt flag of channel 0
-
[1]FTFIF0 (def=0x0) // Full Transfer finish flag of channe 0
-
[2]HTFIF0 (def=0x0) // Half transfer finish flag of channel 0
-
[3]ERRIF0 (def=0x0) // Error flag of channel 0
-
[4]GIF1 (def=0x0) // Global interrupt flag of channel 1
-
[5]FTFIF1 (def=0x0) // Full Transfer finish flag of channe 1
-
[6]HTFIF1 (def=0x0) // Half transfer finish flag of channel 1
-
[7]ERRIF1 (def=0x0) // Error flag of channel 1
-
[8]GIF2 (def=0x0) // Global interrupt flag of channel 2
-
[9]FTFIF2 (def=0x0) // Full Transfer finish flag of channe 2
-
[10]HTFIF2 (def=0x0) // Half transfer finish flag of channel 2
-
[11]ERRIF2 (def=0x0) // Error flag of channel 2
-
[12]GIF3 (def=0x0) // Global interrupt flag of channel 3
-
[13]FTFIF3 (def=0x0) // Full Transfer finish flag of channe 3
-
[14]HTFIF3 (def=0x0) // Half transfer finish flag of channel 3
-
[15]ERRIF3 (def=0x0) // Error flag of channel 3
-
[16]GIF4 (def=0x0) // Global interrupt flag of channel 4
-
[17]FTFIF4 (def=0x0) // Full Transfer finish flag of channe 4
-
[18]HTFIF4 (def=0x0) // Half transfer finish flag of channel 4
-
[19]ERRIF4 (def=0x0) // Error flag of channel 4
0x40020404INTC// Interrupt flag clear register
-
[0]GIFC0 (def=0x0) // Clear global interrupt flag of channel 0
-
[1]FTFIFC0 (def=0x0) // Clear bit for full transfer finish flag of channel 0
-
[2]HTFIFC0 (def=0x0) // Clear bit for half transfer finish flag of channel 0
-
[3]ERRIFC0 (def=0x0) // Clear bit for error flag of channel 0
-
[4]GIFC1 (def=0x0) // Clear global interrupt flag of channel 1
-
[5]FTFIFC1 (def=0x0) // Clear bit for full transfer finish flag of channel 1
-
[6]HTFIFC1 (def=0x0) // Clear bit for half transfer finish flag of channel 1
-
[7]ERRIFC1 (def=0x0) // Clear bit for error flag of channel 1
-
[8]GIFC2 (def=0x0) // Clear global interrupt flag of channel 2
-
[9]FTFIFC2 (def=0x0) // Clear bit for full transfer finish flag of channel 2
-
[10]HTFIFC2 (def=0x0) // Clear bit for half transfer finish flag of channel 2
-
[11]ERRIFC2 (def=0x0) // Clear bit for error flag of channel 2
-
[12]GIFC3 (def=0x0) // Clear global interrupt flag of channel 3
-
[13]FTFIFC3 (def=0x0) // Clear bit for full transfer finish flag of channel 3
-
[14]HTFIFC3 (def=0x0) // Clear bit for half transfer finish flag of channel 3
-
[15]ERRIFC3 (def=0x0) // Clear bit for error flag of channel 3
-
[16]GIFC4 (def=0x0) // Clear global interrupt flag of channel 4
-
[17]FTFIFC4 (def=0x0) // Clear bit for full transfer finish flag of channel 4
-
[18]HTFIFC4 (def=0x0) // Clear bit for half transfer finish flag of channel 4
-
[19]ERRIFC4 (def=0x0) // Clear bit for error flag of channel 4
0x40020408CH0CTL// Channel 0 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x4002040CCH0CNT// Channel 0 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020410CH0PADDR// Channel 0 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40020414CH0MADDR// Channel 0 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x4002041CCH1CTL// Channel 1 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x40020420CH1CNT// Channel 1 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020424CH1PADDR// Channel 1 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40020428CH1MADDR// Channel 1 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x40020430CH2CTL// Channel 2 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x40020434CH2CNT// Channel 2 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020438CH2PADDR// Channel 2 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x4002043CCH2MADDR// Channel 2 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x40020444CH3CTL// Channel 3 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x40020448CH3CNT// Channel 3 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x4002044CCH3PADDR// Channel 3 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40020450CH3MADDR// Channel 3 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
0x40020458CH4CTL// Channel 4 control register
-
[0]CHEN (def=0x0) // Channel enable
-
[1]FTFIE (def=0x0) // Enable bit for channel full transfer finish interrupt
-
[2]HTFIE (def=0x0) // Enable bit for channel half transfer finish interrupt
-
[3]ERRIE (def=0x0) // Enable bit for channel error interrupt
-
[4]DIR (def=0x0) // Transfer direction
-
[5]CMEN (def=0x0) // Circular mode enable
-
[6]PNAGA (def=0x0) // Next address generation algorithm of peripheral
-
[7]MNAGA (def=0x0) // Next address generation algorithm of memory
-
[8:9]PWIDTH (def=0x0) // Transfer data size of peripheral
-
[10:11]MWIDTH (def=0x0) // Transfer data size of memory
-
[12:13]PRIO (def=0x0) // Priority level
-
[14]M2M (def=0x0) // Memory to Memory Mode
0x4002045CCH4CNT// Channel 4 counter register
-
[0:15]CNT (def=0x0) // Transfer counter
0x40020460CH4PADDR// Channel 4 peripheral base address register
-
[0:31]PADDR (def=0x0) // Peripheral base address
0x40020464CH4MADDR// Channel 4 memory base address register
-
[0:31]MADDR (def=0x0) // Memory base address
- [75] DMA1_Channel0 //
- [76] DMA1_Channel1 //
- [77] DMA1_Channel2 //
- [78] DMA1_Channel3 //
- [79] DMA1_Channel4 //
0xA0000000EXMC// External memory controller
0xA0000000SNCTL0// SRAM/NOR flash control register 0
-
[15]ASYNCWAIT (def=0x0) // Asynchronous wait
-
[13]NRWTEN (def=0x1) // NWAIT signal enable
-
[12]WREN (def=0x1) // Write enable
-
[9]NRWTPOL (def=0x0) // NWAIT signal polarity
-
[6]NREN (def=0x1) // NOR Flash access enable
-
[4:5]NRW (def=0x1) // NOR bank memory data bus width
-
[2:3]NRTP (def=0x2) // NOR bank memory type
-
[1]NRMUX (def=0x1) // NOR bank memory address/data multiplexing
-
[0]NRBKEN (def=0x0) // NOR bank enable
0xA0000004SNTCFG0// SRAM/NOR flash timing configuration register 0
-
[16:19]BUSLAT (def=0xF) // Bus latency
-
[8:15]DSET (def=0xFF) // Data setup time
-
[4:7]AHLD (def=0xF) // Address hold time
-
[0:3]ASET (def=0xF) // Address setup time
0xA0000008SNCTL1// SRAM/NOR flash control register 1
-
[15]ASYNCWAIT (def=0x0) // Asynchronous wait
-
[13]NRWTEN (def=0x1) // NWAIT signal enable
-
[12]WREN (def=0x1) // Write enable
-
[9]NRWTPOL (def=0x0) // NWAIT signal polarity
-
[6]NREN (def=0x1) // NOR Flash access enable
-
[4:5]NRW (def=0x1) // NOR bank memory data bus width
-
[2:3]NRTP (def=0x2) // NOR bank memory type
-
[1]NRMUX (def=0x1) // NOR bank memory address/data multiplexing
-
[0]NRBKEN (def=0x0) // NOR bank enable
0x40010400EXTI// External interrupt/event controller
0x40010400INTEN// Interrupt enable register (EXTI_INTEN)
-
[0]INTEN0 (def=0x0) // Enable Interrupt on line 0
-
[1]INTEN1 (def=0x0) // Enable Interrupt on line 1
-
[2]INTEN2 (def=0x0) // Enable Interrupt on line 2
-
[3]INTEN3 (def=0x0) // Enable Interrupt on line 3
-
[4]INTEN4 (def=0x0) // Enable Interrupt on line 4
-
[5]INTEN5 (def=0x0) // Enable Interrupt on line 5
-
[6]INTEN6 (def=0x0) // Enable Interrupt on line 6
-
[7]INTEN7 (def=0x0) // Enable Interrupt on line 7
-
[8]INTEN8 (def=0x0) // Enable Interrupt on line 8
-
[9]INTEN9 (def=0x0) // Enable Interrupt on line 9
-
[10]INTEN10 (def=0x0) // Enable Interrupt on line 10
-
[11]INTEN11 (def=0x0) // Enable Interrupt on line 11
-
[12]INTEN12 (def=0x0) // Enable Interrupt on line 12
-
[13]INTEN13 (def=0x0) // Enable Interrupt on line 13
-
[14]INTEN14 (def=0x0) // Enable Interrupt on line 14
-
[15]INTEN15 (def=0x0) // Enable Interrupt on line 15
-
[16]INTEN16 (def=0x0) // Enable Interrupt on line 16
-
[17]INTEN17 (def=0x0) // Enable Interrupt on line 17
-
[18]INTEN18 (def=0x0) // Enable Interrupt on line 18
0x40010404EVEN// Event enable register (EXTI_EVEN)
-
[0]EVEN0 (def=0x0) // Enable Event on line 0
-
[1]EVEN1 (def=0x0) // Enable Event on line 1
-
[2]EVEN2 (def=0x0) // Enable Event on line 2
-
[3]EVEN3 (def=0x0) // Enable Event on line 3
-
[4]EVEN4 (def=0x0) // Enable Event on line 4
-
[5]EVEN5 (def=0x0) // Enable Event on line 5
-
[6]EVEN6 (def=0x0) // Enable Event on line 6
-
[7]EVEN7 (def=0x0) // Enable Event on line 7
-
[8]EVEN8 (def=0x0) // Enable Event on line 8
-
[9]EVEN9 (def=0x0) // Enable Event on line 9
-
[10]EVEN10 (def=0x0) // Enable Event on line 10
-
[11]EVEN11 (def=0x0) // Enable Event on line 11
-
[12]EVEN12 (def=0x0) // Enable Event on line 12
-
[13]EVEN13 (def=0x0) // Enable Event on line 13
-
[14]EVEN14 (def=0x0) // Enable Event on line 14
-
[15]EVEN15 (def=0x0) // Enable Event on line 15
-
[16]EVEN16 (def=0x0) // Enable Event on line 16
-
[17]EVEN17 (def=0x0) // Enable Event on line 17
-
[18]EVEN18 (def=0x0) // Enable Event on line 18
0x40010408RTEN// Rising Edge Trigger Enable register (EXTI_RTEN)
-
[0]RTEN0 (def=0x0) // Rising edge trigger enable of line 0
-
[1]RTEN1 (def=0x0) // Rising edge trigger enable of line 1
-
[2]RTEN2 (def=0x0) // Rising edge trigger enable of line 2
-
[3]RTEN3 (def=0x0) // Rising edge trigger enable of line 3
-
[4]RTEN4 (def=0x0) // Rising edge trigger enable of line 4
-
[5]RTEN5 (def=0x0) // Rising edge trigger enable of line 5
-
[6]RTEN6 (def=0x0) // Rising edge trigger enable of line 6
-
[7]RTEN7 (def=0x0) // Rising edge trigger enable of line 7
-
[8]RTEN8 (def=0x0) // Rising edge trigger enable of line 8
-
[9]RTEN9 (def=0x0) // Rising edge trigger enable of line 9
-
[10]RTEN10 (def=0x0) // Rising edge trigger enable of line 10
-
[11]RTEN11 (def=0x0) // Rising edge trigger enable of line 11
-
[12]RTEN12 (def=0x0) // Rising edge trigger enable of line 12
-
[13]RTEN13 (def=0x0) // Rising edge trigger enable of line 13
-
[14]RTEN14 (def=0x0) // Rising edge trigger enable of line 14
-
[15]RTEN15 (def=0x0) // Rising edge trigger enable of line 15
-
[16]RTEN16 (def=0x0) // Rising edge trigger enable of line 16
-
[17]RTEN17 (def=0x0) // Rising edge trigger enable of line 17
-
[18]RTEN18 (def=0x0) // Rising edge trigger enable of line 18
0x4001040CFTEN// Falling Egde Trigger Enable register (EXTI_FTEN)
-
[0]FTEN0 (def=0x0) // Falling edge trigger enable of line 0
-
[1]FTEN1 (def=0x0) // Falling edge trigger enable of line 1
-
[2]FTEN2 (def=0x0) // Falling edge trigger enable of line 2
-
[3]FTEN3 (def=0x0) // Falling edge trigger enable of line 3
-
[4]FTEN4 (def=0x0) // Falling edge trigger enable of line 4
-
[5]FTEN5 (def=0x0) // Falling edge trigger enable of line 5
-
[6]FTEN6 (def=0x0) // Falling edge trigger enable of line 6
-
[7]FTEN7 (def=0x0) // Falling edge trigger enable of line 7
-
[8]FTEN8 (def=0x0) // Falling edge trigger enable of line 8
-
[9]FTEN9 (def=0x0) // Falling edge trigger enable of line 9
-
[10]FTEN10 (def=0x0) // Falling edge trigger enable of line 10
-
[11]FTEN11 (def=0x0) // Falling edge trigger enable of line 11
-
[12]FTEN12 (def=0x0) // Falling edge trigger enable of line 12
-
[13]FTEN13 (def=0x0) // Falling edge trigger enable of line 13
-
[14]FTEN14 (def=0x0) // Falling edge trigger enable of line 14
-
[15]FTEN15 (def=0x0) // Falling edge trigger enable of line 15
-
[16]FTEN16 (def=0x0) // Falling edge trigger enable of line 16
-
[17]FTEN17 (def=0x0) // Falling edge trigger enable of line 17
-
[18]FTEN18 (def=0x0) // Falling edge trigger enable of line 18
0x40010410SWIEV// Software interrupt event register (EXTI_SWIEV)
-
[0]SWIEV0 (def=0x0) // Interrupt/Event software trigger on line 0
-
[1]SWIEV1 (def=0x0) // Interrupt/Event software trigger on line 1
-
[2]SWIEV2 (def=0x0) // Interrupt/Event software trigger on line 2
-
[3]SWIEV3 (def=0x0) // Interrupt/Event software trigger on line 3
-
[4]SWIEV4 (def=0x0) // Interrupt/Event software trigger on line 4
-
[5]SWIEV5 (def=0x0) // Interrupt/Event software trigger on line 5
-
[6]SWIEV6 (def=0x0) // Interrupt/Event software trigger on line 6
-
[7]SWIEV7 (def=0x0) // Interrupt/Event software trigger on line 7
-
[8]SWIEV8 (def=0x0) // Interrupt/Event software trigger on line 8
-
[9]SWIEV9 (def=0x0) // Interrupt/Event software trigger on line 9
-
[10]SWIEV10 (def=0x0) // Interrupt/Event software trigger on line 10
-
[11]SWIEV11 (def=0x0) // Interrupt/Event software trigger on line 11
-
[12]SWIEV12 (def=0x0) // Interrupt/Event software trigger on line 12
-
[13]SWIEV13 (def=0x0) // Interrupt/Event software trigger on line 13
-
[14]SWIEV14 (def=0x0) // Interrupt/Event software trigger on line 14
-
[15]SWIEV15 (def=0x0) // Interrupt/Event software trigger on line 15
-
[16]SWIEV16 (def=0x0) // Interrupt/Event software trigger on line 16
-
[17]SWIEV17 (def=0x0) // Interrupt/Event software trigger on line 17
-
[18]SWIEV18 (def=0x0) // Interrupt/Event software trigger on line 18
0x40010414PD// Pending register (EXTI_PD)
-
[0]PD0 (def=0x0) // Interrupt pending status of line 0
-
[1]PD1 (def=0x0) // Interrupt pending status of line 1
-
[2]PD2 (def=0x0) // Interrupt pending status of line 2
-
[3]PD3 (def=0x0) // Interrupt pending status of line 3
-
[4]PD4 (def=0x0) // Interrupt pending status of line 4
-
[5]PD5 (def=0x0) // Interrupt pending status of line 5
-
[6]PD6 (def=0x0) // Interrupt pending status of line 6
-
[7]PD7 (def=0x0) // Interrupt pending status of line 7
-
[8]PD8 (def=0x0) // Interrupt pending status of line 8
-
[9]PD9 (def=0x0) // Interrupt pending status of line 9
-
[10]PD10 (def=0x0) // Interrupt pending status of line 10
-
[11]PD11 (def=0x0) // Interrupt pending status of line 11
-
[12]PD12 (def=0x0) // Interrupt pending status of line 12
-
[13]PD13 (def=0x0) // Interrupt pending status of line 13
-
[14]PD14 (def=0x0) // Interrupt pending status of line 14
-
[15]PD15 (def=0x0) // Interrupt pending status of line 15
-
[16]PD16 (def=0x0) // Interrupt pending status of line 16
-
[17]PD17 (def=0x0) // Interrupt pending status of line 17
-
[18]PD18 (def=0x0) // Interrupt pending status of line 18
- [25] EXTI_Line0 //
- [26] EXTI_Line1 //
- [27] EXTI_Line2 //
- [28] EXTI_Line3 //
- [29] EXTI_Line4 //
- [42] EXTI_line9_5 //
- [59] EXTI_line15_10 //
0x40022000FMC// FMC
0x40022000WS// wait state counter register
-
[0:2]WSCNT (def=0x0) // wait state counter register
0x40022004KEY0// Unlock key register 0
-
[0:31]KEY (def=0x0) // FMC_CTL0 unlock key
0x40022008OBKEY// Option byte unlock key register
-
[0:31]OBKEY (def=0x0) // FMC_ CTL0 option byte operation unlock register
0x4002200CSTAT0// Status register 0
-
[5]ENDF (def=0x0) // End of operation flag bit
-
[4]WPERR (def=0x0) // Erase/Program protection error flag bit
-
[2]PGERR (def=0x0) // Program error flag bit
-
[0]BUSY (def=0x0) // The flash is busy bit
0x40022010CTL0// Control register 0
-
[12]ENDIE (def=0x0) // End of operation interrupt enable bit
-
[10]ERRIE (def=0x0) // Error interrupt enable bit
-
[9]OBWEN (def=0x0) // Option byte erase/program enable bit
-
[7]LK (def=0x1) // FMC_CTL0 lock bit
-
[6]START (def=0x0) // Send erase command to FMC bit
-
[5]OBER (def=0x0) // Option bytes erase command bit
-
[4]OBPG (def=0x0) // Option bytes program command bit
-
[2]MER (def=0x0) // Main flash mass erase for bank0 command bit
-
[1]PER (def=0x0) // Main flash page erase for bank0 command bit
-
[0]PG (def=0x0) // Main flash program for bank0 command bit
0x40022014ADDR0// Address register 0
-
[0:31]ADDR (def=0x0) // Flash erase/program command address bits
0x4002201COBSTAT// Option byte status register
-
[0]OBERR (def=0x0) // Option bytes read error bit
-
[1]SPC (def=0x0) // Option bytes security protection code
-
[2:9]USER (def=0x0) // Store USER of option bytes block after system reset
-
[10:25]DATA (def=0x0) // Store DATA[15:0] of option bytes block after system reset
0x40022020WP// Erase/Program Protection register
-
[0:31]WP (def=0x0) // Store WP[31:0] of option bytes block after system reset
0x40022100PID// Product ID register
-
[0:31]PID (def=0x0) // Product reserved ID code register
0x40003000FWDGT// free watchdog timer
0x40003000CTL// Control register
-
[0:15]CMD (def=0x0) // Key value
0x40003004PSC// Prescaler register
-
[0:2]PSC (def=0x0) // Free watchdog timer prescaler selection
0x40003008RLD// Reload register
-
[0:11]RLD (def=0xFFF) // Free watchdog timer counter reload value
0x4000300CSTAT// Status register
-
[0]PUD (def=0x0) // Free watchdog timer prescaler value update
-
[1]RUD (def=0x0) // Free watchdog timer counter reload value update
0x40010800GPIOA// General-purpose I/Os
0x40010800CTL0// port control register 0
-
[30:31]CTL7 (def=0x1) // Port x configuration bits (x = 7)
-
[28:29]MD7 (def=0x0) // Port x mode bits (x = 7)
-
[26:27]CTL6 (def=0x1) // Port x configuration bits (x = 6)
-
[24:25]MD6 (def=0x0) // Port x mode bits (x = 6)
-
[22:23]CTL5 (def=0x1) // Port x configuration bits (x = 5)
-
[20:21]MD5 (def=0x0) // Port x mode bits (x = 5)
-
[18:19]CTL4 (def=0x1) // Port x configuration bits (x = 4)
-
[16:17]MD4 (def=0x0) // Port x mode bits (x = 4)
-
[14:15]CTL3 (def=0x1) // Port x configuration bits (x = 3)
-
[12:13]MD3 (def=0x0) // Port x mode bits (x = 3 )
-
[10:11]CTL2 (def=0x1) // Port x configuration bits (x = 2)
-
[8:9]MD2 (def=0x0) // Port x mode bits (x = 2 )
-
[6:7]CTL1 (def=0x1) // Port x configuration bits (x = 1)
-
[4:5]MD1 (def=0x0) // Port x mode bits (x = 1)
-
[2:3]CTL0 (def=0x1) // Port x configuration bits (x = 0)
-
[0:1]MD0 (def=0x0) // Port x mode bits (x = 0)
0x40010804CTL1// port control register 1
-
[30:31]CTL15 (def=0x1) // Port x configuration bits (x = 15)
-
[28:29]MD15 (def=0x0) // Port x mode bits (x = 15)
-
[26:27]CTL14 (def=0x1) // Port x configuration bits (x = 14)
-
[24:25]MD14 (def=0x0) // Port x mode bits (x = 14)
-
[22:23]CTL13 (def=0x1) // Port x configuration bits (x = 13)
-
[20:21]MD13 (def=0x0) // Port x mode bits (x = 13)
-
[18:19]CTL12 (def=0x1) // Port x configuration bits (x = 12)
-
[16:17]MD12 (def=0x0) // Port x mode bits (x = 12)
-
[14:15]CTL11 (def=0x1) // Port x configuration bits (x = 11)
-
[12:13]MD11 (def=0x0) // Port x mode bits (x = 11 )
-
[10:11]CTL10 (def=0x1) // Port x configuration bits (x = 10)
-
[8:9]MD10 (def=0x0) // Port x mode bits (x = 10 )
-
[6:7]CTL9 (def=0x1) // Port x configuration bits (x = 9)
-
[4:5]MD9 (def=0x0) // Port x mode bits (x = 9)
-
[2:3]CTL8 (def=0x1) // Port x configuration bits (x = 8)
-
[0:1]MD8 (def=0x0) // Port x mode bits (x = 8)
0x40010808ISTAT// Port input status register
-
[15]ISTAT15 (def=0x0) // Port input status
-
[14]ISTAT14 (def=0x0) // Port input status
-
[13]ISTAT13 (def=0x0) // Port input status
-
[12]ISTAT12 (def=0x0) // Port input status
-
[11]ISTAT11 (def=0x0) // Port input status
-
[10]ISTAT10 (def=0x0) // Port input status
-
[9]ISTAT9 (def=0x0) // Port input status
-
[8]ISTAT8 (def=0x0) // Port input status
-
[7]ISTAT7 (def=0x0) // Port input status
-
[6]ISTAT6 (def=0x0) // Port input status
-
[5]ISTAT5 (def=0x0) // Port input status
-
[4]ISTAT4 (def=0x0) // Port input status
-
[3]ISTAT3 (def=0x0) // Port input status
-
[2]ISTAT2 (def=0x0) // Port input status
-
[1]ISTAT1 (def=0x0) // Port input status
-
[0]ISTAT0 (def=0x0) // Port input status
0x4001080COCTL// Port output control register
-
[15]OCTL15 (def=0x0) // Port output control
-
[14]OCTL14 (def=0x0) // Port output control
-
[13]OCTL13 (def=0x0) // Port output control
-
[12]OCTL12 (def=0x0) // Port output control
-
[11]OCTL11 (def=0x0) // Port output control
-
[10]OCTL10 (def=0x0) // Port output control
-
[9]OCTL9 (def=0x0) // Port output control
-
[8]OCTL8 (def=0x0) // Port output control
-
[7]OCTL7 (def=0x0) // Port output control
-
[6]OCTL6 (def=0x0) // Port output control
-
[5]OCTL5 (def=0x0) // Port output control
-
[4]OCTL4 (def=0x0) // Port output control
-
[3]OCTL3 (def=0x0) // Port output control
-
[2]OCTL2 (def=0x0) // Port output control
-
[1]OCTL1 (def=0x0) // Port output control
-
[0]OCTL0 (def=0x0) // Port output control
0x40010810BOP// Port bit operate register
-
[31]CR15 (def=0x0) // Port 15 Clear bit
-
[30]CR14 (def=0x0) // Port 14 Clear bit
-
[29]CR13 (def=0x0) // Port 13 Clear bit
-
[28]CR12 (def=0x0) // Port 12 Clear bit
-
[27]CR11 (def=0x0) // Port 11 Clear bit
-
[26]CR10 (def=0x0) // Port 10 Clear bit
-
[25]CR9 (def=0x0) // Port 9 Clear bit
-
[24]CR8 (def=0x0) // Port 8 Clear bit
-
[23]CR7 (def=0x0) // Port 7 Clear bit
-
[22]CR6 (def=0x0) // Port 6 Clear bit
-
[21]CR5 (def=0x0) // Port 5 Clear bit
-
[20]CR4 (def=0x0) // Port 4 Clear bit
-
[19]CR3 (def=0x0) // Port 3 Clear bit
-
[18]CR2 (def=0x0) // Port 2 Clear bit
-
[17]CR1 (def=0x0) // Port 1 Clear bit
-
[16]CR0 (def=0x0) // Port 0 Clear bit
-
[15]BOP15 (def=0x0) // Port 15 Set bit
-
[14]BOP14 (def=0x0) // Port 14 Set bit
-
[13]BOP13 (def=0x0) // Port 13 Set bit
-
[12]BOP12 (def=0x0) // Port 12 Set bit
-
[11]BOP11 (def=0x0) // Port 11 Set bit
-
[10]BOP10 (def=0x0) // Port 10 Set bit
-
[9]BOP9 (def=0x0) // Port 9 Set bit
-
[8]BOP8 (def=0x0) // Port 8 Set bit
-
[7]BOP7 (def=0x0) // Port 7 Set bit
-
[6]BOP6 (def=0x0) // Port 6 Set bit
-
[5]BOP5 (def=0x0) // Port 5 Set bit
-
[4]BOP4 (def=0x0) // Port 4 Set bit
-
[3]BOP3 (def=0x0) // Port 3 Set bit
-
[2]BOP2 (def=0x0) // Port 2 Set bit
-
[1]BOP1 (def=0x0) // Port 1 Set bit
-
[0]BOP0 (def=0x0) // Port 0 Set bit
0x40010814BC// Port bit clear register
-
[15]CR15 (def=0x0) // Port 15 Clear bit
-
[14]CR14 (def=0x0) // Port 14 Clear bit
-
[13]CR13 (def=0x0) // Port 13 Clear bit
-
[12]CR12 (def=0x0) // Port 12 Clear bit
-
[11]CR11 (def=0x0) // Port 11 Clear bit
-
[10]CR10 (def=0x0) // Port 10 Clear bit
-
[9]CR9 (def=0x0) // Port 9 Clear bit
-
[8]CR8 (def=0x0) // Port 8 Clear bit
-
[7]CR7 (def=0x0) // Port 7 Clear bit
-
[6]CR6 (def=0x0) // Port 6 Clear bit
-
[5]CR5 (def=0x0) // Port 5 Clear bit
-
[4]CR4 (def=0x0) // Port 4 Clear bit
-
[3]CR3 (def=0x0) // Port 3 Clear bit
-
[2]CR2 (def=0x0) // Port 2 Clear bit
-
[1]CR1 (def=0x0) // Port 1 Clear bit
-
[0]CR0 (def=0x0) // Port 0 Clear bit
0x40010818LOCK// GPIO port configuration lock register
-
[16]LKK (def=0x0) // Lock sequence key
-
[15]LK15 (def=0x0) // Port Lock bit 15
-
[14]LK14 (def=0x0) // Port Lock bit 14
-
[13]LK13 (def=0x0) // Port Lock bit 13
-
[12]LK12 (def=0x0) // Port Lock bit 12
-
[11]LK11 (def=0x0) // Port Lock bit 11
-
[10]LK10 (def=0x0) // Port Lock bit 10
-
[9]LK9 (def=0x0) // Port Lock bit 9
-
[8]LK8 (def=0x0) // Port Lock bit 8
-
[7]LK7 (def=0x0) // Port Lock bit 7
-
[6]LK6 (def=0x0) // Port Lock bit 6
-
[5]LK5 (def=0x0) // Port Lock bit 5
-
[4]LK4 (def=0x0) // Port Lock bit 4
-
[3]LK3 (def=0x0) // Port Lock bit 3
-
[2]LK2 (def=0x0) // Port Lock bit 2
-
[1]LK1 (def=0x0) // Port Lock bit 1
-
[0]LK0 (def=0x0) // Port Lock bit 0
0x40010C00GPIOB//
0x40010C00CTL0// port control register 0
-
[30:31]CTL7 (def=0x1) // Port x configuration bits (x = 7)
-
[28:29]MD7 (def=0x0) // Port x mode bits (x = 7)
-
[26:27]CTL6 (def=0x1) // Port x configuration bits (x = 6)
-
[24:25]MD6 (def=0x0) // Port x mode bits (x = 6)
-
[22:23]CTL5 (def=0x1) // Port x configuration bits (x = 5)
-
[20:21]MD5 (def=0x0) // Port x mode bits (x = 5)
-
[18:19]CTL4 (def=0x1) // Port x configuration bits (x = 4)
-
[16:17]MD4 (def=0x0) // Port x mode bits (x = 4)
-
[14:15]CTL3 (def=0x1) // Port x configuration bits (x = 3)
-
[12:13]MD3 (def=0x0) // Port x mode bits (x = 3 )
-
[10:11]CTL2 (def=0x1) // Port x configuration bits (x = 2)
-
[8:9]MD2 (def=0x0) // Port x mode bits (x = 2 )
-
[6:7]CTL1 (def=0x1) // Port x configuration bits (x = 1)
-
[4:5]MD1 (def=0x0) // Port x mode bits (x = 1)
-
[2:3]CTL0 (def=0x1) // Port x configuration bits (x = 0)
-
[0:1]MD0 (def=0x0) // Port x mode bits (x = 0)
0x40010C04CTL1// port control register 1
-
[30:31]CTL15 (def=0x1) // Port x configuration bits (x = 15)
-
[28:29]MD15 (def=0x0) // Port x mode bits (x = 15)
-
[26:27]CTL14 (def=0x1) // Port x configuration bits (x = 14)
-
[24:25]MD14 (def=0x0) // Port x mode bits (x = 14)
-
[22:23]CTL13 (def=0x1) // Port x configuration bits (x = 13)
-
[20:21]MD13 (def=0x0) // Port x mode bits (x = 13)
-
[18:19]CTL12 (def=0x1) // Port x configuration bits (x = 12)
-
[16:17]MD12 (def=0x0) // Port x mode bits (x = 12)
-
[14:15]CTL11 (def=0x1) // Port x configuration bits (x = 11)
-
[12:13]MD11 (def=0x0) // Port x mode bits (x = 11 )
-
[10:11]CTL10 (def=0x1) // Port x configuration bits (x = 10)
-
[8:9]MD10 (def=0x0) // Port x mode bits (x = 10 )
-
[6:7]CTL9 (def=0x1) // Port x configuration bits (x = 9)
-
[4:5]MD9 (def=0x0) // Port x mode bits (x = 9)
-
[2:3]CTL8 (def=0x1) // Port x configuration bits (x = 8)
-
[0:1]MD8 (def=0x0) // Port x mode bits (x = 8)
0x40010C08ISTAT// Port input status register
-
[15]ISTAT15 (def=0x0) // Port input status
-
[14]ISTAT14 (def=0x0) // Port input status
-
[13]ISTAT13 (def=0x0) // Port input status
-
[12]ISTAT12 (def=0x0) // Port input status
-
[11]ISTAT11 (def=0x0) // Port input status
-
[10]ISTAT10 (def=0x0) // Port input status
-
[9]ISTAT9 (def=0x0) // Port input status
-
[8]ISTAT8 (def=0x0) // Port input status
-
[7]ISTAT7 (def=0x0) // Port input status
-
[6]ISTAT6 (def=0x0) // Port input status
-
[5]ISTAT5 (def=0x0) // Port input status
-
[4]ISTAT4 (def=0x0) // Port input status
-
[3]ISTAT3 (def=0x0) // Port input status
-
[2]ISTAT2 (def=0x0) // Port input status
-
[1]ISTAT1 (def=0x0) // Port input status
-
[0]ISTAT0 (def=0x0) // Port input status
0x40010C0COCTL// Port output control register
-
[15]OCTL15 (def=0x0) // Port output control
-
[14]OCTL14 (def=0x0) // Port output control
-
[13]OCTL13 (def=0x0) // Port output control
-
[12]OCTL12 (def=0x0) // Port output control
-
[11]OCTL11 (def=0x0) // Port output control
-
[10]OCTL10 (def=0x0) // Port output control
-
[9]OCTL9 (def=0x0) // Port output control
-
[8]OCTL8 (def=0x0) // Port output control
-
[7]OCTL7 (def=0x0) // Port output control
-
[6]OCTL6 (def=0x0) // Port output control
-
[5]OCTL5 (def=0x0) // Port output control
-
[4]OCTL4 (def=0x0) // Port output control
-
[3]OCTL3 (def=0x0) // Port output control
-
[2]OCTL2 (def=0x0) // Port output control
-
[1]OCTL1 (def=0x0) // Port output control
-
[0]OCTL0 (def=0x0) // Port output control
0x40010C10BOP// Port bit operate register
-
[31]CR15 (def=0x0) // Port 15 Clear bit
-
[30]CR14 (def=0x0) // Port 14 Clear bit
-
[29]CR13 (def=0x0) // Port 13 Clear bit
-
[28]CR12 (def=0x0) // Port 12 Clear bit
-
[27]CR11 (def=0x0) // Port 11 Clear bit
-
[26]CR10 (def=0x0) // Port 10 Clear bit
-
[25]CR9 (def=0x0) // Port 9 Clear bit
-
[24]CR8 (def=0x0) // Port 8 Clear bit
-
[23]CR7 (def=0x0) // Port 7 Clear bit
-
[22]CR6 (def=0x0) // Port 6 Clear bit
-
[21]CR5 (def=0x0) // Port 5 Clear bit
-
[20]CR4 (def=0x0) // Port 4 Clear bit
-
[19]CR3 (def=0x0) // Port 3 Clear bit
-
[18]CR2 (def=0x0) // Port 2 Clear bit
-
[17]CR1 (def=0x0) // Port 1 Clear bit
-
[16]CR0 (def=0x0) // Port 0 Clear bit
-
[15]BOP15 (def=0x0) // Port 15 Set bit
-
[14]BOP14 (def=0x0) // Port 14 Set bit
-
[13]BOP13 (def=0x0) // Port 13 Set bit
-
[12]BOP12 (def=0x0) // Port 12 Set bit
-
[11]BOP11 (def=0x0) // Port 11 Set bit
-
[10]BOP10 (def=0x0) // Port 10 Set bit
-
[9]BOP9 (def=0x0) // Port 9 Set bit
-
[8]BOP8 (def=0x0) // Port 8 Set bit
-
[7]BOP7 (def=0x0) // Port 7 Set bit
-
[6]BOP6 (def=0x0) // Port 6 Set bit
-
[5]BOP5 (def=0x0) // Port 5 Set bit
-
[4]BOP4 (def=0x0) // Port 4 Set bit
-
[3]BOP3 (def=0x0) // Port 3 Set bit
-
[2]BOP2 (def=0x0) // Port 2 Set bit
-
[1]BOP1 (def=0x0) // Port 1 Set bit
-
[0]BOP0 (def=0x0) // Port 0 Set bit
0x40010C14BC// Port bit clear register
-
[15]CR15 (def=0x0) // Port 15 Clear bit
-
[14]CR14 (def=0x0) // Port 14 Clear bit
-
[13]CR13 (def=0x0) // Port 13 Clear bit
-
[12]CR12 (def=0x0) // Port 12 Clear bit
-
[11]CR11 (def=0x0) // Port 11 Clear bit
-
[10]CR10 (def=0x0) // Port 10 Clear bit
-
[9]CR9 (def=0x0) // Port 9 Clear bit
-
[8]CR8 (def=0x0) // Port 8 Clear bit
-
[7]CR7 (def=0x0) // Port 7 Clear bit
-
[6]CR6 (def=0x0) // Port 6 Clear bit
-
[5]CR5 (def=0x0) // Port 5 Clear bit
-
[4]CR4 (def=0x0) // Port 4 Clear bit
-
[3]CR3 (def=0x0) // Port 3 Clear bit
-
[2]CR2 (def=0x0) // Port 2 Clear bit
-
[1]CR1 (def=0x0) // Port 1 Clear bit
-
[0]CR0 (def=0x0) // Port 0 Clear bit
0x40010C18LOCK// GPIO port configuration lock register
-
[16]LKK (def=0x0) // Lock sequence key
-
[15]LK15 (def=0x0) // Port Lock bit 15
-
[14]LK14 (def=0x0) // Port Lock bit 14
-
[13]LK13 (def=0x0) // Port Lock bit 13
-
[12]LK12 (def=0x0) // Port Lock bit 12
-
[11]LK11 (def=0x0) // Port Lock bit 11
-
[10]LK10 (def=0x0) // Port Lock bit 10
-
[9]LK9 (def=0x0) // Port Lock bit 9
-
[8]LK8 (def=0x0) // Port Lock bit 8
-
[7]LK7 (def=0x0) // Port Lock bit 7
-
[6]LK6 (def=0x0) // Port Lock bit 6
-
[5]LK5 (def=0x0) // Port Lock bit 5
-
[4]LK4 (def=0x0) // Port Lock bit 4
-
[3]LK3 (def=0x0) // Port Lock bit 3
-
[2]LK2 (def=0x0) // Port Lock bit 2
-
[1]LK1 (def=0x0) // Port Lock bit 1
-
[0]LK0 (def=0x0) // Port Lock bit 0
0x40011000GPIOC//
0x40011000CTL0// port control register 0
-
[30:31]CTL7 (def=0x1) // Port x configuration bits (x = 7)
-
[28:29]MD7 (def=0x0) // Port x mode bits (x = 7)
-
[26:27]CTL6 (def=0x1) // Port x configuration bits (x = 6)
-
[24:25]MD6 (def=0x0) // Port x mode bits (x = 6)
-
[22:23]CTL5 (def=0x1) // Port x configuration bits (x = 5)
-
[20:21]MD5 (def=0x0) // Port x mode bits (x = 5)
-
[18:19]CTL4 (def=0x1) // Port x configuration bits (x = 4)
-
[16:17]MD4 (def=0x0) // Port x mode bits (x = 4)
-
[14:15]CTL3 (def=0x1) // Port x configuration bits (x = 3)
-
[12:13]MD3 (def=0x0) // Port x mode bits (x = 3 )
-
[10:11]CTL2 (def=0x1) // Port x configuration bits (x = 2)
-
[8:9]MD2 (def=0x0) // Port x mode bits (x = 2 )
-
[6:7]CTL1 (def=0x1) // Port x configuration bits (x = 1)
-
[4:5]MD1 (def=0x0) // Port x mode bits (x = 1)
-
[2:3]CTL0 (def=0x1) // Port x configuration bits (x = 0)
-
[0:1]MD0 (def=0x0) // Port x mode bits (x = 0)
0x40011004CTL1// port control register 1
-
[30:31]CTL15 (def=0x1) // Port x configuration bits (x = 15)
-
[28:29]MD15 (def=0x0) // Port x mode bits (x = 15)
-
[26:27]CTL14 (def=0x1) // Port x configuration bits (x = 14)
-
[24:25]MD14 (def=0x0) // Port x mode bits (x = 14)
-
[22:23]CTL13 (def=0x1) // Port x configuration bits (x = 13)
-
[20:21]MD13 (def=0x0) // Port x mode bits (x = 13)
-
[18:19]CTL12 (def=0x1) // Port x configuration bits (x = 12)
-
[16:17]MD12 (def=0x0) // Port x mode bits (x = 12)
-
[14:15]CTL11 (def=0x1) // Port x configuration bits (x = 11)
-
[12:13]MD11 (def=0x0) // Port x mode bits (x = 11 )
-
[10:11]CTL10 (def=0x1) // Port x configuration bits (x = 10)
-
[8:9]MD10 (def=0x0) // Port x mode bits (x = 10 )
-
[6:7]CTL9 (def=0x1) // Port x configuration bits (x = 9)
-
[4:5]MD9 (def=0x0) // Port x mode bits (x = 9)
-
[2:3]CTL8 (def=0x1) // Port x configuration bits (x = 8)
-
[0:1]MD8 (def=0x0) // Port x mode bits (x = 8)
0x40011008ISTAT// Port input status register
-
[15]ISTAT15 (def=0x0) // Port input status
-
[14]ISTAT14 (def=0x0) // Port input status
-
[13]ISTAT13 (def=0x0) // Port input status
-
[12]ISTAT12 (def=0x0) // Port input status
-
[11]ISTAT11 (def=0x0) // Port input status
-
[10]ISTAT10 (def=0x0) // Port input status
-
[9]ISTAT9 (def=0x0) // Port input status
-
[8]ISTAT8 (def=0x0) // Port input status
-
[7]ISTAT7 (def=0x0) // Port input status
-
[6]ISTAT6 (def=0x0) // Port input status
-
[5]ISTAT5 (def=0x0) // Port input status
-
[4]ISTAT4 (def=0x0) // Port input status
-
[3]ISTAT3 (def=0x0) // Port input status
-
[2]ISTAT2 (def=0x0) // Port input status
-
[1]ISTAT1 (def=0x0) // Port input status
-
[0]ISTAT0 (def=0x0) // Port input status
0x4001100COCTL// Port output control register
-
[15]OCTL15 (def=0x0) // Port output control
-
[14]OCTL14 (def=0x0) // Port output control
-
[13]OCTL13 (def=0x0) // Port output control
-
[12]OCTL12 (def=0x0) // Port output control
-
[11]OCTL11 (def=0x0) // Port output control
-
[10]OCTL10 (def=0x0) // Port output control
-
[9]OCTL9 (def=0x0) // Port output control
-
[8]OCTL8 (def=0x0) // Port output control
-
[7]OCTL7 (def=0x0) // Port output control
-
[6]OCTL6 (def=0x0) // Port output control
-
[5]OCTL5 (def=0x0) // Port output control
-
[4]OCTL4 (def=0x0) // Port output control
-
[3]OCTL3 (def=0x0) // Port output control
-
[2]OCTL2 (def=0x0) // Port output control
-
[1]OCTL1 (def=0x0) // Port output control
-
[0]OCTL0 (def=0x0) // Port output control
0x40011010BOP// Port bit operate register
-
[31]CR15 (def=0x0) // Port 15 Clear bit
-
[30]CR14 (def=0x0) // Port 14 Clear bit
-
[29]CR13 (def=0x0) // Port 13 Clear bit
-
[28]CR12 (def=0x0) // Port 12 Clear bit
-
[27]CR11 (def=0x0) // Port 11 Clear bit
-
[26]CR10 (def=0x0) // Port 10 Clear bit
-
[25]CR9 (def=0x0) // Port 9 Clear bit
-
[24]CR8 (def=0x0) // Port 8 Clear bit
-
[23]CR7 (def=0x0) // Port 7 Clear bit
-
[22]CR6 (def=0x0) // Port 6 Clear bit
-
[21]CR5 (def=0x0) // Port 5 Clear bit
-
[20]CR4 (def=0x0) // Port 4 Clear bit
-
[19]CR3 (def=0x0) // Port 3 Clear bit
-
[18]CR2 (def=0x0) // Port 2 Clear bit
-
[17]CR1 (def=0x0) // Port 1 Clear bit
-
[16]CR0 (def=0x0) // Port 0 Clear bit
-
[15]BOP15 (def=0x0) // Port 15 Set bit
-
[14]BOP14 (def=0x0) // Port 14 Set bit
-
[13]BOP13 (def=0x0) // Port 13 Set bit
-
[12]BOP12 (def=0x0) // Port 12 Set bit
-
[11]BOP11 (def=0x0) // Port 11 Set bit
-
[10]BOP10 (def=0x0) // Port 10 Set bit
-
[9]BOP9 (def=0x0) // Port 9 Set bit
-
[8]BOP8 (def=0x0) // Port 8 Set bit
-
[7]BOP7 (def=0x0) // Port 7 Set bit
-
[6]BOP6 (def=0x0) // Port 6 Set bit
-
[5]BOP5 (def=0x0) // Port 5 Set bit
-
[4]BOP4 (def=0x0) // Port 4 Set bit
-
[3]BOP3 (def=0x0) // Port 3 Set bit
-
[2]BOP2 (def=0x0) // Port 2 Set bit
-
[1]BOP1 (def=0x0) // Port 1 Set bit
-
[0]BOP0 (def=0x0) // Port 0 Set bit
0x40011014BC// Port bit clear register
-
[15]CR15 (def=0x0) // Port 15 Clear bit
-
[14]CR14 (def=0x0) // Port 14 Clear bit
-
[13]CR13 (def=0x0) // Port 13 Clear bit
-
[12]CR12 (def=0x0) // Port 12 Clear bit
-
[11]CR11 (def=0x0) // Port 11 Clear bit
-
[10]CR10 (def=0x0) // Port 10 Clear bit
-
[9]CR9 (def=0x0) // Port 9 Clear bit
-
[8]CR8 (def=0x0) // Port 8 Clear bit
-
[7]CR7 (def=0x0) // Port 7 Clear bit
-
[6]CR6 (def=0x0) // Port 6 Clear bit
-
[5]CR5 (def=0x0) // Port 5 Clear bit
-
[4]CR4 (def=0x0) // Port 4 Clear bit
-
[3]CR3 (def=0x0) // Port 3 Clear bit
-
[2]CR2 (def=0x0) // Port 2 Clear bit
-
[1]CR1 (def=0x0) // Port 1 Clear bit
-
[0]CR0 (def=0x0) // Port 0 Clear bit
0x40011018LOCK// GPIO port configuration lock register
-
[16]LKK (def=0x0) // Lock sequence key
-
[15]LK15 (def=0x0) // Port Lock bit 15
-
[14]LK14 (def=0x0) // Port Lock bit 14
-
[13]LK13 (def=0x0) // Port Lock bit 13
-
[12]LK12 (def=0x0) // Port Lock bit 12
-
[11]LK11 (def=0x0) // Port Lock bit 11
-
[10]LK10 (def=0x0) // Port Lock bit 10
-
[9]LK9 (def=0x0) // Port Lock bit 9
-
[8]LK8 (def=0x0) // Port Lock bit 8
-
[7]LK7 (def=0x0) // Port Lock bit 7
-
[6]LK6 (def=0x0) // Port Lock bit 6
-
[5]LK5 (def=0x0) // Port Lock bit 5
-
[4]LK4 (def=0x0) // Port Lock bit 4
-
[3]LK3 (def=0x0) // Port Lock bit 3
-
[2]LK2 (def=0x0) // Port Lock bit 2
-
[1]LK1 (def=0x0) // Port Lock bit 1
-
[0]LK0 (def=0x0) // Port Lock bit 0
0x40011400GPIOD//
0x40011400CTL0// port control register 0
-
[30:31]CTL7 (def=0x1) // Port x configuration bits (x = 7)
-
[28:29]MD7 (def=0x0) // Port x mode bits (x = 7)
-
[26:27]CTL6 (def=0x1) // Port x configuration bits (x = 6)
-
[24:25]MD6 (def=0x0) // Port x mode bits (x = 6)
-
[22:23]CTL5 (def=0x1) // Port x configuration bits (x = 5)
-
[20:21]MD5 (def=0x0) // Port x mode bits (x = 5)
-
[18:19]CTL4 (def=0x1) // Port x configuration bits (x = 4)
-
[16:17]MD4 (def=0x0) // Port x mode bits (x = 4)
-
[14:15]CTL3 (def=0x1) // Port x configuration bits (x = 3)
-
[12:13]MD3 (def=0x0) // Port x mode bits (x = 3 )
-
[10:11]CTL2 (def=0x1) // Port x configuration bits (x = 2)
-
[8:9]MD2 (def=0x0) // Port x mode bits (x = 2 )
-
[6:7]CTL1 (def=0x1) // Port x configuration bits (x = 1)
-
[4:5]MD1 (def=0x0) // Port x mode bits (x = 1)
-
[2:3]CTL0 (def=0x1) // Port x configuration bits (x = 0)
-
[0:1]MD0 (def=0x0) // Port x mode bits (x = 0)
0x40011404CTL1// port control register 1
-
[30:31]CTL15 (def=0x1) // Port x configuration bits (x = 15)
-
[28:29]MD15 (def=0x0) // Port x mode bits (x = 15)
-
[26:27]CTL14 (def=0x1) // Port x configuration bits (x = 14)
-
[24:25]MD14 (def=0x0) // Port x mode bits (x = 14)
-
[22:23]CTL13 (def=0x1) // Port x configuration bits (x = 13)
-
[20:21]MD13 (def=0x0) // Port x mode bits (x = 13)
-
[18:19]CTL12 (def=0x1) // Port x configuration bits (x = 12)
-
[16:17]MD12 (def=0x0) // Port x mode bits (x = 12)
-
[14:15]CTL11 (def=0x1) // Port x configuration bits (x = 11)
-
[12:13]MD11 (def=0x0) // Port x mode bits (x = 11 )
-
[10:11]CTL10 (def=0x1) // Port x configuration bits (x = 10)
-
[8:9]MD10 (def=0x0) // Port x mode bits (x = 10 )
-
[6:7]CTL9 (def=0x1) // Port x configuration bits (x = 9)
-
[4:5]MD9 (def=0x0) // Port x mode bits (x = 9)
-
[2:3]CTL8 (def=0x1) // Port x configuration bits (x = 8)
-
[0:1]MD8 (def=0x0) // Port x mode bits (x = 8)
0x40011408ISTAT// Port input status register
-
[15]ISTAT15 (def=0x0) // Port input status
-
[14]ISTAT14 (def=0x0) // Port input status
-
[13]ISTAT13 (def=0x0) // Port input status
-
[12]ISTAT12 (def=0x0) // Port input status
-
[11]ISTAT11 (def=0x0) // Port input status
-
[10]ISTAT10 (def=0x0) // Port input status
-
[9]ISTAT9 (def=0x0) // Port input status
-
[8]ISTAT8 (def=0x0) // Port input status
-
[7]ISTAT7 (def=0x0) // Port input status
-
[6]ISTAT6 (def=0x0) // Port input status
-
[5]ISTAT5 (def=0x0) // Port input status
-
[4]ISTAT4 (def=0x0) // Port input status
-
[3]ISTAT3 (def=0x0) // Port input status
-
[2]ISTAT2 (def=0x0) // Port input status
-
[1]ISTAT1 (def=0x0) // Port input status
-
[0]ISTAT0 (def=0x0) // Port input status
0x4001140COCTL// Port output control register
-
[15]OCTL15 (def=0x0) // Port output control
-
[14]OCTL14 (def=0x0) // Port output control
-
[13]OCTL13 (def=0x0) // Port output control
-
[12]OCTL12 (def=0x0) // Port output control
-
[11]OCTL11 (def=0x0) // Port output control
-
[10]OCTL10 (def=0x0) // Port output control
-
[9]OCTL9 (def=0x0) // Port output control
-
[8]OCTL8 (def=0x0) // Port output control
-
[7]OCTL7 (def=0x0) // Port output control
-
[6]OCTL6 (def=0x0) // Port output control
-
[5]OCTL5 (def=0x0) // Port output control
-
[4]OCTL4 (def=0x0) // Port output control
-
[3]OCTL3 (def=0x0) // Port output control
-
[2]OCTL2 (def=0x0) // Port output control
-
[1]OCTL1 (def=0x0) // Port output control
-
[0]OCTL0 (def=0x0) // Port output control
0x40011410BOP// Port bit operate register
-
[31]CR15 (def=0x0) // Port 15 Clear bit
-
[30]CR14 (def=0x0) // Port 14 Clear bit
-
[29]CR13 (def=0x0) // Port 13 Clear bit
-
[28]CR12 (def=0x0) // Port 12 Clear bit
-
[27]CR11 (def=0x0) // Port 11 Clear bit
-
[26]CR10 (def=0x0) // Port 10 Clear bit
-
[25]CR9 (def=0x0) // Port 9 Clear bit
-
[24]CR8 (def=0x0) // Port 8 Clear bit
-
[23]CR7 (def=0x0) // Port 7 Clear bit
-
[22]CR6 (def=0x0) // Port 6 Clear bit
-
[21]CR5 (def=0x0) // Port 5 Clear bit
-
[20]CR4 (def=0x0) // Port 4 Clear bit
-
[19]CR3 (def=0x0) // Port 3 Clear bit
-
[18]CR2 (def=0x0) // Port 2 Clear bit
-
[17]CR1 (def=0x0) // Port 1 Clear bit
-
[16]CR0 (def=0x0) // Port 0 Clear bit
-
[15]BOP15 (def=0x0) // Port 15 Set bit
-
[14]BOP14 (def=0x0) // Port 14 Set bit
-
[13]BOP13 (def=0x0) // Port 13 Set bit
-
[12]BOP12 (def=0x0) // Port 12 Set bit
-
[11]BOP11 (def=0x0) // Port 11 Set bit
-
[10]BOP10 (def=0x0) // Port 10 Set bit
-
[9]BOP9 (def=0x0) // Port 9 Set bit
-
[8]BOP8 (def=0x0) // Port 8 Set bit
-
[7]BOP7 (def=0x0) // Port 7 Set bit
-
[6]BOP6 (def=0x0) // Port 6 Set bit
-
[5]BOP5 (def=0x0) // Port 5 Set bit
-
[4]BOP4 (def=0x0) // Port 4 Set bit
-
[3]BOP3 (def=0x0) // Port 3 Set bit
-
[2]BOP2 (def=0x0) // Port 2 Set bit
-
[1]BOP1 (def=0x0) // Port 1 Set bit
-
[0]BOP0 (def=0x0) // Port 0 Set bit
0x40011414BC// Port bit clear register
-
[15]CR15 (def=0x0) // Port 15 Clear bit
-
[14]CR14 (def=0x0) // Port 14 Clear bit
-
[13]CR13 (def=0x0) // Port 13 Clear bit
-
[12]CR12 (def=0x0) // Port 12 Clear bit
-
[11]CR11 (def=0x0) // Port 11 Clear bit
-
[10]CR10 (def=0x0) // Port 10 Clear bit
-
[9]CR9 (def=0x0) // Port 9 Clear bit
-
[8]CR8 (def=0x0) // Port 8 Clear bit
-
[7]CR7 (def=0x0) // Port 7 Clear bit
-
[6]CR6 (def=0x0) // Port 6 Clear bit
-
[5]CR5 (def=0x0) // Port 5 Clear bit
-
[4]CR4 (def=0x0) // Port 4 Clear bit
-
[3]CR3 (def=0x0) // Port 3 Clear bit
-
[2]CR2 (def=0x0) // Port 2 Clear bit
-
[1]CR1 (def=0x0) // Port 1 Clear bit
-
[0]CR0 (def=0x0) // Port 0 Clear bit
0x40011418LOCK// GPIO port configuration lock register
-
[16]LKK (def=0x0) // Lock sequence key
-
[15]LK15 (def=0x0) // Port Lock bit 15
-
[14]LK14 (def=0x0) // Port Lock bit 14
-
[13]LK13 (def=0x0) // Port Lock bit 13
-
[12]LK12 (def=0x0) // Port Lock bit 12
-
[11]LK11 (def=0x0) // Port Lock bit 11
-
[10]LK10 (def=0x0) // Port Lock bit 10
-
[9]LK9 (def=0x0) // Port Lock bit 9
-
[8]LK8 (def=0x0) // Port Lock bit 8
-
[7]LK7 (def=0x0) // Port Lock bit 7
-
[6]LK6 (def=0x0) // Port Lock bit 6
-
[5]LK5 (def=0x0) // Port Lock bit 5
-
[4]LK4 (def=0x0) // Port Lock bit 4
-
[3]LK3 (def=0x0) // Port Lock bit 3
-
[2]LK2 (def=0x0) // Port Lock bit 2
-
[1]LK1 (def=0x0) // Port Lock bit 1
-
[0]LK0 (def=0x0) // Port Lock bit 0
0x40011800GPIOE//
0x40011800CTL0// port control register 0
-
[30:31]CTL7 (def=0x1) // Port x configuration bits (x = 7)
-
[28:29]MD7 (def=0x0) // Port x mode bits (x = 7)
-
[26:27]CTL6 (def=0x1) // Port x configuration bits (x = 6)
-
[24:25]MD6 (def=0x0) // Port x mode bits (x = 6)
-
[22:23]CTL5 (def=0x1) // Port x configuration bits (x = 5)
-
[20:21]MD5 (def=0x0) // Port x mode bits (x = 5)
-
[18:19]CTL4 (def=0x1) // Port x configuration bits (x = 4)
-
[16:17]MD4 (def=0x0) // Port x mode bits (x = 4)
-
[14:15]CTL3 (def=0x1) // Port x configuration bits (x = 3)
-
[12:13]MD3 (def=0x0) // Port x mode bits (x = 3 )
-
[10:11]CTL2 (def=0x1) // Port x configuration bits (x = 2)
-
[8:9]MD2 (def=0x0) // Port x mode bits (x = 2 )
-
[6:7]CTL1 (def=0x1) // Port x configuration bits (x = 1)
-
[4:5]MD1 (def=0x0) // Port x mode bits (x = 1)
-
[2:3]CTL0 (def=0x1) // Port x configuration bits (x = 0)
-
[0:1]MD0 (def=0x0) // Port x mode bits (x = 0)
0x40011804CTL1// port control register 1
-
[30:31]CTL15 (def=0x1) // Port x configuration bits (x = 15)
-
[28:29]MD15 (def=0x0) // Port x mode bits (x = 15)
-
[26:27]CTL14 (def=0x1) // Port x configuration bits (x = 14)
-
[24:25]MD14 (def=0x0) // Port x mode bits (x = 14)
-
[22:23]CTL13 (def=0x1) // Port x configuration bits (x = 13)
-
[20:21]MD13 (def=0x0) // Port x mode bits (x = 13)
-
[18:19]CTL12 (def=0x1) // Port x configuration bits (x = 12)
-
[16:17]MD12 (def=0x0) // Port x mode bits (x = 12)
-
[14:15]CTL11 (def=0x1) // Port x configuration bits (x = 11)
-
[12:13]MD11 (def=0x0) // Port x mode bits (x = 11 )
-
[10:11]CTL10 (def=0x1) // Port x configuration bits (x = 10)
-
[8:9]MD10 (def=0x0) // Port x mode bits (x = 10 )
-
[6:7]CTL9 (def=0x1) // Port x configuration bits (x = 9)
-
[4:5]MD9 (def=0x0) // Port x mode bits (x = 9)
-
[2:3]CTL8 (def=0x1) // Port x configuration bits (x = 8)
-
[0:1]MD8 (def=0x0) // Port x mode bits (x = 8)
0x40011808ISTAT// Port input status register
-
[15]ISTAT15 (def=0x0) // Port input status
-
[14]ISTAT14 (def=0x0) // Port input status
-
[13]ISTAT13 (def=0x0) // Port input status
-
[12]ISTAT12 (def=0x0) // Port input status
-
[11]ISTAT11 (def=0x0) // Port input status
-
[10]ISTAT10 (def=0x0) // Port input status
-
[9]ISTAT9 (def=0x0) // Port input status
-
[8]ISTAT8 (def=0x0) // Port input status
-
[7]ISTAT7 (def=0x0) // Port input status
-
[6]ISTAT6 (def=0x0) // Port input status
-
[5]ISTAT5 (def=0x0) // Port input status
-
[4]ISTAT4 (def=0x0) // Port input status
-
[3]ISTAT3 (def=0x0) // Port input status
-
[2]ISTAT2 (def=0x0) // Port input status
-
[1]ISTAT1 (def=0x0) // Port input status
-
[0]ISTAT0 (def=0x0) // Port input status
0x4001180COCTL// Port output control register
-
[15]OCTL15 (def=0x0) // Port output control
-
[14]OCTL14 (def=0x0) // Port output control
-
[13]OCTL13 (def=0x0) // Port output control
-
[12]OCTL12 (def=0x0) // Port output control
-
[11]OCTL11 (def=0x0) // Port output control
-
[10]OCTL10 (def=0x0) // Port output control
-
[9]OCTL9 (def=0x0) // Port output control
-
[8]OCTL8 (def=0x0) // Port output control
-
[7]OCTL7 (def=0x0) // Port output control
-
[6]OCTL6 (def=0x0) // Port output control
-
[5]OCTL5 (def=0x0) // Port output control
-
[4]OCTL4 (def=0x0) // Port output control
-
[3]OCTL3 (def=0x0) // Port output control
-
[2]OCTL2 (def=0x0) // Port output control
-
[1]OCTL1 (def=0x0) // Port output control
-
[0]OCTL0 (def=0x0) // Port output control
0x40011810BOP// Port bit operate register
-
[31]CR15 (def=0x0) // Port 15 Clear bit
-
[30]CR14 (def=0x0) // Port 14 Clear bit
-
[29]CR13 (def=0x0) // Port 13 Clear bit
-
[28]CR12 (def=0x0) // Port 12 Clear bit
-
[27]CR11 (def=0x0) // Port 11 Clear bit
-
[26]CR10 (def=0x0) // Port 10 Clear bit
-
[25]CR9 (def=0x0) // Port 9 Clear bit
-
[24]CR8 (def=0x0) // Port 8 Clear bit
-
[23]CR7 (def=0x0) // Port 7 Clear bit
-
[22]CR6 (def=0x0) // Port 6 Clear bit
-
[21]CR5 (def=0x0) // Port 5 Clear bit
-
[20]CR4 (def=0x0) // Port 4 Clear bit
-
[19]CR3 (def=0x0) // Port 3 Clear bit
-
[18]CR2 (def=0x0) // Port 2 Clear bit
-
[17]CR1 (def=0x0) // Port 1 Clear bit
-
[16]CR0 (def=0x0) // Port 0 Clear bit
-
[15]BOP15 (def=0x0) // Port 15 Set bit
-
[14]BOP14 (def=0x0) // Port 14 Set bit
-
[13]BOP13 (def=0x0) // Port 13 Set bit
-
[12]BOP12 (def=0x0) // Port 12 Set bit
-
[11]BOP11 (def=0x0) // Port 11 Set bit
-
[10]BOP10 (def=0x0) // Port 10 Set bit
-
[9]BOP9 (def=0x0) // Port 9 Set bit
-
[8]BOP8 (def=0x0) // Port 8 Set bit
-
[7]BOP7 (def=0x0) // Port 7 Set bit
-
[6]BOP6 (def=0x0) // Port 6 Set bit
-
[5]BOP5 (def=0x0) // Port 5 Set bit
-
[4]BOP4 (def=0x0) // Port 4 Set bit
-
[3]BOP3 (def=0x0) // Port 3 Set bit
-
[2]BOP2 (def=0x0) // Port 2 Set bit
-
[1]BOP1 (def=0x0) // Port 1 Set bit
-
[0]BOP0 (def=0x0) // Port 0 Set bit
0x40011814BC// Port bit clear register
-
[15]CR15 (def=0x0) // Port 15 Clear bit
-
[14]CR14 (def=0x0) // Port 14 Clear bit
-
[13]CR13 (def=0x0) // Port 13 Clear bit
-
[12]CR12 (def=0x0) // Port 12 Clear bit
-
[11]CR11 (def=0x0) // Port 11 Clear bit
-
[10]CR10 (def=0x0) // Port 10 Clear bit
-
[9]CR9 (def=0x0) // Port 9 Clear bit
-
[8]CR8 (def=0x0) // Port 8 Clear bit
-
[7]CR7 (def=0x0) // Port 7 Clear bit
-
[6]CR6 (def=0x0) // Port 6 Clear bit
-
[5]CR5 (def=0x0) // Port 5 Clear bit
-
[4]CR4 (def=0x0) // Port 4 Clear bit
-
[3]CR3 (def=0x0) // Port 3 Clear bit
-
[2]CR2 (def=0x0) // Port 2 Clear bit
-
[1]CR1 (def=0x0) // Port 1 Clear bit
-
[0]CR0 (def=0x0) // Port 0 Clear bit
0x40011818LOCK// GPIO port configuration lock register
-
[16]LKK (def=0x0) // Lock sequence key
-
[15]LK15 (def=0x0) // Port Lock bit 15
-
[14]LK14 (def=0x0) // Port Lock bit 14
-
[13]LK13 (def=0x0) // Port Lock bit 13
-
[12]LK12 (def=0x0) // Port Lock bit 12
-
[11]LK11 (def=0x0) // Port Lock bit 11
-
[10]LK10 (def=0x0) // Port Lock bit 10
-
[9]LK9 (def=0x0) // Port Lock bit 9
-
[8]LK8 (def=0x0) // Port Lock bit 8
-
[7]LK7 (def=0x0) // Port Lock bit 7
-
[6]LK6 (def=0x0) // Port Lock bit 6
-
[5]LK5 (def=0x0) // Port Lock bit 5
-
[4]LK4 (def=0x0) // Port Lock bit 4
-
[3]LK3 (def=0x0) // Port Lock bit 3
-
[2]LK2 (def=0x0) // Port Lock bit 2
-
[1]LK1 (def=0x0) // Port Lock bit 1
-
[0]LK0 (def=0x0) // Port Lock bit 0
0x40005400I2C0// Inter integrated circuit
0x40005400CTL0// Control register 0
-
[15]SRESET (def=0x0) // Software reset
-
[13]SALT (def=0x0) // SMBus alert
-
[12]PECTRANS (def=0x0) // PEC Transfer
-
[11]POAP (def=0x0) // Position of ACK and PEC when receiving
-
[10]ACKEN (def=0x0) // Whether or not to send an ACK
-
[9]STOP (def=0x0) // Generate a STOP condition on I2C bus
-
[8]START (def=0x0) // Generate a START condition on I2C bus
-
[7]SS (def=0x0) // Whether to stretch SCL low when data is not ready in slave mode
-
[6]GCEN (def=0x0) // Whether or not to response to a General Call (0x00)
-
[5]PECEN (def=0x0) // PEC Calculation Switch
-
[4]ARPEN (def=0x0) // ARP protocol in SMBus switch
-
[3]SMBSEL (def=0x0) // SMBusType Selection
-
[1]SMBEN (def=0x0) // SMBus/I2C mode switch
-
[0]I2CEN (def=0x0) // I2C peripheral enable
0x40005404CTL1// Control register 1
-
[12]DMALST (def=0x0) // Flag indicating DMA last transfer
-
[11]DMAON (def=0x0) // DMA mode switch
-
[10]BUFIE (def=0x0) // Buffer interrupt enable
-
[9]EVIE (def=0x0) // Event interrupt enable
-
[8]ERRIE (def=0x0) // Error interrupt enable
-
[0:5]I2CCLK (def=0x0) // I2C Peripheral clock frequency
0x40005408SADDR0// Slave address register 0
-
[15]ADDFORMAT (def=0x0) // Address mode for the I2C slave
-
[8:9]ADDRESS9_8 (def=0x0) // Highest two bits of a 10-bit address
-
[1:7]ADDRESS7_1 (def=0x0) // 7-bit address or bits 7:1 of a 10-bit address
-
[0]ADDRESS0 (def=0x0) // Bit 0 of a 10-bit address
0x4000540CSADDR1// Slave address register 1
-
[1:7]ADDRESS2 (def=0x0) // Second I2C address for the slave in Dual-Address mode
-
[0]DUADEN (def=0x0) // Dual-Address mode switch
0x40005410DATA// Transfer buffer register
-
[0:7]TRB (def=0x0) // Transmission or reception data buffer register
0x40005414STAT0// Transfer status register 0
-
[15]SMBALT (def=0x0) // SMBus Alert status
-
[14]SMBTO (def=0x0) // Timeout signal in SMBus mode
-
[12]PECERR (def=0x0) // PEC error when receiving data
-
[11]OUERR (def=0x0) // Over-run or under-run situation occurs in slave mode
-
[10]AERR (def=0x0) // Acknowledge error
-
[9]LOSTARB (def=0x0) // Arbitration Lost in master mode
-
[8]BERR (def=0x0) // A bus error occurs indication a unexpected START or STOP condition on I2C bus
-
[7]TBE (def=0x0) // I2C_DATA is Empty during transmitting
-
[6]RBNE (def=0x0) // I2C_DATA is not Empty during receiving
-
[4]STPDET (def=0x0) // STOP condition detected in slave mode
-
[3]ADD10SEND (def=0x0) // Header of 10-bit address is sent in master mode
-
[2]BTC (def=0x0) // Byte transmission completed
-
[1]ADDSEND (def=0x0) // Address is sent in master mode or received and matches in slave mode
-
[0]SBSEND (def=0x0) // START condition sent out in master mode
0x40005418STAT1// Transfer status register 1
-
[8:15]PECV (def=0x0) // Packet Error Checking Value that calculated by hardware when PEC is enabled
-
[7]DUMODF (def=0x0) // Dual Flag in slave mode
-
[6]HSTSMB (def=0x0) // SMBus Host Header detected in slave mode
-
[5]DEFSMB (def=0x0) // Default address of SMBusDevice
-
[4]RXGC (def=0x0) // General call address (00h) received
-
[2]TR (def=0x0) // Whether the I2C is a transmitter or a receiver
-
[1]I2CBSY (def=0x0) // Busy flag
-
[0]MASTER (def=0x0) // A flag indicating whether I2C block is in master or slave mode
0x4000541CCKCFG// Clock configure register
-
[15]FAST (def=0x0) // I2C speed selection in master mode
-
[14]DTCY (def=0x0) // Duty cycle in fast mode
-
[0:11]CLKC (def=0x0) // I2C Clock control in master mode
0x40005420RT// Rise time register
-
[0:5]RISETIME (def=0x2) // Maximum rise time in master mode
- [50] I2C0_EV //
- [51] I2C0_ER //
0x40005800I2C1//
0x40005800CTL0// Control register 0
-
[15]SRESET (def=0x0) // Software reset
-
[13]SALT (def=0x0) // SMBus alert
-
[12]PECTRANS (def=0x0) // PEC Transfer
-
[11]POAP (def=0x0) // Position of ACK and PEC when receiving
-
[10]ACKEN (def=0x0) // Whether or not to send an ACK
-
[9]STOP (def=0x0) // Generate a STOP condition on I2C bus
-
[8]START (def=0x0) // Generate a START condition on I2C bus
-
[7]SS (def=0x0) // Whether to stretch SCL low when data is not ready in slave mode
-
[6]GCEN (def=0x0) // Whether or not to response to a General Call (0x00)
-
[5]PECEN (def=0x0) // PEC Calculation Switch
-
[4]ARPEN (def=0x0) // ARP protocol in SMBus switch
-
[3]SMBSEL (def=0x0) // SMBusType Selection
-
[1]SMBEN (def=0x0) // SMBus/I2C mode switch
-
[0]I2CEN (def=0x0) // I2C peripheral enable
0x40005804CTL1// Control register 1
-
[12]DMALST (def=0x0) // Flag indicating DMA last transfer
-
[11]DMAON (def=0x0) // DMA mode switch
-
[10]BUFIE (def=0x0) // Buffer interrupt enable
-
[9]EVIE (def=0x0) // Event interrupt enable
-
[8]ERRIE (def=0x0) // Error interrupt enable
-
[0:5]I2CCLK (def=0x0) // I2C Peripheral clock frequency
0x40005808SADDR0// Slave address register 0
-
[15]ADDFORMAT (def=0x0) // Address mode for the I2C slave
-
[8:9]ADDRESS9_8 (def=0x0) // Highest two bits of a 10-bit address
-
[1:7]ADDRESS7_1 (def=0x0) // 7-bit address or bits 7:1 of a 10-bit address
-
[0]ADDRESS0 (def=0x0) // Bit 0 of a 10-bit address
0x4000580CSADDR1// Slave address register 1
-
[1:7]ADDRESS2 (def=0x0) // Second I2C address for the slave in Dual-Address mode
-
[0]DUADEN (def=0x0) // Dual-Address mode switch
0x40005810DATA// Transfer buffer register
-
[0:7]TRB (def=0x0) // Transmission or reception data buffer register
0x40005814STAT0// Transfer status register 0
-
[15]SMBALT (def=0x0) // SMBus Alert status
-
[14]SMBTO (def=0x0) // Timeout signal in SMBus mode
-
[12]PECERR (def=0x0) // PEC error when receiving data
-
[11]OUERR (def=0x0) // Over-run or under-run situation occurs in slave mode
-
[10]AERR (def=0x0) // Acknowledge error
-
[9]LOSTARB (def=0x0) // Arbitration Lost in master mode
-
[8]BERR (def=0x0) // A bus error occurs indication a unexpected START or STOP condition on I2C bus
-
[7]TBE (def=0x0) // I2C_DATA is Empty during transmitting
-
[6]RBNE (def=0x0) // I2C_DATA is not Empty during receiving
-
[4]STPDET (def=0x0) // STOP condition detected in slave mode
-
[3]ADD10SEND (def=0x0) // Header of 10-bit address is sent in master mode
-
[2]BTC (def=0x0) // Byte transmission completed
-
[1]ADDSEND (def=0x0) // Address is sent in master mode or received and matches in slave mode
-
[0]SBSEND (def=0x0) // START condition sent out in master mode
0x40005818STAT1// Transfer status register 1
-
[8:15]PECV (def=0x0) // Packet Error Checking Value that calculated by hardware when PEC is enabled
-
[7]DUMODF (def=0x0) // Dual Flag in slave mode
-
[6]HSTSMB (def=0x0) // SMBus Host Header detected in slave mode
-
[5]DEFSMB (def=0x0) // Default address of SMBusDevice
-
[4]RXGC (def=0x0) // General call address (00h) received
-
[2]TR (def=0x0) // Whether the I2C is a transmitter or a receiver
-
[1]I2CBSY (def=0x0) // Busy flag
-
[0]MASTER (def=0x0) // A flag indicating whether I2C block is in master or slave mode
0x4000581CCKCFG// Clock configure register
-
[15]FAST (def=0x0) // I2C speed selection in master mode
-
[14]DTCY (def=0x0) // Duty cycle in fast mode
-
[0:11]CLKC (def=0x0) // I2C Clock control in master mode
0x40005820RT// Rise time register
-
[0:5]RISETIME (def=0x2) // Maximum rise time in master mode
- [52] I2C1_EV //
- [53] I2C1_ER //
0xD2000000ECLIC// Enhanced Core Local Interrupt Controller
0xD2000000CLICCFG// cliccfg Register
-
[1:4]NLBITS (def=0x0) // NLBITS
0xD2000004CLICINFO// clicinfo Register
-
[0:12]NUM_INTERRUPT (def=0x0) // NUM_INTERRUPT
-
[13:20]VERSION (def=0x0) // VERSION
-
[21:24]CLICINTCTLBITS (def=0x0) // CLICINTCTLBITS
0xD200000BMTH// MTH Register
-
[0:7]MTH (def=0x0) // MTH
0xD2001000CLICINTIP_0// clicintip Register
0xD2001004CLICINTIP_1// clicintip Register
0xD2001008CLICINTIP_2// clicintip Register
0xD200100CCLICINTIP_3// clicintip Register
0xD2001010CLICINTIP_4// clicintip Register
0xD2001014CLICINTIP_5// clicintip Register
0xD2001018CLICINTIP_6// clicintip Register
0xD200101CCLICINTIP_7// clicintip Register
0xD2001020CLICINTIP_8// clicintip Register
0xD2001024CLICINTIP_9// clicintip Register
0xD2001028CLICINTIP_10// clicintip Register
0xD200102CCLICINTIP_11// clicintip Register
0xD2001030CLICINTIP_12// clicintip Register
0xD2001034CLICINTIP_13// clicintip Register
0xD2001038CLICINTIP_14// clicintip Register
0xD200103CCLICINTIP_15// clicintip Register
0xD2001040CLICINTIP_16// clicintip Register
0xD2001044CLICINTIP_17// clicintip Register
0xD2001048CLICINTIP_18// clicintip Register
0xD200104CCLICINTIP_19// clicintip Register
0xD2001050CLICINTIP_20// clicintip Register
0xD2001054CLICINTIP_21// clicintip Register
0xD2001058CLICINTIP_22// clicintip Register
0xD200105CCLICINTIP_23// clicintip Register
0xD2001060CLICINTIP_24// clicintip Register
0xD2001064CLICINTIP_25// clicintip Register
0xD2001068CLICINTIP_26// clicintip Register
0xD200106CCLICINTIP_27// clicintip Register
0xD2001070CLICINTIP_28// clicintip Register
0xD2001074CLICINTIP_29// clicintip Register
0xD2001078CLICINTIP_30// clicintip Register
0xD200107CCLICINTIP_31// clicintip Register
0xD2001080CLICINTIP_32// clicintip Register
0xD2001084CLICINTIP_33// clicintip Register
0xD2001088CLICINTIP_34// clicintip Register
0xD200108CCLICINTIP_35// clicintip Register
0xD2001090CLICINTIP_36// clicintip Register
0xD2001094CLICINTIP_37// clicintip Register
0xD2001098CLICINTIP_38// clicintip Register
0xD200109CCLICINTIP_39// clicintip Register
0xD20010A0CLICINTIP_40// clicintip Register
0xD20010A4CLICINTIP_41// clicintip Register
0xD20010A8CLICINTIP_42// clicintip Register
0xD20010ACCLICINTIP_43// clicintip Register
0xD20010B0CLICINTIP_44// clicintip Register
0xD20010B4CLICINTIP_45// clicintip Register
0xD20010B8CLICINTIP_46// clicintip Register
0xD20010BCCLICINTIP_47// clicintip Register
0xD20010C0CLICINTIP_48// clicintip Register
0xD20010C4CLICINTIP_49// clicintip Register
0xD20010C8CLICINTIP_50// clicintip Register
0xD20010CCCLICINTIP_51// clicintip Register
0xD20010D0CLICINTIP_52// clicintip Register
0xD20010D4CLICINTIP_53// clicintip Register
0xD20010D8CLICINTIP_54// clicintip Register
0xD20010DCCLICINTIP_55// clicintip Register
0xD20010E0CLICINTIP_56// clicintip Register
0xD20010E4CLICINTIP_57// clicintip Register
0xD20010E8CLICINTIP_58// clicintip Register
0xD20010ECCLICINTIP_59// clicintip Register
0xD20010F0CLICINTIP_60// clicintip Register
0xD20010F4CLICINTIP_61// clicintip Register
0xD20010F8CLICINTIP_62// clicintip Register
0xD20010FCCLICINTIP_63// clicintip Register
0xD2001100CLICINTIP_64// clicintip Register
0xD2001104CLICINTIP_65// clicintip Register
0xD2001108CLICINTIP_66// clicintip Register
0xD200110CCLICINTIP_67// clicintip Register
0xD2001110CLICINTIP_68// clicintip Register
0xD2001114CLICINTIP_69// clicintip Register
0xD2001118CLICINTIP_70// clicintip Register
0xD200111CCLICINTIP_71// clicintip Register
0xD2001120CLICINTIP_72// clicintip Register
0xD2001124CLICINTIP_73// clicintip Register
0xD2001128CLICINTIP_74// clicintip Register
0xD200112CCLICINTIP_75// clicintip Register
0xD2001130CLICINTIP_76// clicintip Register
0xD2001134CLICINTIP_77// clicintip Register
0xD2001138CLICINTIP_78// clicintip Register
0xD200113CCLICINTIP_79// clicintip Register
0xD2001140CLICINTIP_80// clicintip Register
0xD2001144CLICINTIP_81// clicintip Register
0xD2001148CLICINTIP_82// clicintip Register
0xD200114CCLICINTIP_83// clicintip Register
0xD2001150CLICINTIP_84// clicintip Register
0xD2001158CLICINTIP_85// clicintip Register
0xD200115CCLICINTIP_86// clicintip Register
0xD2001001CLICINTIE_0// clicintie Register
0xD2001005CLICINTIE_1// clicintie Register
0xD2001009CLICINTIE_2// clicintie Register
0xD200100DCLICINTIE_3// clicintie Register
0xD2001011CLICINTIE_4// clicintie Register
0xD2001015CLICINTIE_5// clicintie Register
0xD2001019CLICINTIE_6// clicintie Register
0xD200101DCLICINTIE_7// clicintie Register
0xD2001021CLICINTIE_8// clicintie Register
0xD2001025CLICINTIE_9// clicintie Register
0xD2001029CLICINTIE_10// clicintie Register
0xD200102DCLICINTIE_11// clicintie Register
0xD2001031CLICINTIE_12// clicintie Register
0xD2001035CLICINTIE_13// clicintie Register
0xD2001039CLICINTIE_14// clicintie Register
0xD200103DCLICINTIE_15// clicintie Register
0xD2001041CLICINTIE_16// clicintie Register
0xD2001045CLICINTIE_17// clicintie Register
0xD2001049CLICINTIE_18// clicintie Register
0xD200104DCLICINTIE_19// clicintie Register
0xD2001051CLICINTIE_20// clicintie Register
0xD2001055CLICINTIE_21// clicintie Register
0xD2001059CLICINTIE_22// clicintie Register
0xD200105DCLICINTIE_23// clicintie Register
0xD2001061CLICINTIE_24// clicintie Register
0xD2001065CLICINTIE_25// clicintie Register
0xD2001069CLICINTIE_26// clicintie Register
0xD200106DCLICINTIE_27// clicintie Register
0xD2001071CLICINTIE_28// clicintie Register
0xD2001075CLICINTIE_29// clicintie Register
0xD2001079CLICINTIE_30// clicintie Register
0xD200107DCLICINTIE_31// clicintie Register
0xD2001081CLICINTIE_32// clicintie Register
0xD2001085CLICINTIE_33// clicintie Register
0xD2001089CLICINTIE_34// clicintie Register
0xD200108DCLICINTIE_35// clicintie Register
0xD2001091CLICINTIE_36// clicintie Register
0xD2001095CLICINTIE_37// clicintie Register
0xD2001099CLICINTIE_38// clicintie Register
0xD200109DCLICINTIE_39// clicintie Register
0xD20010A1CLICINTIE_40// clicintie Register
0xD20010A5CLICINTIE_41// clicintie Register
0xD20010A9CLICINTIE_42// clicintie Register
0xD20010ADCLICINTIE_43// clicintie Register
0xD20010B1CLICINTIE_44// clicintie Register
0xD20010B5CLICINTIE_45// clicintie Register
0xD20010B9CLICINTIE_46// clicintie Register
0xD20010BDCLICINTIE_47// clicintie Register
0xD20010C1CLICINTIE_48// clicintie Register
0xD20010C5CLICINTIE_49// clicintie Register
0xD20010C9CLICINTIE_50// clicintie Register
0xD20010CDCLICINTIE_51// clicintie Register
0xD20010D1CLICINTIE_52// clicintie Register
0xD20010D5CLICINTIE_53// clicintie Register
0xD20010D9CLICINTIE_54// clicintie Register
0xD20010DDCLICINTIE_55// clicintie Register
0xD20010E1CLICINTIE_56// clicintie Register
0xD20010E5CLICINTIE_57// clicintie Register
0xD20010E9CLICINTIE_58// clicintie Register
0xD20010EDCLICINTIE_59// clicintie Register
0xD20010F1CLICINTIE_60// clicintie Register
0xD20010F5CLICINTIE_61// clicintie Register
0xD20010F9CLICINTIE_62// clicintie Register
0xD20010FDCLICINTIE_63// clicintie Register
0xD2001101CLICINTIE_64// clicintie Register
0xD2001105CLICINTIE_65// clicintie Register
0xD2001109CLICINTIE_66// clicintie Register
0xD200110DCLICINTIE_67// clicintie Register
0xD2001111CLICINTIE_68// clicintie Register
0xD2001115CLICINTIE_69// clicintie Register
0xD2001119CLICINTIE_70// clicintie Register
0xD200111DCLICINTIE_71// clicintie Register
0xD2001121CLICINTIE_72// clicintie Register
0xD2001125CLICINTIE_73// clicintie Register
0xD2001129CLICINTIE_74// clicintie Register
0xD200112DCLICINTIE_75// clicintie Register
0xD2001131CLICINTIE_76// clicintie Register
0xD2001135CLICINTIE_77// clicintie Register
0xD2001139CLICINTIE_78// clicintie Register
0xD200113DCLICINTIE_79// clicintie Register
0xD2001141CLICINTIE_80// clicintie Register
0xD2001145CLICINTIE_81// clicintie Register
0xD2001149CLICINTIE_82// clicintie Register
0xD200114DCLICINTIE_83// clicintie Register
0xD2001151CLICINTIE_84// clicintie Register
0xD2001155CLICINTIE_85// clicintie Register
0xD2001159CLICINTIE_86// clicintie Register
0xD2001002CLICINTATTR_0// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001006CLICINTATTR_1// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200100ACLICINTATTR_2// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200100ECLICINTATTR_3// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001012CLICINTATTR_4// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001016CLICINTATTR_5// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200101ACLICINTATTR_6// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200101ECLICINTATTR_7// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001022CLICINTATTR_8// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001026CLICINTATTR_9// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200102ACLICINTATTR_10// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200102ECLICINTATTR_11// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001032CLICINTATTR_12// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001036CLICINTATTR_13// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200103ACLICINTATTR_14// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200103ECLICINTATTR_15// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001042CLICINTATTR_16// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001046CLICINTATTR_17// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200104ACLICINTATTR_18// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200104ECLICINTATTR_19// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001052CLICINTATTR_20// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001056CLICINTATTR_21// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200105ACLICINTATTR_22// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200105ECLICINTATTR_23// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001062CLICINTATTR_24// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001066CLICINTATTR_25// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200106ACLICINTATTR_26// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200106ECLICINTATTR_27// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001072CLICINTATTR_28// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001076CLICINTATTR_29// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200107ACLICINTATTR_30// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200107ECLICINTATTR_31// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001082CLICINTATTR_32// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001086CLICINTATTR_33// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200108ACLICINTATTR_34// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200108ECLICINTATTR_35// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001092CLICINTATTR_36// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001096CLICINTATTR_37// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200109ACLICINTATTR_38// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200109ECLICINTATTR_39// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010A2CLICINTATTR_40// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010A6CLICINTATTR_41// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010AACLICINTATTR_42// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010AECLICINTATTR_43// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010B2CLICINTATTR_44// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010B6CLICINTATTR_45// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010BACLICINTATTR_46// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010BECLICINTATTR_47// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010C2CLICINTATTR_48// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010C6CLICINTATTR_49// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010CACLICINTATTR_50// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010CECLICINTATTR_51// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010D2CLICINTATTR_52// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010D6CLICINTATTR_53// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010DACLICINTATTR_54// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010DECLICINTATTR_55// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010E2CLICINTATTR_56// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010E6CLICINTATTR_57// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010EACLICINTATTR_58// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010EECLICINTATTR_59// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010F2CLICINTATTR_60// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010F6CLICINTATTR_61// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010FACLICINTATTR_62// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD20010FECLICINTATTR_63// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001102CLICINTATTR_64// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001106CLICINTATTR_65// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200110ACLICINTATTR_66// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200110ECLICINTATTR_67// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001112CLICINTATTR_68// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001116CLICINTATTR_69// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200111ACLICINTATTR_70// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200111ECLICINTATTR_71// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001122CLICINTATTR_72// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001126CLICINTATTR_73// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200112ACLICINTATTR_74// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200112ECLICINTATTR_75// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001132CLICINTATTR_76// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001136CLICINTATTR_77// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200113ACLICINTATTR_78// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200113ECLICINTATTR_79// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001142CLICINTATTR_80// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001146CLICINTATTR_81// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200114ACLICINTATTR_82// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200114ECLICINTATTR_83// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001152CLICINTATTR_84// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001156CLICINTATTR_85// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD200115ACLICINTATTR_86// clicintattr Register
-
[0]SHV (def=0x0) // SHV
-
[1:2]TRIG (def=0x0) // TRIG
0xD2001003CLICINTCTL_0// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001007CLICINTCTL_1// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200100BCLICINTCTL_2// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200100FCLICINTCTL_3// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001013CLICINTCTL_4// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001017CLICINTCTL_5// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200101BCLICINTCTL_6// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200101FCLICINTCTL_7// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001023CLICINTCTL_8// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001027CLICINTCTL_9// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200102BCLICINTCTL_10// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200102FCLICINTCTL_11// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001033CLICINTCTL_12// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001037CLICINTCTL_13// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200103BCLICINTCTL_14// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200103FCLICINTCTL_15// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001043CLICINTCTL_16// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001047CLICINTCTL_17// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200104BCLICINTCTL_18// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200104FCLICINTCTL_19// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001053CLICINTCTL_20// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001057CLICINTCTL_21// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200105BCLICINTCTL_22// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200105FCLICINTCTL_23// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001063CLICINTCTL_24// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001067CLICINTCTL_25// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200106BCLICINTCTL_26// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200106FCLICINTCTL_27// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001073CLICINTCTL_28// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001077CLICINTCTL_29// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200107BCLICINTCTL_30// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200107FCLICINTCTL_31// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001083CLICINTCTL_32// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001087CLICINTCTL_33// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200108BCLICINTCTL_34// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200108FCLICINTCTL_35// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001093CLICINTCTL_36// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001097CLICINTCTL_37// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200109BCLICINTCTL_38// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200109FCLICINTCTL_39// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010A3CLICINTCTL_40// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010A7CLICINTCTL_41// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010ABCLICINTCTL_42// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010AFCLICINTCTL_43// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010B3CLICINTCTL_44// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010B7CLICINTCTL_45// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010BBCLICINTCTL_46// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010BFCLICINTCTL_47// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010C3CLICINTCTL_48// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010C7CLICINTCTL_49// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010CBCLICINTCTL_50// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010CFCLICINTCTL_51// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010D3CLICINTCTL_52// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010D7CLICINTCTL_53// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010DBCLICINTCTL_54// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010DFCLICINTCTL_55// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010E3CLICINTCTL_56// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010E7CLICINTCTL_57// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010EBCLICINTCTL_58// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010EFCLICINTCTL_59// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010F3CLICINTCTL_60// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010F7CLICINTCTL_61// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010FBCLICINTCTL_62// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD20010FFCLICINTCTL_63// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001103CLICINTCTL_64// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001107CLICINTCTL_65// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200110BCLICINTCTL_66// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200110FCLICINTCTL_67// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001113CLICINTCTL_68// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001117CLICINTCTL_69// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200111BCLICINTCTL_70// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200111FCLICINTCTL_71// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001123CLICINTCTL_72// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001127CLICINTCTL_73// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200112BCLICINTCTL_74// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200112FCLICINTCTL_75// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001133CLICINTCTL_76// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001137CLICINTCTL_77// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200113BCLICINTCTL_78// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200113FCLICINTCTL_79// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001143CLICINTCTL_80// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001147CLICINTCTL_81// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200114BCLICINTCTL_82// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200114FCLICINTCTL_83// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001153CLICINTCTL_84// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD2001157CLICINTCTL_85// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0xD200115BCLICINTCTL_86// clicintctl Register
-
[0:7]LEVEL_PRIORITY (def=0x0) // LEVEL_PRIORITY
0x40007000PMU// Power management unit
0x40007000CTL// power control register
-
[8]BKPWEN (def=0x0) // Backup Domain Write Enable
-
[5:7]LVDT (def=0x0) // Low Voltage Detector Threshold
-
[4]LVDEN (def=0x0) // Low Voltage Detector Enable
-
[3]STBRST (def=0x0) // Standby Flag Reset
-
[2]WURST (def=0x0) // Wakeup Flag Reset
-
[1]STBMOD (def=0x0) // Standby Mode
-
[0]LDOLP (def=0x0) // LDO Low Power Mode
0x40007004CS// power control/status register
-
[8]WUPEN (def=0x0) // Enable WKUP pin
-
[2]LVDF (def=0x0) // Low Voltage Detector Status Flag
-
[1]STBF (def=0x0) // Standby flag
-
[0]WUF (def=0x0) // Wakeup flag
0x40021000RCU// Reset and clock unit
0x40021000CTL// Control register
-
[0]IRC8MEN (def=0x1) // Internal 8MHz RC oscillator Enable
-
[1]IRC8MSTB (def=0x1) // IRC8M Internal 8MHz RC Oscillator stabilization Flag
-
[3:7]IRC8MADJ (def=0x10) // Internal 8MHz RC Oscillator clock trim adjust value
-
[8:15]IRC8MCALIB (def=0x0) // Internal 8MHz RC Oscillator calibration value register
-
[16]HXTALEN (def=0x0) // External High Speed oscillator Enable
-
[17]HXTALSTB (def=0x0) // External crystal oscillator (HXTAL) clock stabilization flag
-
[18]HXTALBPS (def=0x0) // External crystal oscillator (HXTAL) clock bypass mode enable
-
[19]CKMEN (def=0x0) // HXTAL Clock Monitor Enable
-
[24]PLLEN (def=0x0) // PLL enable
-
[25]PLLSTB (def=0x0) // PLL Clock Stabilization Flag
-
[26]PLL1EN (def=0x0) // PLL1 enable
-
[27]PLL1STB (def=0x0) // PLL1 Clock Stabilization Flag
-
[28]PLL2EN (def=0x0) // PLL2 enable
-
[29]PLL2STB (def=0x0) // PLL2 Clock Stabilization Flag
0x40021004CFG0// Clock configuration register 0 (RCU_CFG0)
-
[0:1]SCS (def=0x0) // System clock switch
-
[2:3]SCSS (def=0x0) // System clock switch status
-
[4:7]AHBPSC (def=0x0) // AHB prescaler selection
-
[8:10]APB1PSC (def=0x0) // APB1 prescaler selection
-
[11:13]APB2PSC (def=0x0) // APB2 prescaler selection
-
[14:15]ADCPSC_1_0 (def=0x0) // ADC clock prescaler selection
-
[16]PLLSEL (def=0x0) // PLL Clock Source Selection
-
[17]PREDV0_LSB (def=0x0) // The LSB of PREDV0 division factor
-
[18:21]PLLMF_3_0 (def=0x0) // The PLL clock multiplication factor
-
[22:23]USBFSPSC (def=0x0) // USBFS clock prescaler selection
-
[24:27]CKOUT0SEL (def=0x0) // CKOUT0 Clock Source Selection
-
[28]ADCPSC_2 (def=0x0) // Bit 2 of ADCPSC
-
[29]PLLMF_4 (def=0x0) // Bit 4 of PLLMF
0x40021008INT// Clock interrupt register (RCU_INT)
-
[0]IRC40KSTBIF (def=0x0) // IRC40K stabilization interrupt flag
-
[1]LXTALSTBIF (def=0x0) // LXTAL stabilization interrupt flag
-
[2]IRC8MSTBIF (def=0x0) // IRC8M stabilization interrupt flag
-
[3]HXTALSTBIF (def=0x0) // HXTAL stabilization interrupt flag
-
[4]PLLSTBIF (def=0x0) // PLL stabilization interrupt flag
-
[5]PLL1STBIF (def=0x0) // PLL1 stabilization interrupt flag
-
[6]PLL2STBIF (def=0x0) // PLL2 stabilization interrupt flag
-
[7]CKMIF (def=0x0) // HXTAL Clock Stuck Interrupt Flag
-
[8]IRC40KSTBIE (def=0x0) // IRC40K Stabilization interrupt enable
-
[9]LXTALSTBIE (def=0x0) // LXTAL Stabilization Interrupt Enable
-
[10]IRC8MSTBIE (def=0x0) // IRC8M Stabilization Interrupt Enable
-
[11]HXTALSTBIE (def=0x0) // HXTAL Stabilization Interrupt Enable
-
[12]PLLSTBIE (def=0x0) // PLL Stabilization Interrupt Enable
-
[13]PLL1STBIE (def=0x0) // PLL1 Stabilization Interrupt Enable
-
[14]PLL2STBIE (def=0x0) // PLL2 Stabilization Interrupt Enable
-
[16]IRC40KSTBIC (def=0x0) // IRC40K Stabilization Interrupt Clear
-
[17]LXTALSTBIC (def=0x0) // LXTAL Stabilization Interrupt Clear
-
[18]IRC8MSTBIC (def=0x0) // IRC8M Stabilization Interrupt Clear
-
[19]HXTALSTBIC (def=0x0) // HXTAL Stabilization Interrupt Clear
-
[20]PLLSTBIC (def=0x0) // PLL stabilization Interrupt Clear
-
[21]PLL1STBIC (def=0x0) // PLL1 stabilization Interrupt Clear
-
[22]PLL2STBIC (def=0x0) // PLL2 stabilization Interrupt Clear
-
[23]CKMIC (def=0x0) // HXTAL Clock Stuck Interrupt Clear
0x4002100CAPB2RST// APB2 reset register (RCU_APB2RST)
-
[0]AFRST (def=0x0) // Alternate function I/O reset
-
[2]PARST (def=0x0) // GPIO port A reset
-
[3]PBRST (def=0x0) // GPIO port B reset
-
[4]PCRST (def=0x0) // GPIO port C reset
-
[5]PDRST (def=0x0) // GPIO port D reset
-
[6]PERST (def=0x0) // GPIO port E reset
-
[9]ADC0RST (def=0x0) // ADC0 reset
-
[10]ADC1RST (def=0x0) // ADC1 reset
-
[11]TIMER0RST (def=0x0) // Timer 0 reset
-
[12]SPI0RST (def=0x0) // SPI0 reset
-
[14]USART0RST (def=0x0) // USART0 Reset
0x40021010APB1RST// APB1 reset register (RCU_APB1RST)
-
[0]TIMER1RST (def=0x0) // TIMER1 timer reset
-
[1]TIMER2RST (def=0x0) // TIMER2 timer reset
-
[2]TIMER3RST (def=0x0) // TIMER3 timer reset
-
[3]TIMER4RST (def=0x0) // TIMER4 timer reset
-
[4]TIMER5RST (def=0x0) // TIMER5 timer reset
-
[5]TIMER6RST (def=0x0) // TIMER6 timer reset
-
[11]WWDGTRST (def=0x0) // Window watchdog timer reset
-
[14]SPI1RST (def=0x0) // SPI1 reset
-
[15]SPI2RST (def=0x0) // SPI2 reset
-
[17]USART1RST (def=0x0) // USART1 reset
-
[18]USART2RST (def=0x0) // USART2 reset
-
[19]UART3RST (def=0x0) // UART3 reset
-
[20]UART4RST (def=0x0) // UART4 reset
-
[21]I2C0RST (def=0x0) // I2C0 reset
-
[22]I2C1RST (def=0x0) // I2C1 reset
-
[25]CAN0RST (def=0x0) // CAN0 reset
-
[26]CAN1RST (def=0x0) // CAN1 reset
-
[27]BKPIRST (def=0x0) // Backup interface reset
-
[28]PMURST (def=0x0) // Power control reset
-
[29]DACRST (def=0x0) // DAC reset
0x40021014AHBEN// AHB enable register
-
[0]DMA0EN (def=0x0) // DMA0 clock enable
-
[1]DMA1EN (def=0x0) // DMA1 clock enable
-
[2]SRAMSPEN (def=0x1) // SRAM interface clock enable when sleep mode
-
[4]FMCSPEN (def=0x1) // FMC clock enable when sleep mode
-
[6]CRCEN (def=0x0) // CRC clock enable
-
[8]EXMCEN (def=0x0) // EXMC clock enable
-
[12]USBFSEN (def=0x0) // USBFS clock enable
0x40021018APB2EN// APB2 clock enable register (RCU_APB2EN)
-
[0]AFEN (def=0x0) // Alternate function IO clock enable
-
[2]PAEN (def=0x0) // GPIO port A clock enable
-
[3]PBEN (def=0x0) // GPIO port B clock enable
-
[4]PCEN (def=0x0) // GPIO port C clock enable
-
[5]PDEN (def=0x0) // GPIO port D clock enable
-
[6]PEEN (def=0x0) // GPIO port E clock enable
-
[9]ADC0EN (def=0x0) // ADC0 clock enable
-
[10]ADC1EN (def=0x0) // ADC1 clock enable
-
[11]TIMER0EN (def=0x0) // TIMER0 clock enable
-
[12]SPI0EN (def=0x0) // SPI0 clock enable
-
[14]USART0EN (def=0x0) // USART0 clock enable
0x4002101CAPB1EN// APB1 clock enable register (RCU_APB1EN)
-
[0]TIMER1EN (def=0x0) // TIMER1 timer clock enable
-
[1]TIMER2EN (def=0x0) // TIMER2 timer clock enable
-
[2]TIMER3EN (def=0x0) // TIMER3 timer clock enable
-
[3]TIMER4EN (def=0x0) // TIMER4 timer clock enable
-
[4]TIMER5EN (def=0x0) // TIMER5 timer clock enable
-
[5]TIMER6EN (def=0x0) // TIMER6 timer clock enable
-
[11]WWDGTEN (def=0x0) // Window watchdog timer clock enable
-
[14]SPI1EN (def=0x0) // SPI1 clock enable
-
[15]SPI2EN (def=0x0) // SPI2 clock enable
-
[17]USART1EN (def=0x0) // USART1 clock enable
-
[18]USART2EN (def=0x0) // USART2 clock enable
-
[19]UART3EN (def=0x0) // UART3 clock enable
-
[20]UART4EN (def=0x0) // UART4 clock enable
-
[21]I2C0EN (def=0x0) // I2C0 clock enable
-
[22]I2C1EN (def=0x0) // I2C1 clock enable
-
[25]CAN0EN (def=0x0) // CAN0 clock enable
-
[26]CAN1EN (def=0x0) // CAN1 clock enable
-
[27]BKPIEN (def=0x0) // Backup interface clock enable
-
[28]PMUEN (def=0x0) // Power control clock enable
-
[29]DACEN (def=0x0) // DAC clock enable
0x40021020BDCTL// Backup domain control register (RCU_BDCTL)
-
[0]LXTALEN (def=0x0) // LXTAL enable
-
[1]LXTALSTB (def=0x0) // External low-speed oscillator stabilization
-
[2]LXTALBPS (def=0x0) // LXTAL bypass mode enable
-
[8:9]RTCSRC (def=0x0) // RTC clock entry selection
-
[15]RTCEN (def=0x0) // RTC clock enable
-
[16]BKPRST (def=0x0) // Backup domain reset
0x40021024RSTSCK// Reset source /clock register (RCU_RSTSCK)
-
[0]IRC40KEN (def=0x0) // IRC40K enable
-
[1]IRC40KSTB (def=0x0) // IRC40K stabilization
-
[24]RSTFC (def=0x0) // Reset flag clear
-
[26]EPRSTF (def=0x1) // External PIN reset flag
-
[27]PORRSTF (def=0x1) // Power reset flag
-
[28]SWRSTF (def=0x0) // Software reset flag
-
[29]FWDGTRSTF (def=0x0) // Free Watchdog timer reset flag
-
[30]WWDGTRSTF (def=0x0) // Window watchdog timer reset flag
-
[31]LPRSTF (def=0x0) // Low-power reset flag
0x40021028AHBRST// AHB reset register
-
[12]USBFSRST (def=0x0) // USBFS reset
0x4002102CCFG1// Clock Configuration register 1
-
[0:3]PREDV0 (def=0x0) // PREDV0 division factor
-
[4:7]PREDV1 (def=0x0) // PREDV1 division factor
-
[8:11]PLL1MF (def=0x0) // The PLL1 clock multiplication factor
-
[12:15]PLL2MF (def=0x0) // The PLL2 clock multiplication factor
-
[16]PREDV0SEL (def=0x0) // PREDV0 input Clock Source Selection
-
[17]I2S1SEL (def=0x0) // I2S1 Clock Source Selection
-
[18]I2S2SEL (def=0x0) // I2S2 Clock Source Selection
0x40021034DSV// Deep sleep mode Voltage register
-
[0:1]DSLPVS (def=0x0) // Deep-sleep mode voltage select
0x40002800RTC// Real-time clock
0x40002800INTEN// RTC interrupt enable register
-
[2]OVIE (def=0x0) // Overflow interrupt enable
-
[1]ALRMIE (def=0x0) // Alarm interrupt enable
-
[0]SCIE (def=0x0) // Second interrupt
0x40002804CTL// control register
-
[5]LWOFF (def=0x1) // Last write operation finished flag
-
[4]CMF (def=0x0) // Configuration mode flag
-
[3]RSYNF (def=0x0) // Registers synchronized flag
-
[2]OVIF (def=0x0) // Overflow interrupt flag
-
[1]ALRMIF (def=0x0) // Alarm interrupt flag
-
[0]SCIF (def=0x0) // Sencond interrupt flag
0x40002808PSCH// RTC prescaler high register
-
[0:3]PSC (def=0x0) // RTC prescaler value high
0x4000280CPSCL// RTC prescaler low register
-
[0:15]PSC (def=0x8000) // RTC prescaler value low
0x40002810DIVH// RTC divider high register
-
[0:3]DIV (def=0x0) // RTC divider value high
0x40002814DIVL// RTC divider low register
-
[0:15]DIV (def=0x8000) // RTC divider value low
0x40002818CNTH// RTC counter high register
-
[0:15]CNT (def=0x0) // RTC counter value high
0x4000281CCNTL// RTC counter low register
-
[0:15]CNT (def=0x0) // RTC counter value low
0x40002820ALRMH// Alarm high register
-
[0:15]ALRM (def=0xFFFF) // Alarm value high
0x40002824ALRML// RTC alarm low register
-
[0:15]ALRM (def=0xFFFF) // alarm value low
- [22] RTC //
- [60] RTC_Alarm //
0x40013000SPI0// Serial peripheral interface
0x40013000CTL0// control register 0
-
[15]BDEN (def=0x0) // Bidirectional enable
-
[14]BDOEN (def=0x0) // Bidirectional Transmit output enable
-
[13]CRCEN (def=0x0) // CRC Calculation Enable
-
[12]CRCNT (def=0x0) // CRC Next Transfer
-
[11]FF16 (def=0x0) // Data frame format
-
[10]RO (def=0x0) // Receive only
-
[9]SWNSSEN (def=0x0) // NSS Software Mode Selection
-
[8]SWNSS (def=0x0) // NSS Pin Selection In NSS Software Mode
-
[7]LF (def=0x0) // LSB First Mode
-
[6]SPIEN (def=0x0) // SPI enable
-
[3:5]PSC (def=0x0) // Master Clock Prescaler Selection
-
[2]MSTMOD (def=0x0) // Master Mode Enable
-
[1]CKPL (def=0x0) // Clock polarity Selection
-
[0]CKPH (def=0x0) // Clock Phase Selection
0x40013004CTL1// control register 1
-
[7]TBEIE (def=0x0) // Tx buffer empty interrupt enable
-
[6]RBNEIE (def=0x0) // RX buffer not empty interrupt enable
-
[5]ERRIE (def=0x0) // Error interrupt enable
-
[4]TMOD (def=0x0) // SPI TI mode enable
-
[3]NSSP (def=0x0) // SPI NSS pulse mode enable
-
[2]NSSDRV (def=0x0) // Drive NSS Output
-
[1]DMATEN (def=0x0) // Transmit Buffer DMA Enable
-
[0]DMAREN (def=0x0) // Rx buffer DMA enable
0x40013008STAT// status register
-
[8]FERR (def=0x0) // Format error
-
[7]TRANS (def=0x0) // Transmitting On-going Bit
-
[6]RXORERR (def=0x0) // Reception Overrun Error Bit
-
[5]CONFERR (def=0x0) // SPI Configuration error
-
[4]CRCERR (def=0x0) // SPI CRC Error Bit
-
[3]TXURERR (def=0x0) // Transmission underrun error bit
-
[2]I2SCH (def=0x0) // I2S channel side
-
[1]TBE (def=0x1) // Transmit Buffer Empty
-
[0]RBNE (def=0x0) // Receive Buffer Not Empty
0x4001300CDATA// data register
-
[0:15]SPI_DATA (def=0x0) // Data transfer register
0x40013010CRCPOLY// CRC polynomial register
-
[0:15]CRCPOLY (def=0x7) // CRC polynomial value
0x40013014RCRC// RX CRC register
-
[0:15]RCRC (def=0x0) // RX CRC value
0x40013018TCRC// TX CRC register
-
[0:15]TCRC (def=0x0) // Tx CRC value
0x4001301CI2SCTL// I2S control register
-
[11]I2SSEL (def=0x0) // I2S mode selection
-
[10]I2SEN (def=0x0) // I2S Enable
-
[8:9]I2SOPMOD (def=0x0) // I2S operation mode
-
[7]PCMSMOD (def=0x0) // PCM frame synchronization mode
-
[4:5]I2SSTD (def=0x0) // I2S standard selection
-
[3]CKPL (def=0x0) // Idle state clock polarity
-
[1:2]DTLEN (def=0x0) // Data length
-
[0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
0x40013020I2SPSC// I2S prescaler register
-
[9]MCKOEN (def=0x0) // I2S_MCK output enable
-
[8]OF (def=0x0) // Odd factor for the prescaler
-
[0:7]DIV (def=0x2) // Dividing factor for the prescaler
0x40003800SPI1//
0x40003800CTL0// control register 0
-
[15]BDEN (def=0x0) // Bidirectional enable
-
[14]BDOEN (def=0x0) // Bidirectional Transmit output enable
-
[13]CRCEN (def=0x0) // CRC Calculation Enable
-
[12]CRCNT (def=0x0) // CRC Next Transfer
-
[11]FF16 (def=0x0) // Data frame format
-
[10]RO (def=0x0) // Receive only
-
[9]SWNSSEN (def=0x0) // NSS Software Mode Selection
-
[8]SWNSS (def=0x0) // NSS Pin Selection In NSS Software Mode
-
[7]LF (def=0x0) // LSB First Mode
-
[6]SPIEN (def=0x0) // SPI enable
-
[3:5]PSC (def=0x0) // Master Clock Prescaler Selection
-
[2]MSTMOD (def=0x0) // Master Mode Enable
-
[1]CKPL (def=0x0) // Clock polarity Selection
-
[0]CKPH (def=0x0) // Clock Phase Selection
0x40003804CTL1// control register 1
-
[7]TBEIE (def=0x0) // Tx buffer empty interrupt enable
-
[6]RBNEIE (def=0x0) // RX buffer not empty interrupt enable
-
[5]ERRIE (def=0x0) // Error interrupt enable
-
[4]TMOD (def=0x0) // SPI TI mode enable
-
[3]NSSP (def=0x0) // SPI NSS pulse mode enable
-
[2]NSSDRV (def=0x0) // Drive NSS Output
-
[1]DMATEN (def=0x0) // Transmit Buffer DMA Enable
-
[0]DMAREN (def=0x0) // Rx buffer DMA enable
0x40003808STAT// status register
-
[8]FERR (def=0x0) // Format error
-
[7]TRANS (def=0x0) // Transmitting On-going Bit
-
[6]RXORERR (def=0x0) // Reception Overrun Error Bit
-
[5]CONFERR (def=0x0) // SPI Configuration error
-
[4]CRCERR (def=0x0) // SPI CRC Error Bit
-
[3]TXURERR (def=0x0) // Transmission underrun error bit
-
[2]I2SCH (def=0x0) // I2S channel side
-
[1]TBE (def=0x1) // Transmit Buffer Empty
-
[0]RBNE (def=0x0) // Receive Buffer Not Empty
0x4000380CDATA// data register
-
[0:15]SPI_DATA (def=0x0) // Data transfer register
0x40003810CRCPOLY// CRC polynomial register
-
[0:15]CRCPOLY (def=0x7) // CRC polynomial value
0x40003814RCRC// RX CRC register
-
[0:15]RCRC (def=0x0) // RX CRC value
0x40003818TCRC// TX CRC register
-
[0:15]TCRC (def=0x0) // Tx CRC value
0x4000381CI2SCTL// I2S control register
-
[11]I2SSEL (def=0x0) // I2S mode selection
-
[10]I2SEN (def=0x0) // I2S Enable
-
[8:9]I2SOPMOD (def=0x0) // I2S operation mode
-
[7]PCMSMOD (def=0x0) // PCM frame synchronization mode
-
[4:5]I2SSTD (def=0x0) // I2S standard selection
-
[3]CKPL (def=0x0) // Idle state clock polarity
-
[1:2]DTLEN (def=0x0) // Data length
-
[0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
0x40003820I2SPSC// I2S prescaler register
-
[9]MCKOEN (def=0x0) // I2S_MCK output enable
-
[8]OF (def=0x0) // Odd factor for the prescaler
-
[0:7]DIV (def=0x2) // Dividing factor for the prescaler
0x40003C00SPI2//
0x40003C00CTL0// control register 0
-
[15]BDEN (def=0x0) // Bidirectional enable
-
[14]BDOEN (def=0x0) // Bidirectional Transmit output enable
-
[13]CRCEN (def=0x0) // CRC Calculation Enable
-
[12]CRCNT (def=0x0) // CRC Next Transfer
-
[11]FF16 (def=0x0) // Data frame format
-
[10]RO (def=0x0) // Receive only
-
[9]SWNSSEN (def=0x0) // NSS Software Mode Selection
-
[8]SWNSS (def=0x0) // NSS Pin Selection In NSS Software Mode
-
[7]LF (def=0x0) // LSB First Mode
-
[6]SPIEN (def=0x0) // SPI enable
-
[3:5]PSC (def=0x0) // Master Clock Prescaler Selection
-
[2]MSTMOD (def=0x0) // Master Mode Enable
-
[1]CKPL (def=0x0) // Clock polarity Selection
-
[0]CKPH (def=0x0) // Clock Phase Selection
0x40003C04CTL1// control register 1
-
[7]TBEIE (def=0x0) // Tx buffer empty interrupt enable
-
[6]RBNEIE (def=0x0) // RX buffer not empty interrupt enable
-
[5]ERRIE (def=0x0) // Error interrupt enable
-
[4]TMOD (def=0x0) // SPI TI mode enable
-
[3]NSSP (def=0x0) // SPI NSS pulse mode enable
-
[2]NSSDRV (def=0x0) // Drive NSS Output
-
[1]DMATEN (def=0x0) // Transmit Buffer DMA Enable
-
[0]DMAREN (def=0x0) // Rx buffer DMA enable
0x40003C08STAT// status register
-
[8]FERR (def=0x0) // Format error
-
[7]TRANS (def=0x0) // Transmitting On-going Bit
-
[6]RXORERR (def=0x0) // Reception Overrun Error Bit
-
[5]CONFERR (def=0x0) // SPI Configuration error
-
[4]CRCERR (def=0x0) // SPI CRC Error Bit
-
[3]TXURERR (def=0x0) // Transmission underrun error bit
-
[2]I2SCH (def=0x0) // I2S channel side
-
[1]TBE (def=0x1) // Transmit Buffer Empty
-
[0]RBNE (def=0x0) // Receive Buffer Not Empty
0x40003C0CDATA// data register
-
[0:15]SPI_DATA (def=0x0) // Data transfer register
0x40003C10CRCPOLY// CRC polynomial register
-
[0:15]CRCPOLY (def=0x7) // CRC polynomial value
0x40003C14RCRC// RX CRC register
-
[0:15]RCRC (def=0x0) // RX CRC value
0x40003C18TCRC// TX CRC register
-
[0:15]TCRC (def=0x0) // Tx CRC value
0x40003C1CI2SCTL// I2S control register
-
[11]I2SSEL (def=0x0) // I2S mode selection
-
[10]I2SEN (def=0x0) // I2S Enable
-
[8:9]I2SOPMOD (def=0x0) // I2S operation mode
-
[7]PCMSMOD (def=0x0) // PCM frame synchronization mode
-
[4:5]I2SSTD (def=0x0) // I2S standard selection
-
[3]CKPL (def=0x0) // Idle state clock polarity
-
[1:2]DTLEN (def=0x0) // Data length
-
[0]CHLEN (def=0x0) // Channel length (number of bits per audio channel)
0x40003C20I2SPSC// I2S prescaler register
-
[9]MCKOEN (def=0x0) // I2S_MCK output enable
-
[8]OF (def=0x0) // Odd factor for the prescaler
-
[0:7]DIV (def=0x2) // Dividing factor for the prescaler
0x40012C00TIMER0// Advanced-timers
0x40012C00CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload shadow enable
-
[5:6]CAM (def=0x0) // Counter aligns mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]SPM (def=0x0) // Single pulse mode
-
[2]UPS (def=0x0) // Update source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40012C04CTL1// control register 1
-
[14]ISO3 (def=0x0) // Idle state of channel 3 output
-
[13]ISO2N (def=0x0) // Idle state of channel 2 complementary output
-
[12]ISO2 (def=0x0) // Idle state of channel 2 output
-
[11]ISO1N (def=0x0) // Idle state of channel 1 complementary output
-
[10]ISO1 (def=0x0) // Idle state of channel 1 output
-
[9]ISO0N (def=0x0) // Idle state of channel 0 complementary output
-
[8]ISO0 (def=0x0) // Idle state of channel 0 output
-
[7]TI0S (def=0x0) // Channel 0 trigger input selection
-
[4:6]MMC (def=0x0) // Master mode control
-
[3]DMAS (def=0x0) // DMA request source selection
-
[2]CCUC (def=0x0) // Commutation control shadow register update control
-
[0]CCSE (def=0x0) // Commutation control shadow enable
0x40012C08SMCFG// slave mode configuration register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]SMC1 (def=0x0) // Part of SMC for enable External clock mode1
-
[12:13]ETPSC (def=0x0) // External trigger prescaler
-
[8:11]ETFC (def=0x0) // External trigger filter control
-
[7]MSM (def=0x0) // Master/Slave mode
-
[4:6]TRGS (def=0x0) // Trigger selection
-
[0:2]SMC (def=0x0) // Slave mode selection
0x40012C0CDMAINTEN// DMA/Interrupt enable register
-
[14]TRGDEN (def=0x0) // Trigger DMA request enable
-
[13]CMTDEN (def=0x0) // Commutation DMA request enable
-
[12]CH3DEN (def=0x0) // Channel 3 capture/compare DMA request enable
-
[11]CH2DEN (def=0x0) // Channel 2 capture/compare DMA request enable
-
[10]CH1DEN (def=0x0) // Channel 1 capture/compare DMA request enable
-
[9]CH0DEN (def=0x0) // Channel 0 capture/compare DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[7]BRKIE (def=0x0) // Break interrupt enable
-
[6]TRGIE (def=0x0) // Trigger interrupt enable
-
[5]CMTIE (def=0x0) // commutation interrupt enable
-
[4]CH3IE (def=0x0) // Channel 3 capture/compare interrupt enable
-
[3]CH2IE (def=0x0) // Channel 2 capture/compare interrupt enable
-
[2]CH1IE (def=0x0) // Channel 1 capture/compare interrupt enable
-
[1]CH0IE (def=0x0) // Channel 0 capture/compare interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40012C10INTF// Interrupt flag register
-
[12]CH3OF (def=0x0) // Channel 3 over capture flag
-
[11]CH2OF (def=0x0) // Channel 2 over capture flag
-
[10]CH1OF (def=0x0) // Channel 1 over capture flag
-
[9]CH0OF (def=0x0) // Channel 0 over capture flag
-
[7]BRKIF (def=0x0) // Break interrupt flag
-
[6]TRGIF (def=0x0) // Trigger interrupt flag
-
[5]CMTIF (def=0x0) // Channel commutation interrupt flag
-
[4]CH3IF (def=0x0) // Channel 3 capture/compare interrupt flag
-
[3]CH2IF (def=0x0) // Channel 2 capture/compare interrupt flag
-
[2]CH1IF (def=0x0) // Channel 1 capture/compare interrupt flag
-
[1]CH0IF (def=0x0) // Channel 0 capture/compare interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40012C14SWEVG// Software event generation register
-
[7]BRKG (def=0x0) // Break event generation
-
[6]TRGG (def=0x0) // Trigger event generation
-
[5]CMTG (def=0x0) // Channel commutation event generation
-
[4]CH3G (def=0x0) // Channel 3 capture or compare event generation
-
[3]CH2G (def=0x0) // Channel 2 capture or compare event generation
-
[2]CH1G (def=0x0) // Channel 1 capture or compare event generation
-
[1]CH0G (def=0x0) // Channel 0 capture or compare event generation
-
[0]UPG (def=0x0) // Update event generation
0x40012C18CHCTL0_Output// Channel control register 0 (output mode)
-
[15]CH1COMCEN (def=0x0) // Channel 1 output compare clear enable
-
[12:14]CH1COMCTL (def=0x0) // Channel 1 compare output control
-
[11]CH1COMSEN (def=0x0) // Channel 1 output compare shadow enable
-
[10]CH1COMFEN (def=0x0) // Channel 1 output compare fast enable
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[7]CH0COMCEN (def=0x0) // Channel 0 output compare clear enable
-
[4:6]CH0COMCTL (def=0x0) // Channel 0 compare output control
-
[3]CH0COMSEN (def=0x0) // Channel 0 compare output shadow enable
-
[2]CH0COMFEN (def=0x0) // Channel 0 output compare fast enable
-
[0:1]CH0MS (def=0x0) // Channel 0 I/O mode selection
0x40012C18CHCTL0_Input// Channel control register 0 (input mode)
-
[12:15]CH1CAPFLT (def=0x0) // Channel 1 input capture filter control
-
[10:11]CH1CAPPSC (def=0x0) // Channel 1 input capture prescaler
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[4:7]CH0CAPFLT (def=0x0) // Channel 0 input capture filter control
-
[2:3]CH0CAPPSC (def=0x0) // Channel 0 input capture prescaler
-
[0:1]CH0MS (def=0x0) // Channel 0 mode selection
0x40012C1CCHCTL1_Output// Channel control register 1 (output mode)
-
[15]CH3COMCEN (def=0x0) // Channel 3 output compare clear enable
-
[12:14]CH3COMCTL (def=0x0) // Channel 3 compare output control
-
[11]CH3COMSEN (def=0x0) // Channel 3 output compare shadow enable
-
[10]CH3COMFEN (def=0x0) // Channel 3 output compare fast enable
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[7]CH2COMCEN (def=0x0) // Channel 2 output compare clear enable
-
[4:6]CH2COMCTL (def=0x0) // Channel 2 compare output control
-
[3]CH2COMSEN (def=0x0) // Channel 2 compare output shadow enable
-
[2]CH2COMFEN (def=0x0) // Channel 2 output compare fast enable
-
[0:1]CH2MS (def=0x0) // Channel 2 I/O mode selection
0x40012C1CCHCTL1_Input// Channel control register 1 (input mode)
-
[12:15]CH3CAPFLT (def=0x0) // Channel 3 input capture filter control
-
[10:11]CH3CAPPSC (def=0x0) // Channel 3 input capture prescaler
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[4:7]CH2CAPFLT (def=0x0) // Channel 2 input capture filter control
-
[2:3]CH2CAPPSC (def=0x0) // Channel 2 input capture prescaler
-
[0:1]CH2MS (def=0x0) // Channel 2 mode selection
0x40012C20CHCTL2// Channel control register 2
-
[13]CH3P (def=0x0) // Channel 3 capture/compare function polarity
-
[12]CH3EN (def=0x0) // Channel 3 capture/compare function enable
-
[11]CH2NP (def=0x0) // Channel 2 complementary output polarity
-
[10]CH2NEN (def=0x0) // Channel 2 complementary output enable
-
[9]CH2P (def=0x0) // Channel 2 capture/compare function polarity
-
[8]CH2EN (def=0x0) // Channel 2 capture/compare function enable
-
[7]CH1NP (def=0x0) // Channel 1 complementary output polarity
-
[6]CH1NEN (def=0x0) // Channel 1 complementary output enable
-
[5]CH1P (def=0x0) // Channel 1 capture/compare function polarity
-
[4]CH1EN (def=0x0) // Channel 1 capture/compare function enable
-
[3]CH0NP (def=0x0) // Channel 0 complementary output polarity
-
[2]CH0NEN (def=0x0) // Channel 0 complementary output enable
-
[1]CH0P (def=0x0) // Channel 0 capture/compare function polarity
-
[0]CH0EN (def=0x0) // Channel 0 capture/compare function enable
0x40012C24CNT// counter
-
[0:15]CNT (def=0x0) // current counter value
0x40012C28PSC// prescaler
-
[0:15]PSC (def=0x0) // Prescaler value of the counter clock
0x40012C2CCAR// Counter auto reload register
-
[0:15]CARL (def=0x0) // Counter auto reload value
0x40012C30CREP// Counter repetition register
-
[0:7]CREP (def=0x0) // Counter repetition value
0x40012C34CH0CV// Channel 0 capture/compare value register
-
[0:15]CH0VAL (def=0x0) // Capture or compare value of channel0
0x40012C38CH1CV// Channel 1 capture/compare value register
-
[0:15]CH1VAL (def=0x0) // Capture or compare value of channel1
0x40012C3CCH2CV// Channel 2 capture/compare value register
-
[0:15]CH2VAL (def=0x0) // Capture or compare value of channel 2
0x40012C40CH3CV// Channel 3 capture/compare value register
-
[0:15]CH3VAL (def=0x0) // Capture or compare value of channel 3
0x40012C44CCHP// channel complementary protection register
-
[15]POEN (def=0x0) // Primary output enable
-
[14]OAEN (def=0x0) // Output automatic enable
-
[13]BRKP (def=0x0) // Break polarity
-
[12]BRKEN (def=0x0) // Break enable
-
[11]ROS (def=0x0) // Run mode off-state configure
-
[10]IOS (def=0x0) // Idle mode off-state configure
-
[8:9]PROT (def=0x0) // Complementary register protect control
-
[0:7]DTCFG (def=0x0) // Dead time configure
0x40012C48DMACFG// DMA configuration register
-
[8:12]DMATC (def=0x0) // DMA transfer count
-
[0:4]DMATA (def=0x0) // DMA transfer access start address
0x40012C4CDMATB// DMA transfer buffer register
-
[0:15]DMATB (def=0x0) // DMA transfer buffer
- [43] TIMER0_BRK //
- [44] TIMER0_UP //
- [45] TIMER0_TRG_CMT //
- [46] TIMER0_Channel //
0x40000000TIMER1// General-purpose-timers
0x40000000CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload shadow enable
-
[5:6]CAM (def=0x0) // Counter aligns mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]SPM (def=0x0) // Single pulse mode
-
[2]UPS (def=0x0) // Update source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000004CTL1// control register 1
-
[7]TI0S (def=0x0) // Channel 0 trigger input selection
-
[4:6]MMC (def=0x0) // Master mode control
-
[3]DMAS (def=0x0) // DMA request source selection
0x40000008SMCFG// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]SMC1 (def=0x0) // Part of SMC for enable External clock mode1
-
[12:13]ETPSC (def=0x0) // External trigger prescaler
-
[8:11]ETFC (def=0x0) // External trigger filter control
-
[7]MSM (def=0x0) // Master-slave mode
-
[4:6]TRGS (def=0x0) // Trigger selection
-
[0:2]SMC (def=0x0) // Slave mode control
0x4000000CDMAINTEN// DMA/Interrupt enable register
-
[14]TRGDEN (def=0x0) // Trigger DMA request enable
-
[12]CH3DEN (def=0x0) // Channel 3 capture/compare DMA request enable
-
[11]CH2DEN (def=0x0) // Channel 2 capture/compare DMA request enable
-
[10]CH1DEN (def=0x0) // Channel 1 capture/compare DMA request enable
-
[9]CH0DEN (def=0x0) // Channel 0 capture/compare DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[6]TRGIE (def=0x0) // Trigger interrupt enable
-
[4]CH3IE (def=0x0) // Channel 3 capture/compare interrupt enable
-
[3]CH2IE (def=0x0) // Channel 2 capture/compare interrupt enable
-
[2]CH1IE (def=0x0) // Channel 1 capture/compare interrupt enable
-
[1]CH0IE (def=0x0) // Channel 0 capture/compare interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40000010INTF// interrupt flag register
-
[12]CH3OF (def=0x0) // Channel 3 over capture flag
-
[11]CH2OF (def=0x0) // Channel 2 over capture flag
-
[10]CH1OF (def=0x0) // Channel 1 over capture flag
-
[9]CH0OF (def=0x0) // Channel 0 over capture flag
-
[6]TRGIF (def=0x0) // Trigger interrupt flag
-
[4]CH3IF (def=0x0) // Channel 3 capture/compare interrupt enable
-
[3]CH2IF (def=0x0) // Channel 2 capture/compare interrupt enable
-
[2]CH1IF (def=0x0) // Channel 1 capture/compare interrupt flag
-
[1]CH0IF (def=0x0) // Channel 0 capture/compare interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40000014SWEVG// event generation register
-
[6]TRGG (def=0x0) // Trigger event generation
-
[4]CH3G (def=0x0) // Channel 3 capture or compare event generation
-
[3]CH2G (def=0x0) // Channel 2 capture or compare event generation
-
[2]CH1G (def=0x0) // Channel 1 capture or compare event generation
-
[1]CH0G (def=0x0) // Channel 0 capture or compare event generation
-
[0]UPG (def=0x0) // Update generation
0x40000018CHCTL0_Output// Channel control register 0 (output mode)
-
[15]CH1COMCEN (def=0x0) // Channel 1 output compare clear enable
-
[12:14]CH1COMCTL (def=0x0) // Channel 1 compare output control
-
[11]CH1COMSEN (def=0x0) // Channel 1 output compare shadow enable
-
[10]CH1COMFEN (def=0x0) // Channel 1 output compare fast enable
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[7]CH0COMCEN (def=0x0) // Channel 0 output compare clear enable
-
[4:6]CH0COMCTL (def=0x0) // Channel 0 compare output control
-
[3]CH0COMSEN (def=0x0) // Channel 0 compare output shadow enable
-
[2]CH0COMFEN (def=0x0) // Channel 0 output compare fast enable
-
[0:1]CH0MS (def=0x0) // Channel 0 I/O mode selection
0x40000018CHCTL0_Input// Channel control register 0 (input mode)
-
[12:15]CH1CAPFLT (def=0x0) // Channel 1 input capture filter control
-
[10:11]CH1CAPPSC (def=0x0) // Channel 1 input capture prescaler
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[4:7]CH0CAPFLT (def=0x0) // Channel 0 input capture filter control
-
[2:3]CH0CAPPSC (def=0x0) // Channel 0 input capture prescaler
-
[0:1]CH0MS (def=0x0) // Channel 0 mode selection
0x4000001CCHCTL1_Output// Channel control register 1 (output mode)
-
[15]CH3COMCEN (def=0x0) // Channel 3 output compare clear enable
-
[12:14]CH3COMCTL (def=0x0) // Channel 3 compare output control
-
[11]CH3COMSEN (def=0x0) // Channel 3 output compare shadow enable
-
[10]CH3COMFEN (def=0x0) // Channel 3 output compare fast enable
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[7]CH2COMCEN (def=0x0) // Channel 2 output compare clear enable
-
[4:6]CH2COMCTL (def=0x0) // Channel 2 compare output control
-
[3]CH2COMSEN (def=0x0) // Channel 2 compare output shadow enable
-
[2]CH2COMFEN (def=0x0) // Channel 2 output compare fast enable
-
[0:1]CH2MS (def=0x0) // Channel 2 I/O mode selection
0x4000001CCHCTL1_Input// Channel control register 1 (input mode)
-
[12:15]CH3CAPFLT (def=0x0) // Channel 3 input capture filter control
-
[10:11]CH3CAPPSC (def=0x0) // Channel 3 input capture prescaler
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[4:7]CH2CAPFLT (def=0x0) // Channel 2 input capture filter control
-
[2:3]CH2CAPPSC (def=0x0) // Channel 2 input capture prescaler
-
[0:1]CH2MS (def=0x0) // Channel 2 mode selection
0x40000020CHCTL2// Channel control register 2
-
[13]CH3P (def=0x0) // Channel 3 capture/compare function polarity
-
[12]CH3EN (def=0x0) // Channel 3 capture/compare function enable
-
[9]CH2P (def=0x0) // Channel 2 capture/compare function polarity
-
[8]CH2EN (def=0x0) // Channel 2 capture/compare function enable
-
[5]CH1P (def=0x0) // Channel 1 capture/compare function polarity
-
[4]CH1EN (def=0x0) // Channel 1 capture/compare function enable
-
[1]CH0P (def=0x0) // Channel 0 capture/compare function polarity
-
[0]CH0EN (def=0x0) // Channel 0 capture/compare function enable
0x40000024CNT// Counter register
-
[0:15]CNT (def=0x0) // counter value
0x40000028PSC// Prescaler register
-
[0:15]PSC (def=0x0) // Prescaler value of the counter clock
0x4000002CCAR// Counter auto reload register
-
[0:15]CARL (def=0x0) // Counter auto reload value
0x40000034CH0CV// Channel 0 capture/compare value register
-
[0:15]CH0VAL (def=0x0) // Capture or compare value of channel 0
0x40000038CH1CV// Channel 1 capture/compare value register
-
[0:15]CH1VAL (def=0x0) // Capture or compare value of channel1
0x4000003CCH2CV// Channel 2 capture/compare value register
-
[0:15]CH2VAL (def=0x0) // Capture or compare value of channel 2
0x40000040CH3CV// Channel 3 capture/compare value register
-
[0:15]CH3VAL (def=0x0) // Capture or compare value of channel 3
0x40000048DMACFG// DMA configuration register
-
[8:12]DMATC (def=0x0) // DMA transfer count
-
[0:4]DMATA (def=0x0) // DMA transfer access start address
0x4000004CDMATB// DMA transfer buffer register
-
[0:15]DMATB (def=0x0) // DMA transfer buffer
0x40000400TIMER2//
0x40000400CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload shadow enable
-
[5:6]CAM (def=0x0) // Counter aligns mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]SPM (def=0x0) // Single pulse mode
-
[2]UPS (def=0x0) // Update source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000404CTL1// control register 1
-
[7]TI0S (def=0x0) // Channel 0 trigger input selection
-
[4:6]MMC (def=0x0) // Master mode control
-
[3]DMAS (def=0x0) // DMA request source selection
0x40000408SMCFG// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]SMC1 (def=0x0) // Part of SMC for enable External clock mode1
-
[12:13]ETPSC (def=0x0) // External trigger prescaler
-
[8:11]ETFC (def=0x0) // External trigger filter control
-
[7]MSM (def=0x0) // Master-slave mode
-
[4:6]TRGS (def=0x0) // Trigger selection
-
[0:2]SMC (def=0x0) // Slave mode control
0x4000040CDMAINTEN// DMA/Interrupt enable register
-
[14]TRGDEN (def=0x0) // Trigger DMA request enable
-
[12]CH3DEN (def=0x0) // Channel 3 capture/compare DMA request enable
-
[11]CH2DEN (def=0x0) // Channel 2 capture/compare DMA request enable
-
[10]CH1DEN (def=0x0) // Channel 1 capture/compare DMA request enable
-
[9]CH0DEN (def=0x0) // Channel 0 capture/compare DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[6]TRGIE (def=0x0) // Trigger interrupt enable
-
[4]CH3IE (def=0x0) // Channel 3 capture/compare interrupt enable
-
[3]CH2IE (def=0x0) // Channel 2 capture/compare interrupt enable
-
[2]CH1IE (def=0x0) // Channel 1 capture/compare interrupt enable
-
[1]CH0IE (def=0x0) // Channel 0 capture/compare interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40000410INTF// interrupt flag register
-
[12]CH3OF (def=0x0) // Channel 3 over capture flag
-
[11]CH2OF (def=0x0) // Channel 2 over capture flag
-
[10]CH1OF (def=0x0) // Channel 1 over capture flag
-
[9]CH0OF (def=0x0) // Channel 0 over capture flag
-
[6]TRGIF (def=0x0) // Trigger interrupt flag
-
[4]CH3IF (def=0x0) // Channel 3 capture/compare interrupt enable
-
[3]CH2IF (def=0x0) // Channel 2 capture/compare interrupt enable
-
[2]CH1IF (def=0x0) // Channel 1 capture/compare interrupt flag
-
[1]CH0IF (def=0x0) // Channel 0 capture/compare interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40000414SWEVG// event generation register
-
[6]TRGG (def=0x0) // Trigger event generation
-
[4]CH3G (def=0x0) // Channel 3 capture or compare event generation
-
[3]CH2G (def=0x0) // Channel 2 capture or compare event generation
-
[2]CH1G (def=0x0) // Channel 1 capture or compare event generation
-
[1]CH0G (def=0x0) // Channel 0 capture or compare event generation
-
[0]UPG (def=0x0) // Update generation
0x40000418CHCTL0_Output// Channel control register 0 (output mode)
-
[15]CH1COMCEN (def=0x0) // Channel 1 output compare clear enable
-
[12:14]CH1COMCTL (def=0x0) // Channel 1 compare output control
-
[11]CH1COMSEN (def=0x0) // Channel 1 output compare shadow enable
-
[10]CH1COMFEN (def=0x0) // Channel 1 output compare fast enable
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[7]CH0COMCEN (def=0x0) // Channel 0 output compare clear enable
-
[4:6]CH0COMCTL (def=0x0) // Channel 0 compare output control
-
[3]CH0COMSEN (def=0x0) // Channel 0 compare output shadow enable
-
[2]CH0COMFEN (def=0x0) // Channel 0 output compare fast enable
-
[0:1]CH0MS (def=0x0) // Channel 0 I/O mode selection
0x40000418CHCTL0_Input// Channel control register 0 (input mode)
-
[12:15]CH1CAPFLT (def=0x0) // Channel 1 input capture filter control
-
[10:11]CH1CAPPSC (def=0x0) // Channel 1 input capture prescaler
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[4:7]CH0CAPFLT (def=0x0) // Channel 0 input capture filter control
-
[2:3]CH0CAPPSC (def=0x0) // Channel 0 input capture prescaler
-
[0:1]CH0MS (def=0x0) // Channel 0 mode selection
0x4000041CCHCTL1_Output// Channel control register 1 (output mode)
-
[15]CH3COMCEN (def=0x0) // Channel 3 output compare clear enable
-
[12:14]CH3COMCTL (def=0x0) // Channel 3 compare output control
-
[11]CH3COMSEN (def=0x0) // Channel 3 output compare shadow enable
-
[10]CH3COMFEN (def=0x0) // Channel 3 output compare fast enable
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[7]CH2COMCEN (def=0x0) // Channel 2 output compare clear enable
-
[4:6]CH2COMCTL (def=0x0) // Channel 2 compare output control
-
[3]CH2COMSEN (def=0x0) // Channel 2 compare output shadow enable
-
[2]CH2COMFEN (def=0x0) // Channel 2 output compare fast enable
-
[0:1]CH2MS (def=0x0) // Channel 2 I/O mode selection
0x4000041CCHCTL1_Input// Channel control register 1 (input mode)
-
[12:15]CH3CAPFLT (def=0x0) // Channel 3 input capture filter control
-
[10:11]CH3CAPPSC (def=0x0) // Channel 3 input capture prescaler
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[4:7]CH2CAPFLT (def=0x0) // Channel 2 input capture filter control
-
[2:3]CH2CAPPSC (def=0x0) // Channel 2 input capture prescaler
-
[0:1]CH2MS (def=0x0) // Channel 2 mode selection
0x40000420CHCTL2// Channel control register 2
-
[13]CH3P (def=0x0) // Channel 3 capture/compare function polarity
-
[12]CH3EN (def=0x0) // Channel 3 capture/compare function enable
-
[9]CH2P (def=0x0) // Channel 2 capture/compare function polarity
-
[8]CH2EN (def=0x0) // Channel 2 capture/compare function enable
-
[5]CH1P (def=0x0) // Channel 1 capture/compare function polarity
-
[4]CH1EN (def=0x0) // Channel 1 capture/compare function enable
-
[1]CH0P (def=0x0) // Channel 0 capture/compare function polarity
-
[0]CH0EN (def=0x0) // Channel 0 capture/compare function enable
0x40000424CNT// Counter register
-
[0:15]CNT (def=0x0) // counter value
0x40000428PSC// Prescaler register
-
[0:15]PSC (def=0x0) // Prescaler value of the counter clock
0x4000042CCAR// Counter auto reload register
-
[0:15]CARL (def=0x0) // Counter auto reload value
0x40000434CH0CV// Channel 0 capture/compare value register
-
[0:15]CH0VAL (def=0x0) // Capture or compare value of channel 0
0x40000438CH1CV// Channel 1 capture/compare value register
-
[0:15]CH1VAL (def=0x0) // Capture or compare value of channel1
0x4000043CCH2CV// Channel 2 capture/compare value register
-
[0:15]CH2VAL (def=0x0) // Capture or compare value of channel 2
0x40000440CH3CV// Channel 3 capture/compare value register
-
[0:15]CH3VAL (def=0x0) // Capture or compare value of channel 3
0x40000448DMACFG// DMA configuration register
-
[8:12]DMATC (def=0x0) // DMA transfer count
-
[0:4]DMATA (def=0x0) // DMA transfer access start address
0x4000044CDMATB// DMA transfer buffer register
-
[0:15]DMATB (def=0x0) // DMA transfer buffer
0x40000800TIMER3//
0x40000800CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload shadow enable
-
[5:6]CAM (def=0x0) // Counter aligns mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]SPM (def=0x0) // Single pulse mode
-
[2]UPS (def=0x0) // Update source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000804CTL1// control register 1
-
[7]TI0S (def=0x0) // Channel 0 trigger input selection
-
[4:6]MMC (def=0x0) // Master mode control
-
[3]DMAS (def=0x0) // DMA request source selection
0x40000808SMCFG// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]SMC1 (def=0x0) // Part of SMC for enable External clock mode1
-
[12:13]ETPSC (def=0x0) // External trigger prescaler
-
[8:11]ETFC (def=0x0) // External trigger filter control
-
[7]MSM (def=0x0) // Master-slave mode
-
[4:6]TRGS (def=0x0) // Trigger selection
-
[0:2]SMC (def=0x0) // Slave mode control
0x4000080CDMAINTEN// DMA/Interrupt enable register
-
[14]TRGDEN (def=0x0) // Trigger DMA request enable
-
[12]CH3DEN (def=0x0) // Channel 3 capture/compare DMA request enable
-
[11]CH2DEN (def=0x0) // Channel 2 capture/compare DMA request enable
-
[10]CH1DEN (def=0x0) // Channel 1 capture/compare DMA request enable
-
[9]CH0DEN (def=0x0) // Channel 0 capture/compare DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[6]TRGIE (def=0x0) // Trigger interrupt enable
-
[4]CH3IE (def=0x0) // Channel 3 capture/compare interrupt enable
-
[3]CH2IE (def=0x0) // Channel 2 capture/compare interrupt enable
-
[2]CH1IE (def=0x0) // Channel 1 capture/compare interrupt enable
-
[1]CH0IE (def=0x0) // Channel 0 capture/compare interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40000810INTF// interrupt flag register
-
[12]CH3OF (def=0x0) // Channel 3 over capture flag
-
[11]CH2OF (def=0x0) // Channel 2 over capture flag
-
[10]CH1OF (def=0x0) // Channel 1 over capture flag
-
[9]CH0OF (def=0x0) // Channel 0 over capture flag
-
[6]TRGIF (def=0x0) // Trigger interrupt flag
-
[4]CH3IF (def=0x0) // Channel 3 capture/compare interrupt enable
-
[3]CH2IF (def=0x0) // Channel 2 capture/compare interrupt enable
-
[2]CH1IF (def=0x0) // Channel 1 capture/compare interrupt flag
-
[1]CH0IF (def=0x0) // Channel 0 capture/compare interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40000814SWEVG// event generation register
-
[6]TRGG (def=0x0) // Trigger event generation
-
[4]CH3G (def=0x0) // Channel 3 capture or compare event generation
-
[3]CH2G (def=0x0) // Channel 2 capture or compare event generation
-
[2]CH1G (def=0x0) // Channel 1 capture or compare event generation
-
[1]CH0G (def=0x0) // Channel 0 capture or compare event generation
-
[0]UPG (def=0x0) // Update generation
0x40000818CHCTL0_Output// Channel control register 0 (output mode)
-
[15]CH1COMCEN (def=0x0) // Channel 1 output compare clear enable
-
[12:14]CH1COMCTL (def=0x0) // Channel 1 compare output control
-
[11]CH1COMSEN (def=0x0) // Channel 1 output compare shadow enable
-
[10]CH1COMFEN (def=0x0) // Channel 1 output compare fast enable
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[7]CH0COMCEN (def=0x0) // Channel 0 output compare clear enable
-
[4:6]CH0COMCTL (def=0x0) // Channel 0 compare output control
-
[3]CH0COMSEN (def=0x0) // Channel 0 compare output shadow enable
-
[2]CH0COMFEN (def=0x0) // Channel 0 output compare fast enable
-
[0:1]CH0MS (def=0x0) // Channel 0 I/O mode selection
0x40000818CHCTL0_Input// Channel control register 0 (input mode)
-
[12:15]CH1CAPFLT (def=0x0) // Channel 1 input capture filter control
-
[10:11]CH1CAPPSC (def=0x0) // Channel 1 input capture prescaler
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[4:7]CH0CAPFLT (def=0x0) // Channel 0 input capture filter control
-
[2:3]CH0CAPPSC (def=0x0) // Channel 0 input capture prescaler
-
[0:1]CH0MS (def=0x0) // Channel 0 mode selection
0x4000081CCHCTL1_Output// Channel control register 1 (output mode)
-
[15]CH3COMCEN (def=0x0) // Channel 3 output compare clear enable
-
[12:14]CH3COMCTL (def=0x0) // Channel 3 compare output control
-
[11]CH3COMSEN (def=0x0) // Channel 3 output compare shadow enable
-
[10]CH3COMFEN (def=0x0) // Channel 3 output compare fast enable
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[7]CH2COMCEN (def=0x0) // Channel 2 output compare clear enable
-
[4:6]CH2COMCTL (def=0x0) // Channel 2 compare output control
-
[3]CH2COMSEN (def=0x0) // Channel 2 compare output shadow enable
-
[2]CH2COMFEN (def=0x0) // Channel 2 output compare fast enable
-
[0:1]CH2MS (def=0x0) // Channel 2 I/O mode selection
0x4000081CCHCTL1_Input// Channel control register 1 (input mode)
-
[12:15]CH3CAPFLT (def=0x0) // Channel 3 input capture filter control
-
[10:11]CH3CAPPSC (def=0x0) // Channel 3 input capture prescaler
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[4:7]CH2CAPFLT (def=0x0) // Channel 2 input capture filter control
-
[2:3]CH2CAPPSC (def=0x0) // Channel 2 input capture prescaler
-
[0:1]CH2MS (def=0x0) // Channel 2 mode selection
0x40000820CHCTL2// Channel control register 2
-
[13]CH3P (def=0x0) // Channel 3 capture/compare function polarity
-
[12]CH3EN (def=0x0) // Channel 3 capture/compare function enable
-
[9]CH2P (def=0x0) // Channel 2 capture/compare function polarity
-
[8]CH2EN (def=0x0) // Channel 2 capture/compare function enable
-
[5]CH1P (def=0x0) // Channel 1 capture/compare function polarity
-
[4]CH1EN (def=0x0) // Channel 1 capture/compare function enable
-
[1]CH0P (def=0x0) // Channel 0 capture/compare function polarity
-
[0]CH0EN (def=0x0) // Channel 0 capture/compare function enable
0x40000824CNT// Counter register
-
[0:15]CNT (def=0x0) // counter value
0x40000828PSC// Prescaler register
-
[0:15]PSC (def=0x0) // Prescaler value of the counter clock
0x4000082CCAR// Counter auto reload register
-
[0:15]CARL (def=0x0) // Counter auto reload value
0x40000834CH0CV// Channel 0 capture/compare value register
-
[0:15]CH0VAL (def=0x0) // Capture or compare value of channel 0
0x40000838CH1CV// Channel 1 capture/compare value register
-
[0:15]CH1VAL (def=0x0) // Capture or compare value of channel1
0x4000083CCH2CV// Channel 2 capture/compare value register
-
[0:15]CH2VAL (def=0x0) // Capture or compare value of channel 2
0x40000840CH3CV// Channel 3 capture/compare value register
-
[0:15]CH3VAL (def=0x0) // Capture or compare value of channel 3
0x40000848DMACFG// DMA configuration register
-
[8:12]DMATC (def=0x0) // DMA transfer count
-
[0:4]DMATA (def=0x0) // DMA transfer access start address
0x4000084CDMATB// DMA transfer buffer register
-
[0:15]DMATB (def=0x0) // DMA transfer buffer
0x40000C00TIMER4//
0x40000C00CTL0// control register 0
-
[8:9]CKDIV (def=0x0) // Clock division
-
[7]ARSE (def=0x0) // Auto-reload shadow enable
-
[5:6]CAM (def=0x0) // Counter aligns mode selection
-
[4]DIR (def=0x0) // Direction
-
[3]SPM (def=0x0) // Single pulse mode
-
[2]UPS (def=0x0) // Update source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40000C04CTL1// control register 1
-
[7]TI0S (def=0x0) // Channel 0 trigger input selection
-
[4:6]MMC (def=0x0) // Master mode control
-
[3]DMAS (def=0x0) // DMA request source selection
0x40000C08SMCFG// slave mode control register
-
[15]ETP (def=0x0) // External trigger polarity
-
[14]SMC1 (def=0x0) // Part of SMC for enable External clock mode1
-
[12:13]ETPSC (def=0x0) // External trigger prescaler
-
[8:11]ETFC (def=0x0) // External trigger filter control
-
[7]MSM (def=0x0) // Master-slave mode
-
[4:6]TRGS (def=0x0) // Trigger selection
-
[0:2]SMC (def=0x0) // Slave mode control
0x40000C0CDMAINTEN// DMA/Interrupt enable register
-
[14]TRGDEN (def=0x0) // Trigger DMA request enable
-
[12]CH3DEN (def=0x0) // Channel 3 capture/compare DMA request enable
-
[11]CH2DEN (def=0x0) // Channel 2 capture/compare DMA request enable
-
[10]CH1DEN (def=0x0) // Channel 1 capture/compare DMA request enable
-
[9]CH0DEN (def=0x0) // Channel 0 capture/compare DMA request enable
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[6]TRGIE (def=0x0) // Trigger interrupt enable
-
[4]CH3IE (def=0x0) // Channel 3 capture/compare interrupt enable
-
[3]CH2IE (def=0x0) // Channel 2 capture/compare interrupt enable
-
[2]CH1IE (def=0x0) // Channel 1 capture/compare interrupt enable
-
[1]CH0IE (def=0x0) // Channel 0 capture/compare interrupt enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40000C10INTF// interrupt flag register
-
[12]CH3OF (def=0x0) // Channel 3 over capture flag
-
[11]CH2OF (def=0x0) // Channel 2 over capture flag
-
[10]CH1OF (def=0x0) // Channel 1 over capture flag
-
[9]CH0OF (def=0x0) // Channel 0 over capture flag
-
[6]TRGIF (def=0x0) // Trigger interrupt flag
-
[4]CH3IF (def=0x0) // Channel 3 capture/compare interrupt enable
-
[3]CH2IF (def=0x0) // Channel 2 capture/compare interrupt enable
-
[2]CH1IF (def=0x0) // Channel 1 capture/compare interrupt flag
-
[1]CH0IF (def=0x0) // Channel 0 capture/compare interrupt flag
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40000C14SWEVG// event generation register
-
[6]TRGG (def=0x0) // Trigger event generation
-
[4]CH3G (def=0x0) // Channel 3 capture or compare event generation
-
[3]CH2G (def=0x0) // Channel 2 capture or compare event generation
-
[2]CH1G (def=0x0) // Channel 1 capture or compare event generation
-
[1]CH0G (def=0x0) // Channel 0 capture or compare event generation
-
[0]UPG (def=0x0) // Update generation
0x40000C18CHCTL0_Output// Channel control register 0 (output mode)
-
[15]CH1COMCEN (def=0x0) // Channel 1 output compare clear enable
-
[12:14]CH1COMCTL (def=0x0) // Channel 1 compare output control
-
[11]CH1COMSEN (def=0x0) // Channel 1 output compare shadow enable
-
[10]CH1COMFEN (def=0x0) // Channel 1 output compare fast enable
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[7]CH0COMCEN (def=0x0) // Channel 0 output compare clear enable
-
[4:6]CH0COMCTL (def=0x0) // Channel 0 compare output control
-
[3]CH0COMSEN (def=0x0) // Channel 0 compare output shadow enable
-
[2]CH0COMFEN (def=0x0) // Channel 0 output compare fast enable
-
[0:1]CH0MS (def=0x0) // Channel 0 I/O mode selection
0x40000C18CHCTL0_Input// Channel control register 0 (input mode)
-
[12:15]CH1CAPFLT (def=0x0) // Channel 1 input capture filter control
-
[10:11]CH1CAPPSC (def=0x0) // Channel 1 input capture prescaler
-
[8:9]CH1MS (def=0x0) // Channel 1 mode selection
-
[4:7]CH0CAPFLT (def=0x0) // Channel 0 input capture filter control
-
[2:3]CH0CAPPSC (def=0x0) // Channel 0 input capture prescaler
-
[0:1]CH0MS (def=0x0) // Channel 0 mode selection
0x40000C1CCHCTL1_Output// Channel control register 1 (output mode)
-
[15]CH3COMCEN (def=0x0) // Channel 3 output compare clear enable
-
[12:14]CH3COMCTL (def=0x0) // Channel 3 compare output control
-
[11]CH3COMSEN (def=0x0) // Channel 3 output compare shadow enable
-
[10]CH3COMFEN (def=0x0) // Channel 3 output compare fast enable
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[7]CH2COMCEN (def=0x0) // Channel 2 output compare clear enable
-
[4:6]CH2COMCTL (def=0x0) // Channel 2 compare output control
-
[3]CH2COMSEN (def=0x0) // Channel 2 compare output shadow enable
-
[2]CH2COMFEN (def=0x0) // Channel 2 output compare fast enable
-
[0:1]CH2MS (def=0x0) // Channel 2 I/O mode selection
0x40000C1CCHCTL1_Input// Channel control register 1 (input mode)
-
[12:15]CH3CAPFLT (def=0x0) // Channel 3 input capture filter control
-
[10:11]CH3CAPPSC (def=0x0) // Channel 3 input capture prescaler
-
[8:9]CH3MS (def=0x0) // Channel 3 mode selection
-
[4:7]CH2CAPFLT (def=0x0) // Channel 2 input capture filter control
-
[2:3]CH2CAPPSC (def=0x0) // Channel 2 input capture prescaler
-
[0:1]CH2MS (def=0x0) // Channel 2 mode selection
0x40000C20CHCTL2// Channel control register 2
-
[13]CH3P (def=0x0) // Channel 3 capture/compare function polarity
-
[12]CH3EN (def=0x0) // Channel 3 capture/compare function enable
-
[9]CH2P (def=0x0) // Channel 2 capture/compare function polarity
-
[8]CH2EN (def=0x0) // Channel 2 capture/compare function enable
-
[5]CH1P (def=0x0) // Channel 1 capture/compare function polarity
-
[4]CH1EN (def=0x0) // Channel 1 capture/compare function enable
-
[1]CH0P (def=0x0) // Channel 0 capture/compare function polarity
-
[0]CH0EN (def=0x0) // Channel 0 capture/compare function enable
0x40000C24CNT// Counter register
-
[0:15]CNT (def=0x0) // counter value
0x40000C28PSC// Prescaler register
-
[0:15]PSC (def=0x0) // Prescaler value of the counter clock
0x40000C2CCAR// Counter auto reload register
-
[0:15]CARL (def=0x0) // Counter auto reload value
0x40000C34CH0CV// Channel 0 capture/compare value register
-
[0:15]CH0VAL (def=0x0) // Capture or compare value of channel 0
0x40000C38CH1CV// Channel 1 capture/compare value register
-
[0:15]CH1VAL (def=0x0) // Capture or compare value of channel1
0x40000C3CCH2CV// Channel 2 capture/compare value register
-
[0:15]CH2VAL (def=0x0) // Capture or compare value of channel 2
0x40000C40CH3CV// Channel 3 capture/compare value register
-
[0:15]CH3VAL (def=0x0) // Capture or compare value of channel 3
0x40000C48DMACFG// DMA configuration register
-
[8:12]DMATC (def=0x0) // DMA transfer count
-
[0:4]DMATA (def=0x0) // DMA transfer access start address
0x40000C4CDMATB// DMA transfer buffer register
-
[0:15]DMATB (def=0x0) // DMA transfer buffer
0x40001000TIMER5// Basic-timers
0x40001000CTL0// control register 0
-
[7]ARSE (def=0x0) // Auto-reload shadow enable
-
[3]SPM (def=0x0) // Single pulse mode
-
[2]UPS (def=0x0) // Update source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40001004CTL1// control register 1
-
[4:6]MMC (def=0x0) // Master mode control
0x4000100CDMAINTEN// DMA/Interrupt enable register
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40001010INTF// Interrupt flag register
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40001014SWEVG// event generation register
-
[0]UPG (def=0x0) // Update generation
0x40001024CNT// Counter register
-
[0:15]CNT (def=0x0) // Low counter value
0x40001028PSC// Prescaler register
-
[0:15]PSC (def=0x0) // Prescaler value of the counter clock
0x4000102CCAR// Counter auto reload register
-
[0:15]CARL (def=0x0) // Counter auto reload value
0x40001400TIMER6//
0x40001400CTL0// control register 0
-
[7]ARSE (def=0x0) // Auto-reload shadow enable
-
[3]SPM (def=0x0) // Single pulse mode
-
[2]UPS (def=0x0) // Update source
-
[1]UPDIS (def=0x0) // Update disable
-
[0]CEN (def=0x0) // Counter enable
0x40001404CTL1// control register 1
-
[4:6]MMC (def=0x0) // Master mode control
0x4000140CDMAINTEN// DMA/Interrupt enable register
-
[8]UPDEN (def=0x0) // Update DMA request enable
-
[0]UPIE (def=0x0) // Update interrupt enable
0x40001410INTF// Interrupt flag register
-
[0]UPIF (def=0x0) // Update interrupt flag
0x40001414SWEVG// event generation register
-
[0]UPG (def=0x0) // Update generation
0x40001424CNT// Counter register
-
[0:15]CNT (def=0x0) // Low counter value
0x40001428PSC// Prescaler register
-
[0:15]PSC (def=0x0) // Prescaler value of the counter clock
0x4000142CCAR// Counter auto reload register
-
[0:15]CARL (def=0x0) // Counter auto reload value
0x40013800USART0// Universal synchronous asynchronous receiver transmitter
0x40013800STAT// Status register
-
[9]CTSF (def=0x0) // CTS change flag
-
[8]LBDF (def=0x0) // LIN break detection flag
-
[7]TBE (def=0x1) // Transmit data buffer empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RBNE (def=0x0) // Read data buffer not empty
-
[4]IDLEF (def=0x0) // IDLE frame detected flag
-
[3]ORERR (def=0x0) // Overrun error
-
[2]NERR (def=0x0) // Noise error flag
-
[1]FERR (def=0x0) // Frame error flag
-
[0]PERR (def=0x0) // Parity error flag
0x40013804DATA// Data register
-
[0:8]DATA (def=0x0) // Transmit or read data value
0x40013808BAUD// Baud rate register
-
[4:15]INTDIV (def=0x0) // Integer part of baud-rate divider
-
[0:3]FRADIV (def=0x0) // Fraction part of baud-rate divider
0x4001380CCTL0// Control register 0
-
[13]UEN (def=0x0) // USART enable
-
[12]WL (def=0x0) // Word length
-
[11]WM (def=0x0) // Wakeup method in mute mode
-
[10]PCEN (def=0x0) // Parity check function enable
-
[9]PM (def=0x0) // Parity mode
-
[8]PERRIE (def=0x0) // Parity error interrupt enable
-
[7]TBEIE (def=0x0) // Transmitter buffer empty interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RBNEIE (def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE line detected interrupt enable
-
[3]TEN (def=0x0) // Transmitter enable
-
[2]REN (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup from mute mode
-
[0]SBKCMD (def=0x0) // Send break command
0x40013810CTL1// Control register 1
-
[14]LMEN (def=0x0) // LIN mode enable
-
[12:13]STB (def=0x0) // STOP bits length
-
[11]CKEN (def=0x0) // CK pin enable
-
[10]CPL (def=0x0) // Clock polarity
-
[9]CPH (def=0x0) // Clock phase
-
[8]CLEN (def=0x0) // CK Length
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBLEN (def=0x0) // LIN break frame length
-
[0:3]ADDR (def=0x0) // Address of the USART
0x40013814CTL2// Control register 2
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSEN (def=0x0) // CTS enable
-
[8]RTSEN (def=0x0) // RTS enable
-
[7]DENT (def=0x0) // DMA request enable for transmission
-
[6]DENR (def=0x0) // DMA request enable for reception
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NKEN (def=0x0) // Smartcard NACK enable
-
[3]HDEN (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]ERRIE (def=0x0) // Error interrupt enable
0x40013818GP// Guard time and prescaler register
-
[8:15]GUAT (def=0x0) // Guard time value in Smartcard mode
-
[0:7]PSC (def=0x0) // Prescaler value
0x40004400USART1//
0x40004400STAT// Status register
-
[9]CTSF (def=0x0) // CTS change flag
-
[8]LBDF (def=0x0) // LIN break detection flag
-
[7]TBE (def=0x1) // Transmit data buffer empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RBNE (def=0x0) // Read data buffer not empty
-
[4]IDLEF (def=0x0) // IDLE frame detected flag
-
[3]ORERR (def=0x0) // Overrun error
-
[2]NERR (def=0x0) // Noise error flag
-
[1]FERR (def=0x0) // Frame error flag
-
[0]PERR (def=0x0) // Parity error flag
0x40004404DATA// Data register
-
[0:8]DATA (def=0x0) // Transmit or read data value
0x40004408BAUD// Baud rate register
-
[4:15]INTDIV (def=0x0) // Integer part of baud-rate divider
-
[0:3]FRADIV (def=0x0) // Fraction part of baud-rate divider
0x4000440CCTL0// Control register 0
-
[13]UEN (def=0x0) // USART enable
-
[12]WL (def=0x0) // Word length
-
[11]WM (def=0x0) // Wakeup method in mute mode
-
[10]PCEN (def=0x0) // Parity check function enable
-
[9]PM (def=0x0) // Parity mode
-
[8]PERRIE (def=0x0) // Parity error interrupt enable
-
[7]TBEIE (def=0x0) // Transmitter buffer empty interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RBNEIE (def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE line detected interrupt enable
-
[3]TEN (def=0x0) // Transmitter enable
-
[2]REN (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup from mute mode
-
[0]SBKCMD (def=0x0) // Send break command
0x40004410CTL1// Control register 1
-
[14]LMEN (def=0x0) // LIN mode enable
-
[12:13]STB (def=0x0) // STOP bits length
-
[11]CKEN (def=0x0) // CK pin enable
-
[10]CPL (def=0x0) // Clock polarity
-
[9]CPH (def=0x0) // Clock phase
-
[8]CLEN (def=0x0) // CK Length
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBLEN (def=0x0) // LIN break frame length
-
[0:3]ADDR (def=0x0) // Address of the USART
0x40004414CTL2// Control register 2
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSEN (def=0x0) // CTS enable
-
[8]RTSEN (def=0x0) // RTS enable
-
[7]DENT (def=0x0) // DMA request enable for transmission
-
[6]DENR (def=0x0) // DMA request enable for reception
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NKEN (def=0x0) // Smartcard NACK enable
-
[3]HDEN (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]ERRIE (def=0x0) // Error interrupt enable
0x40004418GP// Guard time and prescaler register
-
[8:15]GUAT (def=0x0) // Guard time value in Smartcard mode
-
[0:7]PSC (def=0x0) // Prescaler value
0x40004800USART2//
0x40004800STAT// Status register
-
[9]CTSF (def=0x0) // CTS change flag
-
[8]LBDF (def=0x0) // LIN break detection flag
-
[7]TBE (def=0x1) // Transmit data buffer empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RBNE (def=0x0) // Read data buffer not empty
-
[4]IDLEF (def=0x0) // IDLE frame detected flag
-
[3]ORERR (def=0x0) // Overrun error
-
[2]NERR (def=0x0) // Noise error flag
-
[1]FERR (def=0x0) // Frame error flag
-
[0]PERR (def=0x0) // Parity error flag
0x40004804DATA// Data register
-
[0:8]DATA (def=0x0) // Transmit or read data value
0x40004808BAUD// Baud rate register
-
[4:15]INTDIV (def=0x0) // Integer part of baud-rate divider
-
[0:3]FRADIV (def=0x0) // Fraction part of baud-rate divider
0x4000480CCTL0// Control register 0
-
[13]UEN (def=0x0) // USART enable
-
[12]WL (def=0x0) // Word length
-
[11]WM (def=0x0) // Wakeup method in mute mode
-
[10]PCEN (def=0x0) // Parity check function enable
-
[9]PM (def=0x0) // Parity mode
-
[8]PERRIE (def=0x0) // Parity error interrupt enable
-
[7]TBEIE (def=0x0) // Transmitter buffer empty interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RBNEIE (def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE line detected interrupt enable
-
[3]TEN (def=0x0) // Transmitter enable
-
[2]REN (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup from mute mode
-
[0]SBKCMD (def=0x0) // Send break command
0x40004810CTL1// Control register 1
-
[14]LMEN (def=0x0) // LIN mode enable
-
[12:13]STB (def=0x0) // STOP bits length
-
[11]CKEN (def=0x0) // CK pin enable
-
[10]CPL (def=0x0) // Clock polarity
-
[9]CPH (def=0x0) // Clock phase
-
[8]CLEN (def=0x0) // CK Length
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBLEN (def=0x0) // LIN break frame length
-
[0:3]ADDR (def=0x0) // Address of the USART
0x40004814CTL2// Control register 2
-
[10]CTSIE (def=0x0) // CTS interrupt enable
-
[9]CTSEN (def=0x0) // CTS enable
-
[8]RTSEN (def=0x0) // RTS enable
-
[7]DENT (def=0x0) // DMA request enable for transmission
-
[6]DENR (def=0x0) // DMA request enable for reception
-
[5]SCEN (def=0x0) // Smartcard mode enable
-
[4]NKEN (def=0x0) // Smartcard NACK enable
-
[3]HDEN (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]ERRIE (def=0x0) // Error interrupt enable
0x40004818GP// Guard time and prescaler register
-
[8:15]GUAT (def=0x0) // Guard time value in Smartcard mode
-
[0:7]PSC (def=0x0) // Prescaler value
0x40004C00UART3// Universal asynchronous receiver transmitter
0x40004C00STAT// Status register
-
[8]LBDF (def=0x0) // LIN break detection flag
-
[7]TBE (def=0x1) // Transmit data buffer empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RBNE (def=0x0) // Read data buffer not empty
-
[4]IDLEF (def=0x0) // IDLE frame detected flag
-
[3]ORERR (def=0x0) // Overrun error
-
[2]NERR (def=0x0) // Noise error flag
-
[1]FERR (def=0x0) // Frame error flag
-
[0]PERR (def=0x0) // Parity error flag
0x40004C04DATA// Data register
-
[0:8]DATA (def=0x0) // Transmit or read data value
0x40004C08BAUD// Baud rate register
-
[4:15]INTDIV (def=0x0) // Integer part of baud-rate divider
-
[0:3]FRADIV (def=0x0) // Fraction part of baud-rate divider
0x40004C0CCTL0// Control register 0
-
[13]UEN (def=0x0) // USART enable
-
[12]WL (def=0x0) // Word length
-
[11]WM (def=0x0) // Wakeup method in mute mode
-
[10]PCEN (def=0x0) // Parity check function enable
-
[9]PM (def=0x0) // Parity mode
-
[8]PERRIE (def=0x0) // Parity error interrupt enable
-
[7]TBEIE (def=0x0) // Transmitter buffer empty interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RBNEIE (def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE line detected interrupt enable
-
[3]TEN (def=0x0) // Transmitter enable
-
[2]REN (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup from mute mode
-
[0]SBKCMD (def=0x0) // Send break command
0x40004C10CTL1// Control register 1
-
[14]LMEN (def=0x0) // LIN mode enable
-
[12:13]STB (def=0x0) // STOP bits length
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBLEN (def=0x0) // LIN break frame length
-
[0:3]ADDR (def=0x0) // Address of the USART
0x40004C14CTL2// Control register 2
-
[7]DENT (def=0x0) // DMA request enable for transmission
-
[6]DENR (def=0x0) // DMA request enable for reception
-
[3]HDEN (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]ERRIE (def=0x0) // Error interrupt enable
0x40004C18GP// Guard time and prescaler register
-
[0:7]PSC (def=0x0) // Prescaler value
0x40005000UART4//
0x40005000STAT// Status register
-
[8]LBDF (def=0x0) // LIN break detection flag
-
[7]TBE (def=0x1) // Transmit data buffer empty
-
[6]TC (def=0x1) // Transmission complete
-
[5]RBNE (def=0x0) // Read data buffer not empty
-
[4]IDLEF (def=0x0) // IDLE frame detected flag
-
[3]ORERR (def=0x0) // Overrun error
-
[2]NERR (def=0x0) // Noise error flag
-
[1]FERR (def=0x0) // Frame error flag
-
[0]PERR (def=0x0) // Parity error flag
0x40005004DATA// Data register
-
[0:8]DATA (def=0x0) // Transmit or read data value
0x40005008BAUD// Baud rate register
-
[4:15]INTDIV (def=0x0) // Integer part of baud-rate divider
-
[0:3]FRADIV (def=0x0) // Fraction part of baud-rate divider
0x4000500CCTL0// Control register 0
-
[13]UEN (def=0x0) // USART enable
-
[12]WL (def=0x0) // Word length
-
[11]WM (def=0x0) // Wakeup method in mute mode
-
[10]PCEN (def=0x0) // Parity check function enable
-
[9]PM (def=0x0) // Parity mode
-
[8]PERRIE (def=0x0) // Parity error interrupt enable
-
[7]TBEIE (def=0x0) // Transmitter buffer empty interrupt enable
-
[6]TCIE (def=0x0) // Transmission complete interrupt enable
-
[5]RBNEIE (def=0x0) // Read data buffer not empty interrupt and overrun error interrupt enable
-
[4]IDLEIE (def=0x0) // IDLE line detected interrupt enable
-
[3]TEN (def=0x0) // Transmitter enable
-
[2]REN (def=0x0) // Receiver enable
-
[1]RWU (def=0x0) // Receiver wakeup from mute mode
-
[0]SBKCMD (def=0x0) // Send break command
0x40005010CTL1// Control register 1
-
[14]LMEN (def=0x0) // LIN mode enable
-
[12:13]STB (def=0x0) // STOP bits length
-
[6]LBDIE (def=0x0) // LIN break detection interrupt enable
-
[5]LBLEN (def=0x0) // LIN break frame length
-
[0:3]ADDR (def=0x0) // Address of the USART
0x40005014CTL2// Control register 2
-
[7]DENT (def=0x0) // DMA request enable for transmission
-
[6]DENR (def=0x0) // DMA request enable for reception
-
[3]HDEN (def=0x0) // Half-duplex selection
-
[2]IRLP (def=0x0) // IrDA low-power
-
[1]IREN (def=0x0) // IrDA mode enable
-
[0]ERRIE (def=0x0) // Error interrupt enable
0x40005018GP// Guard time and prescaler register
-
[0:7]PSC (def=0x0) // Prescaler value
0x50000000USBFS_GLOBAL// USB full speed global registers
0x50000000GOTGCS// Global OTG control and status register (USBFS_GOTGCS)
-
[0]SRPS (def=0x0) // SRP success
-
[1]SRPREQ (def=0x0) // SRP request
-
[8]HNPS (def=0x0) // Host success
-
[9]HNPREQ (def=0x0) // HNP request
-
[10]HHNPEN (def=0x0) // Host HNP enable
-
[11]DHNPEN (def=0x1) // Device HNP enabled
-
[16]IDPS (def=0x0) // ID pin status
-
[17]DI (def=0x0) // Debounce interval
-
[18]ASV (def=0x0) // A-session valid
-
[19]BSV (def=0x0) // B-session valid
0x50000004GOTGINTF// Global OTG interrupt flag register (USBFS_GOTGINTF)
-
[2]SESEND (def=0x0) // Session end
-
[8]SRPEND (def=0x0) // Session request success status change
-
[9]HNPEND (def=0x0) // HNP end
-
[17]HNPDET (def=0x0) // Host negotiation request detected
-
[18]ADTO (def=0x0) // A-device timeout
-
[19]DF (def=0x0) // Debounce finish
0x50000008GAHBCS// Global AHB control and status register (USBFS_GAHBCS)
-
[0]GINTEN (def=0x0) // Global interrupt enable
-
[7]TXFTH (def=0x0) // Tx FIFO threshold
-
[8]PTXFTH (def=0x0) // Periodic Tx FIFO threshold
0x5000000CGUSBCS// Global USB control and status register (USBFS_GUSBCSR)
-
[0:2]TOC (def=0x0) // Timeout calibration
-
[8]SRPCEN (def=0x0) // SRP capability enable
-
[9]HNPCEN (def=0x1) // HNP capability enable
-
[10:13]UTT (def=0x2) // USB turnaround time
-
[29]FHM (def=0x0) // Force host mode
-
[30]FDM (def=0x0) // Force device mode
0x50000010GRSTCTL// Global reset control register (USBFS_GRSTCTL)
-
[0]CSRST (def=0x0) // Core soft reset
-
[1]HCSRST (def=0x0) // HCLK soft reset
-
[2]HFCRST (def=0x0) // Host frame counter reset
-
[4]RXFF (def=0x0) // RxFIFO flush
-
[5]TXFF (def=0x0) // TxFIFO flush
-
[6:10]TXFNUM (def=0x0) // TxFIFO number
0x50000014GINTF// Global interrupt flag register (USBFS_GINTF)
-
[0]COPM (def=0x1) // Current operation mode
-
[1]MFIF (def=0x0) // Mode fault interrupt flag
-
[2]OTGIF (def=0x0) // OTG interrupt flag
-
[3]SOF (def=0x0) // Start of frame
-
[4]RXFNEIF (def=0x0) // RxFIFO non-empty interrupt flag
-
[5]NPTXFEIF (def=0x1) // Non-periodic TxFIFO empty interrupt flag
-
[6]GNPINAK (def=0x0) // Global Non-Periodic IN NAK effective
-
[7]GONAK (def=0x0) // Global OUT NAK effective
-
[10]ESP (def=0x0) // Early suspend
-
[11]SP (def=0x0) // USB suspend
-
[12]RST (def=0x0) // USB reset
-
[13]ENUMF (def=0x0) // Enumeration finished
-
[14]ISOOPDIF (def=0x0) // Isochronous OUT packet dropped interrupt
-
[15]EOPFIF (def=0x0) // End of periodic frame interrupt flag
-
[18]IEPIF (def=0x0) // IN endpoint interrupt flag
-
[19]OEPIF (def=0x0) // OUT endpoint interrupt flag
-
[20]ISOINCIF (def=0x0) // Isochronous IN transfer Not Complete Interrupt Flag
-
[21]PXNCIF_ISOONCIF (def=0x0) // periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not
-
[24]HPIF (def=0x0) // Host port interrupt flag
-
[25]HCIF (def=0x0) // Host channels interrupt flag
-
[26]PTXFEIF (def=0x1) // Periodic TxFIFO empty interrupt flag
-
[28]IDPSC (def=0x0) // ID pin status change
-
[29]DISCIF (def=0x0) // Disconnect interrupt flag
-
[30]SESIF (def=0x0) // Session interrupt flag
-
[31]WKUPIF (def=0x0) // Wakeup interrupt flag
0x50000018GINTEN// Global interrupt enable register (USBFS_GINTEN)
-
[1]MFIE (def=0x0) // Mode fault interrupt enable
-
[2]OTGIE (def=0x0) // OTG interrupt enable
-
[3]SOFIE (def=0x0) // Start of frame interrupt enable
-
[4]RXFNEIE (def=0x0) // Receive FIFO non-empty interrupt enable
-
[5]NPTXFEIE (def=0x0) // Non-periodic TxFIFO empty interrupt enable
-
[6]GNPINAKIE (def=0x0) // Global non-periodic IN NAK effective interrupt enable
-
[7]GONAKIE (def=0x0) // Global OUT NAK effective interrupt enable
-
[10]ESPIE (def=0x0) // Early suspend interrupt enable
-
[11]SPIE (def=0x0) // USB suspend interrupt enable
-
[12]RSTIE (def=0x0) // USB reset interrupt enable
-
[13]ENUMFIE (def=0x0) // Enumeration finish interrupt enable
-
[14]ISOOPDIE (def=0x0) // Isochronous OUT packet dropped interrupt enable
-
[15]EOPFIE (def=0x0) // End of periodic frame interrupt enable
-
[18]IEPIE (def=0x0) // IN endpoints interrupt enable
-
[19]OEPIE (def=0x0) // OUT endpoints interrupt enable
-
[20]ISOINCIE (def=0x0) // isochronous IN transfer not complete interrupt enable
-
[21]PXNCIE_ISOONCIE (def=0x0) // periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer
-
[24]HPIE (def=0x0) // Host port interrupt enable
-
[25]HCIE (def=0x0) // Host channels interrupt enable
-
[26]PTXFEIE (def=0x0) // Periodic TxFIFO empty interrupt enable
-
[28]IDPSCIE (def=0x0) // ID pin status change interrupt enable
-
[29]DISCIE (def=0x0) // Disconnect interrupt enable
-
[30]SESIE (def=0x0) // Session interrupt enable
-
[31]WKUPIE (def=0x0) // Wakeup interrupt enable
0x5000001CGRSTATR_Device// Global Receive status read(Device mode)
-
[0:3]EPNUM (def=0x0) // Endpoint number
-
[4:14]BCOUNT (def=0x0) // Byte count
-
[15:16]DPID (def=0x0) // Data PID
-
[17:20]RPCKST (def=0x0) // Recieve packet status
0x5000001CGRSTATR_Host// Global Receive status read(Host mode)
-
[0:3]CNUM (def=0x0) // Channel number
-
[4:14]BCOUNT (def=0x0) // Byte count
-
[15:16]DPID (def=0x0) // Data PID
-
[17:20]RPCKST (def=0x0) // Reivece packet status
0x50000020GRSTATP_Device// Global Receive status pop(Device mode)
-
[0:3]EPNUM (def=0x0) // Endpoint number
-
[4:14]BCOUNT (def=0x0) // Byte count
-
[15:16]DPID (def=0x0) // Data PID
-
[17:20]RPCKST (def=0x0) // Recieve packet status
0x50000020GRSTATP_Host// Global Receive status pop(Host mode)
-
[0:3]CNUM (def=0x0) // Channel number
-
[4:14]BCOUNT (def=0x0) // Byte count
-
[15:16]DPID (def=0x0) // Data PID
-
[17:20]RPCKST (def=0x0) // Reivece packet status
0x50000024GRFLEN// Global Receive FIFO size register (USBFS_GRFLEN)
-
[0:15]RXFD (def=0x200) // Rx FIFO depth
0x50000028HNPTFLEN// Host non-periodic transmit FIFO length register (Host mode)
-
[0:15]HNPTXRSAR (def=0x200) // host non-periodic transmit Tx RAM start address
-
[16:31]HNPTXFD (def=0x200) // host non-periodic TxFIFO depth
0x50000028DIEP0TFLEN// Device IN endpoint 0 transmit FIFO length (Device mode)
-
[16:31]IEP0TXFD (def=0x200) // in endpoint 0 Tx FIFO depth
-
[0:15]IEP0TXRSAR (def=0x200) // in endpoint 0 Tx RAM start address
0x5000002CHNPTFQSTAT// Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)
-
[0:15]NPTXFS (def=0x200) // Non-periodic TxFIFO space
-
[16:23]NPTXRQS (def=0x8) // Non-periodic transmit request queue space
-
[24:30]NPTXRQTOP (def=0x0) // Top of the non-periodic transmit request queue
0x50000038GCCFG// Global core configuration register (USBFS_GCCFG)
-
[16]PWRON (def=0x0) // Power on
-
[18]VBUSACEN (def=0x0) // The VBUS A-device Comparer enable
-
[19]VBUSBCEN (def=0x0) // The VBUS B-device Comparer enable
-
[20]SOFOEN (def=0x0) // SOF output enable
-
[21]VBUSIG (def=0x0) // VBUS ignored
0x5000003CCID// core ID register
-
[0:31]CID (def=0x1000) // Core ID
0x50000100HPTFLEN// Host periodic transmit FIFO length register (HPTFLEN)
-
[0:15]HPTXFSAR (def=0x600) // Host periodic TxFIFO start address
-
[16:31]HPTXFD (def=0x200) // Host periodic TxFIFO depth
0x50000104DIEP1TFLEN// device IN endpoint transmit FIFO size register (DIEP1TFLEN)
-
[0:15]IEPTXRSAR (def=0x400) // IN endpoint FIFO transmit RAM start address
-
[16:31]IEPTXFD (def=0x200) // IN endpoint TxFIFO depth
0x50000108DIEP2TFLEN// device IN endpoint transmit FIFO size register (DIEP2TFLEN)
-
[0:15]IEPTXRSAR (def=0x400) // IN endpoint FIFO transmit RAM start address
-
[16:31]IEPTXFD (def=0x200) // IN endpoint TxFIFO depth
0x5000010CDIEP3TFLEN// device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN)
-
[0:15]IEPTXRSAR (def=0x400) // IN endpoint FIFO4 transmit RAM start address
-
[16:31]IEPTXFD (def=0x200) // IN endpoint TxFIFO depth
- [61] USBFS_WKUP //
- [86] USBFS //
0x50000400USBFS_HOST// USB on the go full speed host
0x50000400HCTL// host configuration register (HCTL)
-
[0:1]CLKSEL (def=0x0) // clock select for USB clock
0x50000404HFT// Host frame interval register
-
[0:15]FRI (def=0xBB80) // Frame interval
0x50000408HFINFR// FS host frame number/frame time remaining register (HFINFR)
-
[0:15]FRNUM (def=0x0) // Frame number
-
[16:31]FRT (def=0xBB80) // Frame remaining time
0x50000410HPTFQSTAT// Host periodic transmit FIFO/queue status register (HPTFQSTAT)
-
[0:15]PTXFS (def=0x200) // Periodic transmit data FIFO space available
-
[16:23]PTXREQS (def=0x8) // Periodic transmit request queue space available
-
[24:31]PTXREQT (def=0x0) // Top of the periodic transmit request queue
0x50000414HACHINT// Host all channels interrupt register
-
[0:7]HACHINT (def=0x0) // Host all channel interrupts
0x50000418HACHINTEN// host all channels interrupt mask register
-
[0:7]CINTEN (def=0x0) // Channel interrupt enable
0x50000440HPCS// Host port control and status register (USBFS_HPCS)
-
[0]PCST (def=0x0) // Port connect status
-
[1]PCD (def=0x0) // Port connect detected
-
[2]PE (def=0x0) // Port enable
-
[3]PEDC (def=0x0) // Port enable/disable change
-
[6]PREM (def=0x0) // Port resume
-
[7]PSP (def=0x0) // Port suspend
-
[8]PRST (def=0x0) // Port reset
-
[10:11]PLST (def=0x0) // Port line status
-
[12]PP (def=0x0) // Port power
-
[17:18]PS (def=0x0) // Port speed
0x50000500HCH0CTL// host channel-0 characteristics register (HCH0CTL)
-
[0:10]MPL (def=0x0) // Maximum packet size
-
[11:14]EPNUM (def=0x0) // Endpoint number
-
[15]EPDIR (def=0x0) // Endpoint direction
-
[17]LSD (def=0x0) // Low-speed device
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[22:28]DAR (def=0x0) // Device address
-
[29]ODDFRM (def=0x0) // Odd frame
-
[30]CDIS (def=0x0) // Channel disable
-
[31]CEN (def=0x0) // Channel enable
0x50000520HCH1CTL// host channel-1 characteristics register (HCH1CTL)
-
[0:10]MPL (def=0x0) // Maximum packet size
-
[11:14]EPNUM (def=0x0) // Endpoint number
-
[15]EPDIR (def=0x0) // Endpoint direction
-
[17]LSD (def=0x0) // Low-speed device
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[22:28]DAR (def=0x0) // Device address
-
[29]ODDFRM (def=0x0) // Odd frame
-
[30]CDIS (def=0x0) // Channel disable
-
[31]CEN (def=0x0) // Channel enable
0x50000540HCH2CTL// host channel-2 characteristics register (HCH2CTL)
-
[0:10]MPL (def=0x0) // Maximum packet size
-
[11:14]EPNUM (def=0x0) // Endpoint number
-
[15]EPDIR (def=0x0) // Endpoint direction
-
[17]LSD (def=0x0) // Low-speed device
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[22:28]DAR (def=0x0) // Device address
-
[29]ODDFRM (def=0x0) // Odd frame
-
[30]CDIS (def=0x0) // Channel disable
-
[31]CEN (def=0x0) // Channel enable
0x50000560HCH3CTL// host channel-3 characteristics register (HCH3CTL)
-
[0:10]MPL (def=0x0) // Maximum packet size
-
[11:14]EPNUM (def=0x0) // Endpoint number
-
[15]EPDIR (def=0x0) // Endpoint direction
-
[17]LSD (def=0x0) // Low-speed device
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[22:28]DAR (def=0x0) // Device address
-
[29]ODDFRM (def=0x0) // Odd frame
-
[30]CDIS (def=0x0) // Channel disable
-
[31]CEN (def=0x0) // Channel enable
0x50000580HCH4CTL// host channel-4 characteristics register (HCH4CTL)
-
[0:10]MPL (def=0x0) // Maximum packet size
-
[11:14]EPNUM (def=0x0) // Endpoint number
-
[15]EPDIR (def=0x0) // Endpoint direction
-
[17]LSD (def=0x0) // Low-speed device
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[22:28]DAR (def=0x0) // Device address
-
[29]ODDFRM (def=0x0) // Odd frame
-
[30]CDIS (def=0x0) // Channel disable
-
[31]CEN (def=0x0) // Channel enable
0x500005A0HCH5CTL// host channel-5 characteristics register (HCH5CTL)
-
[0:10]MPL (def=0x0) // Maximum packet size
-
[11:14]EPNUM (def=0x0) // Endpoint number
-
[15]EPDIR (def=0x0) // Endpoint direction
-
[17]LSD (def=0x0) // Low-speed device
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[22:28]DAR (def=0x0) // Device address
-
[29]ODDFRM (def=0x0) // Odd frame
-
[30]CDIS (def=0x0) // Channel disable
-
[31]CEN (def=0x0) // Channel enable
0x500005C0HCH6CTL// host channel-6 characteristics register (HCH6CTL)
-
[0:10]MPL (def=0x0) // Maximum packet size
-
[11:14]EPNUM (def=0x0) // Endpoint number
-
[15]EPDIR (def=0x0) // Endpoint direction
-
[17]LSD (def=0x0) // Low-speed device
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[22:28]DAR (def=0x0) // Device address
-
[29]ODDFRM (def=0x0) // Odd frame
-
[30]CDIS (def=0x0) // Channel disable
-
[31]CEN (def=0x0) // Channel enable
0x500005E0HCH7CTL// host channel-7 characteristics register (HCH7CTL)
-
[0:10]MPL (def=0x0) // Maximum packet size
-
[11:14]EPNUM (def=0x0) // Endpoint number
-
[15]EPDIR (def=0x0) // Endpoint direction
-
[17]LSD (def=0x0) // Low-speed device
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[22:28]DAR (def=0x0) // Device address
-
[29]ODDFRM (def=0x0) // Odd frame
-
[30]CDIS (def=0x0) // Channel disable
-
[31]CEN (def=0x0) // Channel enable
0x50000508HCH0INTF// host channel-0 interrupt register (USBFS_HCHxINTF)
-
[0]TF (def=0x0) // Transfer finished
-
[1]CH (def=0x0) // Channel halted
-
[3]STALL (def=0x0) // STALL response received interrupt
-
[4]NAK (def=0x0) // NAK response received interrupt
-
[5]ACK (def=0x0) // ACK response received/transmitted interrupt
-
[7]USBER (def=0x0) // USB bus error
-
[8]BBER (def=0x0) // Babble error
-
[9]REQOVR (def=0x0) // Request queue overrun
-
[10]DTER (def=0x0) // Data toggle error
0x50000528HCH1INTF// host channel-1 interrupt register (HCH1INTF)
-
[0]TF (def=0x0) // Transfer finished
-
[1]CH (def=0x0) // Channel halted
-
[3]STALL (def=0x0) // STALL response received interrupt
-
[4]NAK (def=0x0) // NAK response received interrupt
-
[5]ACK (def=0x0) // ACK response received/transmitted interrupt
-
[7]USBER (def=0x0) // USB bus error
-
[8]BBER (def=0x0) // Babble error
-
[9]REQOVR (def=0x0) // Request queue overrun
-
[10]DTER (def=0x0) // Data toggle error
0x50000548HCH2INTF// host channel-2 interrupt register (HCH2INTF)
-
[0]TF (def=0x0) // Transfer finished
-
[1]CH (def=0x0) // Channel halted
-
[3]STALL (def=0x0) // STALL response received interrupt
-
[4]NAK (def=0x0) // NAK response received interrupt
-
[5]ACK (def=0x0) // ACK response received/transmitted interrupt
-
[7]USBER (def=0x0) // USB bus error
-
[8]BBER (def=0x0) // Babble error
-
[9]REQOVR (def=0x0) // Request queue overrun
-
[10]DTER (def=0x0) // Data toggle error
0x50000568HCH3INTF// host channel-3 interrupt register (HCH3INTF)
-
[0]TF (def=0x0) // Transfer finished
-
[1]CH (def=0x0) // Channel halted
-
[3]STALL (def=0x0) // STALL response received interrupt
-
[4]NAK (def=0x0) // NAK response received interrupt
-
[5]ACK (def=0x0) // ACK response received/transmitted interrupt
-
[7]USBER (def=0x0) // USB bus error
-
[8]BBER (def=0x0) // Babble error
-
[9]REQOVR (def=0x0) // Request queue overrun
-
[10]DTER (def=0x0) // Data toggle error
0x50000588HCH4INTF// host channel-4 interrupt register (HCH4INTF)
-
[0]TF (def=0x0) // Transfer finished
-
[1]CH (def=0x0) // Channel halted
-
[3]STALL (def=0x0) // STALL response received interrupt
-
[4]NAK (def=0x0) // NAK response received interrupt
-
[5]ACK (def=0x0) // ACK response received/transmitted interrupt
-
[7]USBER (def=0x0) // USB bus error
-
[8]BBER (def=0x0) // Babble error
-
[9]REQOVR (def=0x0) // Request queue overrun
-
[10]DTER (def=0x0) // Data toggle error
0x500005A8HCH5INTF// host channel-5 interrupt register (HCH5INTF)
-
[0]TF (def=0x0) // Transfer finished
-
[1]CH (def=0x0) // Channel halted
-
[3]STALL (def=0x0) // STALL response received interrupt
-
[4]NAK (def=0x0) // NAK response received interrupt
-
[5]ACK (def=0x0) // ACK response received/transmitted interrupt
-
[7]USBER (def=0x0) // USB bus error
-
[8]BBER (def=0x0) // Babble error
-
[9]REQOVR (def=0x0) // Request queue overrun
-
[10]DTER (def=0x0) // Data toggle error
0x500005C8HCH6INTF// host channel-6 interrupt register (HCH6INTF)
-
[0]TF (def=0x0) // Transfer finished
-
[1]CH (def=0x0) // Channel halted
-
[3]STALL (def=0x0) // STALL response received interrupt
-
[4]NAK (def=0x0) // NAK response received interrupt
-
[5]ACK (def=0x0) // ACK response received/transmitted interrupt
-
[7]USBER (def=0x0) // USB bus error
-
[8]BBER (def=0x0) // Babble error
-
[9]REQOVR (def=0x0) // Request queue overrun
-
[10]DTER (def=0x0) // Data toggle error
0x500005E8HCH7INTF// host channel-7 interrupt register (HCH7INTF)
-
[0]TF (def=0x0) // Transfer finished
-
[1]CH (def=0x0) // Channel halted
-
[3]STALL (def=0x0) // STALL response received interrupt
-
[4]NAK (def=0x0) // NAK response received interrupt
-
[5]ACK (def=0x0) // ACK response received/transmitted interrupt
-
[7]USBER (def=0x0) // USB bus error
-
[8]BBER (def=0x0) // Babble error
-
[9]REQOVR (def=0x0) // Request queue overrun
-
[10]DTER (def=0x0) // Data toggle error
0x5000050CHCH0INTEN// host channel-0 interrupt enable register (HCH0INTEN)
-
[0]TFIE (def=0x0) // Transfer completed interrupt enable
-
[1]CHIE (def=0x0) // Channel halted interrupt enable
-
[3]STALLIE (def=0x0) // STALL interrupt enable
-
[4]NAKIE (def=0x0) // NAK interrupt enable
-
[5]ACKIE (def=0x0) // ACK interrupt enable
-
[7]USBERIE (def=0x0) // USB bus error interrupt enable
-
[8]BBERIE (def=0x0) // Babble error interrupt enable
-
[9]REQOVRIE (def=0x0) // request queue overrun interrupt enable
-
[10]DTERIE (def=0x0) // Data toggle error interrupt enable
0x5000052CHCH1INTEN// host channel-1 interrupt enable register (HCH1INTEN)
-
[0]TFIE (def=0x0) // Transfer completed interrupt enable
-
[1]CHIE (def=0x0) // Channel halted interrupt enable
-
[3]STALLIE (def=0x0) // STALL interrupt enable
-
[4]NAKIE (def=0x0) // NAK interrupt enable
-
[5]ACKIE (def=0x0) // ACK interrupt enable
-
[7]USBERIE (def=0x0) // USB bus error interrupt enable
-
[8]BBERIE (def=0x0) // Babble error interrupt enable
-
[9]REQOVRIE (def=0x0) // request queue overrun interrupt enable
-
[10]DTERIE (def=0x0) // Data toggle error interrupt enable
0x5000054CHCH2INTEN// host channel-2 interrupt enable register (HCH2INTEN)
-
[0]TFIE (def=0x0) // Transfer completed interrupt enable
-
[1]CHIE (def=0x0) // Channel halted interrupt enable
-
[3]STALLIE (def=0x0) // STALL interrupt enable
-
[4]NAKIE (def=0x0) // NAK interrupt enable
-
[5]ACKIE (def=0x0) // ACK interrupt enable
-
[7]USBERIE (def=0x0) // USB bus error interrupt enable
-
[8]BBERIE (def=0x0) // Babble error interrupt enable
-
[9]REQOVRIE (def=0x0) // request queue overrun interrupt enable
-
[10]DTERIE (def=0x0) // Data toggle error interrupt enable
0x5000056CHCH3INTEN// host channel-3 interrupt enable register (HCH3INTEN)
-
[0]TFIE (def=0x0) // Transfer completed interrupt enable
-
[1]CHIE (def=0x0) // Channel halted interrupt enable
-
[3]STALLIE (def=0x0) // STALL interrupt enable
-
[4]NAKIE (def=0x0) // NAK interrupt enable
-
[5]ACKIE (def=0x0) // ACK interrupt enable
-
[7]USBERIE (def=0x0) // USB bus error interrupt enable
-
[8]BBERIE (def=0x0) // Babble error interrupt enable
-
[9]REQOVRIE (def=0x0) // request queue overrun interrupt enable
-
[10]DTERIE (def=0x0) // Data toggle error interrupt enable
0x5000058CHCH4INTEN// host channel-4 interrupt enable register (HCH4INTEN)
-
[0]TFIE (def=0x0) // Transfer completed interrupt enable
-
[1]CHIE (def=0x0) // Channel halted interrupt enable
-
[3]STALLIE (def=0x0) // STALL interrupt enable
-
[4]NAKIE (def=0x0) // NAK interrupt enable
-
[5]ACKIE (def=0x0) // ACK interrupt enable
-
[7]USBERIE (def=0x0) // USB bus error interrupt enable
-
[8]BBERIE (def=0x0) // Babble error interrupt enable
-
[9]REQOVRIE (def=0x0) // request queue overrun interrupt enable
-
[10]DTERIE (def=0x0) // Data toggle error interrupt enable
0x500005ACHCH5INTEN// host channel-5 interrupt enable register (HCH5INTEN)
-
[0]TFIE (def=0x0) // Transfer completed interrupt enable
-
[1]CHIE (def=0x0) // Channel halted interrupt enable
-
[3]STALLIE (def=0x0) // STALL interrupt enable
-
[4]NAKIE (def=0x0) // NAK interrupt enable
-
[5]ACKIE (def=0x0) // ACK interrupt enable
-
[7]USBERIE (def=0x0) // USB bus error interrupt enable
-
[8]BBERIE (def=0x0) // Babble error interrupt enable
-
[9]REQOVRIE (def=0x0) // request queue overrun interrupt enable
-
[10]DTERIE (def=0x0) // Data toggle error interrupt enable
0x500005CCHCH6INTEN// host channel-6 interrupt enable register (HCH6INTEN)
-
[0]TFIE (def=0x0) // Transfer completed interrupt enable
-
[1]CHIE (def=0x0) // Channel halted interrupt enable
-
[3]STALLIE (def=0x0) // STALL interrupt enable
-
[4]NAKIE (def=0x0) // NAK interrupt enable
-
[5]ACKIE (def=0x0) // ACK interrupt enable
-
[7]USBERIE (def=0x0) // USB bus error interrupt enable
-
[8]BBERIE (def=0x0) // Babble error interrupt enable
-
[9]REQOVRIE (def=0x0) // request queue overrun interrupt enable
-
[10]DTERIE (def=0x0) // Data toggle error interrupt enable
0x500005ECHCH7INTEN// host channel-7 interrupt enable register (HCH7INTEN)
-
[0]TFIE (def=0x0) // Transfer completed interrupt enable
-
[1]CHIE (def=0x0) // Channel halted interrupt enable
-
[3]STALLIE (def=0x0) // STALL interrupt enable
-
[4]NAKIE (def=0x0) // NAK interrupt enable
-
[5]ACKIE (def=0x0) // ACK interrupt enable
-
[7]USBERIE (def=0x0) // USB bus error interrupt enable
-
[8]BBERIE (def=0x0) // Babble error interrupt enable
-
[9]REQOVRIE (def=0x0) // request queue overrun interrupt enable
-
[10]DTERIE (def=0x0) // Data toggle error interrupt enable
0x50000510HCH0LEN// host channel-0 transfer length register
-
[0:18]TLEN (def=0x0) // Transfer length
-
[19:28]PCNT (def=0x0) // Packet count
-
[29:30]DPID (def=0x0) // Data PID
0x50000530HCH1LEN// host channel-1 transfer length register
-
[0:18]TLEN (def=0x0) // Transfer length
-
[19:28]PCNT (def=0x0) // Packet count
-
[29:30]DPID (def=0x0) // Data PID
0x50000550HCH2LEN// host channel-2 transfer length register
-
[0:18]TLEN (def=0x0) // Transfer length
-
[19:28]PCNT (def=0x0) // Packet count
-
[29:30]DPID (def=0x0) // Data PID
0x50000570HCH3LEN// host channel-3 transfer length register
-
[0:18]TLEN (def=0x0) // Transfer length
-
[19:28]PCNT (def=0x0) // Packet count
-
[29:30]DPID (def=0x0) // Data PID
0x50000590HCH4LEN// host channel-4 transfer length register
-
[0:18]TLEN (def=0x0) // Transfer length
-
[19:28]PCNT (def=0x0) // Packet count
-
[29:30]DPID (def=0x0) // Data PID
0x500005B0HCH5LEN// host channel-5 transfer length register
-
[0:18]TLEN (def=0x0) // Transfer length
-
[19:28]PCNT (def=0x0) // Packet count
-
[29:30]DPID (def=0x0) // Data PID
0x500005D0HCH6LEN// host channel-6 transfer length register
-
[0:18]TLEN (def=0x0) // Transfer length
-
[19:28]PCNT (def=0x0) // Packet count
-
[29:30]DPID (def=0x0) // Data PID
0x500005F0HCH7LEN// host channel-7 transfer length register
-
[0:18]TLEN (def=0x0) // Transfer length
-
[19:28]PCNT (def=0x0) // Packet count
-
[29:30]DPID (def=0x0) // Data PID
0x50000800USBFS_DEVICE// USB on the go full speed device
0x50000800DCFG// device configuration register (DCFG)
-
[0:1]DS (def=0x0) // Device speed
-
[2]NZLSOH (def=0x0) // Non-zero-length status OUT handshake
-
[4:10]DAR (def=0x0) // Device address
-
[11:12]EOPFT (def=0x0) // end of periodic frame time
0x50000804DCTL// device control register (DCTL)
-
[0]RWKUP (def=0x0) // Remote wakeup
-
[1]SD (def=0x0) // Soft disconnect
-
[2]GINS (def=0x0) // Global IN NAK status
-
[3]GONS (def=0x0) // Global OUT NAK status
-
[7]SGINAK (def=0x0) // Set global IN NAK
-
[8]CGINAK (def=0x0) // Clear global IN NAK
-
[9]SGONAK (def=0x0) // Set global OUT NAK
-
[10]CGONAK (def=0x0) // Clear global OUT NAK
-
[11]POIF (def=0x0) // Power-on initialization flag
0x50000808DSTAT// device status register (DSTAT)
-
[0]SPST (def=0x0) // Suspend status
-
[1:2]ES (def=0x0) // Enumerated speed
-
[8:21]FNRSOF (def=0x0) // Frame number of the received SOF
0x50000810DIEPINTEN// device IN endpoint common interrupt mask register (DIEPINTEN)
-
[0]TFEN (def=0x0) // Transfer finished interrupt enable
-
[1]EPDISEN (def=0x0) // Endpoint disabled interrupt enable
-
[3]CITOEN (def=0x0) // Control IN timeout condition interrupt enable (Non-isochronous endpoints)
-
[4]EPTXFUDEN (def=0x0) // Endpoint Tx FIFO underrun interrupt enable bit
-
[6]IEPNEEN (def=0x0) // IN endpoint NAK effective interrupt enable
0x50000814DOEPINTEN// device OUT endpoint common interrupt enable register (DOEPINTEN)
-
[0]TFEN (def=0x0) // Transfer finished interrupt enable
-
[1]EPDISEN (def=0x0) // Endpoint disabled interrupt enable
-
[3]STPFEN (def=0x0) // SETUP phase finished interrupt enable
-
[4]EPRXFOVREN (def=0x0) // Endpoint Rx FIFO overrun interrupt enable
-
[6]BTBSTPEN (def=0x0) // Back-to-back SETUP packets interrupt enable
0x50000818DAEPINT// device all endpoints interrupt register (DAEPINT)
-
[0:3]IEPITB (def=0x0) // Device all IN endpoint interrupt bits
-
[16:19]OEPITB (def=0x0) // Device all OUT endpoint interrupt bits
0x5000081CDAEPINTEN// Device all endpoints interrupt enable register (DAEPINTEN)
-
[0:3]IEPIE (def=0x0) // IN EP interrupt interrupt enable bits
-
[16:19]OEPIE (def=0x0) // OUT endpoint interrupt enable bits
0x50000828DVBUSDT// device VBUS discharge time register
-
[0:15]DVBUSDT (def=0x17D7) // Device VBUS discharge time
0x5000082CDVBUSPT// device VBUS pulsing time register
-
[0:11]DVBUSPT (def=0x5B8) // Device VBUS pulsing time
0x50000834DIEPFEINTEN// device IN endpoint FIFO empty interrupt enable register
-
[0:3]IEPTXFEIE (def=0x0) // IN EP Tx FIFO empty interrupt enable bits
0x50000900DIEP0CTL// device IN endpoint 0 control register (DIEP0CTL)
-
[0:1]MPL (def=0x0) // Maximum packet length
-
[15]EPACT (def=0x1) // endpoint active
-
[17]NAKS (def=0x0) // NAK status
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[21]STALL (def=0x0) // STALL handshake
-
[22:25]TXFNUM (def=0x0) // TxFIFO number
-
[26]CNAK (def=0x0) // Clear NAK
-
[27]SNAK (def=0x0) // Set NAK
-
[30]EPD (def=0x0) // Endpoint disable
-
[31]EPEN (def=0x0) // Endpoint enable
0x50000920DIEP1CTL// device in endpoint-1 control register
-
[31]EPEN (def=0x0) // Endpoint enable
-
[30]EPD (def=0x0) // Endpoint disable
-
[29]SD1PID_SODDFRM (def=0x0) // Set DATA1 PID/Set odd frame
-
[28]SD0PID_SEVENFRM (def=0x0) // SD0PID/SEVNFRM
-
[27]SNAK (def=0x0) // Set NAK
-
[26]CNAK (def=0x0) // Clear NAK
-
[22:25]TXFNUM (def=0x0) // Tx FIFO number
-
[21]STALL (def=0x0) // STALL handshake
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[17]NAKS (def=0x0) // NAK status
-
[16]EOFRM_DPID (def=0x0) // EOFRM/DPID
-
[15]EPACT (def=0x0) // Endpoint active
-
[0:10]MPL (def=0x0) // maximum packet length
0x50000940DIEP2CTL// device endpoint-2 control register
-
[31]EPEN (def=0x0) // Endpoint enable
-
[30]EPD (def=0x0) // Endpoint disable
-
[29]SD1PID_SODDFRM (def=0x0) // Set DATA1 PID/Set odd frame
-
[28]SD0PID_SEVENFRM (def=0x0) // SD0PID/SEVNFRM
-
[27]SNAK (def=0x0) // Set NAK
-
[26]CNAK (def=0x0) // Clear NAK
-
[22:25]TXFNUM (def=0x0) // Tx FIFO number
-
[21]STALL (def=0x0) // STALL handshake
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[17]NAKS (def=0x0) // NAK status
-
[16]EOFRM_DPID (def=0x0) // EOFRM/DPID
-
[15]EPACT (def=0x0) // Endpoint active
-
[0:10]MPL (def=0x0) // maximum packet length
0x50000960DIEP3CTL// device endpoint-3 control register
-
[31]EPEN (def=0x0) // Endpoint enable
-
[30]EPD (def=0x0) // Endpoint disable
-
[29]SD1PID_SODDFRM (def=0x0) // Set DATA1 PID/Set odd frame
-
[28]SD0PID_SEVENFRM (def=0x0) // SD0PID/SEVNFRM
-
[27]SNAK (def=0x0) // Set NAK
-
[26]CNAK (def=0x0) // Clear NAK
-
[22:25]TXFNUM (def=0x0) // Tx FIFO number
-
[21]STALL (def=0x0) // STALL handshake
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[17]NAKS (def=0x0) // NAK status
-
[16]EOFRM_DPID (def=0x0) // EOFRM/DPID
-
[15]EPACT (def=0x0) // Endpoint active
-
[0:10]MPL (def=0x0) // maximum packet length
0x50000B00DOEP0CTL// device endpoint-0 control register
-
[31]EPEN (def=0x0) // Endpoint enable
-
[30]EPD (def=0x0) // Endpoint disable
-
[27]SNAK (def=0x0) // Set NAK
-
[26]CNAK (def=0x0) // Clear NAK
-
[21]STALL (def=0x0) // STALL handshake
-
[20]SNOOP (def=0x0) // Snoop mode
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[17]NAKS (def=0x0) // NAK status
-
[15]EPACT (def=0x1) // Endpoint active
-
[0:1]MPL (def=0x0) // Maximum packet length
0x50000B20DOEP1CTL// device endpoint-1 control register
-
[31]EPEN (def=0x0) // Endpoint enable
-
[30]EPD (def=0x0) // Endpoint disable
-
[29]SD1PID_SODDFRM (def=0x0) // SD1PID/SODDFRM
-
[28]SD0PID_SEVENFRM (def=0x0) // SD0PID/SEVENFRM
-
[27]SNAK (def=0x0) // Set NAK
-
[26]CNAK (def=0x0) // Clear NAK
-
[21]STALL (def=0x0) // STALL handshake
-
[20]SNOOP (def=0x0) // Snoop mode
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[17]NAKS (def=0x0) // NAK status
-
[16]EOFRM_DPID (def=0x0) // EOFRM/DPID
-
[15]EPACT (def=0x0) // Endpoint active
-
[0:10]MPL (def=0x0) // maximum packet length
0x50000B40DOEP2CTL// device endpoint-2 control register
-
[31]EPEN (def=0x0) // Endpoint enable
-
[30]EPD (def=0x0) // Endpoint disable
-
[29]SD1PID_SODDFRM (def=0x0) // SD1PID/SODDFRM
-
[28]SD0PID_SEVENFRM (def=0x0) // SD0PID/SEVENFRM
-
[27]SNAK (def=0x0) // Set NAK
-
[26]CNAK (def=0x0) // Clear NAK
-
[21]STALL (def=0x0) // STALL handshake
-
[20]SNOOP (def=0x0) // Snoop mode
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[17]NAKS (def=0x0) // NAK status
-
[16]EOFRM_DPID (def=0x0) // EOFRM/DPID
-
[15]EPACT (def=0x0) // Endpoint active
-
[0:10]MPL (def=0x0) // maximum packet length
0x50000B60DOEP3CTL// device endpoint-3 control register
-
[31]EPEN (def=0x0) // Endpoint enable
-
[30]EPD (def=0x0) // Endpoint disable
-
[29]SD1PID_SODDFRM (def=0x0) // SD1PID/SODDFRM
-
[28]SD0PID_SEVENFRM (def=0x0) // SD0PID/SEVENFRM
-
[27]SNAK (def=0x0) // Set NAK
-
[26]CNAK (def=0x0) // Clear NAK
-
[21]STALL (def=0x0) // STALL handshake
-
[20]SNOOP (def=0x0) // Snoop mode
-
[18:19]EPTYPE (def=0x0) // Endpoint type
-
[17]NAKS (def=0x0) // NAK status
-
[16]EOFRM_DPID (def=0x0) // EOFRM/DPID
-
[15]EPACT (def=0x0) // Endpoint active
-
[0:10]MPL (def=0x0) // maximum packet length
0x50000908DIEP0INTF// device endpoint-0 interrupt register
-
[7]TXFE (def=0x1) // Transmit FIFO empty
-
[6]IEPNE (def=0x0) // IN endpoint NAK effective
-
[4]EPTXFUD (def=0x0) // Endpoint Tx FIFO underrun
-
[3]CITO (def=0x0) // Control in timeout interrupt
-
[1]EPDIS (def=0x0) // Endpoint finished
-
[0]TF (def=0x0) // Transfer finished
0x50000928DIEP1INTF// device endpoint-1 interrupt register
-
[7]TXFE (def=0x1) // Transmit FIFO empty
-
[6]IEPNE (def=0x0) // IN endpoint NAK effective
-
[4]EPTXFUD (def=0x0) // Endpoint Tx FIFO underrun
-
[3]CITO (def=0x0) // Control in timeout interrupt
-
[1]EPDIS (def=0x0) // Endpoint finished
-
[0]TF (def=0x0) // Transfer finished
0x50000948DIEP2INTF// device endpoint-2 interrupt register
-
[7]TXFE (def=0x1) // Transmit FIFO empty
-
[6]IEPNE (def=0x0) // IN endpoint NAK effective
-
[4]EPTXFUD (def=0x0) // Endpoint Tx FIFO underrun
-
[3]CITO (def=0x0) // Control in timeout interrupt
-
[1]EPDIS (def=0x0) // Endpoint finished
-
[0]TF (def=0x0) // Transfer finished
0x50000968DIEP3INTF// device endpoint-3 interrupt register
-
[7]TXFE (def=0x1) // Transmit FIFO empty
-
[6]IEPNE (def=0x0) // IN endpoint NAK effective
-
[4]EPTXFUD (def=0x0) // Endpoint Tx FIFO underrun
-
[3]CITO (def=0x0) // Control in timeout interrupt
-
[1]EPDIS (def=0x0) // Endpoint finished
-
[0]TF (def=0x0) // Transfer finished
0x50000B08DOEP0INTF// device out endpoint-0 interrupt flag register
-
[6]BTBSTP (def=0x0) // Back-to-back SETUP packets
-
[4]EPRXFOVR (def=0x0) // Endpoint Rx FIFO overrun
-
[3]STPF (def=0x0) // Setup phase finished
-
[1]EPDIS (def=0x0) // Endpoint disabled
-
[0]TF (def=0x0) // Transfer finished
0x50000B28DOEP1INTF// device out endpoint-1 interrupt flag register
-
[6]BTBSTP (def=0x0) // Back-to-back SETUP packets
-
[4]EPRXFOVR (def=0x0) // Endpoint Rx FIFO overrun
-
[3]STPF (def=0x0) // Setup phase finished
-
[1]EPDIS (def=0x0) // Endpoint disabled
-
[0]TF (def=0x0) // Transfer finished
0x50000B48DOEP2INTF// device out endpoint-2 interrupt flag register
-
[6]BTBSTP (def=0x0) // Back-to-back SETUP packets
-
[4]EPRXFOVR (def=0x0) // Endpoint Rx FIFO overrun
-
[3]STPF (def=0x0) // Setup phase finished
-
[1]EPDIS (def=0x0) // Endpoint disabled
-
[0]TF (def=0x0) // Transfer finished
0x50000B68DOEP3INTF// device out endpoint-3 interrupt flag register
-
[6]BTBSTP (def=0x0) // Back-to-back SETUP packets
-
[4]EPRXFOVR (def=0x0) // Endpoint Rx FIFO overrun
-
[3]STPF (def=0x0) // Setup phase finished
-
[1]EPDIS (def=0x0) // Endpoint disabled
-
[0]TF (def=0x0) // Transfer finished
0x50000910DIEP0LEN// device IN endpoint-0 transfer length register
-
[19:20]PCNT (def=0x0) // Packet count
-
[0:6]TLEN (def=0x0) // Transfer length
0x50000B10DOEP0LEN// device OUT endpoint-0 transfer length register
-
[29:30]STPCNT (def=0x0) // SETUP packet count
-
[19]PCNT (def=0x0) // Packet count
-
[0:6]TLEN (def=0x0) // Transfer length
0x50000930DIEP1LEN// device IN endpoint-1 transfer length register
-
[29:30]MCPF (def=0x0) // Multi packet count per frame
-
[19:28]PCNT (def=0x0) // Packet count
-
[0:18]TLEN (def=0x0) // Transfer length
0x50000950DIEP2LEN// device IN endpoint-2 transfer length register
-
[29:30]MCPF (def=0x0) // Multi packet count per frame
-
[19:28]PCNT (def=0x0) // Packet count
-
[0:18]TLEN (def=0x0) // Transfer length
0x50000970DIEP3LEN// device IN endpoint-3 transfer length register
-
[29:30]MCPF (def=0x0) // Multi packet count per frame
-
[19:28]PCNT (def=0x0) // Packet count
-
[0:18]TLEN (def=0x0) // Transfer length
0x50000B30DOEP1LEN// device OUT endpoint-1 transfer length register
-
[29:30]STPCNT_RXDPID (def=0x0) // SETUP packet count/Received data PID
-
[19:28]PCNT (def=0x0) // Packet count
-
[0:18]TLEN (def=0x0) // Transfer length
0x50000B50DOEP2LEN// device OUT endpoint-2 transfer length register
-
[29:30]STPCNT_RXDPID (def=0x0) // SETUP packet count/Received data PID
-
[19:28]PCNT (def=0x0) // Packet count
-
[0:18]TLEN (def=0x0) // Transfer length
0x50000B70DOEP3LEN// device OUT endpoint-3 transfer length register
-
[29:30]STPCNT_RXDPID (def=0x0) // SETUP packet count/Received data PID
-
[19:28]PCNT (def=0x0) // Packet count
-
[0:18]TLEN (def=0x0) // Transfer length
0x50000918DIEP0TFSTAT// device IN endpoint 0 transmit FIFO status register
-
[0:15]IEPTFS (def=0x200) // IN endpoint TxFIFO space remaining
0x50000938DIEP1TFSTAT// device IN endpoint 1 transmit FIFO status register
-
[0:15]IEPTFS (def=0x200) // IN endpoint TxFIFO space remaining
0x50000958DIEP2TFSTAT// device IN endpoint 2 transmit FIFO status register
-
[0:15]IEPTFS (def=0x200) // IN endpoint TxFIFO space remaining
0x50000978DIEP3TFSTAT// device IN endpoint 3 transmit FIFO status register
-
[0:15]IEPTFS (def=0x200) // IN endpoint TxFIFO space remaining
0x50000E00USBFS_PWRCLK// USB on the go full speed
0x50000E00PWRCLKCTL// power and clock gating control register (PWRCLKCTL)
-
[0]SUCLK (def=0x0) // Stop the USB clock
-
[1]SHCLK (def=0x0) // Stop HCLK
0x40002C00WWDGT// Window watchdog timer
0x40002C00CTL// Control register
-
[7]WDGTEN (def=0x0) // Activation bit
-
[0:6]CNT (def=0x7F) // 7-bit counter
0x40002C04CFG// Configuration register
-
[9]EWIE (def=0x0) // Early wakeup interrupt
-
[7:8]PSC (def=0x0) // Prescaler
-
[0:6]WIN (def=0x7F) // 7-bit window value
0x40002C08STAT// Status register
-
[0]EWIF (def=0x0) // Early wakeup interrupt flag